FAN6961SY_技术文档

January 2009

FAN6961

Boundary Mode PFC Controller

Features

Description

Boundary Mode PFC Controller

The FAN6961 is an 8-pin, boundary-mode, PFC

controller IC intended for controlling PFC pre-

regulators. The FAN6961 provides a controlled on-time

to regulate the output DC voltage and achieve natural

power factor correction. The maximum on-time of the

external switch is programmable to ensure safe

operation during AC brownouts. An innovative multi-

vector error amplifier is built in to provide rapid transient

response and precise output voltage clamping. A built-

in circuit disables the controller if the output feedback

loop is opened. The start-up current is lower than 20µA

and the operating current has been reduced to under

6mA. The supply voltage can be up to 25V, maximizing

application flexibility.

Low Input Current THD

Controlled On-Time PWM

Zero-Current Detection

Cycle-by-Cycle Current Limiting

Leading-Edge Blanking instead of RC Filtering

Low Start-up Current: 10µA Typical

Low Operating Current: 4.5mA Typical

Feedback Open-Loop Protection

Programmable Maximum On-Time (MOT)

Output Over-Voltage Clamping Protection

Clamped Gate Output Voltage 16.5V

Applications

Electric Lamp Ballasts

AC-DC Switching Mode Power Converter

Open Frame Power Supplies and Power Adapters

Flyback Power Converters with ZCS / ZVS

Ordering Information

Part

Number

Operating

Temperature Range

Packing

Package

Eco Status

Method

Tape & Reel

Tube

FAN6961SZ

FAN6961DZ

FAN6961SY

-40°C to +125°C

8-Pin, Small Outline Package (SOP)

8-Pin, Dual In-line Package (DIP)

8-Pin, Small Outline Package (SOP)

RoHS

Green

-40°C to +125°C

Tape & Reel

For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

FAN6961 • Rev. 1.0.2

www.fairchildsemi.com

Application Diagram

Figure 1.

Typical Application

Block Diagram

Figure 2. Function Block Diagram

FAN6961 • Rev. 1.0.2

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2

Marking Information

F- Fairchild Logo

Z- Plant Code

X- Year Code

Y- Week Code

TT: Die Run Code

T: Package type (S=SOP, D=DIP)

FAN6961

TPM

P: Z: Pb Free

Y: Green Compound

M: Manufacture Flow Code

Figure 3. Marking Information

Pin Configuration

VCC

GATE

GND

ZCD

8

7

6

5

1

2

3

4

INV

COMP MOT

CS

Figure 4.

DIP and SOP Pin Configuration (Top View)

Pin Definitions

Pin #

Name Description

Inverting input of the error amplifier. INV is connected to the converter output via a resistive

divider. This pin is also used for over-voltage clamping and open-loop feedback protection.

1

INV

The output of the error amplifier. To create a precise clamping protection, a compensation

network between this pin and GND is suggested.

2

3

COMP

Maximum On Time A resistor from MOT to GND is used to determine the maximum on-time of

the external power MOSFET. The maximum output power of the converter is a function of the

maximum on time.

MOT

CS

Current Sense. Input to the over-current protection comparator. When the sensed voltage

across the sense resistor reaches the internal threshold (0.8V), the switch is turned off to

activate cycle-by-cycle current limiting.

4

Zero Current Detection. This pin is connected to an auxiliary winding via a resistor to detect

the zero crossing of the switch current. When the zero crossing is detected, a new switching

cycle is started. If it is connected to GND, the device is disabled.

5

6

ZCD

GND

Ground. The power ground and signal ground. Placing a 0.1µF decoupling capacitor between

VCC and GND is recommended.

Driver output. Totem-pole driver output to drive the external power MOSFET. The clamped

gate output voltage is 16.5V.

7

8

GATE

VCC

Power supply. Driver and control circuit supply voltage.

FAN6961 • Rev. 1.0.2

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3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltage, are

given with respect to GND pin.

Symbol

V_VCC

Parameter

Min.

Max.

30

Unit

V

DC Supply Voltage

Gate Driver

V_HIGH

V_LOW

-0.3

30.0

7.0

V

Others (INV, COMP, MOT, CS)

Input Voltage to ZCD Pin

V

V_ZCD

12.0

400

V

SOP

DIP

P_D

T_J

Power Dissipation

mW

°C

800

Operating Junction Temperature

Thermal Resistance (Junction-to-Air)

Storage Temperature Range

-40

-65

+125

150

SOP

DIP

θ_JA

T_STG

T_L

°C/W

°C

113

+150

+230

+260

2.5

SOP

DIP

Lead Temperature (Wave Soldering or IR, 10 Seconds)

°C

Human Body Model: JESD22-A114

Machine Model: JESD22-A115

KV

V

ESD

200

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Min.

Typ.

Max.

Unit

T_A

Operating Ambient Temperature

-40

+125

°C

FAN6961 • Rev. 1.0.2

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4

Electrical Characteristics

V_CC=15V and T_A=25°C unless otherwise noted.

Symbol

Parameter

Conditions

Min. Typ. Max. Units

V_CCSection

V_CC-OPContinuous Operation Voltage

V_CC-ONTurn-on Threshold Voltage

V_CC-OFFTurn-off Threshold Voltage

24.5

13

V

11

12

9.5

10

8.5

10.5

20

V

I_CC-ST

I_CC-OP

Start-up Current

V_CC=V_CC-ON– 0.16V

µA

V_CC=12V, V_CS=0V,

C_L=3nF, f_SW=60KHz

Operating Supply Current

4.5

6

mA

V_CC-OVPV_DDOver-Voltage Protection Level

t_D-VCCOVPV_DDOver-Voltage Protection Debounce

Error Amplifier Section

26.5

27.5

30

28.5

V

µs

V_REF

Gm

Reference Voltage

2.475 2.500 2.525

125

V

μmho

V

Transconductance

V_INVH

V_INVL

Clamp High Feedback Voltage

Clamp Low Feedback Voltage

2.65

2.30

2.70

2.25

4.8

V

V_{OUT HIGH}Output High Voltage

V

V_OZ

Zero Duty Cycle Output Voltage

1.15

2.70

0.40

10

1.25

2.75

0.45

20

1.35

2.80

0.50

V

V_INV-OVPOver Voltage Protection for INV Input

V_INV-UVPUnder Voltage Protection for INV Input

V

V_INV=2.35V, V_COMP=1.5V

V_INV=1.5V,

Source Current

I_COMP

μA

550

10

800

20

Sink Current

V_INV=2.65V, V_COMP=5V

Current-Sense Section

Threshold Voltage for Peak Current Limit

Cycle-by-Cycle Limit

V_PK

0.77

0.82

0.87

V

t_PD

Propagation Delay

200

500

ns

R_MOT=24kΩ, V_COMP=5V

R_MOT=24kΩ,

400

270

t_LEB

Leading-Edge Blanking Time

ns

350

V_COMP=V_OZ+50mV

Gate Section

V_Z-_OUTOutput Voltage Maximum (Clamp)

V_CC=25V

15.0

8

16.5

18.0

1.4

V

V_OL

V_OH

Output Voltage Low

Output Voltage High

V_CC=15V, I_O=100mA

V_CC=14V, I_O=100mA

V

_CC=12V, C_L=3nF,

t_R

t_F

Rising Time

Falling Time

80

40

ns

20~80%

V_CC=12V, C_L=3nF,

80~20%

Continued on the following page…

FAN6961 • Rev. 1.0.2

www.fairchildsemi.com

5

Electrical Characteristics

V_CC=15V and T_A=25°C unless otherwise noted.

Symbol

Parameter

Conditions

Min. Typ. Max. Units

Zero Current Detection Section

V_ZCD

Input Threshold Voltage Rising Edge

Threshold Voltage Hysteresis

V_ZCDIncreasing

1.9

2.1

2.3

12

V

H_YSof

V_ZCD

V_ZCDDecreasing

0.35

V_ZCD-HIGHUpper Clamp Voltage

V_ZCD-LOWLower Clamp Voltage

I_ZCD=3mA

V

I_ZCD=-1.5mA

V_COMP=5V,

0.3

t_DEAD

Maximum Delay, ZCD to Output Turn-On

100

400

700

ns

f

_SW=60KHz

Output Turned Off by

ZCD

t_RESTARTRestart Time

300

500

μs

Inhibit Time (Maximum Switching

Frequency Limit)

t_INHIB

V_DIS

R_MOT=24kΩ

2.8

μs

mV

μs

Disable Threshold Voltage

150

800

200

250

R_MOT=24kΩ,

t_ZCD-DISDisable Function Debounce Time

V_ZCD=100mV

Maximum On Time Section

V_MOT

Maximum On Time Voltage

1.25

1.30

25

1.35

V

Maximum On Time Programming

(Resistor Based)

R_MOT=24kΩ, V_CS=0V,

t_ON-MAX

μs

V_COMP=5V

FAN6961 • Rev. 1.0.2

www.fairchildsemi.com

6

Typical Performance Characteristics

2.525

2.515

2.505

2.495

2.485

2.475

3.0

2.4

1.8

1.2

0.6

0.0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (℃)

Figure 5. V_REFvs. T_A

Figure 6. I_CC-OPvs. T_A

24.60

24.52

24.44

24.36

24.28

24.20

14.0

13.4

12.8

12.2

11.6

11.0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (℃)

Figure 7. t_ON-MAXvs. T_A

Figure 8. V_th-ONvs. T_A

10.5

10.1

9.7

16.0

13.6

11.2

8.8

9.3

8.9

6.4

8.5

4.0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (℃)

Figure 9. V_th-OFFvs. T_A

Figure 10. I_CC-STvs. T_A

FAN6961 • Rev. 1.0.2

www.fairchildsemi.com

7

Typical Performance Characteristics (Continued)

1.350

1.330

1.310

1.290

1.270

1.250

18.0

17.4

16.8

16.2

15.6

15.0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (℃)

Figure 11. V_MOTvs. T_A

Figure 12. V_Z-OUTvs. T_A

0.87

0.85

0.83

0.81

0.79

0.77

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (℃)

Figure 13. V_PKvs. T_A

FAN6961 • Rev. 1.0.2

www.fairchildsemi.com

8

Functional Description

Error Amplifier

Leading-Edge Blanking (LEB)

A turn-on spike on CS pin appears when the power

MOSFET is switched on. At the beginning of each

switching pulse, the current-limit comparator is disabled

for around 400ns to avoid premature termination. The

gate drive output cannot be switched off during the

blanking period. Conventional RC filtering is not

necessary, so the propagation delay of current limit

protection can be minimized.

The inverting input of the error amplifier is referenced to

INV. The output of the error amplifier is referenced to

COMP. The non-inverting input is internally connected

to a fixed 2.5V ± 2% voltage. The output of the error

amplifier is used to determine the on-time of the PWM

output and regulate the output voltage. To achieve a

low input current THD, the variation of the on time

within one input AC cycle should be very small. A multi-

vector error amplifier is built in to provide fast transient

response and precise output voltage clamping.

Under-Voltage Lockout (UVLO)

The turn-on and turn-off threshold voltage is fixed

internally at 12V/9.5V. This hysteresis behavior

guarantees a one-shot start-up with proper start-up

resistor and hold-up capacitor. With an ultra-low start-

up current of 20µA, one 1MΩ R_INis sufficient for start-

For FAN6961, connecting a capacitance, such as 1µF,

between COMP and GND is suggested. The error

amplifier is a trans-conductance amplifier that converts

voltage to current with a 125µmho.

up under low input line voltage, 85V_rms

dissipation on R_INwould be less than 0.1W even under

high line (V_AC=265V_rms) condition.

. Power

Startup Current

Typical startup current is less than 20µA. This ultra-low

startup current allows the usage of high resistance,

low-wattage start-up resistor. For example, 1MΩ/0.25W

startup resistor and a 10µF/25V (V_CChold-up) capacitor

are recommended for an AC-to-DC power adaptor with

Output Driver

With low on resistance and high current driving

capability, the output driver can drive an external

capacitive load larger than 3000pF. Cross conduction

current has been avoided to minimize heat dissipation,

improving efficiency and reliability. This output driver is

internally clamped by a 16.5V Zener diode.

a wide input range 85-265V_AC

.

Operating Current

Operating current is typically 4.5mA. The low operating

current enables a better efficiency and reduces the

requirement of V_CChold-up capacitance.

Zero-Current Detection (ZCD)

The zero-current detection of the inductor is achieved

using its auxiliary winding. When the stored energy of

the inductor is fully released to output, the voltage on

ZCD goes down and a new switching cycle is enabled

after a ZCD trigger. The power MOSFET is always

turned on with zero inductor current such that turn-on

loss and noise can be minimized. The converter works

in boundary mode and peak inductor current is always

exactly twice of the average current. A natural power

factor correction function is achieved with the low-

bandwidth, on-time modulation. An inherent maximum

off time is built in to ensure proper start-up operation.

This ZCD pin can be used as a synchronous input.

Maximum On-Time Operation

Given a fixed inductor value and maximum output

power, the relationship between on-time and line

voltage is:

2 • L • P_o

t_on

=

(1)

2

V_rms•η

If the line voltage is too low or the inductor value is too

high, t_ONis too long. To avoid extra low operating

frequency and achieve brownout protection, the

maximum value of t_ONis programmable by one resistor,

R_I, connected between MOT and GND. A 24kΩ resistor

R_Igenerates corresponds to 25µs maximum on time:

Noise Immunity

25

Noise on the current sense or control signal can cause

significant pulse-width jitter, particularly in the

boundary-mode operation. Slope compensation and

built-in debounce circuit can alleviate this problem.

Because the FAN6961 has a single ground pin, high

sink current at the output cannot be returned

separately. Good high-frequency or RF layout practices

should be followed. Avoiding long PCB traces and

component leads, locating compensation and filter

components near to the FAN6961, and increasing the

power MOSFET gate resistance improve performance.

t_on(max)= R_I(kΩ) •

(μs

)

(2)

24

The range of the maximum on-time is designed as 10 ~

50µs.

Peak Current Limiting

The switch current is sensed by one resistor. The

signal is feed into CS pin and an input terminal of a

comparator. A high voltage in CS pin terminates a

switching cycle immediately and cycle-by-cycle current

limit is achieved. The designed threshold of the

protection point is 0.82V.

FAN6961 • Rev. 1.0.2

www.fairchildsemi.com

9

Reference Circuit

Figure 14. Reference Circuit

FAN6961 • Rev. 1.0.2

www.fairchildsemi.com

10

Physical Dimensions

9.83

9.00

6.67

6.096

8.255

7.61

3.683

3.20

7.62

5.08 MAX

0.33 MIN

3.60

3.00

(0.56)

2.54

0.356

0.20

0.56

0.355

9.957

7.87

1.65

1.27

7.62

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BA

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS.

D) DIMENSIONS AND TOLERANC

ASME Y14.5M-1994

ES PER

E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.

Figure 15. 8-Lead, PDIP, JEDEC MS-001, .300 Inch Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN6961 • Rev. 1.0.2

www.fairchildsemi.com

11

Physical Dimensions (Continued)

5.00

4.80

A

0.65

3.81

8

5

B

1.75

6.20

5.80

4.00

3.80

5.60

1

4

PIN ONE

INDICATOR

1.27

(0.33)

M

0.25

C B A

LAND PATTERN RECOMMENDATION

SEE DETAIL A

0.25

0.10

0.25

0.19

C

1.75 MAX

0.10

C

0.51

0.33

OPTION A - BEVEL EDGE

0.50

0.25

x 45°

R0.10

GAGE PLANE

OPTION B - NO BEVEL EDGE

0.36

NOTES: UNLESS OTHERWISE SPECIFIED

8°

0°

0.90

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

SEATING PLANE

(1.04)

0.406

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

DETAIL A

SCALE: 2:1

Figure 16. 8-Lead, SOIC,JEDEC MS-012, .150 Inch Narrow Body

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN6961 • Rev. 1.0.2

www.fairchildsemi.com

12

FAN6961 • Rev. 1.0.2

www.fairchildsemi.com

13


型号：	FAN6961SY
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Boundary Mode PFC Controller 边界模式PFC控制器功率因数校正控制器
文件：	总13页 (文件大小：657K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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