FAN6982MY_技术文档

February 2010

FAN6982

CCM Power Factor Correction Controller

Features

Description

The FAN6982 is a 14-pin, Continuous Conduction Mode

(CCM) PFC controller IC intended for Power Factor

Correction (PFC) pre-regulators. The FAN6982 includes

circuits for the implementation of leading edge, average

current, “boost”-type power factor correction, and

results in a power supply that fully complies with the

IEC1000-3-2 specification.

Continuous Conduction Mode

Innovative Switching-Charge Multiplier-Divider

Average-Current-Mode for Input-Current Shaping

TriFault Detect™ Prevent Abnormal Operation for

Feedback Loop

Power-On Sequence Control

A TriFault Detect™ function helps reduce external

components and provides full protection for feedback

loops such as open, short, and over voltage. An over-

voltage comparator shuts down the PFC stage in the

event of a sudden load decrease. The RDY signal can

be used for power-on sequence control. The EN

function can choose to enable or disable the range

function. FAN6982 also includes PFC soft-start, peak

current limiting, and input voltage brownout protection.

Soft-Start Capability

Brownout Protection

Cycle-by-Cycle Peak Current Limiting.

Improves Light-Load Efficiency

Fulfills Class-D Requirements of IEC 1000-3-2

Programmable Frequency: 50kHz to 130kHz

Wide Range Universal AC Input Voltage

Maximum Duty Cycle 97%

V_DDUnder-Voltage Lockout (UVLO)

Applications

Desktop PC Power Supply

Internet Server Power Supply

LCD TV/Monitor Power Supply

DC Motor Power Supply

Ordering Information

Operating

Temperature Range

Packing

Part Number

Package

Method

Eco Status

FAN6982MY

-40°C to +105°C

Green

14-Pin Small Outline Package (SOP)

Tape & Reel

For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

FAN6982 • Rev. 1.0.1

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Application Diagram

Figure 1. Typical Application

FAN6982 • Rev. 1.0.1

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2

Block Diagram

14

1

11

VDD

VREF

IEA

VEA

0.5V

7.5V

REFERENCE

12

PFC UVP

PFC OVP

Low-Power

Detect Comparator

2.75V/2.5V

SET

CLR

S

R

Q

V_DD

FBPFC

EN

2.5V

0.3V

28V/27V

V_DDOVP

13

6

R_M

Gm_I

-1.15V

I_SENSE

Gm_V

OPFC

PFC ILIMIT

V_INUVP

10

Range

1.05V/1.9V

V_RMS

SET

CLR

VRMS

IAC

S

R

Q

k

x²

PGND

4

2

V_EA

9

I_MO

R_M

Gain Modulator

2.8V

3

7

ISENSE

RT/CT

RDY

UVLO

V_DD

5

FBPFC

2.4V/1.15V

OSCILLATOR

SGND

8

Figure 2. Functional Block Diagram

Marking Information

F – Fairchild Logo

Z – Plant Code

X – 1-Digit Year Code

Y – 1-Digit Week Code

TT – 2-Digit Die-Run Code

T – Package Type (M: SOP)

P – Y: Green Package

M – Manufacture Flow Code

Figure 3. Top Mark

FAN6982 • Rev. 1.0.1

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3

Pin Configuration

Figure 4. Pin Configuration

Pin Definitions

Pin #

Name

Description

Output of Current Amplifier. This is the output of the PFC current amplifier. The signal from

this pin is compared with sawtooth and determines the pulsewidth for PFC gate drive.

1

IEA

Input AC Current. For normal operation, this input is used to provide current reference for the

multiplier. The suggested maximum I_ACis 100µA.

2

IAC

Current Sense. The non-inverting input of the PFC current amplifier and the output of

multiplier and PFC I_LIMITcomparator.

3

4

ISENSE

VRMS

Line-Voltage Detection. The pin is used for PFC multiplier.

Ready Signal. This pin controls the power-on sequence. Once the FAN6982 is turned on and

the FBPFC voltage exceeds in 2.4V, the RDY pin pulls LOW impedance. If the FBPFC voltage

is lower than 1.15V, the RDY pin pulls HIGH impedance.

5

6

RDY

EN

Enable Range Function. The range function is enabled when EN is connected to V_REF. The

range function is disabled when EN is connected to GND.

7

8

9

RT/CT

SGND

PGND

Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT.

Signal Ground.

Power Ground.

Gate Drive. The totem-pole output drive for PFC MOSFET. This pin is internally clamped

under 15V to protect the MOSFET.

10

OPFC

Power Supply. The threshold voltages for startup and turn-off are 11V and 9.3V, respectively.

The operating current is lower than 10mA.

11

12

13

VDD

VREF

FBPFC

Reference Voltage. Buffered output for the internal 7.5V reference.

Voltage Feedback Input. The feedback input for PFC voltage loop. The inverting input of PFC

error amplifier. This pin is connected to the PFC output through a divider network.

Output of Voltage Amplifier. The error-amplifier output for PFC voltage feedback loop. A

compensation network is connected between this pin and ground.

14

VEA

FAN6982 • Rev. 1.0.1

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4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol

V_DD

Parameter

Min.

Max.

30

Unit

V

DC Supply Voltage

V_H

OPFC, RDY, EN, VREF

-0.3

0

30.0

7.0

V

V_L

IAC, VRMS, RT/CT, FBPFC, VEA

IEA

V

V_IEA

V_N

V_VREF+0.3

0.7

V

ISENSE

-5.0

V

I_AC

Input AC Current

1

mA

A

I_REF

VREF Output Current

5

I_PFC-OUT

P_D

Peak PFC OUT Current, Source or Sink

Power Dissipation, T_A< 50°C

Thermal Resistance (Junction-to-Air)

0.5

800

mW

°C/W

R_{Θ j-a}

104.10

R_{Θ j-c}

T_J

Thermal Resistance (Junction-to-Case)

Operating Junction Temperature

Storage Temperature Range

40.61

+125

+150

+260

°C/W

°C

-40

-55

T_STG

T_L

°C

Lead Temperature (Soldering)

°C

Human Body Model,

JESD22-A114

4.5

1.0

ESD

Electrostatic Discharge Capability

kV

Charged Device Model,

JESD22-C101

Notes:

1. All voltage values, except differential voltage, are given with respect to the GND pin.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Operating Ambient Temperature

Min.

Max.

Unit

T_A

-40

+105

°C

FAN6982 • Rev. 1.0.1

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5

Electrical Characteristics

Unless otherwise noted; V_DD=15V, T_A= 25°C, T_A=T_J, R_T=27kΩ, and C_T=1000pF.

Symbol

Parameter

Conditions

Min. Typ. Max. Units

V_DDSection

Continuously Operating

Voltage

V_DD-OP

22

V

I_{DD ST}

I_DD-OP

Startup Current

V_DD=V_TH-ON-0.1V; OPFC Open

V_DD=13V; OPFC Open

30

2.3

11

80

3.0

12

µA

mA

V

Operating Current

Turn-on Threshold Voltage

Hysteresis

2.0

10

V_TH-ON

1.35

1.90

V

△V_TH

V_DD-OVP

△V_DD-OVP

V_DDOVP

27

60

58

28

1

29

V

V_DDOVP Hysteresis

Oscillator

f_OSC

PFC Frequency

R_T=27kΩ, C_T=1000pF

11V ≦V_DD≦22V

-40°C ~ +105°C

64

67

kHz

(3)

f_DV

Voltage Stability

Temperature Stability

Total Variation

2

%

(3)

f_DT

f_TV

f_RV

Line, Temperature

Valley-to-Peak

70

kHz

V

Ramp Voltage

2.8

I_OSC-DIS

f_RANGE

t_PFC-DEAD

V_REF

Discharge Current

Frequency Range

PFC Dead Time

V_RAMP=0V, V_RT/CT=2.5V

6.5

50

15.0

75

mA

kHz

ns

R_T=27kΩ, C_T=1000pF

400

600

800

V_VREF

Reference Voltage

I_REF=0mA, C_REF=0.1µF

7.4

7.5

30

7.6

50

V

Load Regulation of

Reference Voltage

C_REF=0.1µF, I_REF=0mA to 3.5mA

△V_VREF1

△V_VREF2

mV

V_VDD=14V, Rise/Fall Time > 20µs

Line Regulation of Reference

Voltage

C_REF=0.1µF, V_VDD=11V to 22V

25

mV

Temperature Stability⁽³⁾

Total Variation⁽³⁾

Long-Term Stability⁽³⁾

-40°C ~ +105°C

0.4

0.5

7.65

25

%

V

△V_VREF-DT

△V_VREF-TV

Line, Load, Temperature

T_J=125°C, 0 ~ 1000HRs

V_VREF> 7.35V

7.35

5

△V_VREF-LS

I_REF-MAX

mV

mA

Maximum Current

5

Brownout

V_RMS-UVL

V_RMSThreshold Low

V_RMSThreshold High

Hysteresis

When V_RMS=1.05V at 75 V_RMS

When V_RMS=1.9V at 85 • 1.414

1.00

1.85

750

1.05

1.90

850

1.10

1.95

950

V

V_RMS-UVH

△V_RMS-UVP

mV

Under-Voltage Protection

Debounce Time

t_UVP

340

410

480

ms

RDY Section

FBPFC Voltage Level to Pull

Low Impedance with RDY Pin

V_FBPFC-RD

2.3

2.4

2.5

V

△V_FBPFC-RD

I_RDY-LEK

Hysteresis

1.15

1.25

1.35

500

0.5

V

nA

V

Leakage Current of RDY

High Impedance

V_FBPFC<2.4V

I_SINK=2mA

V_RDY-L

RDY Low Voltage

Continued on the following page…

FAN6982 • Rev. 1.0.1

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6

Electrical Characteristics (Continued)

Unless otherwise noted; V_DD=15V, T_A= 25°C, T_A=T_J, R_T=27kΩ, and C_T=1000pF.

Symbol

Parameter

Conditions

Min. Typ. Max. Units

Voltage Error Amplifier

V_REF

A_V

Reference Voltage

Open-Loop Gain⁽³⁾

2.45 2.50

2.55

90

V

dB

µmho

µA

V

At T_A=25°C

35

50

40

42

70

Gm_V

Transconductance

V_NONINV=V_INV, V_VEA=3.75V at T_A=25°C

V_FBPFC=2V, V_VEA=1.5V

I_FBPFC-L

I_FBPFC-H

I_BS

Maximum Source Current

Maximum Sink Current

Input Bias Current

50

V_FBPFC=3V, V_VEA=6V

-50

-40

1

-1

V_VEA-H

V_VEA-L

Output High Voltage on V_VEA

Output Low Voltage on V_VEA

5.8

6.0

0.1

0.4

0.7

V

Current Error Amplifier

V_ISENSEInput Voltage Range

A_I

-1.5

40

V

dB

µmho

mV

V

Open-Loop Gain⁽³⁾

Transconductance

Input Offset Voltage

Output High Voltage

Output Low Voltage

Source Current

At T_A=25°C

50

88

Gm_I

V_OFFSET

V_IEA-H

V_IEA-L

I_L

V_NONINV=V_INV, V_IEA=3.75V

V_VEA=0V, I_ACOpen

75

100

10

-10

6.8

7.4

0.1

50

8.0

0.4

V

V_ISENSE= -0.6V, V_IEA=1.5V

V_ISENSE= +0.6V, V_IEA=4.0V

35

µA

I_H

Sink Current

-50

-35

PFC OVP Comparator

V_FBPFC-OVPOver Voltage Protection

2.70 2.75

2.80

300

V

△V_FBPFC-OVP

PFC OVP Hysteresis

Low-Power Detect Comparator

V_VEA-OFFVEA Voltage Off OPFC

200

0.2

2.2

7.4

250

0.3

2.8

mV

0.4

3.3

7.6

V

PFC Soft-Start

V_{VEA_CLAMP}PFC Soft-Start

EN Section

V_FBPFC< 2.4V

V_EN-H

V_EN-L

High Voltage Level of V_EN

V_EN=V_VREF

V_EN=GND

7.5

0

V

Low Voltage Level of V_EN

Range

V_VRMS-L

V_VRMS-H

V_VEA-L

V_VEA-H

I_TC

RMS AC Voltage Low

RMS AC Voltage High

VEA Low

When V_VRMS=1.95V at 132V_RMS

When V_VRMS=2.45V at 150 V_RMS

When V_VEA=1.95V at 30% Loading

When V_VEA=2.45V at 40% Loading

1.90 1.95 20.00

V

2.40 2.45

1.90 1.95

2.40 2.45

2.50

2.00

2.50

22

V

VEA High

V

Source Current from FBPFC

18

20

µA

Continued on the following page…

FAN6982 • Rev. 1.0.1

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7

Electrical Characteristics (Continued)

Unless otherwise noted; V_DD=15V, T_A= 25°C, T_A=T_J, R_T=27kΩ, and C_T=1000pF.

Symbol

Parameter

Conditions

Min.

Typ.

Max. Units

Gain Modulator

I_AC

Input for AC Current

Gain Modulator⁽³⁾⁽⁴⁾

Multiplier Linear Range

0

100

µA

I

V

_IAC=17.67µA, V_VRMS=1.080V

_FBPFC=2.25V, at T_A=25°C

7.500 9.000 10.500

I_IAC=20µA, V_VRMS=1.224V

_FBPFC=2.25V, at T_A=25°C

6.367 7.004

3.801 4.182

0.950 1.045

7.704

4.600

1.149

0.798

V

I_IAC=25.69µA, V_VRMS=1.585V

_FBPFC=2.25V, at T_A=25°C

GAIN

V

I_IAC=51.62µA, V_VRMS=3.169V

_FBPFC=2.25V, at T_A=25°C

V

I_IAC=62.23µA, V_VRMS=3.803V

_FBPFC=2.25V, at T_A=25°C

0.660 0.726

2

V

BW

Bandwidth

I_IAC=40µA

kHz

V

Output Voltage=5.7kΩ ×

I_AC=20µA, V_RMS=1.224V

V_FBPFC=2.25V, at T_A=25°C

V_O(GM)

0.710 0.798

0.885

(I_SENSE-I_OFFSET

)

PFC I_LIMITComparator

Peak Current Limit

V_PFC-ILIMITThreshold Voltage

Cycle-by-Cycle Limit

-1.25

200

-1.15 -1.05

V

PFC I_LIMIT-Gain Modulator

I_IAC=17.67µA, V_VRMS=1.08V

_FBPFC=2.25V, at T_A=25°C

△V_pk

mV

Output

V

PFC Output Driver

Gate Output Clamping

V_GATE-CLAMP

Voltage

V_DD=22V

13

15

70

17

V

V_GATE-L

V_GATE-H

Gate Low Voltage

Gate High Voltage

V_DD=15V; I_O=100mA

V_DD=13V; I_O=100mA

1.5

V

8

V_DD=15V; C_L=4.7nF;

O/P= 2V to 9V

t_R

t_F

Gate Rising Time

Gate Falling Time

40

120

110

ns

V_DD=15V; C_L=4.7nF;

40

94

60

97

O/P= 9V to 2V

D_PFC-MAX

D_PFC-MIN

Maximum Duty Cycle

Minimum Duty Cycle

V_IEA<1.2V

%

V_IEA>4.5V

0

Tri-Fault Detect

V_FBPFC=V_FBPFC-OVPto FBPFC

OPEN, 470pF from FBPFC to GND

t_{FBPFC_OPEN}Time to FBPFC Open

2

4

ms

V

PFC Feedback Under-

V_PFC-UVP

0.4

0.5

0.6

Voltage Protection

Notes:

3. This parameter, although guaranteed by design, is not 100% production tested.

4. This gain is the maximum gain of modulation with a given V_RMSvoltage when V_EAis saturated to high.

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FAN6982 • Rev. 1.0.1

8

Typical Performance Characteristics

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

29.0

28.8

28.6

28.4

28.2

28.0

27.8

27.6

27.4

27.2

27.0

-40

-25

-10

5

20

35

50

65

80

95

110

125

12 5

125

-40

-25

-10

5

20

35

50

65

80

95

110

125

Figure 5. I_DD-OPvs. Temperature

Figure 6. V_DD-OVPvs. Temperature

74

72

70

68

66

64

62

60

7.65

7.60

7.55

7.50

7.45

7.40

7.35

-40

-25

-10

5

20

35

50

65

80

95

110

-40

-25

-10

5

20

35

50

65

80

95

110

125

Figure 7. f_OSCvs. Temperature

Figure 8. V_VREFvs. Temperature

1.10

1.08

1.06

1.04

1.02

1.00

1.95

1.93

1.91

1.89

1.87

1.85

-40

-25

-10

5

20

35

50

65

80

95

110

125

-40

-25

-10

5

20

35

50

65

80

95

110

Figure 9. V_RMS-UVLvs. Temperature

Figure 10. V_RMS-UVHvs. Temperature

2.50

2.45

2.40

2.35

2.30

500

450

400

350

300

250

200

150

100

50

0

-40

-25

-10

5

20

35

50

65

80

95

110

125

-40

-25

-10

5

20

35

50

65

80

95

110

Figure 11. V_FBPFC-RDvs. Temperature

Figure 12. I_RDY-LEKvs. Temperature

FAN6982 • Rev. 1.0.1

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Typical Performance Characteristics (Continued)

2.60

2.58

2.56

2.54

2.52

2.50

2.48

2.46

2.44

2.42

2.40

90

85

80

75

70

65

60

55

50

-40

-25

-10

5

20

35

50

65

80

95

110

125

-40

-25

-10

5

20

35

50

65

80

95

110

125

Figure 13. V_REFvs. Temperature

Figure 14. Gm_Vvs. Temperature

10

8

120

6

110

100

90

4

2

0

-2

-4

-6

-8

-10

80

70

60

50

-40

-25

-10

5

20

35

50

65

80

95

110

125

-40

-25

-10

5

20

35

50

65

80

95

110

125

Figure 15. V_OFFSETvs. Temperature

Figure 16. Gm_Ivs. Temperature

2.80

2.79

2.78

2.77

2.76

2.75

2.74

2.73

2.72

2.71

2.70

22 .0

21 .5

21 .0

20 .5

20 .0

19 .5

19 .0

18 .5

18 .0

-40

-25

-10

5

20

35

50

65

80

95

110

125

-40

-25

-10

5

20

35

50

65

80

95

110

125

Figure 17. V_FBPFC-OVPvs. Temperature

Figure 18. I_TCvs. Temperature

-1.05

-1.07

-1.09

-1.11

-1.13

-1.15

-1.17

-1.19

-1.21

-1.23

-1.25

0.87

0.85

0.83

0.81

0.79

0.77

0.75

0.73

0.71

-40

-25

-10

5

20

35

50

65

80

95

110

125

-40

-25

-10

5

20

35

50

65

80

95

110

125

Figure 19. V_O(GM)vs. Temperature

Figure 20. V_PFC-ILIMITvs. Temperature

FAN6982 • Rev. 1.0.1

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10

Typical Performance Characteristics (Continued)

17

16

15

14

13

0.60

0.55

0.50

0.45

0.40

-40

-25

-10

5

20

35

50

65

80

95

110

125

-40

-25

-10

5

20

35

50

65

80

95

110

125

Figure 21. V_GATE-CLAMPvs. Temperature

Figure 22. V_PFC-UVPvs. Temperature

FAN6982 • Rev. 1.0.1

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Functional Description

Oscillator

The internal oscillator frequency of FAN6982 is

determined by the timing resistor and capacitor on the

RT/CT pin. The frequency of the internal oscillator is

given by:

1

G ∝

2

V_RMS

1

f_OSC

=

(1

)

0.56⋅ R_T⋅C_T+ 360C_T

The dead time for the PFC gate drive signal is

determined by

V_RMS

t_DEAD= 360C_T

(2

)

V_RMS-UVP

The dead time should be smaller than 2% of switching

period to minimize line current distortion around line

zero crossing.

Figure 24. Modulation Gain Characteristics

V_IN

Gain Modulator

Gain modulator is the key block for PFC stage because

it provides the reference to the current control error

amplifier for the input current shaping, as shown in

Figure 23. The output current of gain modulator is a

function of V_EA, I_ACand V_RMS. The gain of the gain

modulator is given as a ratio between I_MOand I_ACwith a

given V_RMSwhen V_EAis saturated to high. The gain is

inversely proportional to V_RMS², as shown in Figure 24,

to implement line feed-forward. This automatically

adjusts the reference of current control error amplifier

according to the line voltage such that the input power

of PFC converter is not changed with line voltage, as

shown in, Figure 25.

V_EA

I_L

Figure 25. Line Feed-Forward Operation

To sense the RMS value of the line voltage, an

averaging circuit with two poles is typically employed as

shown in Figure 23. Notice that the input voltage of

PFC is clamped at the peak of the line voltage once

PFC stops switching since the junction capacitance of

bridge diode is not discharged, as shown in Figure 26.

Therefore, the voltage divider for V_RMSshould be

designed considering the brownout protection trip point

and minimum operation line voltage.

I_MO= G ⋅I_AC

K ⋅(V_EA− 0.6)

= I_AC

⋅

PFC stops

V_RMS²(V_EA

− 0.6)

MAX

PFC runs

V_IN

Figure 23. Gain Modulator Block

V_RMS

Figure 26. V_RMSAccording to the PFC Operation

FAN6982 • Rev. 1.0.1

www.fairchildsemi.com

12

The rectified sinusoidal signal is obtained by the current

flowing into the IAC pin. The resistor R_IACshould be

large enough to prevent saturation of the gain

modulator as:

The current-control feedback loop also has a pulse-by-

pulse current limit comparator that forces the PFC

switch to turn off if the ISENSE pin voltage drops below

-1.15V until the next switching cycle.

2V_LINE.BO

⋅G^MAX<159μA

(3)

Voltage-Control of Boost Stage

The voltage-control loop regulates PFC output voltage

using internal error amplifier such that the FBPFC

voltage is same as internal reference of 2.5V.

R_IAC

where V_LINE.BOis the line voltage that trips brownout

protection, G^MAXis the maximum modulator gain when

V_RMSis 1.08V, and 159µA is the maximum output

current of the gain modulator.

To improve system efficiency at low AC line voltage

and light-load condition, FAN6982 provides adjustable

PFC output voltage. As shown in Figure 29, FAN6982

monitors V_EAand V_RMSto adjust the PFC output

voltage. When V_EAand V_RMSare lower than thresholds,

internal current source of 20µA is enabled that flows

through R_FB2, increasing the voltage of the FBPFC pin.

This causes the PFC output voltage to reduce when

20µA is enabled as:

Current-Control of Boost Stage

As shown in Figure 27 the FAN6982 employs two

control loops for power factor correction, a current-

control loop and a voltage-control loop. The current-

control loop shapes inductor current, as shown in

Figure 28, based on the reference signal obtained at

IAC pin as:

R_FB1+ R

V_{OPFC 2}

=

^FB2×(2.5- 20μA× R_FB2

)

(5)

R_FB2

I_L⋅ R_CS1= I_MO⋅ R_M= I_AC⋅G ⋅ R_M

(4)

Figure 29. Block of Adjustable PFC Output

Brownout Protection

FAN6982 has a built-in internal brownout protection

comparator monitoring the voltage of the VRMS pin.

Once the VRMS pin voltage is lower than 1.05V, the

PFC stage is shutdown to protect the system from over

current. FAN6982 starts up the boost stage once the

VRMS voltage increases above 1.9V.

TriFault Detect™

Figure 27. Gain Modulation Block

To improve power supply reliability, reduce system

component count, and simplify compliance to UL 1950

safety standards; the FAN6982 includes TriFault Detect

technology. This feature monitors FBPFC for certain

PFC fault conditions.

I_AC

R_M

I_MO

In the case of a feedback path failure, the output of the

PFC could exceed operating limits. Should FBPFC go

too low, or too high, or open; TriFault Detect senses the

error and terminates the PFC output drive.

R_CS1

I_L

TriFault detect is an entirely internal circuit. It requires

no external components to serve its protective function.

Figure 28. Inductor Current Shaping

FAN6982 • Rev. 1.0.1

www.fairchildsemi.com

13

PFC Soft-Start Function

RDY Function

The FAN6982 PFC soft-start function is shown in

Figure 30. When bulk voltage is under the 96% of

setting voltage; V_EAclamps to 2.8V, the output current

of multiplier cuts half, the rectifier line current is limited

by current loop, and PFC output rise time increases.

The FAN6982 RDY function, is shown in Figure 31, is

controlled by voltage of FBPFC. If the voltage of

FBPFC is over than 96% of 2.5V, the RDY pin is

connected to SGND. If the FBPFC is under the 46% of

2.5V, the RDY appears open-drain situation. Usually

the capacitor is parallel with the RDY pin to prevent the

layout noise.

When bulk voltage is over 96%, the clamping function

is disabled, and the bulk voltage can be regulated by

voltage error amplifier.

The PNP transistor can control the AHB LLC or dual-

forward controller on the same side or the “op-to” to

control the LLC controller on the other side.

There have two advantages with PFC soft-start: one is

the MOSFET experience of current is reduced, which

can obtain more de-rating with MOSFET current level.

The other one is to reduce the overshoot of PFC bulk

voltage at the rising time because the charge current

becomes small, the bulk voltage can not exceed to

setting voltage easily.

Figure 31. RDY Application Circuit

Figure 30. PFC Soft-Start

FAN6982 • Rev. 1.0.1

www.fairchildsemi.com

14

Physical Dimensions

Figure 32. 14-Pin Small Outline Package (SOIC)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN6982 • Rev. 1.0.1

www.fairchildsemi.com

15

FAN6982 • Rev. 1.0.1

www.fairchildsemi.com

16


型号：	FAN6982MY
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	CCM Power Factor Correction Controller CCM功率因数校正控制器功率因数校正控制器
文件：	总16页 (文件大小：560K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN6982MY [FAIRCHILD]

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