DM74LS109A [FAIRCHILD]

Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs; 双上升沿触发JK触发器与预置,清晰,互补输出
DM74LS109A
型号: DM74LS109A
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs
双上升沿触发JK触发器与预置,清晰,互补输出

触发器
文件: 总5页 (文件大小:55K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
June 1986  
Revised March 2000  
DM74LS109A  
Dual Positive-Edge-Triggered J-K Flip-Flop with  
Preset, Clear, and Complementary Outputs  
General Description  
This device contains two independent positive-edge-trig-  
gered J-K flip-flops with complementary outputs. The J and  
K data is accepted by the flip-flop on the rising edge of the  
clock pulse. The triggering occurs at a voltage level and is  
not directly related to the transition time of the rising edge  
of the clock. The data on the J and K inputs may be  
changed while the clock is HIGH or LOW as long as setup  
and hold times are not violated. A low logic level on the  
preset or clear inputs will set or reset the outputs regard-  
less of the logic levels of the other inputs.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS109AM  
DM74LS109AN  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Inputs  
Outputs  
PR  
L
CLR  
H
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
L
X
H
L
X
H (Note 1) H (Note 1)  
H
H
H
L
H
H
H
L
Toggle  
H
H
H
H
H
H
L
L
H
X
H
H
X
Q0  
H
Q0  
L
Q0  
Q0  
H = HIGH Logic Level  
L = LOW Logic Level  
X = Either LOW or HIGH Logic Level  
↑ = Rising Edge of Pulse  
Q
= The output logic level of Q before the indicated input conditions were  
0
established.  
Toggle = Each output changes to the complement of its previous level on  
each active transition of the clock pulse.  
Note 1: This configuration is nonstable; that is, it will not persist when pre-  
set and/or clear inputs return to their inactive (HIGH) state.  
© 2000 Fairchild Semiconductor Corporation  
DS006368  
www.fairchildsemi.com  
Absolute Maximum Ratings(Note 2)  
Note 2: The “Absolute Maximum Ratings” are those values beyond which  
the safety of the device cannot be guaranteed. The device should not be  
operated at these limits. The parametric values defined in the Electrical  
Characteristics tables are not guaranteed at the absolute maximum ratings.  
The “Recommended Operating Conditions” table will define the conditions  
for actual device operation.  
Supply Voltage  
Input Voltage  
7V  
7V  
Operating Free Air Temperature Range  
Storage Temperature Range  
0°C to +70°C  
65°C to +150°C  
Recommended Operating Conditions  
Symbol  
Parameter  
Min  
4.75  
2
Nom  
Max  
Units  
V
VCC  
VIH  
VIL  
Supply Voltage  
5
5.25  
HIGH Level Input Voltage  
LOW Level Input Voltage  
HIGH Level Output Current  
LOW Level Output Current  
Clock Frequency (Note 3)  
Clock Frequency (Note 4)  
Pulse Width  
V
0.8  
0.4  
8
V
IOH  
IOL  
mA  
mA  
MHz  
MHz  
fCLK  
fCLK  
tW  
0
0
25  
20  
Clock HIGH  
Preset LOW  
Clear LOW  
Clock HIGH  
Preset LOW  
Clear LOW  
Data HIGH  
Data LOW  
Data HIGH  
Data LOW  
18  
15  
15  
25  
20  
20  
30↑  
20↑  
35↑  
25↑  
0↑  
(Note 3)  
ns  
ns  
tW  
Pulse Width  
(Note 4)  
tSU  
Setup Time  
ns  
ns  
(Note 3)(Note 5)  
Setup Time  
tSU  
(Note 5)(Note 4)  
Hold Time (Note 6)  
tH  
ns  
TA  
Free Air Operating Temperature  
0
70  
°C  
Note 3: C = 15 pF, R = 2 k, T = 25°C and V = 5V.  
L
L
A
CC  
Note 4: C = 50 pF, R = 2 k, T = 25°C and V = 5V.  
L
L
A
CC  
Note 5: The symbol () indicates the rising edge of the clock pulse is used for reference.  
Note 6: T = 25°C and V = 5V.  
A
CC  
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2
Electrical Characteristics  
over recommended operating free air temperature range (unless otherwise noted)  
Typ  
Symbol  
Parameter  
Conditions  
= Min, I = −18 mA  
Min  
Max  
Units  
(Note 7)  
V
V
Input Clamp Voltage  
HIGH Level  
V
V
V
V
V
1.5  
V
V
I
CC  
CC  
I
= Min, I = Max  
OH  
OH  
2.7  
3.4  
Output Voltage  
LOW Level  
= Max, V = Min  
IH  
IL  
V
= Min, I = Max  
OL  
OL  
CC  
0.35  
0.25  
0.5  
0.4  
Output Voltage  
= Max, V = Min  
V
IL  
IH  
I
= 4 mA, V = Min  
CC  
OL  
I
I
I
Input Current @ Max  
Input Voltage  
V
V
= Max  
J, K  
0.1  
0.1  
0.2  
0.2  
I
CC  
= 7V  
Clock  
Preset  
Clear  
I
mA  
HIGH Level  
V
= Max  
J,K  
20  
20  
40  
40  
IH  
IL  
CC  
Input Current  
V = 2.7V  
Clock  
Preset  
Clear  
I
µA  
LOW Level  
V
= Max  
J, K  
0.4  
0.4  
0.8  
0.8  
100  
8
CC  
Input Current  
V = 0.4V  
Clock  
Preset  
Clear  
I
mA  
I
I
Short Circuit Output Current  
Supply Current  
V
V
= Max (Note 8)  
= Max (Note 9)  
20  
mA  
mA  
OS  
CC  
CC  
CC  
4
Note 7: All typicals are at V = 5V, T = 25°C.  
CC  
A
Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,  
where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where V = 2.125V with the minimum  
O
and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.  
Note 9: I is measured with all outputs OPEN, with CLOCK grounded after setting the Q and Q outputs HIGH in turn.  
CC  
Switching Characteristics  
at VCC = 5V and T = 25°C  
A
R
= 2 kΩ  
From (Input)  
To (Output)  
L
Symbol  
Parameter  
C
= 15 pF  
C
= 50 pF  
Units  
L
L
Min  
25  
Max  
Min  
20  
Max  
f
t
Maximum Clock Frequency  
Propagation Delay Time  
LOW-to-HIGH Level Output  
Propagation Delay Time  
HIGH-to-LOW Level Output  
Propagation Delay Time  
LOW-to-HIGH Level Output  
Propagation Delay Time  
HIGH-to-LOW Level Output  
Propagation Delay Time  
LOW-to-HIGH Level Output  
Propagation Delay Time  
HIGH-to-LOW Level Output  
MHz  
ns  
MAX  
Clock to  
Q or Q  
Clock to  
Q or Q  
Clear  
to Q  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
25  
30  
25  
30  
25  
30  
35  
35  
35  
35  
35  
35  
t
t
t
t
t
ns  
ns  
ns  
ns  
ns  
Clear  
to Q  
Preset  
to Q  
Preset  
to Q  
3
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Physical Dimensions inches (millimeters) unless otherwise noted  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
Package Number M16A  
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Package Number N16E  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
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5
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