DM74LS109AN [NSC]

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs; 双上升沿触发JK触发器与预置,清晰,互补输出
DM74LS109AN
型号: DM74LS109AN
厂家: National Semiconductor    National Semiconductor
描述:

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs
双上升沿触发JK触发器与预置,清晰,互补输出

触发器 逻辑集成电路 光电二极管
文件: 总6页 (文件大小:137K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
June 1989  
54LS109/DM54LS109A/DM74LS109A  
Dual Positive-Edge-Triggered J-K Flip-Flops  
with Preset, Clear, and Complementary Outputs  
General Description  
This device contains two independent positive-edge-trig-  
gered J-K flip-flops with complementary outputs. The J and  
K data is accepted by the flip-flop on the rising edge of the  
clock pulse. The triggering occurs at a voltage level and is  
not directly related to the transition time of the rising edge of  
the clock. The data on the J and K inputs may be changed  
while the clock is high or low as long as setup and hold  
times are not violated. A low logic level on the preset or  
clear inputs will set or reset the outputs regardless of the  
logic levels of the other inputs.  
Features  
Y
Alternate Military/Aerospace device (54LS109) is avail-  
able. Contact a National Semiconductor Sales Office/  
Distributor for specifications  
Connection Diagram  
Dual-In-Line Package  
TL/F/6368–1  
Order Number 54LS109DMQB, 54LS109FMQB, DM54LS109AJ,  
DM54LS109AW, DM74LS109AM or DM74LS109AN  
See NS Package Number J16A, M16A, N16E or W16A  
Function Table  
e
e
e
H
L
High Logic Level  
Inputs  
Outputs  
Low Logic Level  
PR  
CLR  
CLK  
J
K
Q
Q
X
Either Low or High Logic Level  
e
Rising Edge of Pulse  
This configuration is nonstable; that is, it will not persist when preset  
and/or clear inputs return to their inactive (high) state.  
u
*
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
u
u
u
u
L
X
X
X
L
H
L
X
X
X
L
H
L
H*  
L
L
H
H*  
H
e
e
established.  
Q
The output logic level of Q before the indicated input conditions were  
0
L
Toggle  
e
Toggle  
each active transition of the clock pulse.  
Each output changes to the complement of its previous level on  
H
H
X
Q
0
H
Q
0
L
H
X
Q
Q
0
0
C
1995 National Semiconductor Corporation  
TL/F/6368  
RRD-B30M105/Printed in U. S. A.  
Absolute Maximum Ratings (Note)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales  
Office/Distributors for availability and specifications.  
Note: The ‘‘Absolute Maximum Ratings’’ are those values  
beyond which the safety of the device cannot be guaran-  
teed. The device should not be operated at these limits. The  
parametric values defined in the ‘‘Electrical Characteristics’’  
table are not guaranteed at the absolute maximum ratings.  
The ‘‘Recommended Operating Conditions’’ table will define  
the conditions for actual device operation.  
Supply Voltage  
Input Voltage  
7V  
7V  
Operating Free Air Temperature Range  
DM54LS and 54LS  
DM74LS  
b
b
a
a
55 C to 125 C  
§
§
0 C to 70 C  
§
§
a
65 C to 150 C  
Storage Temperature Range  
§
§
Recommended Operating Conditions  
DM54LS109A  
DM74LS109A  
Symbol  
Parameter  
Units  
Min  
4.5  
2
Nom  
Max  
Min  
4.75  
2
Nom  
Max  
V
V
V
Supply Voltage  
5
5.5  
5
5.25  
V
V
CC  
High Level Input Voltage  
Low Level Input Voltage  
High Level Output Current  
Low Level Output Current  
Clock Frequency (Note 2)  
Clock Frequency (Note 3)  
IH  
0.7  
0.8  
V
IL  
b
b
0.4  
I
I
0.4  
mA  
mA  
MHz  
MHz  
OH  
OL  
4
8
f
f
t
0
25  
20  
0
25  
20  
CLK  
CLK  
W
0
0
Pulse Width  
(Note 2)  
Clock High  
18  
15  
15  
25  
20  
20  
18  
15  
15  
25  
20  
20  
Preset Low  
Clear Low  
Clock High  
Preset Low  
Clear Low  
Data High  
Data Low  
Data High  
Data Low  
ns  
t
Pulse Width  
(Note 3)  
W
ns  
ns  
t
t
t
Setup Time  
30  
30  
u
u
u
u
u
SU  
SU  
H
(Notes 1 & 2)  
20  
35  
25  
0
20  
u
Setup Time  
35  
u
ns  
ns  
(Notes 1 & 3)  
25  
u
Hold Time (Note 4)  
0
u
u
b
T
A
Free Air Operating Temperature  
55  
125  
0
70  
C
§
Note 1: The symbol ( ) indicates the rising edge of the clock pulse is used for reference.  
u
L
e
e
e
e
e
e
e
e
e
Note 2: C  
Note 3: C  
Note 4: T  
15 pF, R  
2 kX, T  
2 kX, T  
25 C and V  
§
25 C and V  
§
5V.  
5V.  
L
A
A
CC  
CC  
50 pF, R  
L
L
e
CC  
25 C and V  
§
5V.  
A
2
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)  
Typ  
Symbol  
Parameter  
Conditions  
Min  
Max  
Units  
(Note 1)  
e
e
e b  
e
b
1.5  
V
V
Input Clamp Voltage  
V
Min, I  
Min, I  
18 mA  
V
V
I
CC  
I
High Level Output  
Voltage  
V
V
Max  
Min  
DM54  
DM74  
DM54  
DM74  
DM74  
J, K  
2.5  
2.7  
3.4  
3.4  
OH  
CC  
OH  
e
e
Max, V  
IL  
IH  
e
e
e
V
OL  
Low Level Output  
Voltage  
V
V
Min, I  
Max  
Min  
0.25  
0.35  
0.25  
0.4  
CC  
OL  
e
Max, V  
IH  
IL  
0.5  
0.4  
0.1  
0.1  
0.2  
0.2  
20  
V
e
e
Min  
I
4 mA, V  
CC  
OL  
@
Input Current Max  
e
CC  
I
I
I
V
Max  
I
e
Input Voltage  
V
I
7V  
Clock  
Preset  
Clear  
J,K  
mA  
e
2.7V  
High Level Input  
Current  
V
V
Max  
Max  
Max  
IH  
CC  
e
I
Clock  
Preset  
Clear  
J, K  
20  
mA  
40  
40  
e
0.4V  
b
Low Level Input  
Current  
V
V
0.4  
0.4  
0.8  
0.8  
100  
100  
8
IL  
CC  
e
I
b
b
b
Clock  
Preset  
Clear  
DM54  
DM74  
mA  
e
(Note 2)  
b
b
b
b
I
I
Short Circuit  
V
CC  
20  
20  
OS  
CC  
mA  
mA  
Output Current  
e
Supply Current  
V
CC  
Max (Note 3)  
4
e
e
25 C (See Section 1 for Test Waveforms and Output Load)  
Switching Characteristics at V  
5V and T  
§
CC  
A
e
R
2 kX  
L
From (Input)  
To (Output)  
e
e
L
Symbol  
Parameter  
C
L
15 pF  
C
50 pF  
Max  
Units  
Min  
Max  
Min  
f
t
t
t
t
t
t
Maximum Clock  
Frequency  
MAX  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
25  
20  
MHz  
ns  
Propagation Delay Time  
Low to High Level Output  
Clock to  
Q or Q  
25  
30  
25  
30  
25  
30  
35  
35  
35  
35  
35  
35  
Propagation Delay Time  
High to Low Level Output  
Clock to  
Q or Q  
ns  
Propagation Delay Time  
Low to High Level Output  
Clear  
to Q  
ns  
Propagation Delay Time  
High to Low Level Output  
Clear  
to Q  
ns  
Propagation Delay Time  
Low to High Level Output  
Preset  
to Q  
ns  
Propagation Delay Time  
High to Low Level Output  
Preset  
to Q  
ns  
e
e
25 C.  
Note 1: All typicals are at V  
5V, T  
§
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where  
CC  
A
e
shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where V  
2.25V and 2.125V for DM54 and  
O
DM74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test  
equipment.  
Note 3: I  
CC  
is measured with all outputs open, with CLOCK grounded after setting the Q and Q outputs high in turn.  
3
Physical Dimensions inches (millimeters)  
16-Lead Ceramic Dual-In-Line Package (J)  
Order Number 54LS109DMQB or DM54LS109AJ  
NS Package Number J16A  
4
Physical Dimensions inches (millimeters) (Continued)  
16-Lead Small Outline Molded Package (M)  
Order Number DM74LS109AM  
NS Package Number M16A  
16-Lead Molded Dual-In-Line Package (N)  
Order Number DM74LS109AN  
NS Package Number N16E  
5
Physical Dimensions inches (millimeters) (Continued)  
16-Lead Ceramic Flat Package  
Order Number 54LS109FMQB or DM54LS109AW  
NS Package Number W16A  
LIFE SUPPORT POLICY  
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant  
into the body, or (b) support or sustain life, and whose  
failure to perform, when properly used in accordance  
with instructions for use provided in the labeling, can  
be reasonably expected to result in a significant injury  
to the user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
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