74LCX374SJ_NL [FAIRCHILD]
Bus Driver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20;
| 型号： | 74LCX374SJ_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20 触发器 |
| 文件： | 总12页 (文件大小：556K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1994
Revised March 2005
74LCX374
Low Voltage Octal D-Type Flip-Flop
with 5V Tolerant Inputs and Outputs
General Description
Features
■ 5V tolerant inputs and outputs
The LCX374 consists of eight D-type flip-flops featuring
separate D-type inputs for each flip-flop and 3-STATE out-
puts for bus-oriented applications. A buffered clock (CP)
and Output Enable (OE) are common to all flip-flops. The
LCX374 is designed for low voltage (3.3V or 2.5V) VCC
■ 2.3V–3.6V VCC specifications provided
■ 8.5 ns tPD max (VCC 3.3V), 10 A ICC max
■ Power-down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
applications with capability of interfacing to a 5V signal
environment.
■
24 mA output drive (VCC 3.0V)
The LCX374 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance:
Human Body Model 2000V
Machine Model 200V
■ Leadless Pb-Free DQFN package
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
through a pull-up resistor: the minimum value or the
CC
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Package
Order Number
Package Description
Number
74LCX374WM
74LCX374SJ
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX374BQX
(Preliminary)
(Note 2)
MLP020B Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 4.5mm
74LCX374MSA
74LCX374MTC
MSA20
MTC20
MTC20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX374MTCX_NL
(Note 3)
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 2: DQFN package available in Tape and Reel only.
Note 3: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS011996
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Logic Symbol
Pin Descriptions
Pin Names
Description
Data Inputs
D0–D7
CP
Clock Pulse Input
Output Enable Input
3-STATE Outputs
OE
O0–O7
Connection Diagrams
Truth Table
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Inputs
Outputs
Dn
CP
OE
On
H
L
L
L
H
L
X
X
L
L
O0
Z
X
H
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
LOW-to-HIGH Transition
Previous O before HIGH-to-LOW of CP
O
0
0
Pad Assignments for DQFN
Functional Description
The LCX374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
(Top View)
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 4)
Symbol
VCC
Parameter
Supply Voltage
Value
Conditions
Units
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
V
V
VI
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
0.5 to VCC 0.5 Output in HIGH or LOW State (Note 5)
IIK
DC Input Diode Current
DC Output Diode Current
50
50
VI GND
VO GND
VO VCC
mA
mA
IOK
50
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
50
mA
mA
mA
C
ICC
100
IGND
TSTG
100
65 to 150
Recommended Operating Conditions (Note 6)
Symbol
Parameter
Min
2.0
1.5
0
Max
3.6
3.6
5.5
VCC
5.5
24
Units
VCC
Supply Voltage
Operating
V
V
V
Data Retention
VI
Input Voltage
VO
Output Voltage
HIGH or LOW State
3-STATE
0
0
IOH/IOL
Output Current
VCC 3.0V 3.6V
VCC 2.7V 3.0V
VCC 2.3V 2.7V
12
mA
8
TA
Free-Air Operating Temperature
40
0
85
C
t/ V
Input Edge Rate, VIN 0.8V 2.0V, VCC 3.0V
10
ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 5: I Absolute Maximum Rating must be observed.
O
Note 6: Unused inputs or I/Os must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
V
T
40 C to 85 C
Max
CC
A
Symbol
Parameter
Conditions
Units
(V)
2.3 2.7
2.7 3.6
2.3 2.7
2.7 3.6
2.3 3.6
2.3
Min
1.7
2.0
V
V
V
HIGH Level Input Voltage
IH
V
V
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
IL
I
I
I
I
I
I
I
I
I
I
100
8 mA
A
V
CC
0.2
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
1.8
2.2
2.4
2.2
12 mA
18 mA
24 mA
2.7
V
V
3.0
3.0
V
LOW Level Output Voltage
100
8 mA
A
2.3 3.6
2.3
0.2
0.6
0.4
0.4
0.55
5.0
OL
12 mA
16 mA
24 mA
2.7
3.0
3.0
I
I
Input Leakage Current
0
0
V
V
V
5.5V
5.5V
2.3 3.6
A
A
A
I
I
3-STATE Output Leakage
OZ
O
2.3 3.6
0
5.0
10
V
or V
IL
I
IH
I
Power-Off Leakage Current
V or V
O
5.5V
OFF
I
3
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DC Electrical Characteristics (Continued)
V
T
40 C to 85 C
Max
10
10
CC
A
Symbol
Parameter
Conditions
Units
(V)
Min
I
Quiescent Supply Current
V
V or GND
CC
2.3 3.6
2.3 3.6
2.3 3.6
CC
I
A
A
3.6V V , V
5.5V (Note 7)
I
O
I
Increase in I per Input
V
V
CC
0.6V
500
CC
CC
IH
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
40 C to 85 C, R
500
A
L
V
3.3V 0.3V
50 pF
V
2.7V
V
CC
2.5 0.2
30 pF
CC
CC
Symbol
Parameter
Units
C
C
50 pF
C
L
L
L
Min
150
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.3
Max
Min
Max
Min
150
1.5
1.5
1.5
1.5
1.5
1.5
4.0
2.0
4.0
Max
f
Maximum Clock Frequency
Propagation Delay
150
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.3
MHz
ns
MAX
PHL
PLH
PZL
PZH
PLZ
PHZ
S
t
t
t
t
t
t
t
t
t
t
t
8.5
8.5
8.5
8.5
7.5
7.5
9.5
9.5
9.5
9.5
8.5
8.5
10.5
10.5
10.5
10.5
9.0
CP to O
n
Output Enable Time
ns
ns
Output Disable Time
9.0
Setup Time
ns
ns
ns
Hold Time
H
Pulse Width
W
Output to Output Skew (Note 8)
1.0
1.0
OSHL
OSLH
ns
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSLH
OSHL
Dynamic Switching Characteristics
V
T
25 C
CC
A
Symbol
Parameter
Conditions
Units
(V)
3.3
2.5
3.3
2.5
Typical
0.8
V
Quiet Output Dynamic Peak V
C
C
C
C
50 pF, V
30 pF, V
50 pF, V
30 pF, V
3.3V, V
2.5V, V
3.3V, V
2.5V, V
0V
0V
0V
0V
OLP
OL
L
L
L
L
IH
IH
IH
IH
IL
IL
IL
IL
V
V
0.6
V
Quiet Output Dynamic Valley V
0.8
OLV
OL
0.6
Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
Open, V 0V or V
Typical
Units
pF
C
V
V
V
7
8
IN
CC
CC
CC
I
CC
C
C
3.3V, V 0V or V
CC
pF
OUT
PD
I
3.3V, V 0V or V , f 10 MHz
25
pF
I
CC
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4
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
PZL, tPLZ
Switch
Open
t
6V at VCC 3.3 0.3V
VCC x 2 at VCC 2.5 0.2V
tPZH,tPHZ
GND
3-STATE Output High Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
VCC
Symbol
3.3V 0.3V
1.5V
2.7V
1.5V
2.5V 0.2V
VCC/2
Vmi
Vmo
Vx
1.5V
1.5V
VCC/2
VOL 0.3V
VOH 0.3V
VOL 0.3V
VOH 0.3V
VOL 0.15V
VOH 0.15V
Vy
5
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Schematic Diagram Generic for LCX Family
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6
Tape and Reel Specification
Tape Format for DQFN
Package
Tape
Section
Number
Cavities
125 (typ)
3000
Cavity
Status
Empty
Filled
Cover Tape
Status
Designator
Leader (Start End)
Carrier
Sealed
BQX
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
REEL DIMENSIONS inches (millimeters)
Tape Size
A
B
C
D
N
W1
W2
13.0
0.059
(1.50)
0.512
(13.00)
0.795
(20.20)
2.165
0.488
(12.4)
0.724
(18.4)
12 mm
(330.0)
(55.00)
7
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm
Package Number MLP020B
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
11
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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12
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