74HC4046 [FAIRCHILD]
CMOS Phase Lock Loop; 的CMOS锁相环
| 型号： | 74HC4046 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | CMOS Phase Lock Loop |
| 文件： | 总17页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1984
Revised October 2003
MM74HC4046
CMOS Phase Lock Loop
them. This comparator is more susceptible to noise throw-
ing the loop out of lock, but is less likely to lock onto har-
monics than the other two comparators.
General Description
The MM74HC4046 is a low power phase lock loop utilizing
advanced silicon-gate CMOS technology to obtain high fre-
quency operation both in the phase comparator and VCO
sections. This device contains a low power linear voltage
controlled oscillator (VCO), a source follower, and three
phase comparators. The three phase comparators have a
common signal input and a common comparator input. The
signal input has a self biasing amplifier allowing signals to
be either capacitively coupled to the phase comparators
with a small signal or directly coupled with standard input
logic levels. This device is similar to the CD4046 except
that the Zener diode of the metal gate CMOS device has
been replaced with a third phase comparator.
In a typical application any one of the three comparators
feed an external filter network which in turn feeds the VCO
input. This input is a very high impedance CMOS input
which also drives the source follower. The VCO’s operating
frequency is set by three external components connected
to the C1A, C1B, R1 and R2 pins. An inhibit pin is provided
to disable the VCO and the source follower, providing a
method of putting the IC in a low power state.
The source follower is a MOS transistor whose gate is con-
nected to the VCO input and whose drain connects the
Demodulator output. This output normally is used by tying
a resistor from pin 10 to ground, and provides a means of
looking at the VCO input without loading down modifying
the characteristics of the PLL filter.
Phase Comparator I is an exclusive OR (XOR) gate. It pro-
vides a digital error signal that maintains a 90 phase shift
between the VCO’s center frequency and the input signal
(50% duty cycle input waveforms). This phase detector is
more susceptible to locking onto harmonics of the input fre-
quency than phase comparator I, but provides better noise
rejection.
Features
■ Low dynamic power consumption: (VCC = 4.5V)
■ Maximum VCO operating frequency:
12 MHz (VCC = 4.5V)
Phase comparator III is an SR flip-flop gate. It can be used
to provide the phase comparator functions and is similar to
the first comparator in performance.
■ Fast comparator response time (VCC = 4.5V)
Comparator I: 25 ns
Phase comparator II is an edge sensitive digital sequential
network. Two signal outputs are provided, a comparator
output and a phase pulse output. The comparator output is
a 3-STATE output that provides a signal that locks the VCO
output signal to the input signal with 0 phase shift between
Comparator II: 30 ns
Comparator III: 25 ns
■ VCO has high linearity and high temperature stability
Ordering Code:
Order Number
MM74HC4046M
MM74HC4046SJ
MM74HC4046MTC
MM74HC4046N
Package Number
M16A
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
M16D
MTC16
N16E
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2003 Fairchild Semiconductor Corporation
DS005352
www.fairchildsemi.com
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Block Diagram
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to + 7.0V
−1.5 to VCC +1.5V
−0.5 to VCC + 0.5V
±20 mA
Min
Max Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
6
V
)
)
)
0
VCC
V
)
±25 mA
Operating Temperature Range (TA) −40
Input Rise or Fall Times
+85
°C
)
±50 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C +150°C
(tr, tf) VCC = 2.0V
1000
500
ns
ns
ns
V
CC = 4.5V
CC = 6.0V
600 mW
500 mW
V
400
S.O. Package only
Note 1: Maximum Ratings are those values beyond which damage to the
device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
T
A = 25°C
TA = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
Parameter
Conditions
Units
Typ
Guaranteed Limits
VIH
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
3.15
4.2
VIL
Maximum LOW Level
Input Voltage
0.5
0.5
0.5
1.35
1.8
1.35
1.8
1.35
1.8
VOH
Minimum HIGH Level
Output Voltage
V
IN = VIH or VIL
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA
|IOUT| ≤ 5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
VOL
Maximum Low Level
Output Voltage
V
IN = VIHor VIL
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA
|IOUT| ≤ 5.2 mA
4.5V
6.0V
6.0V
6.0V
6.0V
0.2
0.2
0.26
0.26
±0.1
50
0.33
0.33
±1.0
80
0.4
0.4
V
V
IIN
IIN
IOZ
Maximum Input Current (Pins 3,5,9)
Maximum Input Current (Pin 14)
Maximum 3-STATE Output
Leakage Current (Pin 13)
Maximum Quiescent
VIN = VCCor GND
VIN = VCC or GND
VOUT = VCC or GND
±1.0
100
±10
µA
µA
µA
20
±0.5
±5.0
ICC
V
IN = VCC or GND
6.0V
6.0V
30
80
130
160
µA
µA
Supply Current
I
OUT = 0 µA
IN = VCC or GND
Pin 14 Open
V
600
1500
2400
3000
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
www.fairchildsemi.com
AC Electrical Characteristics VCC = 2.0 to 6.0V, CL = 50 pF, tr = tr = 6 ns (unless otherwise specified.)
T
A=25C
TA = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
Parameters
Conditions
Units
Typ
Guaranteed Limits
AC Coupled
C (series) = 100 pF
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
7
25
50
135
30
9
100
150
200
300
95
200
250
350
110
22
mV
mV
mV
ns
Input Sensitivity,
Signal In
f
IN = 500 kHz
150
250
75
tr, tf
Maximum Output
Rise and Fall Time
15
19
ns
8
12
15
19
ns
CIN
Maximum Input Capacitance
pF
Phase Comparator I
PHL, tPLH Maximum
Propagation Delay
t
2.0V
4.5V
6.0V
65
25
20
200
40
250
50
300
60
ns
ns
ns
34
43
51
Phase Comparator II
tPZL Maximum 3-STATE
Enable Time
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
75
25
22
88
30
25
90
32
28
100
34
27
225
45
280
56
340
68
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
38
48
57
tPZH, tPHZ Maximum 3-STATE
Enable Time
240
48
300
60
360
72
41
51
61
tPLZ
Maximum 3-STATE
Disable Time
240
48
300
60
360
72
41
51
61
t
PHL, tPLH Maximum
250
50
310
63
380
75
Propagation Delay
HIGH-to-LOW to Phase Pulses
43
53
64
Phase Comparator III
tPHL, tPLH Maximum
2.0V
4.5V
6.0V
75
25
200
40
250
50
300
60
ns
ns
ns
pF
Propagation Delay
22
34
43
51
CPD
Maximum Power
All Comparators
IN = VCC and GND
130
Dissipation Capacitance
V
Voltage Controlled Oscillator (Specified to operate from VCC= 3.0V to 6.0V)
fMAX
Maximum
Operating
Frequency
C1 = 50 pF
R1 = 100Ω
R2 = ∞
4.5V
6.0V
7
4.5
7
MHz
MHz
11
VCOin = VCC
C1 = 0 pF
R1 = 100Ω
VCOin = VCC
4.5V
6.0
12
14
MHz
MHz
Duty Cycle
50
%
V
Demodulator Output
Offset Voltage
VCOin–Vdem
Offset
R
s = 20 kΩ
s = 20 kΩ
4.5V
4.5V
0.75
1.3
1.5
1.6
R
Variation
VCOin = 1.75V
2.25V
0.65
0.1
V
2.75V
0.75
www.fairchildsemi.com
4
Typical Performance Characteristics
Typical Center Frequency
Typical Center Frequency
vs R1, C1 CC = 6V
vs R1, C1
V
CC = 4.5V
V
Typical Offset Frequency
vs R2, C1 CC = 4.5V
Typical Offset Frequency
vs R2, C1 CC = 6V
V
V
Typical VCO Power Dissipation
@ Center Frequency vs R1
Typical VCO Power
Dissipation @ fMIN vs R2
5
www.fairchildsemi.com
Typical Performance Characteristics (Continued)
VCOin vs fout
V
CC = 4.5V
VCOin vs fout VCC = 4.5V
VCOout vs
Temperature CC = 4.5V
VCOout vs
V
Temperature VCC = 6V
www.fairchildsemi.com
6
Typical Performance Characteristics (Continued)
HC4046 Typical Source Follower
Power Dissipation vs RS
Typical fMAX/fMIN vs R2/R1
CC = 4.5V & 6V fMAX/fMIN
V
Typical VCO Linaearity vs R1 & C1
Typical VCO Linearity vs R1 & C1
7
www.fairchildsemi.com
Detailed Circuit Description
VOLTAGE CONTROLLED OSCILLATOR/SOURCE
FOLLOWER
The VCO requires two or three external components to
operate. These are R1, R2, C1. Resistor R1 and capacitor
C1 are selected to determine the center frequency of the
VCO. R1 controls the lock range. As R1’s resistance
decreases the range of fMIN to fMAX increases. Thus the
the value of R2 the lock range of the PLL is offset above
0Hz and the gain (Hz/Volt) does not change. In general,
when offset is desired, R2 and C1 should be chosen first,
and then R1 should be chosen to obtain the proper center
frequency.
VCO’s gain increases. As C1 is changed the offset (if used)
of R2, and the center frequency is changed. (See typical
performance curves) R2 can be used to set the offset fre-
quency with 0V at VCO input. If R2 is omitted the VCO
range is from 0Hz. As R2 is decreased the offset frequency
is increased. The effect of R2 is shown in the design infor-
mation table and typical performance curves. By increasing
Internally the resistors set a current in a current mirror as
shown in Figure 1. The mirrored current drives one side of
the capacitor once the capacitor charges up to the thresh-
old of the schmitt trigger the oscillator logic flips the capaci-
tor over and causes the mirror to charge the opposite side
of the capacitor. The output from the internal logic is then
taken to pin 4.
VCO WITHOUT OFFSET
VCO WITH OFFSET
R2 = ∞
Comparator I
Comparator II & III
R2= ∞
R2≠∞
•Given: f0 and fL
R2= ∞
•Given: fMAX
R2≠∞
•Given: f0
•Given: fMIN and fMAX
•Use fMIN with curve titled
offset frequency vs R2,
C to determine R2 and C1
•Calculate fMAX/fMIN
•Use f0 with curve titled
center frequency vs R1, C
to determine R1 and C1
•Calculate fMIN from the
equation fMIN = fo − fL
•Calculate f0 from the
equation fo = fMAX/2
•Use fMIN with curve titled
offset frequency vs R2, C
to determine R2 and C1
•Calculate fMAX/fMIN from
•Use f0 with curve titled
center frequency vs R1, C
to determine R1 and C1
•Use fMAX/fMIN with curve
titled fMAX/fMIN vs R2/R1
to determine ratio R2/R1
to obtain R1
the equation fMAX/fMIN
o + fL/fo − fL
=
f
•Use fMAX/fMIN with curve
titled fMAX/fMIN vs R2/R1
to determine ratio R2/R1
to obtain R1
FIGURE 1.
www.fairchildsemi.com
8
Detailed Circuit Description (Continued)
FIGURE 2. Logic Diagram for VCO
The input to the VCO is a very high impedance CMOS
input and so it will not load down the loop filter, easing the
filters design. In order to make signals at the VCO input
not being used. A logic high on inhibit disables the VCO
and source follower.
The output of the VCO is a standard high speed CMOS
output with an equivalent LSTTL fanout of 10. The VCO
output is approximately a square wave. This output can
either directly feed the comparator input of the phase com-
parators or feed external prescalers (counters) to enable
frequency synthesis.
accessible without degrading the loop performance
a
source follower transistor is provided. This transistor can
be used by connecting a resistor to ground and its drain
output will follow the VCO input signal.
An inhibit signal is provided to allow disabling of the VCO
and the source follower. This is useful if the internal VCO is
PHASE COMPARATORS
All three phase comparators share two inputs, Signal In
and Comparator In. The Signal In has a special DC bias
network that enables AC coupling of input signals. If the
signals are not AC coupled then this input requires logic
levels the same as standard 74HC. The Comparator input
is a standard digital input. Both input structures are shown
in Figure 3.
The outputs of these comparators are essentially standard
74HC voltage outputs. (Comparator II is 3-STATE.)
FIGURE 3. Logic Diagram for Phase Comparator I and the common input circuit for all three comparators
9
www.fairchildsemi.com
Detailed Circuit Description (Continued)
FIGURE 4. Typical Phase Comparator I. Waveforms
Thus in normal operation VCC and ground voltage levels
quency is fMAX then the VCO input must be VCC and the
are fed to the loop filter. This differs from some phase
detectors which supply a current output to the loop filter
and this should be considered in the design. (The CD4046
also provides a voltage.)
phase detector inputs must be 180° out of phase.
The XOR is more susceptible to locking onto harmonics of
the signal input than the digital phase detector II. This can
be seen by noticing that a signal 2 times the VCO fre-
quency results in the same output duty cycle as a signal
equal the VCO frequency. The difference is that the output
frequency of the 2f example is twice that of the other exam-
ple. The loop filter and the VCO range should be designed
to prevent locking on to harmonics.
Figure 5 shows the state tables for all three comparators.
PHASE COMPARATOR I
This comparator is a simple XOR gate similar to the
74HC86, and its operation is similar to an overdriven bal-
anced modulator. To maximize lock range the input fre-
quencies must have a 50% duty cycle. Typical input and
output waveforms are shown in Figure 4. The output of the
phase detector feeds the loop filter which averages the out-
put voltage. The frequency range upon which the PLL will
lock onto if initially out of lock is defined as the capture
range. The capture range for phase detector I is dependent
on the loop filter employed. The capture range can be as
large as the lock range which is equal to the VCO fre-
quency range.
PHASE COMPARATOR II
This detector is a digital memory network. It consists of four
flip-flops and some gating logic, a three state output and a
phase pulse output as shown in Figure 6. This comparator
acts only on the positive edges of the input signals and is
thus independent of signal duty cycle.
Phase comparator II operates in such a way as to force the
PLL into lock with 0 phase difference between the VCO
output and the signal input positive waveform edges. Fig-
ure 7 shows some typical loop waveforms. First assume
that the signal input phase is leading the comparator input.
This means that the VCO’s frequency must be increased to
bring its leading edge into proper phase alignment. Thus
the phase detector II output is set high. This will cause the
loop filter to charge up the VCO input increasing the VCO
frequency. Once the leading edge of the comparator input
is detected the output goes 3-STATE holding the VCO
input at the loop filter voltage. If the VCO still lags the sig-
nal then the phase detector will again charge up to VCO
input for the time between the leading edges of both wave-
forms.
To see how the detector operates refer to Figure 4. When
two square wave inputs are applied to this comparator, an
output waveform whose duty cycle is dependent on the
phase difference between the two signals results. As the
phase difference increases the output duty cycle increases
and the voltage after the loop filter increases. Thus in order
to achieve lock, when the PLL input frequency increases
the VCO input voltage must increase and the phase differ-
ence between comparator in and signal in will increase. At
an input frequency equal fMIN, the VCO input is at 0V and
this requires the phase detector output to be ground hence
the two input signals must be in phase. When the input fre-
www.fairchildsemi.com
10
Detailed Circuit Description (Continued)
Phase Comparator State Diagrams
FIGURE 5. PLL State Tables
11
www.fairchildsemi.com
Detailed Circuit Description (Continued)
FIGURE 6. Logic Diagram for Phase Comparator II
FIGURE 7. Typical Phase Comparator II Output Waveforms
www.fairchildsemi.com
12
Detailed Circuit Description (Continued)
If the VCO leads the signal then when the leading edge of
the VCO is seen the output of the phase comparator goes
LOW. This discharges the loop filter until the leading edge
of the signal is detected at which time the output 3-STATE
itself again. This has the effect of slowing down the VCO to
again make the rising edges of both waveform coincident.
Phase comparator II is more susceptible to noise causing
the phase lock loop to unlock. If a noise pulse is seen on
the signal input, the comparator treats it as another positive
edge of the signal and will cause the output to go HIGH
until the VCO leading edge is seen, potentially for a whole
signal input period. This would cause the VCO to speed up
during that time. When using the phase comparator I the
output of that phase detector would be disturbed for only
the short duration of the noise spike and would cause less
upset.
When the PLL is out of lock the VCO will be running either
slower or faster than the signal input. If it is running slower
the phase detector will see more signal rising edges and so
the output of the phase comparator will be HIGH a majority
of the time, raising the VCO’s frequency. Conversely, if the
VCO is running faster than the signal the output of the
detector will be LOW most of the time and the VCO’s out-
put frequency will be decreased.
PHASE COMPARATOR III
This comparator is a simple S-R Flip-Flop which can func-
tion as a phase comparator Figure 8. It has some similar
characteristics to the edge sensitive comparator. To see
how this detector works assume input pulses are applied to
the signal and comparator inputs as shown in Figure 9.
When the signal input leads the comparator input the flop is
set. This will charge up the loop filter and cause the VCO to
speed up, bringing the comparator into phase with the sig-
nal input. When using short pulses as input this comparator
behaves very similar to the second comparator. But one
can see that if the signal input is a long pulse, the output of
the comparator will be forced to a one no matter how many
comparator input pulses are received. Also if the VCO input
is a square wave (as it is) and the signal input is pulse then
the VCO will force the comparator output LOW much of the
time. Therefore it is ideal to condition the signal and com-
parator input to short pulses. This is most easily done by
using a series capacitor.
As one can see when the PLL is locked the output of phase
comparator II will be almost always 3-STATE except for
minor corrections at the leading edge of the waveforms.
When the detector is 3-STATE the phase pulse output is
HIGH. This output can be used to determine when the PLL
is in the locked condition.
This detector has several interesting characteristics. Over
the entire VCO frequency range there is no phase differ-
ence between the comparator input and the signal input.
The lock range of the PLL is the same as the capture
range. Minimal power is consumed in the loop filter since in
lock the detector output is a high impedance. Also when no
signal is present the detector will see only VCO leading
edges, and so the comparator output will stay LOW forcing
the VCO to fMIN operating frequency.
FIGURE 8. Phase Comparator III Logic Diagram
FIGURE 9. Typical Waveforms for Phase Comparator III
13
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
www.fairchildsemi.com
14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
15
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
www.fairchildsemi.com
16
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
17
www.fairchildsemi.com
相关型号：
74HC4046AD-T
IC PLL FREQUENCY SYNTHESIZER, PDSO16, SOT-109, SO-16, PLL or Frequency Synthesis Circuit
NXP
74HC4046ADB-T
IC PLL FREQUENCY SYNTHESIZER, PDSO16, SOT-338-1, SSOP-16, PLL or Frequency Synthesis Circuit
NXP
©2020 ICPDF网 联系我们和版权申明