74HC4046AD-T [NXP]
IC PLL FREQUENCY SYNTHESIZER, PDSO16, SOT-109, SO-16, PLL or Frequency Synthesis Circuit;
| 型号： | 74HC4046AD-T |
| 厂家： | 
NXP |
| 描述： | IC PLL FREQUENCY SYNTHESIZER, PDSO16, SOT-109, SO-16, PLL or Frequency Synthesis Circuit 光电二极管 |
| 文件： | 总34页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4046A
Phase-locked-loop with VCO
1997 Nov 25
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
provided at pin 10 (DEMOUT). In contrast to conventional
techniques where the DEMOUT voltage is one threshold
voltage lower than the VCO input voltage, here the
DEMOUT voltage equals that of the VCO input. If
DEMOUT is used, a load resistor (RS) should be connected
from DEMOUT to GND; if unused, DEMOUT should be left
open. The VCO output (VCOOUT) can be connected
directly to the comparator input (COMPIN), or connected
via a frequency-divider. The VCO output signal has a duty
factor of 50% (maximum expected deviation 1%), if the
VCO input is held at a constant DC level. A LOW level at
the inhibit input (INH) enables the VCO and demodulator,
while a HIGH level turns both off to minimize standby
power consumption.
FEATURES
• Low power consumption
• Centre frequency of up to 17 MHz (typ.) at VCC = 4.5 V
• Choice of three phase comparators: EXCLUSIVE-OR;
edge-triggered JK flip-flop;
edge-triggered RS flip-flop
• Excellent VCO frequency linearity
• VCO-inhibit control for ON/OFF keying and for low
standby power consumption
• Minimal frequency drift
• Operating power supply voltage range:
VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V
The only difference between the HC and HCT versions is
the input level specification of the INH input. This input
disables the VCO section. The sections of the comparator
are identical, so that there is no difference in the
SIGIN (pin 14) or COMPIN (pin 3) inputs between the HC
and HCT versions.
• Zero voltage offset due to op-amp buffering
• Output capability: standard
• ICC category: MSI.
GENERAL DESCRIPTION
Phase comparators
The 74HC/HCT4046A are high-speed Si-gate CMOS
devices and are pin compatible with the “4046” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The signal input (SIGIN) can be directly coupled to the
self-biasing amplifier at pin 14, provided that the signal
swing is between the standard HC family input logic levels.
Capacitive coupling is required for signals with smaller
swings.
The 74HC/HCT4046A are phase-locked-loop circuits that
comprise a linear voltage-controlled oscillator (VCO) and
three different phase comparators (PC1, PC2 and PC3)
with a common signal input amplifier and a common
comparator input.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network. The signal and
comparator input frequencies (fi) must have a 50% duty
factor to obtain the maximum locking range. The transfer
characteristic of PC1, assuming ripple (fr = 2fi) is
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input
amplifiers. With a passive low-pass filter, the “4046A”
forms a second-order loop PLL. The excellent VCO
linearity is achieved by the use of linear op-amp
techniques.
V
suppressed, is: VDEMOUT
=
CC (φ
– φCOMPIN)
SIGIN
----------
π
where VDEMOUT is the demodulator output at pin 10;
DEMOUT = VPC1OUT (via low-pass filter).
V
VCC
˙
The VCO requires one external capacitor C1 (between
C1A and C1B) and one external resistor R1 (between
R1 and GND) or two external resistors R1 and R2
(between R1 and GND, and R2 and GND). Resistor R1
and capacitor C1 determine the frequency range of the
VCO. Resistor R2 enables the VCO to have a frequency
offset if required.
The phase comparator gain is:Kp
=
(V ⁄ r) .
----------
π
The average output voltage from PC1, fed to the VCO
input via the low-pass filter and seen at the demodulator
output at pin 10 (VDEMOUT), is the resultant of the phase
differences of signals (SIGIN) and the comparator input
(COMPIN) as shown in Fig.6. The average of VDEMOUT is
equal to 1⁄2VCC when there is no signal or noise at
SIGIN and with this input the VCO oscillates at the centre
frequency (fo). Typical waveforms for the PC1 loop locked
at fo are shown in Fig.7.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is
1997 Nov 25
2
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
The frequency capture range (2fc) is defined as the
frequency range of input signals on which the PLL will lock
if it was initially out-of-lock. The frequency lock range
(2fL) is defined as the frequency range of input signals on
which the loop will stay locked if it was initially in lock. The
capture range is smaller or equal to the lock range.
and comparator inputs are equal in both phase and
frequency. At this stable point the voltage on C2 remains
constant as the PC2 output is in 3-state and the VCO input
at pin 9 is a high impedance. Also in this condition, the
signal at the phase comparator pulse output (PCPOUT) is a
HIGH level and so can be used for indicating a locked
condition.
With PC1, the capture range depends on the low-pass
filter characteristics and can be made as large as the lock
range.
This configuration retains lock even with very noisy input
signals. Typical behaviour of this type of phase
comparator is that it can lock to input frequencies close to
the harmonics of the VCO centre frequency.
Thus, for PC2, no phase difference exists between
SIGIN and COMPIN over the full frequency range of the
VCO. Moreover, the power dissipation due to the low-pass
filter is reduced because both p and n-type drivers are
“OFF” for most of the signal input cycle. It should be noted
that the PLL lock range for this type of phase comparator
is equal to the capture range and is independent of the
low-pass filter. With no signal present at SIGIN the
VCO adjusts, via PC2, to its lowest frequency.
Phase comparator 2 (PC2)
This is a positive edge-triggered phase and frequency
detector. When the PLL is using this comparator, the loop
is controlled by positive signal transitions and the duty
factors of SIGIN and COMPIN are not important. PC2
comprises two D-type flip-flops, control-gating and a
3-state output stage. The circuit functions as an up-down
counter (Fig.5) where SIGIN causes an up-count and
COMPIN a down-count. The transfer function of PC2,
assuming ripple (fr = fi) is suppressed,
Phase comparator 3 (PC3)
This is a positive edge-triggered sequential phase detector
using an RS-type flip-flop. When the PLL is using this
comparator, the loop is controlled by positive signal
transitions and the duty factors of SIGIN and COMPIN are
not important. The transfer characteristic of PC3,
assuming ripple (fr = fi) is suppressed,
V
V
CC (φ SIGIN – φCOMPIN
)
is: VDEMOUT
=
CC (φ SIGIN – φCOMPIN
)
is: VDEMOUT
=
----------
----------
2π
4π
where VDEMOUT is the demodulator output at pin 10;
VDEMOUT = VPC3OUT (via low-pass filter).
where VDEMOUT is the demodulator output at pin 10;
VDEMOUT = VPC2OUT (via low-pass filter).
V
V
CC (V ⁄ r) .
The phase comparator gain is:Kp
=
CC (V ⁄ r) .
The phase comparator gain is:Kp
=
----------
----------
2π
4π
The average output from PC3, fed to the VCO via the
low-pass filter and seen at the demodulator output at
pin 10 (VDEMOUT), is the resultant of the phase differences
of SIGIN and COMPIN as shown in Fig.10. Typical
waveforms for the PC3 loop locked at fo are shown in
Fig.11.
VDEMOUT is the resultant of the initial phase differences of
SIGIN and COMPIN as shown in Fig.8. Typical waveforms
for the PC2 loop locked at fo are shown in Fig.9.
When the frequencies of SIGIN and COMPIN are equal but
the phase of SIGIN leads that of COMPIN, the p-type
output driver at PC2OUT is held “ON” for a time
corresponding to the phase difference (φDEMOUT). When
the phase of SIGIN lags that of COMPIN, the n-type driver
is held “ON”.
The phase-to-output response characteristic of PC3
(Fig.10) differs from that of PC2 in that the phase angle
between SIGIN and COMPIN varies between 0° and
360° and is 180° at the centre frequency. Also PC3 gives
a greater voltage swing than PC2 for input phase
differences but as a consequence the ripple content of the
VCO input signal is higher. The PLL lock range for this type
of phase comparator and the capture range are dependent
on the low-pass filter. With no signal present at SIGIN the
VCO adjusts, via PC3, to its lowest frequency.
When the frequency of SIGIN is higher than that of
COMPIN, the p-type output driver is held “ON” for most of
the input signal cycle time, and for the remainder of the
cycle both n and p- type drivers are ”OFF” (3-state). If the
SIGIN frequency is lower than the COMPIN frequency, then
it is the n-type driver that is held “ON” for most of the cycle.
Subsequently, the voltage at the capacitor (C2) of the
low-pass filter connected to PC2OUT varies until the signal
1997 Nov 25
3
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C
TYPICAL
UNIT
SYMBOL
PARAMETER
VCO centre frequency
CONDITIONS
HC HCT
fo
C1 = 40 pF; R1 = 3 kΩ; VCC = 5 V 19
3.5 3.5
24 24
19
MHz
pF
CI
input capacitance (pin 5)
CPD
power dissipation capacitance per
package
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz.
fo = output frequency in MHz.
CL = output load capacitance in pF.
VCC = supply voltage in V.
∑ (CL × VCC2 × fo) = sum of outputs.
2. Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator
sections see Figs 22, 23 and 24.
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
APPLICATIONS
• FM modulation and demodulation
• Frequency synthesis and multiplication
• Frequency discrimination
• Tone decoding
• Data synchronization and conditioning
• Voltage-to-frequency conversion
• Motor-speed control.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
1997 Nov 25
4
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
PCPOUT
PC1OUT
COMPIN
VCOOUT
INH
phase comparator pulse output
phase comparator 1 output
comparator input
2
3
4
VCO output
5
inhibit input
6
C1A
capacitor C1 connection A
capacitor C1 connection B
ground (0 V)
7
C1B
8
GND
9
VCOIN
DEMOUT
R1
VCO input
10
11
12
13
14
15
16
demodulator output
resistor R1 connection
resistor R2 connection
phase comparator 2 output
signal input
R2
PC2OUT
SIGIN
PC3OUT
VCC
phase comparator 3 output
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1997 Nov 25
5
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
C1
6
7
4
3
14
C1
C1
V
COMP
SIG
IN
A
B
CO OUT
IN
4046A
identical to 4046A
R
R
12
11
2
1
PC1
7046A
PHASE
COMPARATOR
1
OUT
2
R2
R1
PC2
PHASE
COMPARATOR
2
OUT 13
VCO
PC2
OUT 13
R3
PHASE
COMPARATOR PCP
2
OUT
1
R4
C2
LOCK
DETECTOR
PC3
PHASE
COMPARATOR
3
OUT 15
LD
1
C
DEM
VCO
IN
LD
INH
OUT
5
10
R
9
MGA847
15
C
CLD
S
(a)
(b)
Fig.4 Functional diagram.
Fig.5 Logic diagram.
6
1997 Nov 25
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
VCC
VDEMOUT = VPC2OUT
=
---------- (φ SIGIN – φCOMPIN
)
π
φDEMOUT = (φSIGIN − φCOMPIN).
Fig.6 Phase comparator 1: average output voltage versus input phase difference.
Fig.7 Typical waveforms for PLL using phase comparator 1, loop locked at fo.
VCC
VDEMOUT = VPC2OUT
=
---------- (φ SIGIN – φCOMPIN
)
4π
φDEMOUT = (φSIGIN − φCOMPIN).
Fig.8 Phase comparator 2: average output voltage versus input phase difference.
7
1997 Nov 25
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
Fig.9 Typical waveforms for PLL using phase comparator 2, loop locked at fo.
VCC
VDEMOUT = VPC3OUT
=
---------- (φ SIGIN – φCOMPIN
2π
)
φDEMOUT = (φSIGIN − φCOMPIN).
Fig.10 Phase comparator 3: average output voltage versus input phase difference:
Fig.11 Typical waveforms for PLL using phase comparator 3, loop locked at fo.
8
1997 Nov 25
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT
74HC
74HCT
SYMBOL
PARAMETER
UNIT CONDITIONS
min. typ. max. min. typ. max.
VCC
VCC
DC supply voltage
3.0
2.0
5.0 6.0
5.0 6.0
4.5
4.5
5.0
5.0
5.5
5.5
V
V
DC supply voltage if VCO
section is not used
VI
DC input voltage range
DC output voltage range
0
VCC
VCC
0
0
VCC
VCC
V
V
VO
0
Tamb
operating ambient
temperature range
−40
+85 −40
+85 °C
see DC and AC
CHARACTERISTICS
Tamb
tr, tf
operating ambient
temperature range
−40
+125 −40
+125 °C
input rise and fall times (pin 5)
6.0 1000
6.0
6.0
6.0
500 ns
500 ns
500 ns
VCC = 2.0 V
VCC = 4.5 V
6.0 500
6.0 400
VCC = 6.0 V
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
PARAMETER
MIN.
MAX. UNIT
CONDITIONS
VCC
±IIK
±IOK
±IO
DC supply voltage
−0.5
+7
20
20
25
V
DC input diode current
DC output diode current
mA
mA
mA
for VI < −0.5 V or VI > VCC + 0.5 V
for VO < −0.5 V or VO > VCC + 0.5 V
for −0.5 V < VO < VCC + 0.5 V
DC output source or sink
current
±ICC; ±IGND DC VCC or GND current
50
mA
Tstg
Ptot
storage temperature range
−65
+150
°C
power dissipation per package
for temperature range: − 40 to +125 °C
74HC/HCT
plastic DIL
750
500
mW
mW
above + 70 °C: derate linearly with 12 mW/K
plastic mini-pack (SO)
above + 70 °C: derate linearly with 8 mW/K
1997 Nov 25
9
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
DC CHARACTERISTICS FOR 74HC
Quiescent supply current
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
VCC
OTHER
(V)
74HC
SYMBOL PARAMETER
+25
UNIT
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
quiescent supply
current (VCO
disabled)
pins 3, 5, and 14 at VCC;
6.0 pin 9 at GND; II at pins
ICC
8.0
80.0
160.0 µA
3 and 14 to be excluded
Phase comparator section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
VCC
(V)
SYM-
BOL
PARAMETER
UNIT
OTHER
+25
−40 to +85 −40 to +125
VI
min. typ. max. min. max. min. max.
VIH
DC coupled
HIGH level input voltage
SIGIN, COMPIN
1.5
1.2
1.5
1.5
V
V
V
2.0
4.5
6.0
2.0
4.5
6.0
3.15 2.4
3.15
4.2
3.15
4.2
4.2
3.2
VIL
DC coupled
LOW level input voltage
SIGIN, COMPIN
0.8 0.5
2.1 1.35
2.8 1.8
2.0
0.5
0.5
1.35
1.8
1.35
1.8
VOH
HIGH level output voltage 1.9
PCPOUT, PCnOUT
1.9
1.9
4.4
5.9
3.7
5.2
2.0 VIH −IO = 20 µA
or
VIL
4.4
4.5
4.4
4.5
6.0
−IO = 20 µA
−IO = 20 µA
5.9
6.0
5.9
VOH
HIGH level output voltage 3.98 4.32
PCPOUT, PCnOUT
3.84
5.34
V
V
4.5 VIH −IO = 4.0 mA
or
VIL
5.48 5.81
6.0
−IO = 5.2 mA
VOL
LOW level output voltage
PCPOUT, PCnOUT
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.4
0.4
2.0 VIH IO = 20 µA
or
VIL
0.1
4.5
6.0
IO = 20 µA
IO = 20 µA
0.1
VOL
LOW level output voltage
PCPOUT, PCnOUT
0.15 0.26
0.16 0.26
0.33
0.33
V
4.5 VIH IO = 4.0 mA
or
6.0
IO = 5.2 mA
VIL
±II
input leakage current
SIGIN, COMPIN
3.0
4.0
5.0
µA
2.0 VCC
or
GND
7.0
9.0
11.0
27.0
45.0
10.0
3.0
18.0
30.0
0.5
23.0
38.0
5.0
4.5
6.0
±IOZ
3-state
µA
6.0 VIH VO = VCC or
OFF-state current
PC2OUT
or
VIL
GND
1997 Nov 25
10
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
T
amb (°C)
TEST CONDITIONS
VCC
74HC
SYM-
PARAMETER
BOL
UNIT
OTHER
(V)
+25
−40 to +85 −40 to +125
VI
min. typ. max. min. max. min. max.
RI
input resistance
SIGIN, COMPIN
800
250
150
kΩ
kΩ
kΩ
3.0 VI at self-bias
operating point;
∆ VI = 0.5 V;
6.0
4.5
see Figs 12, 13
and 14
VCO section
Voltages are referenced to GND (ground = 0 V)
T
amb (°C)
TEST CONDITIONS
74HC
VCC
(V)
SYM-
BOL
PARAMETER
UNIT
OTHER
VI
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
VIH
HIGH level
input voltage
INH
2.1
1.7
2.1
2.1
V
V
V
3.0
4.5
6.0
3.0
4.5
6.0
3.15 2.4
3.15
4.2
3.15
4.2
4.2
3.2
1.3
2.1
2.8
3.0
4.5
6.0
VIL
LOW level
input voltage
INH
0.9
0.9
0.9
1.35
1.8
1.35
1.8
1.35
1.8
VOH
HIGH level
output voltage
VCOOUT
2.9
4.4
5.9
2.9
2.9
4.4
5.9
3.7
5.2
3.0 VIH
−IO = 20 µA
−IO = 20 µA
−IO = 20 µA
−IO = 4.0 mA
−IO = 5.2 mA
or
VIL
4.4
4.5
5.9
6.0
VOH
HIGH level
output voltage
VCOOUT
3.98 4.32
5.48 5.81
3.84
5.34
V
V
4.5 VIH
or
VIL
6.0
VOL
LOW level
output voltage
VCOOUT
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.4
0.4
3.0 VIH
IO = 20 µA
IO = 20 µA
IO = 20 µA
IO = 4.0 mA
IO = 5.2 mA
or
VIL
0.1
4.5
0.1
6.0
VOL
VOL
±II
LOW level
output voltage
VCOOUT
0.15 0.26
0.16 0.26
0.33
0.33
V
4.5 VIH
or
VIL
6.0
LOW level output
voltage C1A, C1B
0.40
0.40
0.47
0.47
0.54
0.54
V
4.5 VIH
IO = 4.0 mA
IO = 5.2 mA
or
VIL
6.0
input leakage
current
INH, VCOIN
0.1
1.0
1.0
µA
kΩ
6.0 VCC
or
GND
R1
resistor range
3.0
3.0
3.0
300
300
300
3.0
4.5
6.0
note 1
1997 Nov 25
11
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
T
amb (°C)
TEST CONDITIONS
VCC
74HC
SYM-
BOL
PARAMETER
UNIT
kΩ
pF
OTHER
(V)
+25
−40 to +85 −40 to +125
VI
min. typ. max. min. max. min. max.
R2
resistor range
3.0
3.0
3.0
40
300
300
300
3.0
4.5
6.0
3.0
4.5
6.0
3.0
4.5
6.0
note 1
C1
capacitor range
no
limit
40
40
VVCOIN operating voltage
range at VCOIN
1.1
1.1
1.1
1.9
3.4
4.9
V
over the range
specified for
R1; for linearity
see Figs 20
and 21
Note
1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/ or
R2 are/is > 10 kΩ.
Demodulator section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
OTHER
74HC
SYMBOL PARAMETER
UNIT
VCC
V
+25
−40 to+85 −40 to +125
min. typ. max. min. max. min. max.
RS
resistor range
50
50
50
300
300
300
kΩ
3.0 at RS > 300 kΩ
the leakage current can
influence VDEMOUT
4.5
6.0
VOFF
offset voltage
VCOIN to VDEMOUT
±30
±20
±10
25
mV 3.0 VI = VVCOIN = 1/2 VCC;
values taken over
RS range; see Fig.15
6.0
4.5
RD
dynamic output
Ω
3.0 VDEMOUT = 1/2 VCC
resistance at DEMOUT
25
4.5
6.0
25
1997 Nov 25
12
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
AC CHARACTERISTICS FOR 74HC
Phase comparator section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
TEST
CONDITIONS
74HC
OTHER
UNIT
SYMBOL PARAMETER
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL
tPLH
/
/
/
propagation delay
SIGIN, COMPIN
to PC1OUT
63
23
18
96
35
28
77
28
22
83
30
24
99
36
29
19
7
200
40
250
50
300
60
ns
ns
ns
ns
ns
ns
mV
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
3.0
4.5
6.0
Fig.16
Fig.16
Fig.16
Fig.17
Fig.17
Fig.16
fi = 1 MHz
34
43
51
tPHL
tPLH
propagation delay
SIGIN, COMPIN
to PCPOUT
340
68
425
85
510
102
87
58
72
tPHL
tPLH
propagation delay
SIGIN, COMPIN
to PC3OUT
270
54
340
68
405
81
46
58
69
tPZH
tPZL
/
/
3-state output enable
time SIGIN, COMPIN
to PC2OUT
280
56
350
70
420
84
48
60
71
tPHZ
tPLZ
3-state output disable
time SIGIN, COMPIN
to PC2OUT
325
65
405
81
490
98
55
69
83
tTHL
/
output transition time
75
95
110
22
tTLH
15
19
6
13
16
19
VI(p-p)
AC coupled input sensitivity
(peak-to-peak value) at
SIGIN or COMPIN
9
11
15
33
1997 Nov 25
13
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
VCO section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
+25
UNIT
OTHER
VCC
(V)
−40 to +85 −40 to +125
min. typ. max. typ. max. min. max.
∆f/T
fo
frequency stability
with temperature
change
0.20
0.15
0.14
%/K 3.0 VI = VVCOIN = 1/2 VCC;
R1 = 100 kΩ; R2 = ∞;
C1 = 100 pF; see Fig.18
4.5
6.0
VCO centre
7.0
10.0
MHz 3.0 VVCOIN = 1/2 VCC;
frequency (duty
factor = 50%)
R1 = 3 kΩ; R2 = ∞;
C1 = 40 pF; see Fig.19
11.0 17.0
4.5
6.0
13.0 21.0
∆fVCO
VCO frequency
linearity
1.0
0.4
0.3
50
%
%
3.0 R1 = 100 kΩ; R2 = ∞;
C1 = 100 pF;
see Figs 20 and 21
6.0
4.5
δVCO
duty factor at
VCOOUT
3.0
4.5
6.0
50
50
DC CHARACTERISTICS FOR 74HCT
Quiescent supply current
Voltages are referenced to GND (ground = 0 V)
T
amb (°C)
74HCT
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
TEST CONDITIONS
SYMBOL PARAMETER
UNIT
OTHER
VCC
(V)
+25
ICC
quiescent supply
current
(VCO disabled)
8.0
80.0
160.0 µA
6.0
pins 3, 5 and 14
at VCC; pin 9 at
GND; II at
pins 3 and 14 to
be excluded
∆ICC
additional quiescent
supply current per
input pin for unit load
coefficient is 1 (note 1)
VI = VCC − 2.1 V
100 360
450
490
µA
4.5
to
5.5
pins 3 and 14
at VCC
;
pin 9 at GND;
II at pins 3 and 14
to be excluded
Note
1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given above.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
INH
1.00
1997 Nov 25
14
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
DC CHARACTERISTICS FOR 74HCT
Phase comparator section
Voltages are referenced to GND (ground = 0 V)
T
amb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VI
OTHER
VCC
(V)
+25
−40 to +85 −40 to +125
min typ. max min max min. max.
VIH
VIL
DC coupled
HIGH level input
voltage SIGIN, COMPIN
3.15 2.4
V
4.5
4.5
DC coupled
LOW level input
voltage
2.1 1.35
V
SIGIN, COMPIN
VOH
VOH
VOL
VOL
±II
HIGH level output
4.4 4.5
3.98 4.32
0
4.4
4.4
3.7
V
4.5 VIH −IO = 20 µA
voltage PCPOUT
PCnOUT
,
or
VIL
HIGH level output
3.84
V
4.5 VIH −IO = 4.0 mA
voltage PCPOUT
PCnOUT
,
or
VIL
LOW level output
voltage
PCPOUT, PCnOUT
0.1
0.1
0.33
38
0.1
0.4
45
V
4.5 VIH IO = 20 µA
or
VIL
LOW level output
voltage
PCPOUT, PCnOUT
0.15 0.26
30
V
4.5 VIH IO = 4.0 mA
or
VIL
input leakage current
SIGIN, COMPIN
µA
5.5 VCC
or
GN
D
±IOZ
3-state OFF-state
current PC2OUT
0.5
5.0
10.0 µA
kΩ
5.5 VIH VO = VCC or
or
GND
VIL
RI
input resistance
SIGIN, COMPin
250
4.5 VI at self-bias
operating
point;
∆ VI = 0.5 V;
see Figs 12, 13 and
14
1997 Nov 25
15
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
DC CHARACTERISTICS FOR 74HCT
VCO section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
+25
UNIT
VI
OTHER
VCC
(V)
−40 to +85 −40 to +125
min typ. max min max min. max.
VIH
VIL
HIGH level
input voltage INH
2.0
1.6
2.0
2.0
V
4.5
to
5.5
LOW level
input voltage INH
1.2 0.8
4.5
0.8
0.8
V
4.5
to
5.5
VOH
VOH
VOL
VOL
VOL
±II
HIGH level output
voltage VCOOUT
4.4
4.4
4.4
3.7
V
4.5 VIH −IO = 20 µA
or
VIL
HIGH level output
voltage VCOOUT
3.98 4.32
3.84
V
4.5 VIH −IO = 4.0 mA
or
VIL
LOW level output
voltage VCOOUT
0
0.1
0.1
0.1
0.4
V
4.5 VIH IO = 20 µA
or
VIL
LOW level output
voltage VCOOUT
0.15 0.26
0.40
0.33
0.47
1.0
V
4.5 VIH IO = 4.0 mA
or
VIL
LOW level output
voltage C1A, C1B
(test purposes only)
0.54
1.0
V
4.5 VIH IO = 4.0 mA
or
VIL
input leakage
current
0.1
µA
5.5 VCC
or
INH, VCOIN
GND
R1
R2
C1
resistor range
resistor range
capacitor range
3.0
3.0
40
300
300
kΩ
kΩ
pF
4.5
4.5
4.5
note 1
note 1
no
limit
VVCOIN
operating voltage
range at VCOIN
1.1
3.4
V
4.5
over the
range
specified for
R1; for
linearity see
Figs 20
and 21
Note
1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2
are/is > 10 kΩ.
1997 Nov 25
16
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
DC CHARACTERISTICS FOR 74HCT
Demodulator section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
OTHER
74HCT
SYMBOL PARAMETER
+25
UNIT
VCC
(V)
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
50 300
RS
resistor range
kΩ
4.5
at RS > 300 kΩ
the leakage current can
influence VDEMOUT
VOFF
offset voltage
VCOIN to
VDEMOUT
±20
mV
4.5
4.5
VI = VVCOIN = 1/2 VCC
values taken over
RS range; see Fig.15
;
RD
dynamic output
resistance at
DEMOUT
25
Ω
VDEMOUT = 1/2 VCC
AC CHARACTERISTICS FOR 74HCT
Phase comparator section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
OTHER
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL
tPLH
/
/
/
propagation delay
SIGIN, COMPIN
to PC1OUT
23
35
28
30
40
68
54
56
50
85
68
70
60
ns
4.5
4.5
4.5
4.5
Fig.16
Fig.16
Fig.16
Fig.17
tPHL
tPLH
propagation delay
SIGIN, COMPIN
to PCPOUT
102 ns
tPHL
tPLH
propagation delay
SIGIN, COMPIN
to PC3OUT
81
84
ns
ns
tPZH
tPZL
/
3-state output enable
time SIGIN, COMPIN
to PC2OUT
1997 Nov 25
17
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
OTHER
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHZ
tPLZ
/
3-state output disable
time SIGIN, COMPIN
to PC2OUT
36
65
15
81
19
98
22
ns
4.5
Fig.17
tTHL
tTLH
VI (p-p)
/
output transition time
7
ns
4.5
4.5
Fig.16
AC coupled input
sensitivity
15
mV
fi = 1 MHz
(peak-to-peak value)
at
SIGIN or COMPIN
VCO section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
74HCT
−40 to +85 −40 to +125
TEST CONDITIONS
SYMBOL PARAMETER
UNIT
OTHER
VCC
(V)
+25
min. typ. max min. max min. max.
∆f/T
frequency stability
with temperature
change
0.15
%/K 4.5
VI = VVCOIN withi
n recommended
range;
R1 = 100 kΩ;
R2 = ∞;
C1 = 100 pF;
see Fig.18b
fo
VCO centre frequency 11.0 17.0
(duty factor = 50%)
MHz 4.5
VVCOIN = 1/2 VCC
;
R1 = 3 kΩ;
R2 = ∞;
C1 = 40 pF;
see Fig.19
∆fVCO
VCO frequency
linearity
0.4
50
%
%
4.5
4.5
R1 = 100 kΩ;
R2 = ∞;
C1 = 100 pF;
see Figs 20
and 21
δVCO
duty factor at VCOOUT
1997 Nov 25
18
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
FIGURE REFERENCES FOR DC CHARACTERISTICS
Fig.12 Typical input resistance curve at SIGIN,
COMPIN.
Fig.13 Input resistance at SIGIN, COMPIN with
∆VI = 0.5 V at self-bias point.
RS = 50 kΩ
- - - - RS = 300 kΩ
Fig.14 Input current at SIGIN, COMPIN with
Fig.15 Offset voltage at demodulator output as a
function of VCOIN and RS.
∆VI = 0.5 V at self-bias point.
1997 Nov 25
19
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
Fig.16 Waveforms showing input (SIGIN, COMPIN) to output (PCPOUT, PC1OUT, PC3OUT) propagation delays
and the output transition times.
(1) HC : VM = 50%; VI = GND to VCC
Fig.17 Waveforms showing the 3-state enable and disable times for PC2OUT
.
1997 Nov 25
20
MSB710
MSB711
MSB712
25
25
25
book, halfpage
handbook, halfpage
handbook, halfpage
V
=
∆
CC
3 V
5 V
f
∆ f
(%)
∆ f
(%)
(%)
3 V
5 V
20
20
15
20
15
6 V
6 V
V
=
15
CC
V
=
CC
6 V
5 V
3 V
3 V
3 V
5 V
6 V
A
10
5
10
5
10
5
5 V
6 V
3 V
4.5 V
5 V
6 V
0
0
0
−5
−10
−15
−20
5
10
15
20
5
10
15
20
−25
−50
25
50
25
50
0
50
100
150
0
50
100
T
150
0
50
100
T
150
o
o
o
T
( C)
( C)
( C)
amb
amb
amb
(a)
(b)
(c)
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
Fig.18 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter.
without offset (R2 = ∞): (a) R1 = 3 kΩ; (b) R1 = 10 kΩ; (c) R1 = 300 kΩ.
− − − with offset
In (b), the frequency stability for R1 = R2 = 10 kΩ at 5 V is also given (curve A). This curve is set by the total VCO bias current, and is
not simply the addition of the two 10 kΩ stability curves. C1 = 100 pF; VVCO IN = 0.5 VCC
(R1 = ∞): (a) R2 = 3 kΩ; (b) R2 = 10 kΩ; (c) R2 = 300 kΩ.
.
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
(d) R2 = 3 kΩ
R1 = ∞
(e) R2 = 10 kΩ
R1 = ∞
(f) R2 = 300 kΩ
R1 = ∞
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
Fig.18 Continued.
1997 Nov 25
22
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
(b) R1 = 3 kΩ;
C1 = 100 nF
(a) R1 = 3 kΩ;
C1 = 40 pF
(d) R1 = 300 kΩ;
C1 = 100 nF
(c) R1 = 300 kΩ;
C1 = 40 pF
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
Fig.19 Graphs showing VCO frequency (fVCO) as a function of the VCO input voltage (VVCOIN).
1997 Nov 25
23
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
Fig.20 Definition of VCO frequency linearity:
∆V = 0.5 V over the VCC range:
for VCO linearity
f1 + f2
f‘ =
--------------
0
2
f‘0 – f
0 × 100%
----------------
Fig.21 Frequency linearity as a function of R1, C1
linearity =
f‘0
and VCC: R2 = ∞ and ∆V = 0.5 V.
C1 = 40 pF
- - - -C1 = 1 µF
C1 = 40 pF
- - - - C1 = 1 µF
Fig.24 Typical dc power
Fig.22 Power dissipation
versus the value of R1:
CL = 50 pF;
Fig.23 Power dissipation
versus the value of R2:
CL = 50 pF;
dissipation of
demodulator sections
as a function of RS:
R1 = R2 = ∞;
R2 = ∞;
R1 = ∞;
VVCOIN = 1/2 VCC
Tamb = 25 °C.
;
VVCOIN = GND = 0 V;
Tamb = 25 °C.
Tamb = 25 °C;
VVCOIN = 1/2 VCC.
1997 Nov 25
24
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
APPLICATION INFORMATION
This information is a guide for the approximation of values of external components to be used with the 74HC/HCT4046A
in a phase-lock-loop system.
References should be made to Figs 29, 30 and 31 as indicated in the table.
Values of the selected components should be within the following ranges:
R1
R2
between 3 kΩ and 300 kΩ;
between 3 kΩ and 300 kΩ;
R1 + R2 parallel value > 2.7 kΩ;
C1
greater than 40 pF.
PHASE
COMPARATOR
SUBJECT
DESIGN CONSIDERATIONS
VCO frequency characteristic
VCO frequency
without extra
offset
PC1, PC2 or PC3
With R2 = ∞ and R1 within the range 3 kΩ < R1 < 300 kΩ, the
characteristics of the VCO operation will be as shown in Fig.25.
(Due to R1, C1 time constant a small offset remains when R2 = ∞.).
Fig.25 Frequency characteristic of VCO operating without offset:
f0 = centre frequency; 2fL = frequency lock range.
Selection of R1 and C1
PC1
Given fo, determine the values of R1 and C1 using Fig.29.
PC2 or PC3
Given fmax and fo, determine the values of R1 and C1 using Fig.29, use
Fig.31 to obtain 2fL and then use this to calculate fmin
.
1997 Nov 25
25
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
PHASE
SUBJECT
DESIGN CONSIDERATIONS
VCO frequency characteristic
COMPARATOR
VCO frequency
with extra
offset
PC1, PC2 or PC3
With R1 and R2 within the ranges 3 kΩ < R1 < 300 kΩ,
3 kΩ < R2 < 300 kΩ, the characteristics of the VCO operation will be as
shown in Fig.26.
Fig.26 Frequency characteristic of VCO operating with offset:
fo = centre frequency; 2fL = frequency lock range.
Selection of R1, R2 and C1
PC1, PC2 or PC3
Given fo and fL, determine the value of product R1C1 by using Fig.31.
Calculate foff from the equation foff = fo
1.6fL.
Obtain the values of C1 and R2 by using Fig.30.
Calculate the value of R1 from the value of C1 and the product R1C1.
PLL conditions
with no signal at
the SIGIN input
PC1
PC2
PC3
VCO adjusts to fo with φDEMOUT = 90° and VVCOIN = 1/2 VCC (see Fig.6).
VCO adjusts to fo with φDEMOUT = −360° and VVCOIN = min. (see Fig.8).
VCO adjusts to fo with φDEMOUT = −360° and VVCOIN = min. (see Fig.10).
1997 Nov 25
26
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
PHASE
SUBJECT
DESIGN CONSIDERATIONS
COMPARATOR
PLL frequency
capture range
PC1, PC2 or PC3
Loop filter component selection
(a) τ = R3 x C2 (b) amplitude characteristic (c) pole-zero diagram
1
π
A small capture range (2f ) is obtained if 2f ≈
2 π f L ⁄ τ
--
c
c
Fig. 27 Simple loop filter for PLL without offset; R3 ≥ 500 Ω.
(a) τ1 = R3 x C2; (b) amplitude characteristic (c) pole-zero diagram
τ2 = R4 x C2;
τ3 = (R3 + R4) x C2
Fig.28 Simple loop filter for PLL with offset; R3 + R4 ≥ 500 Ω.
PLL locks on
harmonics at
centre frequency
PC1 or PC3
PC2
yes
no
noise rejection at
signal input
PC1
high
PC2 or PC3
PC1
low
AC ripple content
when PLL is
locked
fr = 2fi, large ripple content at φDEMOUT = 90°
fr = fi, small ripple content at φDEMOUT = 0°
fr = fi, large ripple content at φDEMOUT = 180°
PC2
PC3
1997 Nov 25
27
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.
Interpolation for various values of R1 can be easily calculated because a constant R1C1 product will produce almost the same VCO output frequency.
Fig.29 Typical value of VCO centre frequency (fo) as a function of C1: R2 = ∞; VVCOIN = 1/2 VCC; INH = GND;
Tamb = 25 °C.
1997 Nov 25
28
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.
Interpolation for various values of R2 can be easily calculated because a constant R2C1 product will produce almost the same VCO output frequency.
Fig.30 Typical value of frequency offset as a function of C1: R1 = ∞; VVCOIN = 1/2 VCC; INH = GND; Tamb = 25 °C.
1997 Nov 25
29
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
Fig.31 Typical frequency lock range (2fL) versus the product R1C1: VVCOIN range = 0.9 to (VCC − 0.9) V;
R2 = ∞; VCO gain:
2fL
------------------------------------
VVCOIN range
˙
2 π (r ⁄ s ⁄ V) .
KV
=
1997 Nov 25
30
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
PLL design example
The VCO gain is:
and the damping value ζ is defined as
follows:
˙
2fL × 2 × π
The frequency synthesizer, used in
the design example shown in Fig.32,
has the following parameters:
Kv
=
=
----------------------------------------------
1 + Kp × Kv × Kn × τ2
1
0.9 – (VCC – 0.9)
ζ =
×
---------- -----------------------------------------------------
2ωn (τ1 + τ2)
Output frequency: 2 MHz to 3 MHz
frequency steps : 100 kHz
1 MHz
-----------------
3.2
In Fig.33 the output frequency response to
a step of input frequency is shown.
=
× 2 π ≈ 2 × 106 r/s/V
settling time
overshoot
:
:
1 ms
< 20%
The overshoot and settling time
percentages are now used to determine
ωn. From Fig.33 it can be seen that the
damping ratio ζ = 0.45 will produce an
overshoot of less than 20% and settle to
within 5% at ωnt = 5. The required settling
time is 1 ms.
The gain of the phase
comparator is:
The open-loop gain is
H (s) x G (s) = Kp × Kf × Ko × Kn.
VCC
Kp
=
= 0.4 V/r.
------------
4 × π
Where:
The transfer gain of the filter is
given by:
Kp = phase comparator gain
Kf = low-pass filter transfer gain
Ko = Kv/s VCO gain
This results in:
1 + τ2s
Kf =
.
------------------------------------
5
--
t
5
1 + (τ1 + τ2) s
Kn = 1/n divider ratio
ω n
=
=
= 5 × 103 r/s.
--------------
0.001
The programmable counter ratio
Kn can be found as follows:
Where:
Rewriting the equation for natural
frequency results in:
τ 1 = R3C2 and τ2 = R4C2.
fout
2 MHz
---------------------
100 kHz
Nmin.
=
=
= 20
----------
fstep
Kp × Kv × Kn
The characteristics equation is:
1 + H (s) × G (s) = 0.
(τ1 + τ2) =
.
-------------------------------
ω2n
This results in:
fout
3 MHz
---------------------
100 kHz
The maximum overshoot occurs at Nmax.:
Nmax.
=
=
= 30
----------
fstep
1 + Kp × Kv × Kn × τ
s2 +
2s+
0.4 × 2 × 106
50002 × 30
-----------------------------------------------------
(τ1 + τ2)
(τ 1 + τ 2 ) =
= 0.0011 s.
---------------------------------
The VCO is set by the values of R1,
R2 and C1, R2 = 10 kΩ (adjustable).
The values can be determined using
the information in the section
“DESIGN CONSIDERATIONS”.
With fo = 2.5 MHz and fL = 500 kHz
this gives the following values
(VCC = 5.0 V):
Kp × Kv × Kn
When C2 = 470 nF, then
(τ1 + τ2) × 2 × ωn × ζ – 1
= 0.
-------------------------------
(τ1 + τ2)
R4 =
= 315 Ω
----------------------------------------------------------------
Kp × Kv × Kn × C2
The natural frequency ωn is
defined as follows:
now R3 can be calculated:
Kp × Kv × Kn
τ1
ωn
=
------------------------------- .
R1 = 10 kΩ
R2 = 10 kΩ
R3 =
– R4 = 2 kΩ.
-------
(τ1 + τ2)
C2
C1 = 500 pF
1997 Nov 25
31
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
Fig.32 Frequency synthesizer.
note
For an extensive description and application example
please refer to application note ordering number
9398 649 90011.
Also available a computer design program for PLL’s
ordering number 9398 961 10061.
MSB740
0.6
1.6
= 0.3
0.5
0.707
1.0
ζ
1.4
1.2
0.4
0.2
∆ω (t)
∆Θ (t)
e
e
∆ω /ω
∆Θ /ω
e
n
e n
= 5.0
ζ
0
1.0
0.8
= 2.0
ζ
0.2
0.6
0.4
0.2
0.4
0.6
0.8
0
1.0
0
1
2
3
4
5
6
7
8
ω
t
n
Fig.33 Type 2, second order frequency step response.
Since the output frequency is proportional to the VCO
control voltage, the PLL frequency response can be
observed with an oscilloscope by monitoring pin 9 of the
VCO. The average frequency response, as calculated by
the Laplace method, is found experimentally by smoothing
this voltage at pin 9 with a simple RC filter, whose time
constant is long compared to the phase detector sampling
rate but short compared to the PLL response time.
Fig.34 Frequency compared to the time response.
1997 Nov 25
32
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
WAVE SOLDERING
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
DIP
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
Even with these conditions:
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
• Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
• Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
REPAIRING SOLDERED JOINTS
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
SO, SSOP and TSSOP
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
REPAIRING SOLDERED JOINTS
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method.
1997 Nov 25
33
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
74HC/HCT4046A
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Nov 25
34
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