74F533PC [FAIRCHILD]
Octal Transparent Latch with 3-STATE Outputs; 八路透明锁存器具有三态输出
| 型号： | 74F533PC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Transparent Latch with 3-STATE Outputs |
| 文件： | 总6页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised August 1999
74F533
Octal Transparent Latch with 3-STATE Outputs
General Description
Features
■ Eight latches in a single package
■ 3-STATE outputs for bus interfacing
■ Inverted version of the 74F373
The 74F533 consists of eight latches with 3-STATE outputs
for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state. The 74F533 is the same as the
74F373, except that the outputs are inverted.
Ordering Code:
Order Number Package Number
Package Description
74F533SC
74F533SJ
74F533PC
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009548
www.fairchildsemi.com
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Data Inputs
Output IOH/IOL
HIGH/LOW
1.0/1.0
D0–D7
LE
20 µA/−0.6 mA
20 µA/−0.6 mA
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Complementary 3-STATE Outputs
1.0/1.0
OE
1.0/1.0
20 µA/−0.6 mA
O0–O7
150/40 (33.3)
−3 mA/24 mA (20 mA)
Function Table
Functional Description
The 74F533 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
Inputs
Output
LE
H
H
L
OE
L
D
H
L
O
L
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
L
H
L
X
X
O0
Z
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to
−55°C to +125°C
−55°C to +150°C
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
Ground Pin
−0.5V to +7.0V
−0.5V to +7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−30 mA to +5.0 mA
−0.5V to VCC
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
3-STATE Output
−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
4000V
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
Input Clamp Diode Voltage
−1.2
Min
Min
I
I
I
I
I
I
= −18 mA
CD
OH
IN
Output HIGH
Voltage
10% V
2.5
2.4
2.7
2.7
= −1 mA
= −3 mA
= −1 mA
= −3 mA
= 24 mA
= 2.7V
CC
OH
OH
OH
OH
OL
10% V
CC
V
5% V
5% V
CC
CC
V
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown (I/O)
Output HIGH
10% V
0.5
5.0
V
Min
OL
CC
I
I
µA
Max
V
IH
IN
BVI
7.0
0.5
50
µA
mA
µA
V
Max
Max
Max
0.0
V
= 7.0V
= 5.5V
IN
I
I
BVIT
CEX
V
V
IN
= V
OUT
CC
Leakage Current
Input Leakage
V
I
= 1.9 µA
ID
ID
4.75
Test
All Other Pins Grounded
= 150 mV
I
Output Leakage
Circuit Current
V
IOD
OD
3.75
µA
0.0
All Other Pins Grounded
I
I
I
I
I
I
Input LOW Current
Output Leakage Current
Output Leakage Current
−0.6
50
mA
µA
Max
Max
Max
Max
0.0V
Max
V
V
V
V
V
V
= 0.5V
IL
IN
= 2.7V
= 0.5V
= 0V
OZH
OZL
OS
OUT
OUT
OUT
OUT
−50
−150
500
61
µA
Output Short-Circuit Current
Bus Drainage Test
−60
mA
µA
= 5.25V
ZZ
Power Supply Current
41
mA
= HIGH Z
O
CCZ
3
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AC Electrical Characteristics
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
CC
Symbol
Parameter
Units
C
C
L
L
Min
4.0
2.5
Typ
6.7
4.4
Max
9.0
Min
4.0
2.5
Max
Min
4.0
2.5
Max
t
Propagation Delay
to O
12.0
9.0
10.0
8.0
PLH
ns
t
7.0
D
PHL
n
n
t
Propagation Delay
5.0
3.0
7.1
4.7
11.0
7.0
5.0
3.0
14.0
9.0
5.0
3.0
13.0
8.0
PLH
ns
ns
ns
t
LE to O
n
PHL
t
Output Enable Time
2.0
2.0
1.5
1.5
5.9
5.6
3.4
2.7
10.0
7.5
2.0
2.0
1.5
1.5
12.5
10.5
8.5
2.0
2.0
1.5
1.5
11.0
8.5
7.0
6.5
PZH
t
PZL
t
Output Disable Time
6.5
PHZ
t
5.5
7.5
PLZ
AC Operating Requirements
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
Symbol
Parameter
V
= +5.0V
V
= +5.0V
V = +5.0V
CC
Units
CC
CC
Min
2.0
2.0
3.0
3.0
6.0
Max
Min
2.0
2.0
3.0
3.0
6.0
Max
Min
2.0
2.0
3.0
3.0
6.0
Max
t (H)
Setup Time, HIGH or LOW
to LE
S
ns
t (L)
D
n
S
t
t
t
(H)
(L)
Hold Time, HIGH or LOW
to LE
H
ns
ns
D
H
n
(H)
LE Pulse Width, HIGH
W
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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相关型号：
74F533SCQR
Bus Driver, F/FAST Series, 1-Func, 8-Bit, Inverted Output, TTL, PDSO20, 0.150 INCH, SOIC-20
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