74F533PMX [NSC]
Octal Transparent Latch with TRI-STATE Outputs; 八路透明锁存器具有三态输出
| 型号： | 74F533PMX |
| 厂家： | 
National Semiconductor |
| 描述： | Octal Transparent Latch with TRI-STATE Outputs |
| 文件： | 总8页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1995
54F/74F533
Octal Transparent Latch with TRI-STATE Outputs
É
General Description
Features
Y
Eight latches in a single package
The ’F533 consists of eight latches with TRI-STATE outputs
for bus organized system applications. The flip-flops appear
transparent to the data when Latch Enable (LE) is HIGH.
When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH the bus output is in the high
impedance state. The ’F533 is the same as the ’F373, ex-
cept that the outputs are inverted.
Y
TRI-STATE outputs for bus interfacing
Y
Inverted version of the ’F373
Y
Guaranteed 4000V minimum ESD protection
Package
Commercial
74F533PC
Military
Package Description
Number
N20A
J20A
20-Lead (0.300 Wide) Molded Dual-In-Line
×
54F533DM (Note 2)
20-Lead Ceramic Dual-In-Line
74F533SC (Note 1)
74F533SJ (Note 1)
M20B
M20D
W20A
E20A
20-Lead (0.300 Wide) Molded Small Outline, JEDEC
×
20-Lead (0.300 Wide) Molded Small Outline, EIAJ
×
54F533FM (Note 2)
54F533LM (Note 2)
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
e
Note 1: Devices also available in 13 reel. Use suffix
SCX and SJX.
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
Pin Assignment
for LCC
IEEE/IEC
TL/F/9548–3
TL/F/9548–4
TL/F/9548–2
TL/F/9548–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9548
RRD-B30M75/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I /I
HIGH/LOW
OH OL
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
D –D
0
Data Inputs
1.0/1.0
1.0/1.0
7
LE
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Complementary TRI-STATE Outputs
b
OE
1.0/1.0
20 mA/ 0.6 mA
b
O –O
0
150/40 (33.3)
3 mA/24 mA (20 mA)
7
Function Table
Inputs
Output
O
LE
OE
D
H
H
L
L
L
H
L
L
H
L
X
X
O
0
X
H
Z
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
Functional Description
The ’F533 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D inputs enters the latches. In this condition
n
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D in-
puts a setup time preceding the HIGH-to-LOW transition of
LE. The TRI-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Logic Diagram
TL/F/9548–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
b
a
55 C to 125 C
§
0 C to 70 C
§
§
b
b
a
65 C to 150 C
Storage Temperature
§
§
§
§
§
a
§
a
55 C to 125 C
Ambient Temperature under Bias
§
Supply Voltage
Military
Commercial
b
b
a
a a
4.5V to 5.5V
a a
4.5V to 5.5V
Junction Temperature under Bias
Plastic
55 C to 175 C
§
§
a
55 C to 150 C
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
b
a
30 mA to 5.0 mA
e
in HIGH State (with V
Standard Output
TRI-STATE Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
54F/74F
Symbol
Parameter
Units
V
CC
Conditions
Min
Typ
Max
V
V
V
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
1.2
Min
Min
I
IN
CD
OH
e b
e b
e b
e b
e b
e b
Output HIGH
Voltage
54F 10% V
2.5
2.4
2.5
2.4
2.7
2.7
I
I
I
I
I
I
1 mA
3 mA
1 mA
3 mA
1 mA
3 mA
CC
CC
CC
CC
OH
OH
OH
OH
OH
OH
54F 10% V
74F 10% V
74F 10% V
V
74F 5% V
74F 5% V
CC
CC
e
e
V
Output LOW
Voltage
54F 10% V
74F 10% V
0.5
I
I
20 mA
24 mA
OL
CC
OL
OL
V
Min
Max
Max
Max
Max
0.0
0.5
CC
I
I
I
I
Input HIGH
Current
54F
74F
20.0
5.0
IH
e
e
e
mA
mA
mA
mA
V
V
V
V
V
2.7V
7.0V
5.5V
IN
IN
IN
Input HIGH Current
Breakdown Test
54F
74F
100
7.0
BVI
Input HIGH Current
Breakdown (I/O)
54F
74F
1.0
0.5
BVIT
CEX
Output HIGH
54F
74F
250
50
e
V
CC
OUT
Leakage Current
e
All Other Pins Grounded
V
ID
Input Leakage
Test
I
ID
1.9 mA
74F
74F
4.75
e
IOD
All Other Pins Grounded
I
Output Leakage
Circuit Current
V
150 mV
OD
3.75
mA
0.0
b
e
0.5V
I
I
I
I
I
I
Input LOW Current
0.6
mA
mA
mA
mA
mA
mA
Max
Max
Max
Max
0.0V
Max
V
V
V
V
V
V
IL
IN
e
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
50
2.7V
0.5V
0V
OZH
OZL
OS
OUT
OUT
OUT
OUT
b
e
e
e
50
b
b
60
150
500
61
5.25V
ZZ
e
Power Supply Current
41
3
HIGH Z
CCZ
O
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
e
50 pF
T
, V
CC
e
Mil
T
, V
A CC
Com
A
e a
Symbol
Parameter
V
Units
CC
e
C
C
L
L
e
C
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
t
t
Propagation Delay
4.0
2.5
6.7
4.4
9.0
7.0
4.0
2.5
12.0
9.0
4.0
2.5
10.0
8.0
PLH
ns
ns
ns
ns
D
n
to O
n
PHL
t
t
Propagation Delay
LE to O
5.0
3.0
7.1
4.7
11.0
7.0
5.0
3.0
14.0
9.0
5.0
3.0
13.0
8.0
PLH
PHL
n
t
t
Output Enable Time
2.0
2.0
5.9
5.6
10.0
7.5
2.0
2.0
12.5
10.5
2.0
2.0
11.0
8.5
PZH
PZL
t
t
Output Disable Time
1.5
1.5
3.4
2.7
6.5
5.5
1.5
1.5
8.5
7.5
1.5
1.5
7.0
6.5
PHZ
PLZ
AC Operating Requirements
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
T
, V
CC
Mil
Max
T
, V
CC
Com
Max
Units
A
A
e a
V
CC
Min
Max
Min
Min
t (H)
s
Setup Time, HIGH or LOW
2.0
2.0
2.0
2.0
2.0
2.0
ns
t (L)
s
D to LE
n
t (H)
h
Hold Time, HIGH or LOW
D to LE
n
3.0
3.0
3.0
3.0
3.0
3.0
ns
ns
t (L)
h
t (H)
w
LE Pulse Width, HIGH
6.0
6.0
6.0
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:
74F 533
S
C
X
Temperature Range Family
Special Variations
e
e
e
e
74F
54F
Commercial
Military
X
QB
Devices shipped in 13 reels
×
Military grade device with
environmental and burn-in
processing shipped in tubes
Device Type
Package Code
Temperature Range
e
e
e
e
e
e
P
D
F
L
S
SJ
Plastic DIP
Ceramic DIP
Flatpak
Leadless Chip Carrier (LCC)
Small Outline SOIC JEDEC
Small Outline SOIC EIAJ
e
e
a
C
M
Commercial (0 C to 70 C)
§
§
b a
Military ( 55 C to 125 C)
§
§
4
Physical Dimensions inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
5
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300 Wide) Molded Small Outline Package, JEDEC (S)
×
NS Package Number M20B
20-Lead (0.300 Wide) Molded Small Outline Package, EIAJ (SJ)
×
NS Package Number M20D
6
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300 Wide) Molded Dual-In-Line Package (P)
×
NS Package Number N20A
7
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
LIFE SUPPORT POLICY
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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