74F109PCQR [FAIRCHILD]
J-Kbar Flip-Flop, F/FAST Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP16, PLASTIC, DIP-16;
| 型号： | 74F109PCQR |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | J-Kbar Flip-Flop, F/FAST Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP16, PLASTIC, DIP-16 触发器 |
| 文件： | 总7页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised September 2000
74F109
Dual JK Positive Edge-Triggered Flip-Flop
Asynchronous Inputs:
General Description
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
The F109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D-type flip-flop (refer
to F74 data sheet) by connecting the J and K inputs.
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes
both Q and Q HIGH
Ordering Code:
Order Number Package Number
Package Description
74F109SC
74F109SJ
74F109PC
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009471
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Truth Table
Inputs
Outputs
SD
CD
CP
X
J
X
X
X
I
K
X
X
X
I
Q
H
L
Q
L
L
H
L
H
L
X
H
H
H
L
X
H
L
H
H
H
H
H
H
H
H
H
H
h
I
I
Toggle
h
h
X
Q
H
Q
Q
L
h
X
L
Q
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
= LOW-to-HIGH Transition
X = Immaterial
Q
0 (Q0) = Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
Unit Loading/Fan Out
U.L.
Input IIH/IIL
Pin Names
Description
HIGH/LOW Output IOH/IOL
J1, J2, K1, K2 Data Inputs
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
50/33.3
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−1.8 mA
20 µA/−1.8 mA
−1 mA/20 mA
CP1, CP2
D1, CD2
SD1, SD2
Q1, Q2, Q1, Q2 Outputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
C
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to
−65°C to +150°C
−55°C to +125°C
−55°C to +175°C
Free Air Ambient Temperature
0°C to +70°C
+4.5V to +5.5V
Supply Voltage
Ground Pin
−0.5V to +7.0V
−0.5V to +7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with Vcc = 0V)
Standard Output
−30 mA to +5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
VIL
Input LOW Voltage
0.8
VCD
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
−1.2
Min
Min
I
I
I
I
IN = −18 mA
OH = −1 mA
OH = −1 mA
OL = 20 mA
10% VCC
5% VCC
2.5
2.7
V
VOL
IIH
Output LOW Voltage
Input HIGH Current
10% VCC
0.5
5.0
7.0
50
V
Min
Max
Max
Max
µA
µA
µA
V
V
V
IN = 2.7V
IN = 7.0V
OUT = VCC
IBVI
ICEX
VID
Input HIGH Current Breakdown Test
Output HIGH Leakage Current
Input Leakage Test
I
ID = 1.9 µA
All Other Pins Grounded
IOD = 150 mV
All Other Pins Grounded
4.75
V
0.0
0.0
IOD
Output Leakage
Circuit Current
V
3.75
µA
IIL
Input LOW Current
−0.6
−1.8
−150
17.0
mA
mA
mA
mA
Max
Max
Max
Max
V
V
V
IN = 0.5V (Jn, Kn)
IN = 0.5V (CDn, SDn
OUT = 0V
)
IOS
ICC
Output Short-Circuit Current
Power Supply Current
−60
11.7
CP = 0V
3
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AC Electrical Characteristics
T
A = +25°C
T
A = 0°C to +70°C
CC = +5.0V
L = 50 pF
Max
V
CC = +5.0V
V
Symbol
Parameter
Units
C
L = 50 pF
C
Min
100
3.8
4.4
3.2
Typ
125
5.3
6.2
5.2
Max
Min
90
fMAX
Maximum Clock Frequency
MHz
ns
tPLH
tPHL
tPLH
Propagation Delay
CPn to Qn or Qn
7.0
8.0
7.0
3.8
4.4
3.2
8.0
9.2
8.0
Propagation Delay
ns
tPHL
CDn or SDn to
Qn or Qn
3.5
7.0
9.0
3.5
10.5
ns
AC Operating Requirements
T
A = +25°C
CC = +5.0V
Max
T
A = 0°C to +70°C
CC = +5.0V
Max
Symbol
Parameter
V
V
Units
Min
3.0
3.0
1.0
1.0
4.0
5.0
Min
3.0
3.0
1.0
1.0
4.0
5.0
tS(H)
Setup Time, HIGH or LOW
Jn or Kn to CPn
tS(L)
tH(H)
tH(L)
tW(H)
tW(L)
ns
ns
Hold Time, HIGH or LOW
Jn or Kn to CPn
CPn Pulse Width
HIGH or LOW
tW(L)
tREC
CDn or SDn Pulse Width LOW
Recovery Time
4.0
2.0
4.0
2.0
ns
ns
CDn or SDn to CP
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4
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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