74F109SC [TI]
Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop; 双JK （注：横线在K）正边沿触发触发器
| 型号： | 74F109SC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop |
| 文件： | 总12页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
54F109,74F109
Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop
Literature Number: SNOS149A
November 1994
54F/74F109
Dual JK Positive Edge-Triggered Flip-Flop
LOW input to CD sets Q to LOW level
General Description
Clear and Set are independent of clock
The ’F109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop (refer to ’F74
data sheet) by connecting the J and K inputs.
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
n Guaranteed 4000V mnimum ESD .
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
Ordering Code: See Section 0
DSXXX
Commercial
Military
Package
Number
N16E
Descript
74F109PC
16-Lead (0e) Mold Dual-in-Line
Lead CeDual-in-L
54F109DM (Note 2)
J16A
74F109SC (Note 1)
74F109SJ (Note 1)
M16A
16-d (0.15ide) Mded Small Outline,
JEDEC
M16D
-Lead (0" Wide) Molded Small Outline,
54F109FM (Note 2)
54F109LM (Note 2)
W1
E20
Cerpack
Ceramic Leadless Chip Carrier, Type C
=
Note 1: Devices also available in 13" reel. Use suffix Sand SJX.
=
Note 2: Military grade device with environmental and n-in processing. Use suffix DMQB, FMQB and LMQB.
Logic Symbols
IEEE/IEC
DS009471-4
DS009471-6
FAST® and TRI-STATE® are registered trademarks of National Semiconductor Corporation.
© 1997 National Semiconductor Corporation
DS009471
www.national.com
1
PrintDate=1997/08/28 PrintTime=11:45:22 10182 ds009471 Rev. No. 1 cmserv Proof
1
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
Pin Assignment
for LCC
DS009471-1
Unit Loading/Fan Out
See Section 0 for U.L. definitions
DSXXX
54F/74
Pin Names
Description
U.L.
HIGH/LOW
1.0/1
Input IL
Output IOH
/−0.6 mA
µA/−6 mA
20 µA/−8 mA
20 µA/.8 mA
mA/20 mA
J1, J2, K1, K2
CP1, CP2
Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
1.0
C
D1, CD2
1.0/
S
D1, SD2
1.0/3.
Q1, Q2, Q1, Q2
/33.3
Truth Table
Inputs
Output
SD
L
CD
H
L
CP
X
J
X
X
X
l
K
X
X
X
l
Q
L
L
H
L
X
H
H
L
X
H
N
N
N
H
H
H
H
H
H
H
H
H
H
h
l
Toggle
Q0
H
Q0
L
L
Q0
Q0
H (hel
L
ransition of Clock
te of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
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2
PrintDate=1997/08/28 PrintTime=11:45:23 10182 ds009471 Rev. No. 1 cmserv Proof
2
Logic Diagram (One Half Shown)
DS-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used propagatilays
3
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PrintDate=1997/08/28 PrintTime=11:45:24 10182 ds009471 Rev. No. 1 cmserv Proof
3
Absolute Maximum Ratings (Note 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
4000V
ESD Last Passing Voltage (Min)
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
−65˚C to +150˚C
−55˚C to +125˚C
−55˚C to +175˚C
−55˚C to +150˚C
−55˚C to +125˚C
0˚C to +70˚C
VCC Pin Potential to
Ground Pin
Commercial
−0.5V to +7.0V
−0.5V to +7.0V
Supply Voltage
Military
Input Voltage (Note 4)
Input Current (Note 4)
Voltage Applied to Output
+4.5V to +5.5V
+4.5V to +5.5V
−30 mA to +5.0 mA
Commercial
Note 3: Absolute maximum ratings are ich the device may
be damaged or have its useful life impaoperatin under these
conditions is not implied.
=
in HIGH State (with VCC 0V)
Standard Output
TRI-STATE® Output
−0.5V to VCC
Note 4: Either voltagit ourrent fficient to pct inputs.
−0.5V to +5.5V
DC Electrical Characteristics
Symbol
Parameter
54F/74F
Typ
VCC
Conditions
Min
M
VIH
Input HIGH Voltage
2.0
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
VIL
Input LOW Voltage
0.
=
Min IIN −18 mA
VCD
VOH
Input Clamp Diode Voltage
−1.2
=
IOH −1 mA
Output HIGH
Voltage
54F 10% VCC
2.5
2
=
Min IOH −1 mA
74F 10% VCC
74F 5% VCC
54F 10% VCC
74F 10% VCC
54F
V
V
=
IOH −1 mA
=
Min IOL 20 mA
VOL
Output LOW
Voltage
0.5
0.5
20.0
5.0
100
7.0
250
50
=
IOL 20 mA
=
Max VIN 2.7V
IIH
Input HIGH
µA
µA
µA
V
Current
74F
=
Max VIN 7.0V
IBVI
ICEX
VID
IOD
IIL
Input HIGH Current
Breakdown Test
Output HIGH
Leakage rent
Input Leakag
T
54F
74F
=
Max VOUT VCC
=
4.75
0.0
0.0
IID 1.9 µA
All Other Pins Grounded
=
age
nt
3.75
µA
VIOD 150 mV
All Other Pins Grounded
=
Max VIN 0.5V (Jn, Kn)
−0.6
−1.8
−150
17.0
mA
mA
mA
mA
=
Max VIN 0.5V (CDn, SDn
)
=
Max VOUT 0V
IOS
ICC
uit Current
Current
−60
=
11.7
Max CP 0V
AC Electrical Characteristics
See Section 0 for Waveforms and Load Configurations
74F
DSXXX
54F
74F
=
=
=
TA +25˚C
TA, VCC Mil
TA, VCC Com
Fig.
No.
=
=
=
Symbol
Parameter
VCC +5.0V
CL 50 pF
CL 50 pF
Units
=
CL 50 pF
Min
Typ
Max
Min
70
Max
Min
90
Max
fmax
Maximum Clock
Frequency
100
125
MHz
kk
-kk
DSXXX
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PrintDate=1997/08/28 PrintTime=11:45:27 10182 ds009471 Rev. No. 1 cmserv Proof
4
AC Electrical Characteristics (Continued)
See Section 0 for Waveforms and Load Configurations
DSXXX
74F
54F
74F
=
=
=
TA +25˚C
TA, VCC Mil
TA, VCC Com
Fig.
No.
=
=
=
Symbol
Parameter
VCC +5.0V
CL 50 pF
CL 50 pF
Units
ns
=
CL 50 pF
Min
3.8
4.4
3.2
3.5
Typ
5.3
6.2
5.2
7.0
Max
7.0
8.0
7.0
9.0
Min
Max
9.0
Min
Max
8.0
tPLH
tPHL
tPLH
tPHL
Propagation Delay
CPn to Qn or Qn
Propagation Delay
CDn or SDn to
3.8
4.4
3.2
3.5
3.8
4.4
3.2
3.5
kk
kk
-
kk
kk
DSXXX
DSXXX
10.5
9.0
9.2
8.0
11.5
10.5
-
Qn or Qn
AC Operating Requirements
See Section 0 for Waveforms
DSXXX
74F
54F
74
=
=
=
Symbol
Parameter
TA +25˚C
TA, VCC Mil
, VCC C
Units
Fig.
No.
=
VCC +5.0V
Min
3.0
3.0
1.0
1.0
4.0
5.0
4.0
Max
Min
3
4.0
1.0
1.0
M
n
3.0
3.0
1.0
4.0
5.0
4.0
Max
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
tw(L)
Setup Time, HIGH or LOW
Jn or Kn to CPn
ns
kk
-
kk
DSXXX
Hold Time, HIGH or LOW
Jn or Kn to CPn
CPn Pulse Width
HIGH or LOW
ns
ns
ns
kk
kk
kk
-kk
-kk
-kk
DSXXX
DSXXX
DSXXX
CDn or SDn Pulse Width,
LOW
trec
Recovery Time
2.0
2.0
CDn or SDn to CP
Ordering Information
The device number is used torm ied pursing code where the package type and temperature range are de-
fined as follows:
Book
Extract
End
DS009471-7
5
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PrintDate=1997/08/28 PrintTime=11:45:30 10182 ds009471 Rev. No. 1 cmserv Proof
5
THIS PAGE IS IGNORED IN THE DATABOOK
6
PrintDate=1997/08/28 PrintTime=11:45:31 10182 ds009471 Rev. No. 1 cmserv Proof
6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Ceramic Lea(L)
NS Package N
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
7
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PrintDate=1997/08/28 PrintTime=11:45:32 10182 ds009471 Rev. No. 1 cmserv Proof
7
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead (0.150" Wide) Molded SmOutline kage, JEDC (S)
NS Package NumM16A
16-Lead (0.300" Wide) Molded Small Outline Package, EIAJ (SJ)
NS Package Number M16D
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8
PrintDate=1997/08/28 PrintTime=11:45:32 10182 ds009471 Rev. No. 1 cmserv Proof
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead (0.300" Wide) Molded Dual-In-Line Pack
NS Package Number N16E
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
9
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9
PrintDate=1997/08/28 PrintTime=11:45:33 10182 ds009471 Rev. No. 1 cmserv Proof
9
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