74ALVCH16374T [FAIRCHILD]
Low Voltage 16-Bit D-Type Flip-Flop with Bushold; 低电压16位D型触发器与Bushold
| 型号： | 74ALVCH16374T |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit D-Type Flip-Flop with Bushold |
| 文件： | 总7页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2001
Revised February 2002
74ALVCH16374
Low Voltage 16-Bit D-Type Flip-Flop with Bushold
General Description
Features
The ALVCH16374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
■ 1.65V to 3.6V VCC supply operation
■ 3.6V tolerant control inputs and outputs
■ Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
■ tPD
The ALVCH16374 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
4.2 ns max for 3.0V to 3.6V VCC
5.3 ns max for 2.3V to 2.7V VCC
7.8 ns max for 1.65V to 1.95V VCC
The 74ALVCH16374 is designed for low voltage (1.65V to
3.6V) VCC applications with output compatibility up to 3.6V.
■ Uses patented noise/EMI reduction circuitry
■ Latch-up conforms to JEDEC JED78
■ ESD performance:
The 74ALVCH16374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Human body model > 2000V
Machine model > 200V
Ordering Code:
Package
Order Number
Package Descriptions
Number
74ALVCH16374T
(Note 1)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation
DS500627
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Connection Diagrams
Pin Descriptions
Pin Assignment for TSSOP
Pin Names
Description
OEn
Output Enable Input (Active LOW)
Clock Pulse Input
Bushold Inputs
CPn
I0–I15
O0–O15
NC
Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
O0
O2
NC
O1
OE1
NC
CP1
NC
NC
I1
I0
I2
O4
O3
VCC
VCC
I3
I4
O6
O5
GND GND
GND GND
GND GND
I5
I6
O8
O7
I7
I8
O10
O12
O14
O9
I9
I10
I12
I14
G
H
O11
O13
VCC
NC
VCC
NC
I11
I13
J
O15
NC
OE2
CP2
NC
I15
Truth Tables
Inputs
Outputs
O0–O7
CP1
OE1
I0–I7
Pin Assignment for FBGA
L
L
H
L
H
L
L
L
X
X
O0
Z
X
H
Inputs
OE2
Outputs
O8–O15
CP2
I8–I15
L
L
H
L
H
L
L
L
X
X
O0
Z
(Top Thru View)
X
H
H
L
= HIGH Voltage Level
= LOW Voltage Level
X
Z
O
= Immaterial (HIGH or LOW, control inputs may not float)
= High Impedance
0 = Previous O0 before HIGH-to-LOW of CP
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2
Functional Description
The 74ALVCH16374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte func-
tioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each clock has a buffered clock and buffered Output
Enable common to all flip-flops within that byte. The
description which follows applies to each byte. Each
flip-flop will store the state of their individual I inputs that
meet the setup and hold time requirements on the
LOW-to-HIGH Clock (CPn) transition. With the Output
Enable (OEn) LOW, the contents of the flip-flops are avail-
able at the outputs. When OEn is HIGH, the outputs go to
the high impedance state. Operations of the OEn input
does not affect the state of the flip-flops.
Logic Diagram
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to 4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO) (Note 3)
−0.5V to VCC +0.5V
Operating
1.65V to 3.6V
0V to VCC
DC Input Diode Current (IIK
)
Input Voltage (VI)
VI < 0V
−50 mA
−50 mA
±50 mA
Output Voltage (VO)
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (∆t/∆V)
0V to VCC
DC Output Diode Current (IOK
O < 0V
DC Output Source/Sink Current
(IOH/IOL
)
−40°C to +85°C
V
V
IN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
)
DC VCC or GND Current per
Supply Pin (ICC or GND)
±100 mA
Storage Temperature Range (TSTG
)
−65°C to +150°C
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Conditions
Min
Max
Units
(V)
HIGH Level Input Voltage
1.65 - 1.95 0.65 x VCC
2.3 - 2.7
2.7 - 3.6
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
1.65 - 3.6
1.65
1.7
2.0
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.35 x VCC
0.7
V
V
0.8
VOH
I
OH = 100 µA
OH = −4 mA
OH = −6 mA
OH = −12 mA
VCC - 0.2
1.2
I
I
2.3
2.0
I
2.3
1.7
2.7
2.2
3.0
2.4
I
OH = −24 mA
OL = 100 µA
OL = 4 mA
OL = 6 mA
OL = 12 mA
3.0
2
VOL
LOW Level Output Voltage
I
1.65 - 3.6
1.65
0.2
0.45
0.4
I
I
2.3
V
I
2.3
0.7
2.7
0.4
I
OL = 24 mA
3.0
0.55
±5.0
II
Input Leakage Current
Bushold Input Maximum
Drive Hold Current
0 ≤ VI ≤ 3.6V
3.6
µA
II(HOLD)
VIN = 0.58V
VIN = 1.07V
VIN = 0.7V
VIN = 1.7V
VIN = 0.8V
VIN = 2.0V
1.65
25
−25
45
1.65
2.3
2.3
−45
75
µA
3.0
3.0
−75
0 < VO ≤ 3.6V
0 ≤ VO ≤ 3.6V
3.6
±500
±10
40
IOZ
3-STATE Output Leakage
Quiescent Supply Current
Increase in ICC per Input
3.6
µA
µA
µA
ICC
VI = VCC or GND, IO = 0
IH = VCC − 0.6V
3.6
∆ICC
V
3 - 3.6
750
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4
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500Ω
C
L = 50 pF
C
L = 30 pF
CC = 1.8V ± 0.15V
Symbol
Parameter
Units
V
CC = 3.3V ± 0.3V
VCC = 2.7V
V
CC = 2.5V ± 0.2V
V
Min
Max
Min
Max
Min
Max
Min
Max
fCLOCK
Clock Frequency
150
150
150
100
MHz
ns
tW
Pulse Width
3.3
1.9
0.5
150
1.0
1.0
1.0
3.3
2.2
0.5
150
3.3
2.1
0.6
150
1.0
1.0
1.0
4.0
2.5
1.0
100
1.5
1.5
1.5
tS
Setup Time
ns
tH
Hold Time
ns
fMAX
Maximum Clock Frequency
Propagation Delay
Output Enable Time
Output Disable Time
MHz
ns
tPHL, tPLH
tPZL, tPZH
PLZ, tPHZ
4.2
4.8
4.3
4.9
5.9
4.7
5.3
6.2
5.3
7.8
9.2
6.8
ns
t
ns
Capacitance
T
A = +25°C
Symbol
Parameter
Conditions
Units
VCC
Typical
CIN
Input Capacitance
Control
Data
VI = 0V or VCC
VI = 0V or VCC
VI = 0V or VCC
3.3
3.3
3.3
3.3
2.5
3.3
2.5
3
6
pF
pF
COUT
CPD
Output Capacitance
Power Dissipation Capacitance
7
Outputs Enabled f = 10 MHz, CL = 50 pF
30
31
18
16
pF
Outputs Disabled f = 10 MHz, CL = 50 pF
5
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AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
SWITCH
Open
VL
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
2.5V ± 0.2V
VCC/2
1.8V ± 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
1.5V
VCC/2
VCC/2
V
OL + 0.3V
V
OL + 0.3V
V
OL + 0.15V
VOL + 0.15V
VY
V
OH − 0.3V
V
OH − 0.3V
V
OH − 0.15V
V
OH − 0.15V
VL
6V
6V
VCC*2
VCC*2
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
REC Waveforms
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
t
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6
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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