74ALVCH16409DGGRG4 [TI]
ALVC/VCX/A SERIES, DUAL 9-BIT EXCHANGER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56;型号: | 74ALVCH16409DGGRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | ALVC/VCX/A SERIES, DUAL 9-BIT EXCHANGER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56 光电二极管 输出元件 逻辑集成电路 |
文件: | 总11页 (文件大小:145K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G–JULY 1995–REVISED OCTOBER 2004
FEATURES
DGG OR DL PACKAGE
(TOP VIEW)
•
Member of the Texas Instruments Widebus™
Family
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PRE
SEL0
1A1
GND
1A2
CLK
SELEN
1B1
GND
1B2
•
UBE™ (Universal Bus Exchanger) Allows
Synchronous Data Exchange
2
3
•
•
•
•
Operates From 1.65 V to 3.6 V
Max tpd of 5.1 ns at 3.3 V
4
5
±24-mA Output Drive at 3.3 V
6
1A3
1B3
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
7
V
CC
V
CC
8
1A4
1A5
1A6
GND
1A7
1A8
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B4
1B5
1B6
GND
1B7
1B8
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
•
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
This 9-bit, 4-port universal bus exchanger is designed
for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16409 allows synchronous data
exchange between four different buses. Data flow is
controlled by the select (SEL0–SEL4) inputs. A
data-flow state is stored on the rising edge of the
clock (CLK) input if the select-enable (SELEN) input
is low. Once a data-flow state has been established,
data is stored in the flip-flop on the rising edge of
CLK if SELEN is high.
V
CC
V
CC
2A7
2A8
2B7
2B8
GND
2A9
SEL1
SEL2
GND
2B9
SEL4
SEL3
The data-flow control logic is designed to allow
glitch-free data transmission.
When preset (PRE) transitions high, the outputs are
disabled immediately, without waiting for a clock
pulse. To leave the high-impedance state, both PRE
and SELEN must be low, and a clock pulse must be
applied.
To ensure the high-impedance state during power up or power down, PRE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74ALVCH16409DL
TOP-SIDE MARKING
ALVCH16409
Tube
SSOP - DL
-40°C to 85°C
Tape and reel
Tape and reel
SN74ALVCH16409DLR
TSSOP - DGG
SN74ALVCH16409DGGR
ALVCH16409
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBE are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G–JULY 1995–REVISED OCTOBER 2004
FUNCTION TABLES
INPUTS
OUTPUT
RECEIVE PORT
CLK
X
SEND PORT
(1)
X
L
B0
X
L
H
L
X
H
L
↑
↑
H
X
X
H
(1)
H
L
B0
(1)
B0
(1) Output level before the indicated steady-state input conditions were
established
DATA-FLOW CONTROL
INPUTS
DATA FLOW
PRE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
SELEN
CLK
X
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
SEL0
X
X
0
SEL1
X
X
0
SEL2
X
X
0
SEL3
X
X
0
SEL4
X
X
0
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
All outputs disabled
No change
None, all I/Os off
Not used
0
0
0
0
1
0
0
0
1
0
Not used
0
0
0
1
1
Not used
0
0
1
0
0
Not used
0
0
1
0
1
Not used
0
0
1
1
0
Not used
0
0
1
1
1
Not used
0
1
0
0
0
2A to 1A and 1B to 2B
2A to 1A
0
1
0
0
1
0
1
0
1
0
2B to 1B
0
1
0
1
1
2A to 1A and 2B to 1B
1A to 2A and 1B to 2B
1A to 2A
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
1B to 2B
0
1
1
1
1
1A to 2A and 2B to 1B
1A to 1B and 2B to 2A
1A to 1B
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
2A to 2B
1
0
0
1
1
1A to 1B and 2A to 2B
1B to 1A and 2A to 2B
1B to 1A
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
2B to 2A
1
0
1
1
1
1B to 1A and 2B to 2A
2B to 1A and 2A to 1B
1B to 2A
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
2B to 1A
1
1
0
1
1
2B to 1A and 1B to 2A
1A to 2B and 1B to 2A
1A to 2B
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
2A to 1B
1
1
1
1
1
1A to 2B and 2A to 1B
2
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G–JULY 1995–REVISED OCTOBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
56
1
28
29
30
CLK
PRE
55
SELEN
SEL2
SEL3
2
SEL0
SEL1
Flow and Storage Control
27
SEL4
3
3
2Ax 1Ax
1Bx 2Ax
2Bx 2Bx
CLK
D
CLK
D
1A
2A
1B
2B
1Bx
CLK
1Ax
CLK
3
3
1Ax
1Bx
2Bx
1Ax
2Ax
1Bx
D
D
2Ax
2Bx
One of Nine Channels
3
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G–JULY 1995–REVISED OCTOBER 2004
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
-0.5
-0.5
-0.5
-0.5
MAX
4.6
UNIT
VCC
VI
Supply voltage range
Input voltage range
V
Except I/O ports(2)
I/O ports(2)(3)
4.6
V
VCC + 0.5
VCC + 0.5
-50
VO
IIK
Output voltage range(2)(3)
Input clamp current
V
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
-50
Continuous output current
Continuous current through each VCC or GND
±50
±100
64
DGG package
DL package
θJA
Package thermal impedance(4)
Storage temperature range
°C/W
°C
56
Tstg
-65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
MAX
UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
V
0.35 × VCC
0.7
0.8
VCC
VCC
-4
VIL
Low-level input voltage
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
-12
-12
-24
4
IOH
High-level output current
Low-level output current
mA
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
12
IOL
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
TA
-40
85
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G–JULY 1995–REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN TYP(1) MAX UNIT
VCC - 0.2
IOH = -100 µA
IOH = -4 mA
IOH = -6 mA
1.2
2
VOH
2.3 V
1.7
2.2
2.4
2
V
IOH = -12 mA
2.7 V
3 V
IOH = -24 mA
IOL = 100 µA
IOL = 4 mA
IOL = 6 mA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
VOL
V
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
VI = VCC or GND
VI = 0.58 V
VI = 1.07 V
VI = 0.7 V
3 V
0.55
±5
II
3.6 V
µA
1.65 V
1.65 V
2.3 V
25
-25
45
II(hold)
VI = 1.7 V
2.3 V
-45
75
µA
VI = 0.8 V
3 V
VI = 2 V
3 V
-75
VI = 0 to 3.6 V(2)
3.6 V
±500
±10
40
(3)
IOZ
VO = VCC or GND
3.6 V
µA
µA
µA
pF
pF
ICC
∆ICC
Ci
VI = VCC or GND, IO = 0
One input at VCC - 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
3.6 V
3 V to 3.6 V
3.3 V
750
Control inputs
A or B ports
4
8
Cio
VO = VCC or GND
3.3 V
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
5
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G–JULY 1995–REVISED OCTOBER 2004
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
120
MIN
MAX
MIN
MAX
120
(1)
fclock
tw
Clock frequency
120
MHz
ns
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Pulse duration, CLK high or low
4.2
1.9
5.1
2.5
1
4.2
1.9
4.2
2.5
1
3
1.4
3.5
1.8
0.7
1
A or B before CLK↑
SEL before CLK↑
SELEN before CLK↑
PRE before CLK↑
A or B after CLK↑
SEL after CLK↑
tsu
Setup time
Hold time
ns
ns
0.8
0
0.8
0
th
0
SELEN after CLK↑
0.5
0.5
0.8
(1) This information was not available at the time of publication.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN TYP MIN MAX MIN MAX MIN MAX
(1)
fmax
tpd
120
1.5
2.4
2.3
2.8
120
120
1.5
2
MHz
ns
(1)
(1)
(1)
(1)
CLK
CLK
CLK
PRE
A or B
A or B
6
6.9
7.1
7.5
5.7
6.3
6
5.1
5.7
5.7
6.1
ten
ns
2
tdis
A or B
ns
6.5
2.5
(1) This information was not available at the time of publication.
OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
Power dissipation
capacitance
per exchanger
TEST CONDITIONS
UNIT
TYP
TYP
TYP
(1)
All outputs enabled
All outputs disabled
60
60
Cpd
CL = 50 pF, f = 10 MHz
pF
(1)
60
60
(1) This information was not available at the time of publication.
6
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G–JULY 1995–REVISED OCTOBER 2004
TIMING DIAGRAM
CLK
t
t
t
su
h
h
SELEN
t
su
SEL(0−4)
t
su
t
h
Selected
Input Port
Selected
Output Port
t
pd
CLK to Output
7
SN74ALVCH16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES022G–JULY 1995–REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
S1
GND
t
Open
V
LOAD
GND
pd
/t
/t
C
t
t
L
PLZ PZL
R
L
(see Note A)
PHZ PZH
LOAD CIRCUIT
INPUT
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
V
/2
/2
2 × V
2 × V
6 V
6 V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
t
w
V
I
V
I
V
M
V
M
Input
Timing
Input
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
I
Output
Control
(low-level
enabling)
Data
Input
V
I
V
V
M
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at V
LOAD
(see Note B)
V
V
/2
LOAD
V
I
V
M
Input
V
M
V
M
V + V
∆
OL
0 V
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− V
∆
V
M
Output
V
M
V
M
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
74ALVCH16409DLG4
SN74ALVCH16409DL
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SSOP
SSOP
DL
56
56
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
ALVCH16409
ACTIVE
DL
20
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 85
ALVCH16409
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
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