74ACT843SPC [FAIRCHILD]
9-Bit Transparent Latch; 9位透明锁存器
| 型号： | 74ACT843SPC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 9-Bit Transparent Latch |
| 文件： | 总6页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1988
Revised September 2000
74ACT843
9-Bit Transparent Latch
General Description
The ACT843 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths.
Features
■ TTL compatible inputs
■ 3-STATE outputs for bus interfacing
Ordering Code:
Order Number Package Number
Package Description
74ACT843SC
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACT843SPC
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D8
Description
Data Inputs
Data Outputs
Output Enable
Latch Enable
Clear
O0–O8
OE
LE
CLR
PRE
Preset
FACT is a trademark of Fairchild Semiconductor Corporation
© 2000 Fairchild Semiconductor Corporation
DS009800
www.fairchildsemi.com
Functional Description
The ACT843 consists of nine D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion. On the LE HIGH-to-LOW transition, the data that
meets the setup times is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state. In addition to
the LE and OE pins, the ACT843 has a Clear (CLR) pin
and a Preset (PRE) pin. These pins are ideal for parity bus
interfacing in high performance systems. When CLR is
LOW, the outputs are LOW if OE is LOW. When CLR is
HIGH, data can be entered into the latch. When PRE is
LOW, the outputs are HIGH if OE is LOW. Preset overrides
CLR.
Function Tables
Inputs
Internal
Outputs
Function
High Z
CLR
H
H
H
H
H
H
H
L
PRE
H
H
H
H
H
H
L
OE
H
H
H
L
LE
H
H
L
D
L
Q
L
O
Z
H
X
L
H
Z
High Z
NC
L
Z
Latched
H
H
L
L
Transparent
Transparent
Latched
L
H
X
X
X
X
X
X
H
H
NC
H
L
L
NC
H
L
X
X
X
L
Preset
H
L
L
L
Clear
L
L
H
H
Z
Preset
L
H
L
H
H
L
Clear/High Z
Preset/High Z
H
L
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC +0.5V
Output Voltage (VO)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC +0.5V
Operating Temperature (TA)
−40°C to +85°C
125 mV/ns
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
V
V
O = −0.5V
−20 mA
+20 mA
V
IN from 0.8V to 2.0V
O = VCC +0.5V
VCC @ 4.5V, 5.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC +0.5V
or Sink Current (IO)
±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
140°C
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
VOUT = 0.1V
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
1.5
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
1.5
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
O = 24 mA
OL = 24 mA (Note 2)
IIN
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum
5.5
5.5
5.5
±0.1
±0.5
±1.0
±5.0
1.5
µA
µA
VI = VCC, GND
IOZ
VI = VIL, VIH
VO = VCC, GND
ICCT
0.6
mA
VI = VCC − 2.1V
ICC/Input
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
OLD = 1.65V Max
VOHD = 3.85V Min
IN = VCC
−75
V
5.5
8.0
80.0
µA
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
3
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AC Electrical Characteristics
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 4)
Min
Typ
Max
Min
tPLH
Propagation Delay
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
2.5
5.5
5.5
5.5
5.5
6.5
7.5
5.5
5.5
6.0
6.0
6.0
5.5
9.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
10.0
10.0
10.0
10.0
16.0
17.5
10.5
10.5
11.0
11.0
11.0
10.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Dn to On
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPHL
tPLH
Propagation Delay
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
9.5
9.0
Dn to On
Propagation Delay
LE to On
Propagation Delay
LE to On
9.0
Propagation Delay
PRE to On
14.0
15.5
9.5
Propagation Delay
CLR to On
Output Enable Time
OE to On
Output Enable Time
OE to On
9.5
Output Disable Time
OE to On
10.5
10.5
10.5
9.5
Output Disable Time
OE to On
Propagation Delay
PRE to On
Propagation Delay
CLR to On
Note 4: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements
VCC
T
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
C
C
L = 50 pF
Symbol
Parameter
(V)
Units
(Note 5)
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
5.0
5.0
−0.5
0.5
2.0
1.0
ns
ns
D
n to LE
Hold Time, HIGH or LOW
n to LE
tH
0.5
2.0
D
tW
tW
tW
LE Pulse Width, HIGH
PRE Pulse Width, LOW
CLR Pulse Width, LOW
PRE Recovery Time
CLR Recovery Time
5.0
5.0
5.0
5.0
5.0
2.0
5.0
3.5
8.5
9.5
2.0
1.0
3.5
10.0
11.0
2.0
ns
ns
ns
ns
ns
5.5
trec
trec
0.5
−0.5
1.0
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
4.5
44
Units
pF
Conditions
CIN
Input Capacitance
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
pF
V
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4
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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