74ACT843SPCQR [NSC]
IC AC SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDIP24, 0.300 INCH, SLIM, PLASTIC, DIP-24, Bus Driver/Transceiver;
| 型号： | 74ACT843SPCQR |
| 厂家： | 
National Semiconductor |
| 描述： | IC AC SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDIP24, 0.300 INCH, SLIM, PLASTIC, DIP-24, Bus Driver/Transceiver 锁存器 |
| 文件： | 总10页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1993
74AC843 74ACT843
#
9-Bit Transparent Latch
General Description
The ’AC/’ACT843 bus interface latch is designed to elimi-
nate the extra packages required to buffer existing latches
and provide extra data width for wider address/data paths.
Features
Y
’ACT843 has TTL-compatible inputs
Y
TRI-STATE outputs for bus interfacing
É
The ’AC/’ACT843 is functionally and pin compatible with
AMD’s Am29843.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP and SOIC
TL/F/9800–1
IEEE/IEC
TL/F/9800–2
TL/F/9800–3
Pin Names
D –D
Description
Data Inputs
Data Outputs
Output Enable
Latch Enable
Clear
0
8
O –O
0
OE
8
LE
CLR
PRE
Preset
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation
FACTTM is a trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL/F/9800
RRD-B30M75/Printed in U. S. A.
Functional Description
The ’AC/’ACT843 consists of nine D-type latches with
TRI-STATE outputs. The flip-flops appear transparent to the
data when Latch Enable (LE) is HIGH. This allows asyn-
chronous operation, as the output transition follows the data
in transition. On the LE HIGH-to-LOW transition, the data
that meets the setup times is latched. Data appears on the
bus when the Output Enable (OE) is LOW. When OE is
HIGH, the bus output is in the high impedance state. In
addition to the LE and OE pins, the ’AC/’ACT843 has a
Clear (CLR) pin and a Preset (PRE) pin. These pins are ideal
for parity bus interfacing in high performance systems.
When CLR is LOW, the outputs are LOW if OE is LOW.
When CLR is HIGH, data can be entered into the latch.
When PRE is LOW, the outputs are HIGH if OE is LOW.
Preset overrides CLR.
Function Tables
Inputs
OE
Internal
Q
Outputs
O
Function
CLR
PRE
LE
D
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
L
H
H
L
L
H
X
L
L
H
Z
Z
High Z
High Z
NC
L
Z
Latched
H
H
L
L
Transparent
Transparent
Latched
L
H
X
X
X
X
X
X
H
H
NC
H
L
L
NC
H
L
X
X
X
L
Preset
H
L
L
L
Clear
L
L
H
H
Z
Preset
L
H
L
H
H
L
Clear/High Z
Preset/High Z
H
L
H
Z
e
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
Z
High Impedance
e
NC
No Change
Logic Diagram
TL/F/9800–5
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (V
’AC
’ACT
)
CC
2.0V to 6.0V
4.5V to 5.5V
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
DC Input Diode Current (I
)
IK
Input Voltage (V )
I
0V to V
0V to V
CC
e b
b
a
V
I
V
I
0.5V
a
20 mA
20 mA
Output Voltage (V
)
O
CC
e
V
CC
0.5V
Operating Temperature (T )
A
74AC/ACT
b
b
a
0.5V
DC Input Voltage (V )
I
0.5V to V
0.5V to V
CC
b
a
40 C to 85 C
§
§
DC Output Diode Current (I
)
OK
Minimum Input Edge Rate (DV/Dt)
’AC Devices
e b
b
a
V
V
0.5V
a
20 mA
20 mA
O
O
e
V
CC
0.5V
V
V
from 30% to 70% of V
@
IN
CC
a
0.5V
DC Output Voltage (V
DC Output Source
)
O
CC
3.3V, 4.5V, 5.5V
125 mV/ns
125 mV/ns
CC
Minimum Input Edge Rate (DV/Dt)
’ACT Devices
g
or Sink Current (I
)
O
50 mA
DC V
or Ground Current
V
V
from 0.8V to 2.0V
@
CC
IN
g
per Output Pin (I or I
CC
)
50 mA
4.5V, 5.5V
GND
)
CC
b
a
65 C to 150 C
Storage Temperature (T
§
§
STG
Junction Temperature (T )
J
PDIP
140 C
§
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACTTM circuits outside databook specifications.
DC Electrical Characteristics for ’AC Family Devices
74AC
74AC
e
T
A
V
CC
(V)
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
40 C to 85 C
§
Guaranteed Limits
§
Typ
e
0.1V
V
V
V
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.1
2.1
V
IH
OUT
b
2.25
2.75
3.15
3.85
3.15
3.85
V
V
V
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
0.9
0.9
V
OUT
0.1V
IL
b
2.25
2.75
1.35
1.65
1.35
1.65
or V
CC
0.1V
e b
OUT
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
50 mA
OH
e
*V
IN
V
or V
IH
12 mA
IL
b
b
b
3.0
4.5
5.5
2.56
3.86
4.86
2.46
3.76
4.76
V
V
I
24 mA
24 mA
OH
e
I
OUT
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
50 mA
e
*V
IN
V
IL
or V
IH
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
24 mA
24 mA
V
I
OL
e
I
Maximum Input
Leakage Current
V
I
V
CC
, GND
IN
g
g
1.0
5.5
0.1
mA
*All outputs loaded; thresholds on input associated with output under test.
3
DC Electrical Characteristics for ’AC Family Devices (Continued)
74AC
74AC
e
T
A
V
CC
(V)
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
40 C to 85 C
§
Guaranteed Limits
§
Typ
e
I
Maximum TRI-STATE
Leakage Current
V (OE)
I
V
, V
IL IH
OZ
e
g
g
5.0
5.5
0.5
mA
V
V
V
, GND
CC
I
e
V
CC
, GND
O
e
e
²
I
I
I
Minimum Dynamic
5.5
5.5
75
mA
mA
V
V
V
1.65V Max
3.85V Min
OLD
OHD
CC
OLD
OHD
Output Current
b
75
e
Maximum Quiescent
Supply Current
V
CC
IN
5.5
8.0
80.0
mA
or GND
²
Maximum test duration 2.0 ms, one output loaded at a time.
@
@
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V
Note: I and I
IN
.
CC
CC
DC Electrical Characteristics for ’ACT Family Devices
74ACT
74ACT
e
T
A
V
CC
(V)
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
40 C to 85 C
§
Guaranteed Limits
§
Typ
e
0.1V
V
V
V
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
IH
OUT
V
V
V
b
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
OUT
0.1V
IL
b
or V
CC
0.1V
e b
OUT
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
50 mA
OH
e
*V
IN
V
IL
or V
IH
24 mA
24 mA
b
b
4.5
5.5
3.86
4.86
3.76
4.76
V
V
I
OH
e
e
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
I
50 mA
OUT
*V
IN
V or V
IL IH
4.5
5.5
0.36
0.36
0.44
0.44
24 mA
V
I
OL
24 mA
e
I
I
I
Maximum Input
Leakage Current
V
V
, GND
CC
IN
I
g
g
g
g
5.5
5.5
5.5
0.1
0.5
1.0
5.0
mA
mA
mA
e
Maximum TRI-STATE
Leakage Current
V
V
V , V
IL IH
OZ
I
e
V
, GND
CC
O
e
b
2.1V
Maximum
V
V
CC
CCT
I
0.6
1.5
75
I
/Input
CC
e
²
I
I
I
Minimum Dynamic
5.5
5.5
mA
mA
V
V
V
1.65V Max
e
3.85V Min
OLD
OHD
CC
OLD
Output Current
b
75
OHD
e
Maximum Quiescent
Supply Current
V
CC
IN
5.5
8.0
80.0
mA
or GND
*All outputs loaded; thresholds on input associated with output under test.
²
Maximum test duration 2.0 ms, one output loaded at a time.
4
AC Electrical Characteristics
74AC
74AC
e b
T
40 C
§
A
e a
A
V
*
T
25 C
§
50 pF
CC
a
Symbol
Parameter
to 85 C
Units
§
50 pF
e
(V)
C
L
e
C
L
Min
Typ
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
Propagation Delay
3.3
5.0
3.5
2.0
6.5
4.5
12.0
8.5
2.5
1.5
13.0
9.0
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PHL
PLH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
n
to O
n
Propagation Delay
to O
3.3
5.0
4.0
2.5
7.0
5.0
12.0
8.5
3.0
1.5
13.0
9.0
D
n
n
Propagation Delay
LE to O
3.3
5.0
3.5
2.0
6.5
4.5
12.0
8.5
13.0
1.5
2.5
9.0
n
Propagation Delay
LE to O
3.3
5.0
4.0
2.5
7.0
5.0
12.0
8.5
3.0
1.5
13.0
9.0
n
Propagation Delay
PRE to O
3.3
5.0
5.5
3.5
8.5
6.0
19.0
13.0
4.5
2.5
21.5
14.5
n
Propagation Delay
CLR to O
3.3
5.0
7.5
5.0
11.0
7.5
21.5
15.0
6.0
4.0
24.0
17.0
n
Output Enable Time
OE to O
3.3
5.0
3.5
2.0
6.0
4.5
11.0
8.0
3.0
1.5
12.0
9.0
n
Output Enable Time
OE to O
3.3
5.0
4.0
2.0
6.5
5.0
11.0
8.0
2.5
1.5
12.0
9.0
n
Output Disable Time
OE to O
3.3
5.0
4.0
3.0
6.5
5.0
10.5
8.0
3.5
2.5
11.0
8.5
n
Output Disable Time
OE to O
3.3
5.0
3.0
2.0
6.0
4.5
10.5
8.0
2.5
1.5
11.0
8.5
n
Propagation Delay
PRE to O
3.3
5.0
4.5
3.0
7.0
5.0
12.5
9.0
3.5
2.0
13.5
9.5
n
Propagation Delay
CLR to O
3.3
5.0
4.5
3.0
7.0
5.0
12.5
9.0
3.5
2.0
13.5
9.5
n
g
*Voltage Range 3.3 is 3.3V 0.3V
g
*Voltage Range 5.0 is 5.0V 0.5V
5
AC Operating Requirements
74AC
74AC
e b
a
T
40 C
§
§
A
e a
V
*
T
25 C
§
50 pF
CC
A
Symbol
Parameter
Units
to 85 C
e
(V)
C
L
e
C
50 pF
L
Typ
Guaranteed Minimum
t
t
t
t
t
t
t
Setup Time, HIGH or LOW
3.3
5.0
0
3.0
1.5
3.5
2.0
s
ns
ns
ns
ns
ns
ns
ns
b
D
n
to LE
0.5
Hold Time, HIGH or LOW
to LE
3.3
5.0
2.0
2.5
2.0
2.5
h
b
D
n
0.5
LE Pulse Width, HIGH
PRE Pulse Width, LOW
CLR Pulse Width, LOW
PRE Recovery Time
CLR Recovery Time
3.3
5.0
1.5
3.0
3.0
3.0
3.0
w
1.5
3.3
5.0
5.0
3.0
12.0
8.5
14.5
10.0
w
3.3
5.0
5.5
4.0
14.0
10.0
16.5
12.0
w
3.3
5.0
1.0
0
3.0
1.5
3.0
1.5
rec
rec
3.3
5.0
0
1.5
0.5
1.5
0.5
b
0.5
g
*Voltage Range 3.3 is 3.3V 0.3V
g
*Voltage Range 5.0 is 5.0V 0.5V
6
AC Electrical Characteristics
74ACT
74ACT
e b
T
40 C
§
to 85 C
A
e a
A
V
*
T
25 C
§
50 pF
CC
a
e
Symbol
Parameter
Units
§
50 pF
e
(V)
C
L
C
L
Min
Typ
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
Propagation Delay
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PHL
PLH
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
2.5
5.5
9.5
2.0
10.0
10.0
10.0
10.0
16.0
17.5
10.5
10.5
11.0
11.0
11.0
10.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
to O
n
n
Propagation Delay
to O
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
5.5
5.5
5.5
6.5
7.5
5.5
5.5
6.0
6.0
6.0
5.5
9.5
9.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
D
n
n
Propagation Delay
LE to O
n
Propagation Delay
LE to O
9.0
n
Propagation Delay
PRE to O
14.0
15.5
9.5
n
Propagation Delay
CLR to O
n
Output Enable Time
OE to O
n
Output Enable Time
OE to O
9.5
n
Output Disable Time
OE to O
10.5
10.5
10.5
9.5
n
Output Disable Time
OE to O
n
Propagation Delay
PRE to O
n
Propagation Delay
CLR to O
n
g
*Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
74AC
74AC
e b
a
T
40 C
§
§
A
e a
V
*
T
A
25 C
§
50 pF
CC
Symbol
Parameter
Units
to 85 C
e
(V)
C
L
e
C
50 pF
L
Typ
Guaranteed Minimum
t
t
Setup Time, HIGH or LOW
s
b
5.0
5.0
0.5
0.5
2.0
1.0
2.0
ns
ns
D
n
to LE
Hold Time, HIGH or LOW
to LE
h
0.5
D
n
t
t
t
t
t
LE Pulse Width, HIGH
PRE Pulse Width, LOW
CLR Pulse Width, LOW
PRE Recovery Time
CLR Recovery Time
5.0
5.0
5.0
5.0
5.0
2.0
5.0
5.5
0.5
3.5
8.5
9.5
2.0
1.0
3.5
10.0
11.0
2.0
ns
ns
ns
ns
ns
w
w
w
rec
rec
b
0.5
1.0
g
*Voltage Range 5.0 is 5.0V 0.5V
7
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
44
Units
pF
Conditions
e
e
C
C
V
V
OPEN
5.0V
IN
CC
pF
PD
CC
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:
74AC 843
P
C
QR
Temperature Range Family
e
e
74ACT Commercial TTL-Compatible
Special Variations
e
74AC Commercial
X
Devices shipped in
13 reels
×
e
QR
Commercial grade device
with burn-in
Device Type
Package Code
e
Temperature Range
e
SP
S
Slim Plastic DIP
Small Outline (SOIC)
b a
Commercial ( 40 C to 85 C)
C
§
§
e
8
Physical Dimensions inches (millimeters)
24-Lead Small Outline Integrated Circuit (S)
NS Package Number M24B
9
Ý
Lit. 114638
Physical Dimensions inches (millimeters) (Continued)
24-Lead Slim (0.300 Wide) Plastic Dual-In-Line Package (SP)
×
NS Package Number N24C
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support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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相关型号：
74ACT844FC
Bus Driver, ACT Series, 1-Func, 9-Bit, Inverted Output, CMOS, CDFP24, CERAMIC, FP-24
FAIRCHILD
74ACT844FCQR
Bus Driver, ACT Series, 1-Func, 9-Bit, Inverted Output, CMOS, CDFP24, CERAMIC, FP-24
FAIRCHILD
74ACT844FCT
Bus Driver, ACT Series, 1-Func, 9-Bit, Inverted Output, CMOS, CDFP24, CERAMIC, FP-24
FAIRCHILD
74ACT844FCTR
Bus Driver, ACT Series, 1-Func, 9-Bit, Inverted Output, CMOS, CDFP24, CERAMIC, FP-24
FAIRCHILD
74ACT844FCX
Bus Driver, ACT Series, 1-Func, 9-Bit, Inverted Output, CMOS, CDFP24, CERAMIC, FP-24
FAIRCHILD
74ACT844FCXR
Bus Driver, ACT Series, 1-Func, 9-Bit, Inverted Output, CMOS, CDFP24, CERAMIC, FP-24
FAIRCHILD
74ACT844LCTR
Bus Driver, ACT Series, 1-Func, 9-Bit, Inverted Output, CMOS, CQCC28, CERAMIC, LCC-28
FAIRCHILD
74ACT844LCXR
Bus Driver, ACT Series, 1-Func, 9-Bit, Inverted Output, CMOS, CQCC28, CERAMIC, LCC-28
FAIRCHILD
74ACT844PC
Bus Driver, ACT Series, 1-Func, 9-Bit, Inverted Output, CMOS, PDIP24, PLASTIC, DIP-24
FAIRCHILD
74ACT844SCTR
Bus Driver, ACT Series, 1-Func, 9-Bit, Inverted Output, CMOS, PDSO24, SOIC-24
FAIRCHILD
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