74ABT16952CMTD [FAIRCHILD]
16-Bit Registered Transceiver with 3-STATE Outputs; 16位寄存收发器与3态输出
| 型号： | 74ABT16952CMTD |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 16-Bit Registered Transceiver with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1993
Revised January 1999
74ABT16952
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
Features
The ABT16952 is a 16-bit registered transceiver. Two 8-bit
back to back registers store data flowing in both directions
between two bidirectional buses. Separate clock, clock
enable and 3-STATE output enable signals are provided for
each register. The output pins are guaranteed to source 32
mA and to sink 64 mA.
■ Separate clock, clock enable and 3-STATE output
enable provided for each register
■ A and B output sink capability of 64 mA source capability
of 32 mA
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Nondestructive hot insertion capability
Ordering Code:
Order Number
74ABT16952CSSC
74ABT16952CMTD
Package Number
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD56
Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.
Pin Descriptions
Connection Diagram
Pin Assignment for SSOP
Pin Names
Description
A0–A15
Data Register A Inputs/
B-Register 3-STATE Outputs
Data Register B Inputs/
A-Register 3-STATE Outputs
Clock Pulse Inputs
B0–B15
CPABn, CPBAn
CEAn, CEBn
Clock Enable
Output Enable Inputs
OEABn, OEBAn
Output Control
OE
Internal
Q
Output
Function
H
L
L
X
L
Z
L
Disable Outputs
Enable Outputs
H
H
Register Function Table
(Applies to A or B Register)
Inputs
Internal
D
X
L
CP
CE
H
Q
NC
L
Function
Hold Data
Load Data
X
L
H
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
= LOW-to-HIGH Transition
X = Immaterial
NC = No Change
© 1999 Fairchild Semiconductor Corporation
DS011647.prf
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Block Diagram
n for either byte 1 or byte 2
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2
DC Latchup Source Current
Over Voltage Latchup (I/O)
−500 mA
Absolute Maximum Ratings(Note 1)
10V
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to
−55°C to +125°C
−55°C to +150°C
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
−40°C to +85°C
+4.5V to +5.5V
Ground Pin
−0.5V to +7.0V
−0.5V to +7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disable or Power-Off State
in the HIGH State
Minimum Input Edge Rate (∆V/∆t)
Data Input
−30 mA to +5.0 mA
50 mV/ns
20 mV/ns
100 mV/ns
Enable Input
−0.5V to +5.5V
−0.5V to VCC
Clock Input
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
Recognized HIGH Signal
Recognized LOW Signal
CC
V
2.0
V
V
V
IH
V
V
V
Input LOW Voltage
0.8
IL
Input Clamp Diode Voltage
Output HIGH Voltage
−1.2
Min
I
I
I
I
I
= −18 mA (Non I/O Pins)
CD
OH
IN
2.5
2.0
= −3 mA (A , B )
n n
OH
OH
OL
= −32 mA (A , B )
n
n
V
V
Output LOW Voltage
Input Leakage Test
0.55
= 64 mA (A , B )
n n
OL
ID
4.75
V
0.0
Max
= 1.9 µA (Non-I/O Pins)
ID
All Other Pins Grounded
I
I
I
I
I
Input HIGH Current
1
1
7
µA
µA
µA
µA
µA
V
V
V
= 2.7V (Non-I/O Pins) (Note 4)
IH
IN
IN
IN
= V (Non-I/O Pins)
CC
Input HIGH Current
Breakdown Test
Max
= 7.0V (Non-I/O Pins)
BVI
BVIT
IL
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
100
Max
V
= 5.5V (A , B )
n n
IN
−1
−1
10
Max
V
V
V
= 0.5V (Non-I/O Pins) (Note 4)
= 0.0V (Non-I/O Pins)
IN
IN
+ I
Output Leakage Current
0V–5.5V
= 2.7V (A , B );
OUT n n
IH
IL
OZH
OEA or OEB = 2.0V
0V–5.5V V = 0.5V (A , B );
OUT
I
+ I
Output Leakage Current
−10
µA
OZL
n
n
OEA or OEB = 2.0V
I
I
I
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
−100
−275
50
mA
µA
µA
Max
Max
0.0V
V
V
V
= 0V (A , B )
n n
OS
CEX
ZZ
OUT
OUT
OUT
= V (A , B )
CC
n
n
100
= 5.5V (A , B );
n n
All Others GND
All Outputs HIGH
All Outputs LOW
Outputs 3-STATE;
All Others GND
I
I
I
Power Supply Current
Power Supply Current
Power Supply Current
1.0
60
mA
mA
mA
Max
Max
Max
CCH
CCL
CCZ
1.0
I
Additional I /Input
2.5
mA
Max
Max
V = V − 2.1V; All Others
I CC
CCT
CC
at V or GND
CC
I
Dynamic I
(Note 4)
No Load
Outputs Open
CCD
CC
0.18
mA/MHz
OEA or OEB = GND,
Non-I/O = GND or V
CC
One Bit toggling, 50% duty cycle
(Note 3)
Note 3: For 8-bit toggling, I
<1.4 mA/MHz.
CCD
Note 4: Guaranteed, but not tested.
3
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AC Electrical Characteristics
(SSOP Package)
T
V
= +25°C
T = −40°C to +85°C
A
A
= +5.0V
= 50 pF
V
= 4.5V to 5.5V
CC
CC
Symbol
Parameter
Units
C
C = 50 pF
L
L
Min
Max
Min
Max
f
Max Clock
Frequency
200
200
MHz
ns
max
t
t
Propagation Delay
1.5
1.5
5.3
5.3
1.5
1.5
5.3
5.3
PLH
PHL
CPAB or CPBA to
n
n
A
or B
n
n
t
t
Output Enable Time
OEAB or OEBA to
1.5
1.5
5.5
5.5
1.5
1.5
5.5
5.5
ns
ns
PZH
PZL
n
n
A
or B
n
n
t
t
Output Disable Time
OEAB or OEBA to
1.5
1.5
6.0
6.0
1.5
1.5
6.0
6.0
PHZ
PLZ
n
n
A
or B
n
n
AC Operating Requirements
T
= +25°C
T = −40°C to +85°C
A
A
V
= +5.0V
V
= 4.5V to 5.5V
CC
CC
Symbol
Parameter
Units
C
= 50 pF
C = 50 pF
L
L
Min
2.5
2.5
Max
Min
2.5
2.5
Max
t (H)
Setup Time, HIGH
or LOW A or B
ns
S
t (L)
S
n
n
to CPAB or CPBA
n
n
t
t
(H)
(L)
Hold Time, HIGH
1.5
1.5
1.5
1.5
ns
ns
H
H
or LOW A or B
n
n
to CPAB or CPBA
n
n
t (H)
S
Setup Time, HIGH
2.5
2.5
2.5
2.5
t (L)
S
or LOW CEA or CEB
n
n
n
to CPAB or CPBA
n
n
t
t
(H)
(L)
Hold Time, HIGH
1.5
1.5
1.5
1.5
ns
ns
H
H
or LOW CEA or CEB
n
to CPAB or CPBA
n
n
t
t
(H)
(L)
Pulse Width,
3.0
3.0
3.0
3.0
W
W
HIGH or LOW
to CPAB or CPBA
n
n
Capacitance
Typ
Conditions
Symbol
Parameter
Units
T
= 25°C
A
C
Input Capacitance
Output Capacitance
5
pF
pF
V
V
= 0V (Non I/O Pins)
IN
CC
CC
C
(Note 5)
11
= 5.0V (A , B )
n n
I/O
Note 5: C is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
I/O
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4
AC Loading
*Includes jig and probe capacitance
FIGURE 2. Test Input Signal Levels
FIGURE 1. Standard AC Test Load
Amplitude Rep. Rate
3.0V 1 MHz
tW
tr
tf
500 ns
2.5 ns
2.5 ns
FIGURE 3. Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5
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Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS56A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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