XRT91L33IG [EXAR]
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT; STS - 12 / STS - 3多速率时钟及数据恢复单元
| 型号： | XRT91L33IG |
| 厂家： | 
EXAR CORPORATION |
| 描述： | STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT |
| 文件： | 总16页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
AUG 2008
REV. V1.0.0
FEATURES
APPLICATIONS
• Performs clock and data recovery for selectable
data of 622.08 Mbps (STS-12/STM-4) or 155.52
Mbps (STS-3/STM-1) NRZ data
• SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Meets Telcordia, ANSI and ITU-T G.783 and G.825
SDH jitter requirements including T1.105.03 - 2002
SONET Jitter Tolerance specification, and GR-253
CORE, GR-253 ILR SONET Jitter specifications.
• Cross Connect Equipment
• ATM and Multi-Service Switches, Routers and
Switch/Routers
• Lock output pin monitors data run length and
frequency drift from reference clock
• DSLAMS
• SONET/SDH Test Equipment
• DWDM Termination Equipment
• Data is resampled at the output
• Active High Signal Detect (SIGD) LVPECL input
• Low jitter, high-speed outputs support LVPECL and
low-power LVDS termination
GENERAL DESCRIPTION
• 19.44 MHz reference frequency LVTTL input
• Low power: 215 mW typical
• 3.3V power supply
The XRT91L33 is a fully integrated multirate Clock
and Data Recovery (CDR) device for SONET/SDH
622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/
STM-1 applications. The device provides Clock and
Data Recovery (CDR) function by synchronizing its
on-chip Voltage Controlled Oscillator (VCO) to the
incoming serial scrambled non-return to zero (NRZ)
data stream. Figure 1 shows the block diagram of
the XRT91L33.
• 20-pin TSSOP package
• Requires one external capacitor
• PLL bypass operation facilitates board debug
process
• ESD greater than 2kV on all pins
FIGURE 1. BLOCK DIAGRAM OF XRT91L33
STS12_MODE
REFCK
19.44 MHz
CAP+
1u F
PLL
RX LOOP
FILTER
CAP+
TEST
LVDS/LVPECL
Output Drivers
Differential
Receiver
RXDIP
RECVD-
DATAOUT
RXDOP
0
RXDATAIN
CDR
RXDIN
RXDON
STS-12/3
1
Internal
biasing
or
STM-4/1
Clock and Data
Recovery
External
100R
termination
RECVD-
CLKOUT
RXCLKOP
RXCLKON
LOCK
LCKTOREFN
SIGD
MUTE
RXDO
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
CLOCK AND DATA RECOVERY OVERVIEW
REV. V1.0.0
The clock and data recovery (CDR) unit accepts high speed NRZ serial data from the Differential receiver and
generates a clock with a frequency equal to that of the incoming data. The CDR block uses a reference clock to
train and monitor its clock recovery PLL. Upon startup, the PLL locks to the local reference clock. Once this is
achieved, the PLL attempts to lock onto the incoming receive serial data stream. Whenever the recovered
clock frequency deviates from the local reference clock frequency by more than approximately ±500 ppm, the
clock recovery PLL will switch and lock back onto the local reference clock and declare a Loss of Lock.
Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will continue to supply a recovered clock
(based on the local reference) to the framer/mapper device. An LOS condition occurs when either SIGD or
LCKTOREFN is low. In this case, the receive serial data output is forced to a logic zero state for the entire
duration of the LOS condition. This acts as a receive data mute upon LOS function to prevent random noise
from being misinterpreted as valid incoming data. When SIGD becomes active again, the recovered clock is
determined to be within ±500 ppm accuracy with respect to the local reference source and LOS is no longer
declared, the clock recovery PLL will switch and lock back onto the incoming receive serial data stream.
FIGURE 2. 20 PIN TSSOP OF XRT91L33 (TOP VIEW)
1
2
VDDA
RXDIP
RXDIN
VSSA
VDDA 20
VSSA
CAP+
19
18
17
16
15
14
13
12
11
3
4
CAP-
5
TEST
LOCK
6
STS12_MODE
REFCK
SIGD
7
RXDOP
RXDON
RXCLKOP
RXCLKON
8
LCKTOREFN
VSS
9
10
VDD
TABLE 1: ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
-40°C to +85°C
XRT91L33IG
20-pin TSSOP Package
-40°C to +85°C
XRT91L33IG-F
20-Pin TSSOP Lead-Free Package
2
XRT91L33
REV. V1.0.0
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
FEATURES......................................................................................................................... 1
APPLICATIONS ................................................................................................................. 1
GENERAL DESCRIPTION................................................................................................. 1
FIGURE 1. BLOCK DIAGRAM OF XRT91L33...................................................................................................................................... 1
CLOCK AND DATA RECOVERY OVERVIEW ....................................................................................................... 2
FIGURE 2. 20 PIN TSSOP OF XRT91L33 (TOP VIEW).................................................................................................................... 2
TABLE 1: ORDERING INFORMATION................................................................................................................................................... 2
1.0 PIN DESCRIPTIONS .............................................................................................................................. 4
TABLE 2: PIN DESCRIPTION TABLE ................................................................................................................................................... 4
..................................................................................................................................................................... 5
2.0 FUNCTIONAL DESCRIPTION ............................................................................................................... 6
2.1 REFERENCE CLOCK INPUT ........................................................................................................................... 6
2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................... 6
2.3 EXTERNAL RECEIVE LOOP FILTER CAPACITOR ....................................................................................... 6
2.4 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ........................................................................... 6
2.5 SIGNAL DETECTION ....................................................................................................................................... 6
FIGURE 3. CONTROL DIAGRAM FOR SIGNAL DETECTION CIRCUIT AND PLL TEST OPERATION ............................................................ 7
2.6 LOCK DETECTION ........................................................................................................................................... 7
2.7 PLL TEST OPERATION ................................................................................................................................... 7
TABLE 3: SIGNAL DETECT AND PLL TEST OPERATION CONTROL .................................................................................................... 8
3.0 ELECTRICAL CHARACTERISTICS ..................................................................................................... 9
3.1 ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 9
TABLE 4: ABSOLUTE MAXIMUM RATINGS........................................................................................................................................... 9
3.2 OPERATING CONDITIONS .............................................................................................................................. 9
TABLE 5: RECOMMENDED OPERATING CONDITIONS .......................................................................................................................... 9
3.3 LVPECL SINGLE ENDED INPUT AND OUTPUT DC CHARACTERISTICS .................................................. 9
TABLE 6: LVPECL SINGLE ENDED INPUTS AND OUTPUTS................................................................................................................. 9
3.4 LVPECL DIFFERENTIAL INPUT AND OUTPUT DC CHARACTERISTICS ................................................. 10
TABLE 7: LVPECL DIFFERENTIAL INPUTS AND OUPUTS .................................................................................................................. 10
FIGURE 4. DIFFERENTIAL VOLTAGE SWING DEFINITIONS (INPUT OR OUTPUT) FOR CLOCK AND DATA ................................................... 10
TABLE 8: LVDS OUTPUTS............................................................................................................................................................. 10
TABLE 9: LVTTL INPUTS................................................................................................................................................................ 11
3.5 AC CHARACTERISTICS ................................................................................................................................ 11
TABLE 10: PERFORMANCE SPECIFICATIONS.................................................................................................................................... 11
4.0 JITTER PERFORMANCE .................................................................................................................... 12
4.1 SONET JITTER REQUIREMENTS ................................................................................................................. 12
4.1.1 RX JITTER TOLERANCE:.......................................................................................................................................... 12
FIGURE 5. GR-253/G.783 JITTER TOLERANCE MASK ..................................................................................................................... 12
FIGURE 6. XRT91L33 JITTER TOLERANCE AT 155 MBPS OC3/STM-1.......................................................................................... 13
FIGURE 7. XRT91L33 JITTER TOLERANCE AT 622 MBPS OC12/STM-4........................................................................................ 13
4.1.2 JITTER GENERATION................................................................................................................................................ 13
5.0 HIGH-SPEED OUTPUTS ..................................................................................................................... 14
FIGURE 8. HIGH SPEED OUTPUTS, LVDS TERMINATION.................................................................................................................. 14
FIGURE 9. HIGH-SPEED OUTPUTS, LVPECL TERMINATION OPTIONS ............................................................................................... 14
6.0 RESAMPLED DATA AND CLOCK OUTPUTS .................................................................................. 15
FIGURE 10. OUTPUT DATA AND CLOCK AFTER RESAMPLING............................................................................................................ 15
TABLE 11: OUTPUT TIMING ............................................................................................................................................................ 15
7.0 PACKAGE DIMENSIONS .................................................................................................................... 16
TABLE 12: REVISION HISTORY........................................................................................................................................................ 16
3
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
1.0 PIN DESCRIPTIONS
REV. V1.0.0
TABLE 2: PIN DESCRIPTION TABLE
NAME
VDDA
RXDIP
LEVEL
PWR
TYPE
PWR
I
PIN
1
DESCRIPTION
3.3V Power supply
LVDS/PECL
2
Positive side of receive data input. The high-speed output clock
(RXCLKOP/N) is recovered from this high-speed differential
inupt data.
RXDIN
LVDS/PECL
I
3
Negative side of receive data input. The high-speed output
clock (RXCLKOP/N) is recovered from this high-speed differen-
tial input data.
VSSA
LOCK
PWR
PWR
O
4
5
Ground pin
LVPECL
Active HIGH to indicate that the PLL is locked to serial data
input and valid clock and data are present at the serial outputs
(RXDOP/N and RXCLKOP/N). The LOCK will go inactive under
the following conditions:
• If SIGD is set LOW
• If LCKTOREFN is set LOW
• If the VCO has drifted away from the local reference
clock, REFCK, by more than +/- 500 ppm
STS12_MODE
REFCK
LVTTL
LVTTL
I
I
6
7
STS-12 or STS-3 mode selection. Set HIGH to select the
STS-12 operation. Set LOW for STS-3 operation
Local 19.44 MHz reference clock input for the CDR. REFCK is
used for the PLL phase adjustment during power up. It also
serves as a stable clock source in the absence of serial input
data.
LCKTOREFN
LVTTL
I
8
Lock to REFCK input. When set LOW, this pin causes the out-
put clock, RXCLKOP/N to be held within +/- 500ppm of the
input reference clock REFCL and forces the RXDOP/N to a low
state.
VSS
VDD
PWR
PWR
PWR
PWR
O
9
Ground pin
10
11
3.3V power supply
RXCLKON
LVDS/
LVPECL
High-speed clock output, negative. This clock is recovered
from the receive data input (RXDIP/N) and supports either
LVDS or LVPECL termination
RXCLKOP
LVDS/
LVPECL
O
12
High-speed clock output, positive This clock is recovered from
the receive data input (RXDIP/N) and supports either LVDS or
LVPECL. termination
High-speed output, negative This is the retimed version of the
recovered data stream from RXDIP/N and can be in either LVDS
or LVPECL termination
RXDON
RXDOP
LVDS/
LVPECL
O
O
13
14
LVDS/
LVPECL
High-speed output, positive. This is the retimed version of the
recovered data stream from RXDIP/N and can be in either
LVDS or LVPECL termination
4
XRT91L33
REV. V1.0.0
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
NAME
LEVEL
TYPE
PIN
DESCRIPTION
SIGD
LVPECL
I
15
Signal detect. SIGD should be connected to the SIGD output
on the optical module. SIGD is active HIGH. When SIGD is set
HIGH, it means there is sufficient optical power. When SIGD is
LOW, this indicates an LOS condition, the RXCLKOP/N output
signal will be held to within +/- 500 ppm of the REFCK input.
Additionally, the RXDOP/N will be held in the LOW state.
TEST
CAP-
LVTTL
Analog
I
I
16
17
Used for production testing. Set to VSS for normal operation.
Negative side of the external loop filter. The loop filter capacitor
should be connected to these pins. The capacitor value should
be 1.0 μF +/- 10 %
CAP+
Analog
I
18
Positive side of the external loop filter. The loop filter capacitor
should be connected to these pins. The capacitor value should
be 1.0 μF +/- 10 %.
VSSA
VDDA
PWR
PWR
PWR
PWR
19
20
Ground pin
3.3V power supply
5
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
2.0 FUNCTIONAL DESCRIPTION
REV. V1.0.0
The XRT91L33 CDR is designed to operate with a SONET Framer/ASIC device and provide a high-speed
serial clock and data recovery interface to optical networks. The CDR receives a differential NRZ serial bit
stream running at STS-12/STM-4 or STS-3/STM-1 and generates recovered serial clock and data via
differential LVDS/LVPECL drivers.
2.1
Reference Clock Input
The XRT91L33 accepts a 19.44 MHz LVTTL clock input at REFCK. The REFCK should be generated from a
source that has a frequency accuracy better than ±100ppm in order for the CDR Loss of Lock detector to have
the necessary accuracy required for SONET systems.
2.2
Receive Clock and Data Recovery
The clock and data recovery (CDR) unit accepts the high-speed NRZ serial data from the Differential receiver
and generates a clock that is the same frequency as the incoming data. The clock recovery block utilizes the
reference clock from REFCK to train and monitor its clock recovery PLL. Upon startup, the PLL locks to the
local reference clock. Once this is achieved, the PLL then attempts to lock onto the incoming receive serial
data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by
more than approximately ±500ppm, the clock recovery PLL will switch to the local reference clock, declare a
Loss of Lock and output a LOW level signal on the LOCK output pin. Whenever a Loss of Lock (LOL) or a
Loss of Signal (LOS) event occurs, the CDR will continue to supply a receive clock (based on the local
reference).
2.3
External Receive Loop Filter Capacitor
For STS12/STM4 and STS3/STM1 operation, the XRT91L33 uses a 1.0uF (or greater) external loop filter
capacitor to achieve the required receiver jitter performance. It must be well isolated to prohibit noise entering
the CDR block and should be placed as close to the pins as possible. The non-polarized capacitor should be of
±10% tolerance. Use type X7R or X5R capacitors for improved stability over temperature.
2.4
STS-12/STM-4 and STS-3/STM-1 Mode of Operation
The VCO output signal is fed into a programmable frequency divider allowing to properly set the PLL operating
frequency corresponding to the desired data rate. For 622.08 Mbps signal STS12_MODE is set HIGH and for
155.52 Mbps, STS12_MODE is set LOW.
2.5
Signal Detection
XRT91L33 has two control pins that are used to indicate an LOS condition (Loss Of Signal). The SIGD pin is a
LVPECL input and the LCKTOREFN pin is a LVTTL input. They are internally connected as shown in Figure 3.
If either of these two inputs goes LOW and TEST is LOW, XRT91L33 will enter a Loss of Signal (LOS) state,
and will mute the RXDOP/N. During the LOS state, XRT91L33 will also maintain RXCLKOP/N within ±500ppm
of the input reference clock, REFCK. Most optical modules have an SIGD output. This SIGD output indicates
that there is sufficient optical power and is typically active HIGH. If the SIGD output on the optical module is
LVPECL, it should be connected directly to the SIGD input of XRT91L33, and the LCKTOREFN input should
be tied HIGH. If the SIGD output is LVTTL, it should be connected directly to the LCKTOREFN input and the
SIGD input should be tied HIGH. The SIGD and LCKTOREFN inputs also can be used for other applications
when it is required to hold RXCLKOP/N output within ±500ppm of the input reference clock and mute the serial
data output lines.
6
XRT91L33
REV. V1.0.0
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
FIGURE 3. CONTROL DIAGRAM FOR SIGNAL DETECTION CIRCUIT AND PLL TEST OPERATION
2
2
RXDOP/N
RXDIP/N
PLL Clock
(Internal)
0
2
RXCLKOP/N
REFCK
1
STS12_MODE
TEST
LOS (Internal)
LCKTOREFN
SIGD
2.6
Lock Detection
XRT91L33 features a PLL lock detection circuit. The lock detect (LOCK) output goes HIGH to indicate that the
PLL is locked to the serial data input and valid data and clock are present at the high-speed differential output.
The LOCK output will go LOW if either the LOCKTOREFN or the SIGD input is forced LOW. Additionally,
LOCK will also go low if the incoming data frequency is more than +/-500ppm away from the reference clock
frequency (REFCK x 32 in OC12 mode, REFCLK x 8 in OC3 mode). When LOCK output is driven LOW, the
VCO is forced to lock to REFCK and then released to lock on the incoming data. If the incoming data frequency
remains outside the +/-500ppm window, the training mode is repeated. Debounce logic stabilizes the LOCK
output pin to stay LOW for incoming frequencies well beyond the +/-500ppm window.
2.7
PLL Test Operation
The TEST pin is intended for use in production test and should be set at logic LOW in normal operation. If both
TEST and STS12_MODE pins are set to logic HIGH, XRT91L33 will bypass the PLL and present an inverted
version of the REFCK to the clock output RXCLKOP/N. REFCK’s rising edge is used to capture the input data
and transmit data to RXDOP/N. This bypass test operation can be used to facilitate board level debugging
process.
7
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
REV. V1.0.0
.
TABLE 3: SIGNAL DETECT AND PLL TEST OPERATION CONTROL
STS12_MODE
1
TEST
0
LCKTOREFN
SIGD
1
RXDO
RXDI
RXCLKO
1
1
0
0
X
1
1
0
0
X
PLL clock
PLL clock
PLL clock
PLL clock
REFCK
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
Muted
Muted
Muted
RXDI
1
0
X
1
RXDI
PLL clock
PLL clock
PLL clock
PLL clock
Not allowed
0
Muted
Muted
Muted
Not allowed
1
0
X
8
XRT91L33
REV. V1.0.0
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
3.0 ELECTRICAL CHARACTERISTICS
3.1 Absolute Maximum RATINGS
TABLE 4: ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
MINIMUM MAXIMUM UNIT
VDD
Power supply voltage, referenced to GND
-0.5
4.0
V
DC input voltage (LVPECL, LVTTL)
Output current (LVDS or LVPECL)
Storage Temperature
-0.5 VDD+0.5
V
-50
-65
+50
150
mA
TS
°C
VESD
Electrostatic discharge voltage, human body model
-2000
2000
V
3.2
Operating Conditions
TABLE 5: RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP
MAX.
UNITS
VDD
Power supply voltage
3.135
3.3
3.465
V
Operating Temperature under bias 1
Temp
-40
85
°
C
IDD
PD
Power supply current (outputs unterminated)
Power dissipation (outputs unterminated)
65
80
mA
215
277
mW
1. Lower limit of specification is ambient temperature, and upper limit is case temperature.
3.3
LVPECL Single Ended Input and Output DC characteristics
TABLE 6: LVPECL SINGLE ENDED INPUTS AND OUTPUTS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
VIH
Input HIGH voltage
VDD-1.125
VDD-0.5
V
Guaranteed input
HIGH voltage
VIL
Input LOW voltage
VDD-2.0
VDD-1.5
V
Guaranteed input
LOW voltage
IIH
IIL
Input HIGH current
Input LOW current
Output LOW voltage
Output HIGH voltage
-0.5
-0.5
10
10
VIN = VDD - 0.5V
VIN=VDD-2.0V
μ A
μA
VOL
VOH
VDD-2.0
VDD-1.25
VDD-1.8
VDD-0.67
V
50Ω to (VDD-2.0V)
50Ω to (VDD-2.0V)
V
9
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
REV. V1.0.0
3.4
LVPECL Differential Input and Output DC characteristics
TABLE 7: LVPECL DIFFERENTIAL INPUTS AND OUPUTS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
VIH
Input HIGH voltage
VDD-1.75
VDD-0.4
V
Guaranteed input
HIGH voltage
VIL
Input LOW voltage
VDD-2.0
VDD-0.7
V
Guaranteed input
LOW voltage
IIH
IIL
Input HIGH current
Input LOW current
-0.5
-0.5
250
10
10
VIN DIFF =0.5V
VIN DIFF =0.5V
μ A
μA
VIDIFF
Input PECL Differential Voltage, peak-
mV
to-peak swing (see Figure 4)
VOCM
Output Common-Mode Voltage
0.8
1.35
1.7
V
50Ω to (VDD-2.0V)
50Ω to (VDD-2.0V)
VODIFF
Output LVPECL Differential Voltage,
peak-to-peak swing (see Figure 4)
800
1700
mV
FIGURE 4. DIFFERENTIAL VOLTAGE SWING DEFINITIONS (INPUT OR OUTPUT) FOR CLOCK AND DATA
V(+)
VSINGLE
V(-)
VDIFF = V(+)-V(-)
2 x VSINGLE
0 V
TABLE 8: LVDS OUTPUTS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
VOCM
Output common-mode voltage
1.0
1.35
1.7
V
100Ω between
RXDOP/N and
RXCLKP/N
VODIFF
Output LVDS Differential Voltage,
peak-to-peak Swing (see Figure 4)
700
1700
mV
100Ω between
RXDOP/N and
RXCLKP/N
10
XRT91L33
REV. V1.0.0
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
TABLE 9: LVTTL INPUTS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
VIH
Input HIGH voltage
2.0
VDD
V
VIL
IIH
Input LOW voltage
Input HIGH current
0
0.8
50
V
-50
VIN = 2.75 V, VDD
Maximum
=
μA
IIL
Input LOW current
-50
50
VIN = 0.5 V, VDD
Maximum
=
μA
3.5
AC Characteristics
TABLE 10: PERFORMANCE SPECIFICATIONS
Test Condition: VDD = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONDITIONS
f
VCO center frequency
622.08
MHz
ppm
fTOL
CDR’s reference clock frequency
OC-12/STS-12 capture range
-250
-500
250
500
fTREF_CLK
ppm with respect to the fixed
reference frequency
CLKOUTDC
tLOCK
Clock output duty cycle
45
55
16
% UI 20% minimum transition
density
OC-12/STS-12 acquisition lock time
Valid REFCK and
device already pow-
ered up
μs
tLOCK_R
,
LOCK output rise and fall time
500
ps
10% to 90%, with 100Ω
and 5 pF capacitive
equivalent load
tLOCK_F
JGEN_CLCK
JTOL
RXCLKOP/N iitter generation
OC-12/STS-12 jitter tolerance
0.005
0.5
0.01
UIrms
UI
0.40
Sinusoidal input jitter of
RXDIP/N from 250 KHz
to 5MHz
11
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
REV. V1.0.0
4.0 JITTER PERFORMANCE
4.1
SONET Jitter Requirements
SONET receive equipment jitter requirements are specified jitter tolerance and jitter transfer. The definitions of
each of these types of jitter are given below.
4.1.1
Rx Jitter Tolerance:
OC-3/STM-1, and OC-12/STM-4 category II SONET interfaces should tolerate, the input jitter applied
according to the mask of Figure 6, with the corresponding specified parameters. Jitter measurements are
done with standard SONET/SDH testers such as Acterna ANT20 as well as Agilent Omniber testers.
FIGURE 5. GR-253/G.783 JITTER TOLERANCE MASK
A3
slope= -20dB/decade
Input
Jitter
Amplitude
(UIpp
)
A2
slope= -20dB/decade
A1
f0
f1
f2
Jitter Frequency (Hz)
f4
f3
OC-N STM-X LEVEL
F0 (HZ)
10
F1 (HZ)
F2 (HZ)
300
F3 (HZ)
2K
F4 (HZ)
20K
A1 (UIPP) A2 (UIPP) A3 (UIPP)
OC1/STS1
STM0
STM1
0.15
0.15
0.15
1.5
1.5
1.5
15
15
OC3/STS3
10
30
300
6.5K
25K
65K
OC12/STS12 STM4
10
30
300
250K
12
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
FIGURE 6. XRT91L33 JITTER TOLERANCE AT 155 MBPS OC3/STM-1
XRT91L33 Jitter Tolerance OC3
100.00
Jitter
(UI)
10.00
1.00
0.10
0.01
0.10
1.00
10.00
100.00 1,000.00 10,000.00
Jitter
Frequency (KHz)
Mask
FIGURE 7. XRT91L33 JITTER TOLERANCE AT 622 MBPS OC12/STM-4
XRT91L33 Jitter Tolerance OC12
1,000.00
Jitter
(UI)
100.00
10.00
1.00
0.10
0.01
0.10
1.00
10.00
100.00 1,000.00 10,000.00
Jitter
Frequency (KHz)
Mask
4.1.2
Jitter Generation
Maximum jitter generation is less than 0.01 UI rms within the SONET/SDH band, when rms jitter of less than
14 ps (OC-12) or 56 ps (OC-3) is presented to the serial data inputs.
13
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
5.0 HIGH-SPEED OUTPUTS
REV. V1.0.0
The high-speed output buffers, RXDOP/N and RXCLKOP/N can be terminated as either LVDS or LVPECL
outputs. In LVDS mode, the transmission lines must be routed with 100 Ω differential impedance and
terminated at the receive end with a line-to-line 100Ω resistor (See Figure 8).
FIGURE 8. HIGH SPEED OUTPUTS, LVDS TERMINATION
XRT91L33
Receiver
For LVPECL conections, the transmission line must be terminated with 50Ω pull-down resistors near the
receiving end or an equivalent circuit. (See Figure 9)
FIGURE 9. HIGH-SPEED OUTPUTS, LVPECL TERMINATION OPTIONS
VDD – 2.0V
XRT91L33
Receiver
VDD – 2.0V
VDD
Creates 2V bias
when VDD = 3.3V
XRT91L33
Receiver
VDD
VSS
(Unbiased and No internal
termination)
VSS
XRT91L33
Receiver
(Baised with internal
termination)
14
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
6.0 RESAMPLED DATA AND CLOCK OUTPUTS
It is recommended that the retimed data output be captured with the rising edge of the clock output as shown in
Figure 10. Data valid time is longer for OC-3/STS-3 mode of operation than that of OC-12/STS-12. Data valid
time before the output clock’s rising edge is the available setup time (t ), while the data valid time after the
SU
clock’s rising edge is the available hold time (t ).
H
FIGURE 10. OUTPUT DATA AND CLOCK AFTER RESAMPLING
RXDOP/N
RXCLKOP/N
tH
tSU
TABLE 11: OUTPUT TIMING
SYMBOL
PARAMETER
MINIMUM MAXIMUM
UNIT
ps
CONDITION
tSU
Available setup time
450
2.0
STS-12 operation (622.08 MHz)
STS-3 operation (155.52 MHz)
STS-12 operation (622.08 MHz)
STS-3 operation (155.52 MHz)
ns
tH
Available hold time
650
3.0
ps
ns
15
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
REV. V1.0.0
7.0 PACKAGE DIMENSIONS
20 pin Surface mount TSSOP
TABLE 12: REVISION HISTORY
REVISION #
DATE
DESCRIPTION
V1.0.0
Aug 2008
Product Release Datasheet
16
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