XRT91L34_技术文档

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

OCTOBER 2007

REV. 1.0.1

attempts to lock onto the incoming receive serial data

GENERAL DESCRIPTION

stream. Whenever the recovered clock frequency

deviates from the local reference clock frequency by

more than approximately ±500 ppm, the clock

recovery PLL will switch and lock back onto the local

reference clock and declare a Loss of Lock.

Whenever a Loss of Lock or a Loss of Signal event

occurs, the CDR will continue to supply a recovered

clock (based on the local reference) to the framer/

mapper device. When the SDEXT is de-asserted by

the optical module or when internal DLOS is

asserted, the receive serial data output will be forced

to a logic zero state for the entire duration that a LOS

condition is declared. This acts as a receive data

mute upon LOS function to prevent random noise

from being misinterpreted as valid incoming data.

When the SDEXT becomes active and the recovered

clock is determined to be within ±500 ppm accuracy

with respect to the local reference source and LOS is

no longer declared, the clock recovery PLL will switch

and lock back onto the incoming receive serial data

stream. Figure 1 shows the block diagram of the

XRT91L34.

The XRT91L34 is a fully integrated quad channel

multirate Clock and Data Recovery (CDR) device for

SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52

Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0

applications. The device provides Clock and Data

Recovery (CDR) function by synchronizing its on-chip

Voltage Controlled Oscillator (VCO) to the incoming

serial data stream. The device internally monitors

Loss of Lock (LOL) conditions and automatically

mutes recovered data upon Loss of Signal (LOS)

conditions.

C

LOCK AND DATA RECOVERY OVERVIEW

The clock and data recovery (CDR) unit accepts the

high speed NRZ serial data from the LVDS or

Differential LVPECL receiver and generates a clock

that is the same frequency as the incoming data. The

CDR block uses a reference clock to train and

monitor its clock recovery PLL. All four channels

share a single 77.76MHz or 19.44MHz reference

clock. Upon startup, the PLL locks to the local

reference clock. Once this is achieved, the PLL

FIGURE 1. BLOCK

D

IAGRAM OF XRT91L34

TEST

RESET

OUTCFG

HOST /HW

XRT91L34

0

CDRREFSEL

DLOSDIS

DLOSDIS /SDI

SDI

REFCLKP

REFCLKN

Global Control Block

1

19.44 / 77.76 MHz

Serial Proccesor

INT

TTLREFCLK

Interface

CS

LVDS/LVPECL LEVEL SELECT

RCLKDIS0

SCLK

SDO

LVDS/LVPECL

Output Drivers

LVDS/LVPECL

Input Drivers

RECVD-

DATAOUT

RXDI0P

RXDI0N

RXDO0P

RXDO0N

0

RXDATAIN

100

CDR

1

STS-12/3/1

or

STM-4/1/0

Clock and Data

Recovery

RECVD-

0

RXCLKO0P

RXCLKO0N

CLKOUT

RX LOOP

FILTER

1

HOST MODE

ONLY

DLOSDIS

DLOS

LOL0

Channel Control Block

CDRDIS0

DATA0RATE1

DATA0RATE0

SDEXT0

POL0

Channel 0

Channel 1

Channel 2

Channel 3

Exar Corporation 48720 Kato Road, Fremont CA, 94538

•

(510) 668-7000

•

FAX (510) 668-7017 • www.exar.com

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

APPLICATIONS

•

SONET/SDH-based Transmission Systems

Add/Drop Multiplexers

Cross Connect Equipment

ATM and Multi-Service Switches, Routers and Switch/Routers

DSLAMS

SONET/SDH Test Equipment

DWDM Termination Equipment

FEATURES

•

Quad Channel CDR targeted for SONET STS-12/STS-3/STS-1 and SDH STM-4/STM-1/STM-0 Applications

Selectable data rate operation between 622.08 Mbps, 155.52 Mbps, or 51.84 Mbps.

Single-chip fully integrated solution containing quad-channel clock and data recovery (CDR) functions

Optional flexibility to configure for LVDS or Differential LVPECL High Speed I/O Interface

Internal 100Ω termination for the high speed LVDS/Differential LVPECL inputs included

Utilizes reference clock frequency of either 19.44 MHz or 77.76 MHz

Host mode serial microprocessor interface simplifies monitor and control, including LOS monitoring

Diagnostics features include LOS monitoring in Host Mode and automatic recovered data mute upon LOS

Loss of Lock Detect output for each channel

Permits mixed data rate configuration of the four channels

Independent power down control of unused channels for lower power operation

Meets Telcordia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002

SONET Jitter Tolerance specification, and GR-253 CORE, GR-253 ILR SONET Jitter specifications.

•

Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V Differential LVPECL, and

JESD 8-B LVTTL and LVCMOS standard.

•

Operates with dual power supply of 1.8V core and 3.3V IO supply

90mW LVDS/ 350mW Differential LVPECL per channel Typical Power Dissipation

Package: 14 x 14 x 1.4 mm 128-pin LQFP

RoHS Compliant Lead-Free package availability

ESD greater than 2kV on all pins

2

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

F

IGURE 2. 128 LQFP PIN

O

UT OF THE XRT91L34 (TOP

VIEW)

n/c

1

2

3

4

5

6

7

8

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

VDD_IO

RXDO0P

RXDO0N

GND_IO

RXDI0P

RXDI0N

VDD_IO

GND_IO

n/c

GND_IO

RXCLKO0P

RXCLKO0N

VDD_IO

9

n/c

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

VDD_IO

RXDI1P

RXDI1N

VDD_IO

GND_IO

VDD_IO

RXDI2N

RXDI2P

n/c

RXDO1P

RXDO1N

GND_IO

RXCLKO1P

RXCLKO1N

RXCLKO2N

RXCLKO2P

GND_IO

XRT91L34

GND_IO

RXDO2N

RXDO2P

VDD_IO

n/c

VDD_IO

GND_IO

VDD_IO

RXDI3N

RXDI3P

n/c

RXCLKO3N

RXCLKO3P

GND_IO

RXDO3N

RXDO3P

VDD_IO

n/c

VDD_IO

ORDERING INFORMATION

P

ART

NUMBER

P

ACKAGE

OPERATING TEMPERATURE RANGE

-40^°C to +85^°C

XRT91L34IV

128 Pin Lead LQFP

XRT91L34IV-F

128 Pin Lead-Free LQFP

3

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

TABLE OF CONTENTS

GENERAL DESCRIPTION .................................................................................................1

F

IGURE 1. BLOCK DIAGRAM OF XRT91L34 ...................................................................................................................................... 1

APPLICATIONS...........................................................................................................................................2

FEATURES......................................................................................................................................................2

F

IGURE 2. 128 LQFP PIN OUT OF THE XRT91L34 (TOP VIEW)........................................................................................................ 3

ORDERING INFORMATION.....................................................................................................................3

ABLE OF

T

C

ONTENTS .......................................................................................................... IV

PIN DESCRIPTIONS ..........................................................................................................6

H

R

P

ARDWARE

ECEIVER

OWER AND

SERIAL

C

S

G

ONTROL ....................................................................................................................................6

ECTION........................................................................................................................................9

ROUND ..................................................................................................................................10

ICROPROCESSOR INTERFACE......................................................................................................11

M

1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12

1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 12

1.2 STS-12/STM-4 AND STS-3/STM-1 AND STS-1/STM-0 MODE OF OPERATION ......................................... 12

T

ABLE 1: CHANNEL DATA RATE SELECTION.................................................................................................................................... 12

1.3 REFERENCE CLOCK INPUT ......................................................................................................................... 13

T

ABLE 2: CDR REFERENCE

F

REQUENCY PTIONS (LVDS/ DIFF LVPECL OR

O

SINGLE-ENDED LVTTL/LVCMOS)............................ 13

F

IGURE 3. REFERENCE LOCK

C

D

ESIGN OPTIONS............................................................................................................................ 13

2.0 RECEIVE SECTION .............................................................................................................................14

2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 14

F

IGURE 4. RECEIVE

S

ERIAL

INPUT

INTERFACE USING LVDS/DIFF LVPECL DC COUPLING INTERNAL TERM....................................... 14

F

IGURE 5. RECEIVE

S

ERIAL

INPUT

I

NTERFACE USING IFF LVPECL AC COUPLING INTERNAL TERMINATION ..................................... 15

D

2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15

T

ABLE 3: CLOCK AND

D

ATA

R

ECOVERY

U

NIT

PERFORMANCE.......................................................................................................... 16

2.2.1 INTERNAL CLOCK AND DATA RECOVERY DISABLE ........................................................................................... 16

2.3 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16

F

IGURE 6. EXTERNAL LOOP FILTERS .............................................................................................................................................. 16

2.4 INTERNAL DIGITAL LOSS OF SIGNAL AND EXTERNAL SIGNAL DETECTION ...................................... 17

F

IGURE 7. LOSS OF

S

IGNAL

D

ECLARATION

C

IRCUIT ........................................................................................................................ 17

T

ABLE 4: EXTERNAL LOS DECLARATION

P

OLARITY SETTING........................................................................................................... 17

2.5 MULTICHANNEL RECOVERED OUTPUT INTERFACE ............................................................................... 18

F

IGURE 8. MULTICHANNEL RECOVERED OUTPUT INTERFACE BLOCK................................................................................................ 18

2.6 DIFFERENTIAL RECOVERED DATA OUTPUT TIMING ............................................................................... 19

F

T

IGURE 9. DIFFERENTIAL RECOVERED OUTPUT TIMING................................................................................................................... 19

ABLE 5: RECOVERED

ABLE 6: RECOVERED

ABLE 7: RECOVERED

D

ATA

O

UTPUT

T

IMING (STS-12/STM-4 OPERATION).................................................................................... 19

IMING (STS-3/STM-1 OPERATION)...................................................................................... 19

IMING (STS-1/STM-0 OPERATION)...................................................................................... 19

3.0 JITTER PERFORMANCE ....................................................................................................................20

3.1 SONET JITTER REQUIREMENTS ................................................................................................................. 20

3.1.1 RX JITTER TOLERANCE: .......................................................................................................................................... 20

F

IGURE 10. GR-253/G.783 JITTER

IGURE 11. XRT91L34 MEASURED

IGURE 12. XRT91L34 MEASURED

IGURE 13. XRT91L34 MEASURED

TOLERANCE MASK ................................................................................................................... 20

J

ITTER

T

OLERANCE AT 51.84 MBPS STS-1/STM-0.................................................................. 20

OLERANCE AT 155.52 MBPS STS-3/STM-1................................................................ 21

OLERANCE AT 622.08 MBPS STS-12/STM-4.............................................................. 21

3.1.2 RX JITTER TRANSFER .............................................................................................................................................. 22

F

IGURE 14. XRT91L34 MEASURED

IGURE 15. XRT91L34 MEASURED

IGURE 16. XRT91L34 MEASURED

J

ITTER

T

RANSFER AT 51.84 MBPS STS-1/STM-0.................................................................... 22

RANSFER AT 155.52 MBPS STS-3/STM-1.................................................................. 22

RANSFER AT 622.08 MBPS STS-12/STM-4................................................................ 23

4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ..........................................................................24

F

IGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 24

4.1 SERIAL TIMING INFORMATION .................................................................................................................... 24

F

IGURE 18. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 24

4.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 25

4.2.1 R/W (SCLK1)............................................................................................................................................................... 25

4.2.2 A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. 25

4.2.3 X (DUMMY BIT SCLK8) .............................................................................................................................................. 25

4.2.4 D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 25

4.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 25

IV

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

5.0 REGISTER MAP AND BIT DESCRIPTIONS ....................................................................................... 26

T

ABLE 8: MICROPROCESSOR

ABLE 9: MICROPROCESSOR

I

NTERFACE

R

EGISTER

M

AP ................................................................................................................ 26

NTERFACE

EGISTER

0

X

00 BIT ESCRIPTION.................................................................................... 27

D

ABLE 10: MICROPROCESSOR

ABLE 11: MICROPROCESSOR

ABLE 12: MICROPROCESSOR

ABLE 13: MICROPROCESSOR

ABLE 14: MICROPROCESSOR

ABLE 15: MICROPROCESSOR

ABLE 16: MICROPROCESSOR

ABLE 17: MICROPROCESSOR

I

NTERFACE

R

EGISTER

0

X

01 BIT

D

ESCRIPTION.................................................................................. 28

ESCRIPTION.................................................................................. 29

NTERFACE

EGISTER

02 BIT

03 BIT

04 BIT

05 BIT

D

08, 0

X

10, 0

11, 0

X

18, 0

19, 0

X

20 BIT

21 BIT

D

ESCRIPTION .................................................... 30

ESCRIPTION .................................................... 31

09, 0

X

0A, 0X12, 0X1A, 0X22 BIT DESCRIPTION ................................................... 32

6.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 33

AXIMUM RATINGS .................................................................................................................. 33

A

BSOLUTE M

T

F

T

ABLE 18: ABSOLUTE

ABLE 19: POWER AND

ABLE 20: LVDS/DIFFERENTIAL LVPECL INPUT

IGURE 19. LVDS/DIFFERENTIAL LVPECL VOLTAGE

ABLE 21: LVDS OUTPUT OGIC IGNAL DC ELECTRICAL

ABLE 22: DIFFERENTIAL LVPECL OUTPUT OGIC IGNAL DC ELECTRICAL

ABLE 23: LVTTL/LVCMOS SIGNAL DC ELECTRICAL

ABLE 24: ORDERING NFORMATION............................................................................................................................................... 37

M

C

AXIMUM

URRENT DC ELECTRICAL

OGIC

P

OWER

A

ND

I

NPUT/OUTPUT

R

ATINGS ........................................................................................... 33

HARACTERISTICS ............................................................................................ 33

HARACTERISTICS................................................ 34

ONVENTION ............................................................................. 35

HARACTERISTICS................................................................................. 36

HARACTERISTICS....................................................... 36

HARACTERISTICS ....................................................................................... 36

C

L

S

IGNAL DC ELECTRICAL

C

P

ARAMETER

C

L

S

C

L

S

C

I

PACKAGE DIMENSIONS ................................................................................................ 37

T

ABLE 25: REVISION

HISTORY........................................................................................................................................................ 38

V

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

PIN DESCRIPTIONS

HARDWARE CONTROL

NAME

L

EVEL

TYPE

P

IN

DESCRIPTION

RESET

LVTTL,

I

46

Master Reset Input

LVCMOS

Active "Low." When this pin is pulled "Low", the internal state

machines and registers are set to their default state.

"Low" = Master Hardware Reset

"High" = Normal Operation

This pin is provided with an internal pull-up.

TEST

LVTTL,

I

45

Test Input

LVCMOS

Active "High." When this pin is pulled "High", the 91L34 internal

state machines will enter into a factory test mode.

"Low" = Normal Operation

"High" = Factory Test Diagnostic Mode

N

OTE: This pin should be pulled Low for normal operation.

This pin is provided with an internal pull-down.

DATA0RATE[1:0]

DATA1RATE[1:0]

DATA2RATE[1:0]

DATA3RATE[1:0]

LVTTL,

I

115, 116 Data Rate Selection

Selects SONET/SDH reception speed rate for each of the four

channels independently according to the logic below.

LVCMOS

LVTTL,

113, 114

LVCMOS

DATA

N

RATE[1:0]

0

DATA RATE

0

LVTTL,

50, 49

STS-1/STM-0

51.84 Mbps

LVCMOS

0

1

0

1

STS-3/STM-1

155.52 Mbps

LVTTL,

48, 47

LVCMOS

STS-12/STM-4

622.08 Mbps

STS-12/STM-4

622.08 Mbps

N

OTE: These pins have no function in Host Mode.

These pins are provided with internal pull-down.

6

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

NAME

L

EVEL

TYPE

P

IN

DESCRIPTION

CDRREFSEL

LVTTL,

I

119

Clock and Data Recovery Unit Reference Frequency Select

LVCMOS

Selects the Clock and Data Recovery Unit reference frequency

on REFCLKP/N pins or TTLREFCLK pin based on the table

below.

"Low" = 77.76 MHz reference clock

"High" = 19.44 MHz reference clock

REFCLKP/N OR

TTLREFCLK

C

HANNEL 0 - 3

CDRREFSEL

A

VAILABLE ATA ATES

D

R

FREQUENCY

0

1

77.76 MHz

19.44 MHz

STS-12/STM-4 622.08 Mbps

STS-3/STM-1 155.52 Mbps

STS-1/STM-0 51.84 Mbps

N

OTE: REFCLKP/N or TTLREFCLK input should be generated

from a crystal oscillator which has a frequency

accuracy better than 100ppm in order for the received

data rate frequency to have the necessary accuracy

required for SONET systems.

OTE: This pin has no function in Host Mode.

This pin is provided with an internal pull-down.

OUTCFG

LVTTL,

I

44

Output Configuration

LVCMOS

Globally selects recovered clock and data outputs to be LVDS

or Differential LVPECL on all four channels based on table

below.

"Low" = LVDS Standard Output

"High" = Differential LVPECL Standard Output

OUTCFG

Input

Output

Configuration

0

1

LVDS/

LVDS

Differential LVPECL

LVDS/

Differential LVPECL

This pin is provided with an internal pull-down.

CDRDIS0

CDRDIS1

CDRDIS2

CDRDIS3

LVTTL,

I

107

106

56

Clock and Data Recovery Unit Disable

LVCMOS

Active "High." Disables internal Clock and Data Recovery unit

for respective channel. This enables lower power operation

when channel is unused.

55

"Low" = Internal CDR unit is Enabled

"High" = Internal CDR unit is Disabled

N

OTE: These pins have no function in Host Mode.

These pins are provided with internal pull-down.

7

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

NAME

L

EVEL

TYPE

P

IN

DESCRIPTION

DLOSDIS

/SDI

LVTTL,

I

39

DLOS (Digital Loss of Signal) Disable

LVCMOS

Hardware Mode Disables internal DLOS monitoring and auto-

matic muting of RXDO[3:0]P/N recovered data output pins upon

DLOS detection. DLOS is declared when the incoming data

stream has no transition for more than 2.5µs. DLOS is cleared

when transitions are detected within a 128µs interval sliding

window.

"Low" = Monitor & Mute recovered data upon DLOS declaration

"High" = Disable internal DLOS monitoring

This pin is provided with an internal pull-down.

Host Mode This pin is functions as the microprocessor Serial

Data Input.

POL0

POL1

POL2

POL3

LVTTL,

I

126

124

36

Polarity for SDEXT Input

LVCMOS

Controls the Signal Detect polarity convention of SDEXT.

"Low" = SDEXT is active "Low."

34

"High" = SDEXT is active "High."

N

OTE: These pins have no function in Host Mode.

These pins are provided with internal pull-down.

SDEXT0

SDEXT1

SDEXT2

SDEXT3

LVTTL,

127

125

35

Signal Detect Input from Optical Module

LVCMOS,

When inactive, it will immediately declare a Loss of Signal

(LOS) condition and assert LOS register bit and mute the activ-

ity of the RXDO[3:0]P/N serial data output on the respective

channel.

33

"Active" = Normal Operation

"Inactive" = LOS Condition (SDEXT detects signal absence)

These pins are provided with internal pull-down.

REFCLKP

REFCLKN

LVDS,

I

117

118

Reference Clock Input (77.76 MHz or 19.44 MHz)

Diff LVPECL

This differential reference clock input will accept either a 77.76

MHz or a 19.44 MHz LVDS/Differential LVPECL clock source.

Pin CDRREFSEL determines the value used as the reference.

See Pin CDRREFSEL for more details. REFCLKP/N inputs are

internally biased to 1.2V via 15kΩ resistance. These pins are

equipped with a 100Ω line-to-line internal termination.

N

OTE: In the event that TTLREFCLK LVTTL/LVCMOS input is

used instead of these differential inputs for clock

reference, the REFCLKP should be left unconnected

and REFCLKN should be tied to GND.

TTLREFCLK

LVTTL,

I

120

TTL Reference Clock Input (77.76 MHz or 19.44 MHz)

LVCMOS

This optional single-ended clock input reference can be used

instead of the differential REFCLKP/N input. It will accept

either a 77.76 MHz or a 19.44 MHz LVTTL clock source. Pin

CDRREFSEL determines the value used as the reference. See

Pin CDRREFSEL for more details.

N

OTE

:

In the event that REFCLKP/N differential inputs are

used instead of this LVTTL/LVCMOS input for clock

reference, the TTLREFCLK should be tied to ground.

This pin is provided with an internal pull-down.

8

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

RECEIVER SECTION

NAME

L

EVEL

TYPE

P

IN

DESCRIPTION

RXDI0P

RXDI0N

RXDI1P

RXDI1N

RXDI2P

RXDI2N

RXDI3P

RXDI3N

LVDS,

I

3

Receive Serial Data Input

Diff LVPECL

4

The differential receive serial data stream of 622.08 Mbps

STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 or 51.84 Mbps

STS-1/STM-0 is applied to these differential input pins. These

pins accept LVDS or Differential LVPECL input standard.

11

12

22

21

30

29

These pins are internally biased to 1.2V via 15kΩ resistance

and are equipped with a 100Ω line-to-line internal termination.

RXDO0P

RXDO0N

RXDO1P

RXDO1N

RXDO2P

RXDO2N

RXDO3P

RXDO3N

LVDS,

O

94

93

86

85

75

76

67

68

Recovered Serial Data Output

Diff LVPECL

622.08 Mbps STS-12/STM-4 / 155.52 Mbps STS-3/STM-1 /

51.84 Mbps STS-1/STM-0 differential recovered serial data out-

put that is updated simultaneously on the falling edge of the

corresponding channel RXCLKO output. User selectable LVDS

standard or Differential LVPECL standard output based on

OUTCFG pin state.

RXCLKO0P

RXCLKO0N

RXCLKO1P

RXCLKO1N

RXCLKO2P

RXCLKO2N

RXCLKO3P

RXCLKO3N

LVDS,

O

90

89

82

81

79

80

71

72

Recovered Clock Output

Diff LVPECL

(622.08 MHz/ 155.52 MHz/ 51.84 MHz)

622.08 MHz STS-12/STM-4 / 155.52 MHz STS-3/STM-1 /

51.84 MHz STS-1/STM-0 differential clock output for the corre-

sponding recovered data output RXDO[0:3]P/N. The recovered

serial data output port will be updated on the falling edge of

this clock. User selectable LVDS standard or Differential

LVPECL standard output based on OUTCFG pin state.

LOL0

LOL1

LOL2

LOL3

LVCMOS

O

98

99

63

64

CDR LOL Detect Output

This pin is used to monitor the lock condition of the PLL in the

clock and data recovery unit of each channel.

"Low" = CDR Locked

"High" = CDR Out of Lock

CAP0P

CAP0N

Analog

-

109

108

CDR Non-polarized External Loop Filter Capacitors

Mode of Operation:

1. STS12/STM4: CAP[0:3]P/N = 0.47µF ± 10% tolerance

2. STS3/STM1: CAP[0:3]P/N = 0.47µF ± 10% tolerance

3. STS1/STM0: CAP[0:3]P/N = 1.0µF ± 10% tolerance

Use type X7R or X5R for improved stability over temperature.

(Isolate from noise and place close to pin)

CAP1P

CAP1N

103

102

CAP2P

CAP2N

59

60

CAP3P

CAP3N

53

54

9

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

POWER AND GROUND

NAME

TYPE

P

IN

DESCRIPTION

AVDD1.8

DVDD1.8

VDD_IO

PWR

42, 57, 58, 104, 105,

123

1.8V Analog Core Power Supply

AVDD1.8 should be isolated from DVDD1.8 and 3.3V VDD_IO

power supplies. For best results, use a ferrite bead along with an

internal power plane separation. The AVDD1.8 power supply pins

should have bypass capacitors to the nearest ground.

51, 112

1.8V Digital Core Power Supply

DVDD1.8 should be isolated from AVDD1.8 and 3.3V VDD_IO

power supplies. For best results, use an internal power plane

separation. The DVDD1.8 power supply pins should have bypass

capacitors to the nearest ground.

5, 6, 13, 14, 19, 20, 27, 3.3V Input/Output Bus Power Supply

28, 65, 66, 73, 74, 87,

88, 95, 96

These pins require a 3.3V potential voltage for properly biasing

the Differential LVDS/Differential LVPECL and LVCMOS/LVTTL

input and output pins.

VDD_IO should be isolated from the AVDD1.8 and DVDD1.8

Core power supplies. For best results, use a ferrite bead along

with an internal power plane separation. The VDD_IO power sup-

ply pins should have bypass capacitors to the nearest ground.

GND_IO

GND

7, 8, 15, 16, 17, 18, 25, Ground for 3.3V VDD Input/Output Power Supplies

26, 69, 70, 77, 78, 83,

84, 91, 92

It is recommended that all ground pins of this device be tied

together.

GND 43, 52, 61, 62, 100, 101, Power Supply and Thermal Ground

110, 111, 121

It is recommended that all ground pins of this device be tied

together.

NC

1, 2, 9, 10, 23, 24, 31, No Connect

32, 97, 128

10

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

SERIAL MICROPROCESSOR INTERFACE

NAME

L

EVEL

TYPE

P

IN

DESCRIPTION

HOST/HW

LVTTL,

I

122

Host or Hardware Mode Select Input

LVCMOS

The XRT91L34 offers two modes of operation for interfacing to the

device. The Host mode uses a serial microprocessor interface for

programming individual registers. The Hardware mode is controlled

by the state of the hardware pins set by the user. When left uncon-

nected, by default, the device is configured in the Hardware mode.

"Low" = Hardware Mode

"High" = Host Mode

This pin is provided with an internal pull-down.

CS

LVTTL,

I

38

Chip Select Input (Host Mode)

LVCMOS

Active "Low" signal. This signal enables the serial microprocessor

interface by pulling chip select "Low". The serial microprocessor is

disabled when the chip select signal returns "High".

NOTES:

1. The serial microprocessor interface does not support burst

mode. Chip Select must be de-asserted after each

operation cycle.

2. Chip Select is only active in Host Mode.

This pin is provided with an internal pull-up.

SCLK

LVTTL,

I

37

39

Serial Clock Input (Host Mode Only)

LVCMOS

Once CS is pulled "Low", the serial microprocessor interface

requires 16 clock cycles for a complete Read or Write operation.

Serial Clock Input is only active in Host Mode.

This pin is provided with an internal pull-down.

DLOSDIS

/SDI

LVTTL,

Serial Data Input (Host Mode Only)

LVCMOS

When CS is pulled "Low", the serial data input is sampled on the ris-

ing edge of SCLK.

Serial Data Input is only active in Host Mode.

This pin is provided with an internal pull-down.

Hardware Mode This pin is functions as the DLOSDIS control pin.

SDO

LVCMOS

O

40

41

Serial Data Output (Host Mode Only)

If a Read function is initiated, the serial data output is updated on

the falling edge of SCLK8 through SCLK15, with the LSB (D0)

updated first. This enables the data to be sampled on the rising

edge of SCLK9 through SCLK16.

Serial Data Output is only active in Host Mode.

INT

Interrupt Output (Host Mode Only)

Active "Low" signal. This signal is asserted "Low" when a change in

alarm status occurs. Once the status registers have been read, the

interrupt pin will return "High".

Interrupt Output is only active in Host Mode.

NOTE

:

This open-drain output pin requires an external pull-up

resistor.

11

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

1.0 FUNCTIONAL DESCRIPTION

REV. 1.0.1

The XRT91L34 Quad Channel CDR is designed to operate with a multichannel SONET Framer/ASIC device

and provide a high-speed serial clock and data recovery interface to optical networks. The CDR receives

differential NRZ serial bit stream running at STS-12/STM-4 or STS-3/STM-1 or STS-1/STM-0, and outputs

recovered serial clock and data via differential LVDS/LVPECL drivers. It implements four independently

configurable receive clock and data recovery (CDR) units and a LOL and LOS detection circuit (Host Mode

Only) for each channel. The CDR is used to provide the front end component of SONET equipment.

1.1

Hardware Mode vs. Host Mode

Functional control of the receiver can be configured by using either Host mode or Hardware mode. Hardware

mode is selected by pulling HOST/HW "Low" or leaving this pin unconnected. The receiver functionality is then

controlled by the hardware pins described in the Hardware Pin Descriptions. Host mode is selected by pulling

HOST/HW "High". In Host mode the functionality is controlled by programming internal R/W registers using the

Serial Microprocessor interface. Host mode offers functions not available in Hardware mode, such as Loss of

Signal Monitoring, Interrupt Generation and Disabling of the recovered clock output.

1.2

STS-12/STM-4 and STS-3/STM-1 and STS-1/STM-0 Mode of Operation

The data rate of each receiver channel can be configured by using the appropriate signal level on the

DATAnRATE1:0] pins (where n = channel 0, 1, 2, or 3) as shown in Table 1.

TABLE 1: CHANNEL

D

ATA

R

ATE

SELECTION

D

ATA RATE

S

ELECTED FOR

DATA RATE[1:0]

N

CHANNEL N

0

STS-1/STM-0

51.84 Mbps

0

1

0

1

STS-3/STM-1

155.52 Mbps

STS-12/STM-4

622.08 Mbps

STS-12/STM-4

622.08 Mbps

NOTE: n denotes channel number.

12

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

1.3

Reference Clock Input

The XRT91L34 can accept either a 19.44 MHz or 77.76 MHz Differential clock input at REFCLKP/N or a

Single-Ended LVTTL clock input at TTLREFCLK. The REFCLKP/N or TTLREFCLK should be generated from

a source which has a frequency accuracy better than ±100ppm in order for the CDR Loss of Lock detector to

have the necessary accuracy required for SONET systems. The reference clock can be provided with one of

two frequencies chosen by CDRREFSEL. The reference frequency options for the XRT91L34 are listed in

Table 2. Figure 3 illustrate the reference clock design options.

TABLE 2: CDR REFERENCE FREQUENCY OPTIONS (LVDS/ DIFF LVPECL OR SINGLE-ENDED LVTTL/LVCMOS)

REFCLKP/N OR TTLREFCLK

C

HANNEL 0 - 3

CDRREFSEL

FREQUENCY

A

VAILABLE ATA ATES

D

R

0

1

77.76 MHz

19.44 MHz

STS-1/STM-0 51.84 Mbps

STS-3/STM-1 155.52 Mbps

STS-12/STM-4 622.08 Mbps

FIGURE 3. REFERENCE CLOCK DESIGN OPTIONS

Single-Ended LVTTL/LVCMOS

Reference Clock Option

Differential LVPECL or LVDS

Reference Clock Option

REFCLKP and REFCLKN pins

internally biased and terminated with

100 Ohm line-to-line

REFCLKP

Differential Clock

Source

77.76/19.44 MHz

Leave REFCLKP unconnected

and

VBB_1.2

100

REFCLKN

130 Ohm

tie REFCLKN pin to GND

Resistors for LVPECL

Remove for LVDS

Internal

REFCLK

TTLREFCLK

Tie unused TTLREFCLK

input pin to GND

Single Ended

Clock Source

77.76/19.44 MHz

XRT91L34

13

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

2.0 RECEIVE SECTION

REV. 1.0.1

The receive section of XRT91L34 includes four differential input buffers RXDI[3:0]P/N, followed by clock and

data recovery units (CDR) and recovered serial data and clock differential output drivers. The receiver accepts

the high speed Non-Return to Zero (NRZ) serial data at 622.08/155.52/51.84 Mbps through the input interfaces

RXDI[3:0]P/N. The clock and data recovery unit recovers the high-speed receive clock from the incoming data

stream. The recovered serial data is presented to the RXDO[3:0]P/N differential output driver interface. The

high-speed recovered clock RXCLKO[3:0]P/N, is used to synchronize the transfer of the RXDO[3:0]P/N data

with the receive portion of a framer/mapper device. The recovered data RXDO[3:0]P/N and clock

RXCLKO[3:0]P/N differential output driver interfaces are designed for ultimate flexibility by supporting either

LVDS or Differential LVPECL protocol level. Upon initialization or loss of signal or loss of lock, the external

reference clock signal of 19.44 MHz or 77.76 MHz is used to start-up the clock recovery phase-locked loop for

proper operation. The included CDR blocks in the XRT91L34 can be individually disabled by asserting the

CDRDIS[3:0] pins to permit the flexibility of powering down unused channels.

2.1

Receive Serial Input

The receive serial inputs are applied to RXDI[3:0]P/N. The XRT91L34 includes internal termination, this has

the advantage of reducing the number of external board components. The XRT91L34 terminates the receive

inputs using 100Ω line-to-line method of termination. Differential LVPECL operation of receive inputs can be

supported, provided each optical module Differential LVPECL output pin must have a 130Ω DC current path

resistor to GND whether internally or externally. A simplified LVDS/Differential LVPECL DC coupling block

diagram is shown in Figure 4.

FIGURE 4. RECEIVE

S

ERIAL

INPUT

I

NTERFACE USING LVDS/DIFF LVPECL DC COUPLING INTERNAL TERM

Internal 100 Ohm line-to-line

LVDS or DIFF LVPECL Operation

termination active on

RXDI[3:0]P and RXDI[3:0]N pins

Internal 130 Ohm line to GND DC current path resistors

required for Optical Module DIFF LVPECL Operation

RXDI0P

100

VBB_1.2

Channel 0

Channel 1

Channel 2

Channel 3

Optical Module

RXDI0N

Optical Fiber

RXDI1P

RXDI1N

XRT91L34

VBB_1.2100

STS-12/3/1

or

STM-4/1/0

Clock and Data

Recovery

RXDI2P

RXDI2N

RXDI3P

RXDI3N

NOTE: Some optical modules integrate AC coupling capacitors and DC current path resistors internally within the module.

AC or DC coupling is largely specific to system design and optical module of choice.

14

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

The receive serial inputs can also be AC coupled to an optical module or an electrical interface. A simplified

Differential LVPECL AC coupling using external passive components block diagram is shown in Figure 5.

F

IGURE 5. RECEIVE SERIAL INPUT INTERFACE USING DIFF LVPECL AC COUPLING INTERNAL TERMINATION

D

IFF LVPECL A/C Coupling using

Internal 100 Ohm line-to-line

termination active on

RXDI[3:0]P and RXDI[3:0]N pins

External Passive Components

Channel 0

RXDI0P

Optical Fiber

VBB_1.2

100

Optical Module

RXDI0N

Channel 1

RXDI1P

RXDI1N

VBB_1.2

XRT91L34

100

Optical Module

STS-12/3/1

or

Channel 2

RXDI2P

RXDI2N

STM-4/1/0

Clock and Data

Recovery

100

Optical Module

VBB_1.2

Channel 3

RXDI3P

RXDI3N

100

Optical Module

VBB_1.2

130 x 8

Install DC current path resistors

as close to Optical Module

LVPECL output driver pins

NOTE: Some optical modules integrate AC coupling capacitors and DC current path resistors internally within the module.

2.2

Receive Clock and Data Recovery

The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential receiver

and generates a clock that is the same frequency as the incoming data. The clock recovery block utilizes the

reference clock from REFCLKP/N or TTLREFCLK to train and monitor its clock recovery PLL. Upon startup,

the PLL locks to the local reference clock. Once this is achieved, the PLL then attempts to lock onto the

incoming receive serial data stream. Whenever the recovered clock frequency deviates from the local

reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch to the

local reference clock, declare a Loss of Lock and output a high level signal on the LOL output pin. Whenever a

Loss of Lock (LOL) or a Loss of Signal (LOS) event occurs, the CDR will continue to supply a receive clock

(based on the local reference). When the SDEXT becomes active and internal DLOS is cleared and the

recovered clock is determined to be within ±500 ppm accuracy with respect to the local reference source, the

clock recovery PLL will switch back to the incoming receive serial data stream. Table 3 specifies the Clock and

Data Recovery Unit performance characteristics.

15

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

T

ABLE 3: CLOCK AND

D

ATA

R

ECOVERY

UNIT

P

ERFORMANCE

IN

NAME

P

ARAMETER

M

TYP

M

AX

UNITS

REF

TOL

Reference clock duty cycle

Reference clock frequency tolerance

40

60

%

DUTY

TOL

JIT

2

-100

0.3

45

+100

ppm

UI

Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern

Clock output duty cycle

0.4

OCLK

55

%

DUTY

Jitter specification is defined using a 12kHz to 0.4/1.3/5MHz LP-HP single-pole filter.

1

These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUI ).

rms

2

Required to meet SONET output frequency stability requirements.

2.2.1

Internal Clock and Data Recovery Disable

Optionally, each of the four internal CDR unit can be disabled and powered down when the channel is not in

use. Asserting the CDRDISn pin (where n = channel 0, 1, 2, or 3 ) "High" in Hardware Mode or setting

CDRDISn bit (where n = channel 0, 1, 2, or 3 ) in Host Mode, disables the internal Clock and Data Recovery

unit for that particular channel.

2.3

External Receive Loop Filter Capacitors

For STS12/STM4 and STS3/STM1 operation, use 0.47µF (or greater) non-polarized external loop filter

capacitors to achieve the required receiver jitter performance for each of the channels. For STS1/STM0

operation, use a minimum of 1.0µF non-polarized capacitors. If all 3 data rates STS12/STS3/STS1 are

required in an application, then use 1uF loop filter capacitors. They must be well isolated to prohibit noise

entering the CDR block and should be placed as close to the pins as possible. Figure 6 shows the pin

connections and external loop filter components. These four non-polarized capacitors should be of +/- 10%

tolerance. Use type X7R or X5R capacitors for improved stability over temperature.

FIGURE 6. EXTERNAL LOOP FILTERS

0.47uF

non-polarized

0.47uF

non-polarized

Channel 0LoopFilter

External Capacitor

Channel 1LoopFilter

External Capacitor

pin 108

pin 109

pin 103

pin 102

CAP0P

CAP0N

CAP1P

CAP1N

Use1...0uFnon-polarized

capacitorsfor

STS1/STM0Operation

..

0.47uF

non-polarized

0.47uF

non-polarized

Channel 2LoopFilter

External Capacitor

Channel 3LoopFilter

External Capacitor

pin 59

pin 53

pin 60

Pin 54

CAP3P

CAP3N

CAP2P

CAP2N

16

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

2.4

Internal Digital Loss of Signal and External Signal Detection

XRT91L34 has an integrated Digital Loss of Signal (DLOS) circuit and supports external Signal Detection

(SDEXT) for detecting and determining received signal integrity. The internal DLOS circuit monitors the

incoming data stream. If the incoming data stream has no transition for more than 2.5µs, Loss of Signal is

declared. This LOS condition will be cleared when the circuit detects transitions in a 128µs interval sliding

window. Pulling the DLOSDIS pin signal to a high level in hardware mode or setting DLOSDIS bit in host mode

will disable the internal DLOS detection circuit to permit the framer/mapper interface to determine the Loss of

Signal declaration and clearance criteria for specific applications. The external Signal Detect function is

supported by the SDEXT input. An LVCMOS/LVTTL signal comes from the optical module through an output

usually called “SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the

manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High." The

SDEXT and POL inputs are Exclusive OR’ed to determine external Loss of Signal (LOS) condition. In the event

that internal DLOS is detected or an external SDEXT input indicates signal absence, the recovered serial data

output will be forced to a logic state "0," and the LOS status register is set whenever the host mode serial

microprocessor interface is active. This acts as a receive data mute upon LOS function to prevent data

chattering and to prevent random noise from being misinterpreted as valid incoming data. Figure 7 shows the

Loss of Signal Detection logic circuit. Table 4 specifies LOS declaration polarity settings.

FIGURE 7. LOSS OF SIGNAL DECLARATION CIRCUIT

DLOSDIS

LOS Declaration

and

(Internal) DLOS Detect

POL

Recovered Data Mute

(External) SDEXT

TABLE 4: EXTERNAL LOS DECLARATION POLARITY SETTING

LOS BIT STATE

(HOST MODE NLY

SDEXT

0

POL

0

I

NTERNAL

S

IGNAL

D

ETECT

RXDO[3:0]P/N

O

)

Active Low. Optical signal presence

indicated by SDEXT logic 0 input from

optical module.

Normal

Low

Operation

0

1

0

1

Active High. Optical signal presence

indicated by SDEXT logic 1 input from

optical module.

High

Muted

LOS declared

Active Low. Optical signal presence

indicated by SDEXT logic 0 input from

optical module.

High

LOS declared

Active High. Optical signal presence

indicated by SDEXT logic 1 input from

optical module.

Normal

Low

Operation

17

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

2.5

Multichannel Recovered Output Interface

The recovered data RXDO[3:0]P/N differential output drivers along with the recovered clock RXCLKO[3:0]P/N

differential output drivers can be configured for LVDS or Differential LVPECL standard operation. In addition,

Host Mode operation permits each of the channelized recovered clock output to be independently disabled

such as in repeater applications to save power.

F

IGURE 8. MULTICHANNEL

R

ECOVERED

O

UTPUT

INTERFACE

B

LOCK

LVDS Operation

OUTCFG = 0

RXDO0P

RXDO0N

Channel 0

Channel 1

Channel 2

Channel 3

100

SONET Framer/

ASIC

RXDO1P

RXDO1N

XRT91L34

STS-12/3/1

or

STM-4/1/0

Clock and Data

Recovery

Internal or External 100 Ohm

line-to-line termination required on

RXDO[3:0]P and RXDO[3:0]N pins

on the SONET Framer/ASIC end

RXDO2P

RXDO2N

RXDO3P

RXDO3N

RXCLKO[3:0]P and

RXCLKO[3:0]N

Clock Output pins

terminated similarly

OUTCFG = 1

VDD_IO

Install terminators as close to

SONET Framer/ ASIC pins

120 x 8

LVPECL Operation

RXDO0P

Channel 0

RXDO0N

SONET Framer/

ASIC

RXDO1P

RXDO1N

XRT91L34

Channel 1

STS-12/3/1

or

STM-4/1/0

Clock and Data

Recovery

RXDO2P

RXDO2N

Channel 2

Channel 3

RXDO3P

RXDO3N

RXCLKO[3:0]P and

RXCLKO[3:0]N

82 x 8

Clock Output pins

terminated similarly

18

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

2.6

Differential Recovered Data Output Timing

The differential recovered data and clock outputs operating at the STS-12/STM-4 or STS-3/STM-1 or STS-1/

STM-0 datarates will adhere to the data valid output timing shown in Figure 9 ,Table 5, Table 6, and Table 7.

F

IGURE 9. DIFFERENTIAL RECOVERED OUTPUT TIMING

t_RXCLKO

RXCLKO[3:0]P/N

RXDO[3:0]P/N

D1

D2

D3

D4

D5

t_{RXDO_VALID}

TABLE 5: RECOVERED

D

ATA

OUTPUT TIMING (STS-12/STM-4 OPERATION)

S

YMBOL

P

ARAMETER

MIN

TYP

MAX

UNITS

t

Recovered high-speed output clock period

1.608

ns

RXCLKO

t

Time the data is valid on RXDO[3:0]P/N before and after the

rising edge of RXCLKO[3:0]P/N

0.5

ns

RXDO_VALID

TABLE 6: RECOVERED

D

ATA

OUTPUT TIMING (STS-3/STM-1 OPERATION)

S

YMBOL

P

ARAMETER

MIN

TYP

MAX

UNITS

t

Recovered high-speed output clock period

6.43

ns

RXCLKO

t

Time the data is valid on RXDO[3:0]P/N before and after the

rising edge of RXCLKO[3:0]P/N

2.8

ns

RXDO_VALID

TABLE 7: RECOVERED

D

ATA

OUTPUT TIMING (STS-1/STM-0 OPERATION)

S

YMBOL

P

ARAMETER

MIN

TYP

MAX

UNITS

t

Recovered high-speed output clock period

19.29

ns

RXCLKO

t

Time the data is valid on RXDO[3:0]P/N before and after the

rising edge of RXCLKO[3:0]P/N

8.3

ns

RXDO_VALID

19

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

3.0 JITTER PERFORMANCE

REV. 1.0.1

3.1

SONET Jitter Requirements

SONET receive equipment jitter requirements are specified jitter tolerance and jitter transfer. The definitions of

each of these types of jitter are given below.

3.1.1

Rx Jitter Tolerance:

OC-1/STM-0, OC-3/STM-1, and OC-12/STM-4 category II SONET interfaces should tolerate, the input jitter

applied according to the mask of Figure 10, with the corresponding parameters specified in the figure.

F

IGURE 10. GR-253/G.783 JITTER TOLERANCE MASK

A₃

slope= -20dB/decade

Input

Jitter

Amplitude

(UI_pp)

A₂

slope= -20dB/decade

A₁

f₀

f₁

f₂

Jitter Frequency (Hz)

f₄

f₃

OC-N STM-X LEVEL

F0 (HZ)

10

F1 (HZ)

30

F2 (HZ)

300

F3 (HZ)

22KK

F4 (HZ)

A1 (UIPP) A2 (UIPP) A3 (UIPP)

OC1/STS11

STM0

STM1

2200KK

65K

00..1155

0.15

1.5

1155

15

OC3/STS33

10

30

300

6.5K

25K

OC12/STS1212 STM4

10

30

300

250K

F

IGURE 11. XRT91L34 MEASURED JITTER TOLERANCE AT 51.84 MBPS STS-1/STM-0

Jitter Tolerance, GR-253, OC-1 (51 Mbps)

Mask

Jitter Tolerance

100.00

10.00

1.00

0.10

0.01

1E+0

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

Frequency (Hz)

20

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

F

IGURE 12. XRT91L34 MEASURED JITTER TOLERANCE AT 155.52 MBPS STS-3/STM-1

Jitter Tolerance, GR-253, OC-3 (155 Mbps)

Jitter Tolerance

Mask

100.00

10.00

1.00

0.10

0.01

1E+0

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

Frequency (Hz)

FIGURE 13. XRT91L34 MEASURED JITTER TOLERANCE AT 622.08 MBPS STS-12/STM-4

Jitter Tolerance, GR-253, OC-12 (622 Mbps)

Jitter Tolerance

Mask

1000.00

100.00

10.00

1.00

0.10

0.01

1E+0

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

Frequency (Hz)

21

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

3.1.2

Rx Jitter Transfer

Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input

versus frequency. It displays the ability of the component unit to attenuate jitter at the specified injected jitter

frequencies. There are two distinct characteristics in jitter transfer, jitter gain (jitter peaking) defined as the

highest ratio above 0dB and jitter transfer bandwidth. The overall jitter transfer bandwidth is controlled by a low

bandwidth loop.

The XRT91L34 meets the latest jitter transfer characteristics as shown in the Figure 14, Figure 15, and

Figure 16. The XRT91L34 complies with STS-12/3/1 and STM-4/1/0 jitter transfer masks set forth by Bellcore

GR-253 Core section 5.6.2.1 and ITUT G.783 section 15.1.3 as defined in G.825.

F

IGURE 14. XRT91L34 MEASURED

JITTER TRANSFER AT 51.84 MBPS STS-1/STM-0

Jitter Transfer, GR253H, OC-1 (52Mbps)

Mask

Jitter Transfer

5

0

-5

-10

-15

-20

-25

-30

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

Frequuency (Hz)

F

IGURE 15. XRT91L34 MEASURED JITTER TRANSFER AT 155.52 MBPS STS-3/STM-1

Jitter Transfer, GR253H, OC-3 (155 Mbps)

Mask

Jitter Transfer

5

0

-5

-10

-15

-20

-25

-30

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

Frequuency (Hz)

22

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

F

IGURE 16. XRT91L34 MEASURED JITTER TRANSFER AT 622.08 MBPS STS-12/STM-4

Jitter Transfer, GR253H, OC-12 (622 Mbps)

Mask

Jitter Transfer

5

0

-5

-10

-15

-20

-25

-30

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

Frequuency (Hz)

23

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK

REV. 1.0.1

The Serial Microprocessor Interface uses a standard 3-pin serial port with CS, SCLK, and SDI for programming

the device. Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the registers,

monitor the device via an interrupt pin, and reset the device to its default configuration by pulling reset "Low"

for more than 10ns. A simplified block diagram of the Serial Microprocessor Interface is shown in Figure 17.

FIGURE 17. SIMPLIFIED

B

LOCK

D

IAGRAM OF THE

S

ERIAL

M

ICROPROCESSOR INTERFACE

SDI

Data out

SDO

Shift Register

SCLK

Address

bus

Data

bus

CS

INT

Register

Bank

Status bits and error

Flags from CDRs

Controls to

CDRs

RESET

4.1 SERIAL

TIMING INFORMATION

The serial port requires 16 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor

Interface samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device

until all 16 bits of serial data have been sampled. A timing diagram of the Serial Microprocessor Interface is

shown in Figure 18.

FIGURE 18. TIMING

DIAGRAM FOR THE

S

ERIAL MICROPROCESSOR INTERFACE

CS

SCLK

SDI

25nS

50nS

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

R/W

A0

A1

A2

A3

A4

A5

X

D0

D1

D2

D3

D4

D5

D6

D7

High-Z

D1

D2

D3

D4

D5

D6

D7

SDO

NOTE: The serial microprocessor interface does NOT support "burst write" or "burst read" operations. Chip Select (active

"Low") must be de-asserted at the end of each write or read operation.

24

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

4.2 16-BIT

SERIAL DATA INPUT DESCRITPTION

The serial data input is sampled on the rising edge of SCLK. For read operations, the SDO signal is updated

on the falling edge of SCLK. The serial data must be applied to the serial port LSB first. The 16 bits of serial

data are described below.

4.2.1 R/W (SCLK1)

The first serial bit applied to the device SDI pin determines whether a Read or Write operation is desired. If the

R/W bit is set to “0”, the serial port is configured for a Write operation. If the R/W bit is set to “1”, the serial port

is configured for a Read operation.

4.2.2 A[5:0] (SCLK2 - SCLK7)

The next 6 SCLK cycles are used to provide the address to which a Read or Write operation will occur. A0

(LSB) must be sent to the SDI pin first followed by A1 and so forth until all 6 address bits have been sampled

by SCLK.

4.2.3 X (Dummy Bit SCLK8)

The dummy bit sampled by SCLK8 is used to allow sufficient time for the serial data output pin to update data

if the readback mode is selected by setting R/W = “1”. Therefore, the state of this bit is ignored and can hold

either “0” or “1” during both Read and Write operations.

4.2.4 D[7:0] (SCLK9 - SCLK16)

The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the ad-

dress bits. D0 (LSB) must be sent to the SDI pin first followed by D1 and so forth until all 8 data bits have been

sampled by SCLK. Once 16 SCLK cycles have been complete, the data is held until CS is pulled “High”

whereby, the serial port latches the data into the selected internal register.

4.3 8-BIT

SERIAL DATA OUTPUT DESCRIPTION

When R/W is set to “1” (Read operation) the serial data output is updated on the falling edge of SCLK8 -

SCLK16, D0 (LSB) is provided at the SDO pin on the falling edge of SCLK8, followed by D1 and so forth until

all 8 data bits have been updated after which the SDO output pin returns to a high impedance state until the

next read operation.

25

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

5.0 REGISTER MAP AND BIT DESCRIPTIONS

REV. 1.0.1

The XRT91L34 consists of 6 Common Registers including the Device ID and Revision ID registers and 12

channelized registers. Table 8 below presents the overall Register Map.

T

ABLE 8: MICROPROCESSOR

I

NTERFACE

R

EGISTER

D3

M

AP

D2

R

EG ADDR

TYPE

D7

D6

D5

D4

D1

D0

Control Registers (0x00 - 0x22)

0

1

2

0x00

0x01

0x02

R/W

RO

Reserved

DLOSDIS

Reserved

INTS3

MINT_EN

INTS2

CDRREFSEL

INTS1

SWRST

INTS0

Device ID MSB (See Bit Description)

Device ID LSB (See Bit Description)

3

4

5

0x03

0x04

0x05

RO

Revision ID MSB (Register value is 0x00)

Revision ID LSB (See Bit Description)

6

7

0x06

0x07

R/W

Reserved

C

HANNEL

0

8

9

0x08

0x09

0x0A

R/W

Reserved

RCLKDIS0

Reserved

CDRDIS0

LOL0_IE

LOL0_IS

POL0

DATA0RATE1 DATA0RATE0

LOL0 LOS0

LOS0_IE

LOS0_IS

10

RO

RUR

0x0B - 0x0F

RO

Reserved

C

HANNEL

1

16

0x10

0x11

0x12

R/W

Reserved

RCLKDIS1

Reserved

CDRDIS1

LOL1_IE

LOL1_IS

POL1

17

18

DATA1RATE1 DATA1RATE0

LOL1 LOS1

LOS1_IE

LOS1_IS

RO

RUR

0x13 - 0x17

RO

Reserved

C

HANNEL

2

24

0x18

0x19

0x1A

R/W

Reserved

RCLKDIS2

Reserved

CDRDIS2

LOL2_IE

LOL2_IS

POL2

25

26

DATA2RATE1 DATA2RATE0

LOL2 LOS2

LOS2_IE

LOS2_IS

RO

RUR

0x1B - 0x1F

RO

Reserved

C

HANNEL

3

32

0x20

0x21

0x22

R/W

Reserved

RCLKDIS3

Reserved

CDRDIS3

LOL3_IE

LOL3_IS

POL3

33

34

DATA3RATE1 DATA3RATE0

LOL3 LOS3

LOS3_IE

LOS3_IS

RO

RUR

26

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

COMMON CONTROL REGISTERS

TABLE 9: MICROPROCESSOR

INTERFACE

R

EGISTER

0X00 BIT DESCRIPTION

G

LOBAL

C

ONTROL

R

EGISTER (0 00)

X

Regis-

ter

Default

Value

B

IT

N

AME

F

UNCTION

Type

(HW Reset)

D7

D6

D5

D4

Reserved

DLOSDIS

This Register Bit is Not Used

RO

0

RO

DLOS (Digital Loss of Signal) Disable

R/W

This global bit is used to disable the channelized internal DLOS

monitoring and automatic muting of RXDO[3:0]P/N recovered data

output pins upon DLOS detection.

"0" = Monitor & Mute recovered data upon LOS declaration

"1" = Disable internal DLOS monitoring

D3

D2

Reserved

MINT_EN

This Register Bit is Not Used

RO

0

Master Interrupt Enable

R/W

"0" = Disables Interrupt generation

"1" = Enables Interrupt generation

D1

D0

CDRREFSEL Clock and Data Recovery Unit Reference Frequency Select

This bit is used to select the clock input reference.

"0" = 77.76 MHz reference frequency support

R/W

0

"1" = 19.44 MHz reference frequency support

SWRST

Software Reset

A "0" to "1" transition will asynchronously reset the device and all

register bit settings to their default state. This bit will automatically

reset itself to "0". User does not have to write "0" to this bit to resume

normal operation.

"0" = Normal Operation

"1" = Resets all registers to default values

27

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

T

ABLE 10: MICROPROCESSOR

I

NTERFACE

R

EGISTER

0

X

01 BIT

01)

DESCRIPTION

C

HANNEL

INTERRUPT TATUS

S

R

EGISTER (0

X

Regis-

ter

Default

Value

B

IT

N

AME

FUNCTION

Type

(HW Reset)

D7

D6

D5

D4

D3

Reserved

INTS3

This Register Bit is Not Used

Channel 3 Interrupt Status

RO

0

This bit indicates an interrupt occuring in Channel 3.

"0" = No Interrupt Generated

"1" = Channel Interrupt Occurring

D2

D1

D0

INTS2

INTS1

INTS0

Channel 2 Interrupt Status

RO

0

This bit indicates an interrupt occuring in Channel 2.

"0" = No Interrupt Generated

"1" = Channel Interrupt Occurring

Channel 1 Interrupt Status

This bit indicates an interrupt occuring in Channel 1.

"0" = No Interrupt Generated

"1" = Channel Interrupt Occurring

Channel 0 Interrupt Status

This bit indicates an interrupt occuring in Channel 0.

"0" = No Interrupt Generated

"1" = Channel Interrupt Occurring

T

ABLE 11: MICROPROCESSOR

I

NTERFACE

R

EGISTER

02)

0X02 BIT DESCRIPTION

D

EVICE "ID" REGISTER (0

X

Register

Type

Default

Value

B

IT

N

AME

FUNCTION

(HW reset)

D7

D6

D5

D4

D3

D2

D1

D0

Device "ID" The device "ID" of the XRT91L34 CDR is 0x8405h. Along with the

RO

1

0

1

0

revision "ID", the device "ID" is used to enable software to identify

the silicon adding flexibility for system control and debug.

MSB

28

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

T

ABLE 12: MICROPROCESSOR

I

NTERFACE

R

EGISTER

03)

0X03 BIT DESCRIPTION

D

EVICE "ID" REGISTER (0

X

Register

Type

Default

Value

B

IT

N

AME

FUNCTION

(HW reset)

D7

D6

D5

D4

D3

D2

D1

D0

Device "ID" The device "ID" of the XRT91L34 CDR is 0x8405h. Along with the

RO

0

1

0

1

revision "ID", the device "ID" is used to enable software to identify

the silicon adding flexibility for system control and debug.

LSB

T

ABLE 13: MICROPROCESSOR

I

NTERFACE

R

EGISTER

04)

0X04 BIT DESCRIPTION

R

EVISION "ID" REGISTER (0

X

Register

Type

Default

Value

B

IT

N

AME

FUNCTION

(HW reset)

D7

D6

D5

D4

D3

D2

D1

D0

Revision The revision "ID" of the XRT91L34 CDR is used to enable software

RO

0

"ID"

to identify which revision of silicon is currently being tested. This

MSB revision "ID" register will always contain the value 0x00h.

MSB

T

ABLE 14: MICROPROCESSOR

I

NTERFACE

R

EGISTER

05)

0X05 BIT DESCRIPTION

R

EVISION "ID" REGISTER (0

X

Register

Type

Default

Value

B

IT

N

AME

FUNCTION

(HW reset)

D7

D6

D5

D4

D3

D2

D1

D0

Revision The revision "ID" of the XRT91L34 CDR is used to enable software

RO

This byte

shows the

revision of

the device.

"ID"

to identify which revision of silicon is currently being tested. The

revision "ID" for the first revision of silicon (Revision A) will be

0x01h.

LSB

29

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

CHANNELIZED REGISTERS

REV. 1.0.1

TABLE 15: MICROPROCESSOR

I

NTERFACE

REGISTER

0

X

08, 0

X

10, 0

X

18, 0

X

20 BIT ESCRIPTION

D

C

HANNEL

CONTROL

R

EGISTER (C

H

0 = 0

X

08, C

H1 = 0

X

10, C

H2 = 0

X

18, C 3 = 0X20)

H

Register

Type

Default

Value

B

IT

N

AME

FUNCTION

(HW reset)

D7

D6

D5

D4

D3

D2

Reserved

RCLKDISn

This Register Bit is Not Used

RO

R/W

0

Recovered Serial Clock Output Disable

This bit is used to control the activity of the 622.08/155.52/51.84

MHz differential serial clock output. Tristating RXCLKOnP/N output

reduces power consumption.

"0" = RXCLKOnP/N output Enabled

"1" = RXCLKOnP/N output Tristated

D1

D0

CDRDISn

POLn

Clock and Data Recovery Unit Disable

Disables Internal Clock and Data Recovery Unit.

"0" = Internal CDR Unit is Enabled

R/W

0

"1" = Internal CDR Unit is Disabled

Polarity for SDEXT Input

Controls the Signal Detect polarity convention of SDEXT.

"0" = SDEXT is active "Low"

"1" = SDEXT is active "High"

NOTE: n denotes channel number.

30

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

T

ABLE 16: MICROPROCESSOR

I

NTERFACE

R

EGISTER

0

X

09, 0

X

11, 0

X

19, 0

X

21 BIT

D

ESCRIPTION

19, C 3 = 0X21)

C

ONFIGURATION AND

I

NTERRUPT

ENABLE HANNEL

C

R

EGISTER (C

H

0 = 0

X

09, C

H

1 = 0

X

11, C

H2 = 0

X

H

Register

Type

Default

Value

B

IT

N

AME

FUNCTION

(HW reset)

D7

D6

D5

D4

Reserved

This Register Bit is Not Used

RO

0

DATAnRATE1 Data Rate Selection Bit-1 and Bit-0

R/W

These bits selects SONET/SDH reception speed rate for each of

the four channels independently according to the logic below.

DATAnRATE0

DATA

0

N

RATE[1:0]

DATA RATE

0

STS-1/STM-0

51.84 Mbps

0

1

0

1

STS-3/STM-1

155.52 Mbps

STS-12/STM-4

622.08 Mbps

STS-12/STM-4

622.08 Mbps

D3

D2

D1

Reserved

LOLn_IE

This Register Bit is Not Used

Loss of Lock Interrupt Enable

RO

0

R/W

"0" = Masks the LOL interrupt generation

"1" = Enables Interrupt generation

D0

LOSn_IE

Loss of Signal Interrupt Enable

"0" = Masks the LOS interrupt generation

"1" = Enables Interrupt generation

R/W

0

NOTE: n denotes channel number.

31

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

T

ABLE 17: MICROPROCESSOR

I

NTERFACE

R

EGISTER

0

X

0A, 0

X

12, 0

X

1A, 0

X

22 BIT

1A, C

D

ESCRIPTION

I

NTERRUPT

STATUS

C

ONTROL EGISTER (C

R

H

0 = 0 0A, C

X

H

1 = 0

X

12, C

H

2 = 0

X

H

3 = 0 22)

X

Register

Type

Default

Value

B

IT

N

AME

FUNCTION

(HW reset)

D7

D6

D5

Reserved This Register Bit is Not Used

RO

0

LOLn

Loss of Lock Detection

The Loss of Lock Detect is used to indicate whether the CDR PLL

is locked.

"0" = CDR Locked

"1" = CDR Out of Lock

D4

LOSn

Loss of Signal

RO

0

The LOS indicates the Loss of Signal activity.

"0" = No Alarm

"1" = A LOS condition is present

D3

D2

D1

Reserved This Register Bit is Not Used

LOLn_IS Loss of Lock Interrupt Status

RO

0

RUR

An external interrupt will not occur unless the LOLn_IE interrupt

enable bit is set in the appropriate registers 0x09, 0x11, 0x19, and

0x21 for channels 0, 1, 2, and 3 respectively.

"0" = No Change

"1" = Change in CDR Lock Status Occurred

D0

LOSn_IS Loss of Signal Interrupt Status

RUR

0

An external interrupt will not occur unless the LOSn_IE interrupt

enable bit is set in the appropriate registers 0x09, 0x11, 0x19, and

0x21 for channels 0, 1, 2, and 3 respectively.

"0" = No Change

"1" = Change in LOS Status Occurred

NOTE: n denotes channel number.

32

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

6.0 ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Operating Temperature Range.................-40°C t o 85°C

Case Temperature under bias..................-55°C to 125°C

Storage Temperature ...............................-65°C to 150°C

Air Thermal Resistance of LQFP Package.....Θ_jA

Case Thermal Resistance of LQFP Package.Θ_jC

=

25°C/W

°C/W

4

ESD Protection (HBM)..........................................>2000V

TABLE 18: ABSOLUTE

MAXIMUM

POWER AND INPUT/OUTPUT RATINGS

S

YMBOL

TYPE

P

ARAMETER

M

IN.

TYP

.

M

AX

.

U

NITS

VDD

1.8V Core Power Supplies

-0.5

3.6

5.5

V

1.8

VDD

3.3V Input/Output Power Supplies

DC logic signal input voltage

V

IO

LVDS

VDD +0.5

IO

LVPECL DC logic signal input voltage

VDD +0.5

IO

LVTTL/ DC logic signal input voltage

LVCMOS

VDD +0.5

IO

LVDS

DC logic signal output voltage

-0.5

VDD +0.5

V

IO

LVPECL DC logic signal output voltage

LVCMOS DC logic signal output voltage

VDD +0.5

IO

VDD +0.5

IO

LVDS

Input current

-200

200

mA

LVPECL Input current

LVTTL/ Input current

LVCMOS

N

OTE: Stresses listed under Absolute Maximum Power and I/O ratings may be applied to devices one at a time without

causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for

extended periods will severely affect device reliability.

TABLE 19: POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS

Test Conditions: VDD = 1.8V + 5%, VDD = 3.3V + 5% unless otherwise specified

1.8

IO

S

YMBOL

TYPE

P

ARAMETER

M

IN

.

TYP

.

M

AX

.

U

NITS

CONDITIONS

VDD

Core Power Supply Voltage

1.710

3.135

1.8

3.3

1.890

3.465

V

1.8

VDD

I/O Power Supply Voltage

V

IO

I

1.8V 51.84Mbps Total Power Supply Current

1.8V 155.52Mbps Total Power Supply Current

1.8V 622.08Mbps Total Power Supply Current

3.3V 51.84Mbps Total Power Supply Current

3.3V 155.52Mbps Total Power Supply Current

mA

LVDS Mode

DD1.8-OC1

DD1.8-OC3

I

117

DD1.8-OC12

I

DD3.3-OC1

DD3.3-OC3

I

33

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

TABLE 19: POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS

Test Conditions: VDD = 1.8V + 5%, VDD = 3.3V + 5% unless otherwise specified

1.8

IO

S

YMBOL

TYPE

P

ARAMETER

M

IN

.

TYP

.

M

AX

.

U

NITS

C

ONDITIONS

I

3.3V 622.08Mbps Total Power Supply Current

50

30

mA

LVDS Mode

DD3.3-OC12

LVDS Mode

RXCLKO dis-

abled

P

Total Power Consumption

mW

LVDS Mode

DD-OC1

DD-OC3

P

376

310

DD-OC12

RXCLKO dis-

abled

I

1.8V 51.84Mbps Total Power Supply Current

1.8V 155.52Mbps Total Power Supply Current

1.8V 622.08Mbps Total Power Supply Current

3.3V 51.84Mbps Total Power Supply Current

3.3V 155.52Mbps Total Power Supply Current

3.3V 622.08Mbps Total Power Supply Current

mA

LVPECL Mode

DD1.8-OC1

DD1.8-OC3

DD1.8-OC12

I

117

I

DD3.3-OC1

DD3.3-OC3

I

386

198

DD3.3-OC12

I

RXCLKO dis-

abled

P

Total Power Consumption

mW

LVPECL Mode

DD-OC1

DD-OC3

P

1485

865

DD-OC12

RXCLKO dis-

abled

TABLE 20: LVDS/DIFFERENTIAL LVPECL INPUT

L

OGIC

S

IGNAL DC ELECTRICAL

C

HARACTERISTICS

Test Condition: VDD = 1.8V + 5%, VDD = 3.3V + 5% unless otherwise specified

1.8

IO

S

YMBOL

TYPE

P

ARAMETER

M

IN

TYP

M

AX

U

NITS

CONDITIONS

V

LVDS/LVPECL Input High Voltage

LVDS/LVPECL Input Low Voltage

LVDS/LVPECL Input Differential Voltage

VDD + 100 mV

IH

IO

V

VDD - 100

mV

IL

IO

V

100

2400

mV

IDIFF

| V - V

|

IL

IH

V

LVDS/LVPECL Input Common Mode Voltage

0

1200

VDD

IO

mV

ICOMM

34

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

FIGURE 19. LVDS/DIFFERENTIAL LVPECL VOLTAGE

PARAMETER CONVENTION

"1"

"0"

"1"

VIN_P

V_IH

V_IDIFF

V_ICOMM

VIN_N

V_IL

V_ICOMM= ( V_IH+ V_IL) / 2

V_IDIFF

=

|

V_IH- V_IL

|

35

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

TABLE 21: LVDS OUTPUT LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS

Test Condition: VDD = 1.8V + 5%, VDD = 3.3V + 5% unless otherwise specified

1.8

IO

S

YMBOL

TYPE

P

ARAMETER

M

IN

TYP

M

AX

U

NITS

C

ONDITIONS

V

LVDS

Output High Voltage

Output Low Voltage

1100

700

250

1250

900

1500

1200

450

mV

100

Ω

line - line

OH

V

100

OL

V

Output Differential Voltage

ODIFF

| V - V

|

OL

OH

V

LVDS

Output Common Mode Voltage

850

1050

1350

mV

100

Ω

line - line

OCOMM

TABLE 22: DIFFERENTIAL LVPECL OUTPUT

LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS

Test Conditions: VDD = 1.8V + 5%, VDD = 3.3V + 5% unless otherwise specified

1.8

IO

ARAMETER

S

YMBOL

TYPE

P

M

IN

TYP

M

AX

U

NITS

CONDITIONS

V

LVPECL Output High Voltage

LVPECL Output Low Voltage

VDD - 900

mV

OH

IO

V

VDD - 1800

IO

OL

V

LVPECL Output Differential Voltage

| V - V

600

1100

Terminate with

50 to

VDD_IO-2.0

ODIFF

Ω

|

OL

OH

V

LVPECL Output Common Mode Voltage

VDD - 1350

V

OCOMM

IO

TABLE 23: LVTTL/LVCMOS SIGNAL DC ELECTRICAL

CHARACTERISTICS

Test Condition: VDD = 1.8V + 5%, VDD = 3.3V + 5% unless otherwise specified

1.8

IO

ARAMETER

S

YMBOL

TYPE

P

M

IN

TYP

M

AX

U

NITS

C

ONDITIONS

V

LVCMOS Output High Voltage

LVCMOS Output Low Voltage

2.4

0

VDD

V

I

= -8.0mA

= 8.0mA

OH

_IO

OH

V

0.4

VDD

V

I

OH

OL

V

LVTTL/ Input High Voltage

LVCMOS

2.0

IH

_IO

V

LVTTL/ Input Low Voltage

LVCMOS

0

0.8

10

V

IL

I

LVTTL/ Input Leakage Current

LVCMOS

-10

µ

A

V

= VDD

IN _IO

LEAK

or V = 0

IN

I

LVTTL/ Input Leakage Current with

-100

-10

10

µ

V

= 0

IN

LEAK_PU

LEAK_PD

Pull-Up Resistor

LVCMOS

I

LVTTL/ Input Leakage Current with

Pull-Down Resistor

100

V

= VDD

IN _IO

LVCMOS

NOTE: All input control pins are LVCMOS and LVTTL compatible. All output control pins are LVCMOS compatible only.

36

XRT91L34

REV. 1.0.1

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

TABLE 24: ORDERING INFORMATION

P

ART

N

UMBER

P

ACKAGE

O

PERATING TEMPERATURE RANGE

°

XRT91L34IV

128-pin Plastic Quad Flat Pack (14.0 x 14.0 x 1.4 mm, LQFP)

128-pin Pb-Free Quad Flat Pack (14.0 x 14.0 x 1.4 mm, LQFP)

-40 C to +85 C

°

XRT91L34IV-F

-40 C to +85 C

PACKAGE DIMENSIONS

128-PIN Low Profile QUAD FLAT PACK

(14 x 14 x 1.4 mm, LQFP)

Rev. 1.00

D

D₁

96

65

97

64

D₁

D

33

128

1

32

B

e

A₂

C

A

α

Seating

Plane

L

A₁

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

1.60

A

A1

A2

B

0.055

0.063

1.40

0.05

1.35

0.13

0.09

15.80

13.90

0.002

0.053

0.005

0.004

0.622

0.547

0.006

0.057

0.009

0.008

0.638

0.555

0.15

1.45

0.23

C

0.20

D

16.20

14.10

D1

e

0.0157BSC

0.40BSC

L

0.018

0^o

0.030

7^o

0.45

0^o

0.75

7^o

α

Note: The control dimension is in millimeter.

37

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

TABLE 25: REVISION

H

ISTORY

ESCRIPTION

R

EVISION

1.0.0

#

D

ATE

D

September 2007 New Release

October 2007

1.0.1

Fixed V , V and V specs in Figure 21 as per design input and prod-

OCOMM

OH

OL

uct engineering characterization.

38


型号：	XRT91L34
厂家：	EXAR CORPORATION
描述：	QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR 四通道多速率的STS -12 /3/1和STM-4 /1/0的SONET / SDH的CDR CD
文件：	总38页 (文件大小：404K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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