XRK69774CR [EXAR]
1:14 LVCMOS PLL CLOCK GENERATOR; 1:14 LVCMOS PLL时钟发生器
| 型号： | XRK69774CR |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 1:14 LVCMOS PLL CLOCK GENERATOR |
| 文件： | 总11页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
APRIL 2006
REV.P1.0.1
GENERAL DESCRIPTION
to125MHz and an input frequency range of 4.16MHz to
62.5MHz.
The XRK69774 is a PLL based LVCMOS Clock Generator
targeted for high performance and low skew clock distribu-
tion applications. The XRK69774 can select between one
of two reference inputs and provides 15 LVCMOS outputs -
14 outputs (2 banks of 5 and 1 bank of 4) for clock distribu-
tion and 1 for feedback.
FEATURES
• Fully Integrated PLL
• 15 LVCMOS outputs
■ 2 banks with 5 outputs and 1 with 4 outputs
each
The XRK69774 has two LVCMOS inputs to support clock
redundancy. Switching the internal reference clock is con-
trolled by the control input, CLK_SEL.
■ 1 dedicated feedback for frequency control
■ Output Frequency of each Bank can be
individually controlled
The XRK69774 uses PLL technology to frequency lock its
outputs to the input reference clock. The divider in the feed-
back path will determine the frequency of the VCO. Each of
the separate output banks can individually divide down the
VCO output frequency. This allows the XRK69774 to gen-
erate a multitude of different bank frequency ratios and out-
put-to-input frequency ratios.
• VCO Range 200MHz to 500MHz
• Output freq. range: 8.33MHz to 125MHz
• Max Output Skew of 175ps
• Max Cycle-to-cycle jitter: 90ps
• LVCMOS inputs for reference clock source
The outputs of the XRK69774 can be immobilized, in the
low state, by use of the stop clock feature. Global output
disabling and reset can be achieved with the control input
MR/OE.
APPLICATIONS
• System Clock generator
• Zero Delay Buffer
The XRK69774 has an output frequency range of 8.33MHz
FIGURE 1. BLOCK DIAGRAM OF THE XRK69774
VDD
QA0
QA1
Divider Select
÷2
0
0
1
CLK0
0
STOP
CLK
÷2, ÷4
÷2, ÷4
QA2
QA3
QA4
Ref
VCO
1
÷4
1
CLK1
CLK_SEL
PLL
÷4, ÷6
VDD
200-500MHz
÷4, ÷6, ÷8, ÷12
QB0
QB1
QB2
QB3
QB4
FB_IN
PLL_EN
FB
STOP
CLK
VCO_SEL
FSEL_A
FSEL_B
FSEL_C
2
FSEL_FB[1:0]
QC0
QC1
QC2
QC3
STOP
CLK
VDD
VDD
__________
STOP_CLK
POR
QFB
___
MR/OE
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRK69774
PRELIMINARY
1:14 LVCMOS PLL CLOCK GENERATOR
REV.P1.0.1
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER
XRK69774CR
XRK69774IR
PACKAGE TYPE
52-LEAD LQFP
52-LEAD LQFP
OPERATING TEMPERATURE RANGE
0°C to +70°C
-40°C to +85°C
FIGURE 2. PIN OUT OF THE XRK69774
52 51 50 49 48 47 46 45 44 43 42 41 40
39
GND
___
MR/OE
1
2
GND
QB1
VDD
QB2
GND
QB3
VDD
QB4
FB_IN
GND
QFB
VDD
NC
38
37
36
35
34
33
32
31
30
29
28
27
_________
STOP_CLK
FSEL_B
FSEL_C
PLL_EN
FSEL_A
CLK_SEL
CLK0
3
4
5
6
7
XRK69774
8
9
CLK1
10
11
12
13
NC
VDD
VDD_PLL
14 15 16 17 18 19 20 21 22 23 24 25 26
2
PRELIMINARY
XRK69774
REV. P1.0.1
1:14 LVCMOS PLL CLOCK GENERATOR
PIN DESCRIPTIONS
PIN #
NAME
TYPE
DESCRIPTION
1,15, 19, 24,
30, 35, 39,
43, 47, 51
GND
POWER
Power supply ground
2
MR/OE
INPUT
INPUT
Master reset and output enable.
High = output enabled, Low = device reset & outputs tri-stated
NOTE: 25kΩ Pull-Up resistor.
3
STOP_CLK
Clock input for serial control
NOTE: 25kΩ Pull-Up resistor.
7
4
5
FSEL_A,
FSEL_B,
FSEL_C
Select inputs for control of feedback divide value.
INPUT
INPUT
NOTE: Each input has a 25kΩ Pull-Down resistor.
6
PLL_EN
PLL bypass
High = PLL Enabled. Low = PLL bypass
NOTE: 25kΩ Pull-Up resistor.
8
CLK_SEL
INPUT
CLK0 or CLK1 Select.
High = CLK1 selected, Low = CLK0 selected
NOTE: 25kΩ Pull-Down resistor.
9
CLK0
CLK1
INPUT
INPUT
PLL Reference Clock Inputs
10
NOTE: CLK1 has 25kΩ Pull-Up resistor. CLK0 has 25kΩ Pull-Down
resistor.
11, 27, 42
NC
-
NO CONNECT
Power supply
12, 17, 22,
26, 28, 33,
37, 41, 45, 49
VDD
POWER
13
VDD_PLL
POWER
Analog supply for PLL
14
20
FSEL_FB0
FSEL_FB1
INPUT
INPUT
Frequency Divider Select for QFB output
NOTE: Each input has a 25kΩ Pull-Down resistor.
16, 18,21,
23, 25
QA[4:0]
OUTPUT Clock outputs (Bank A)
29
31
QFB
OUTPUT Feedback clock output
FB_IN
INPUT
Feedback input
NOTE: 25kΩ Pull-Up resistor.
32, 34, 36,
38, 40
QB[4:0]
OUTPUT Clock outputs (Bank B)
44, 46, 48, 50
52
QC[3:0]
OUTPUT Clock outputs (Bank C)
VCO_SEL
INPUT
VCO select. high = VCO/1, low = VCO/2.
NOTE: 25kΩ Pull-Down resistor.
3
XRK69774
PRELIMINARY
1:14 LVCMOS PLL CLOCK GENERATOR
1.0 ELECTRICAL SPECIFICATIONS
REV.P1.0.1
TABLE 1: GENERAL SPECIFICATIONS
SYMBOL
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
V
Output Termination Voltage
VDD÷2
V
TT
ESD
ESD Protection (Machine model)
200
V
V
MM
ESD
ESD Protection (Human body
model)
2000
HBM
LU
Latch-up Immunity
Input capacitance
200
mA
pf
C
Per input
4
IN
TABLE 2: ABSOLUTE MAXIMUM RATINGS
SYMBOL
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
V
Supply Voltage
-0.3
3.9
V
DD
V
DC Input Voltage
DC Output Voltage
DC Input Current
-0.3
-0.3
V
V
+ 0.3
V
V
IN
DD
DD
V
+ 0.3
OUT
I
+/-20
mA
mA
°C
IN
I
DC Output Current
Storage Temperature
+/-50
125
OUT
T
-65
S
TABLE 3: DC CHARACTERISTICS (V
= 3.3V +/- 5%)
DD
SYMBOL
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
V
PLL Supply Voltage
LVCMOS
3.0
V
V
DD_PLL
DD
V
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
LVCMOS
LVCMOS
2.0
V
+ 0.3
V
V
V
V
IH
DD
V
0.8
IL
V
IOH=-24mA
2.4
OH
V
IOL = 24mA
IOL = 12mA
0.55
0.30
OL
Z
Output Impedance
14 -17
5.0
Ω
OUT
I
Input Pull-Up/Down Current
V
= GND
IN
+200
μA
PU
or V
DD
I
PLL Supply Current
@ V
7.5
8
mA
mA
DD_PLL
DD_PLL
Pin
I
Quiescent Supply Current
All V pins
DDQ
DD
4
PRELIMINARY
XRK69774
REV. P1.0.1
1:14 LVCMOS PLL CLOCK GENERATOR
TABLE 4: AC CHARACTERISTICS (V
= 3.3V +/- 5%)
DD
SYMBOL
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
f
Input reference frequency
÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
25.0
16.6
12.5
8.33
6.25
4.16
62.5
41.6
MHz
MHz
MHz
MHz
MHz
MHz
REF
31.25
20.83
15.625
10.41
PLL bypass mode
250
500
MHz
MHz
f
f
VCO frequency range
Output frequency
200
VCO
÷4 output
÷8 output
÷12 output
÷16 output
÷24 output
50.0
25.0
16.6
12.5
8.33
125
62.5
MHz
MHz
MHz
MHz
MHz
MAX
41.6
31.25
20.83
t
CLKx pulse width
2.0
ns
ns
PW
It , It
Input CLKx Rise/Fall time
Propagation Delay (static
0.8V to 2.0V
1
R
F
t
CLK to FB_IN
(∅)
a
f
= 50MHz & FB = ÷8
-250
+100
ps
phase offset)
REF
t
Output to output skew
Bank A (QAx to QAy)
Bank B (QBx to QBy)
Bank C (QCx to QCy)
all outputs (QXy to QWz)
100
125
100
175
ps
ps
ps
ps
SK(O)
DC
Output duty cycle
47
50
53
%
Ot , Ot
Output Rise/Fall time
0.55 to 2.4V
0.1
1.0
ns
R
F
t
t
t
Output Disable Time
Output Enable Time
10
10
90
ns
ns
ps
PLZ, PHZ
t
PZL, PZH
t
Cycle-to-Cycle Jitter Time
All outputs @ same
frequency
JIT(CC)
t
Period Jitter
All outputs @ same
frequency
90
ps
JIT(PER)
t
I/O Phase Jitter (rms)
VCO= 400MHz
÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
15
49
18
22
26
34
ps
ps
ps
ps
ps
ps
JIT(∅)
NOTE:
a. t = +50ps ± ± (÷ (120 x f
)) for any reference frequency.
(∅)
REF
5
XRK69774
PRELIMINARY
1:14 LVCMOS PLL CLOCK GENERATOR
REV.P1.0.1
TABLE 5: AC CHARACTERISTICS (V
DD
= 3.3V +/- 5%)
SYMBOL
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
BW
PLL closed loop bandwidth
÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
0.50-1.80
0.30-1.00
0.25-0.70
0.17-0.40
0.12-0.30
0.07-0.20
MHz
MHz
MHz
MHz
MHz
MHz
t
Maximum PLL Lock Time
10
ms
LOCK
FIGURE 3. TEST LOAD
Transmission Line
Z = 50Ω
50Ω
VTT
6
PRELIMINARY
XRK69774
REV. P1.0.1
1:14 LVCMOS PLL CLOCK GENERATOR
2.0 CONFIGURATION TABLES
TABLE 6: FUNCTION CONTROLS
CONTROL PIN
DEFAULT
LOGIC 0
LOGIC 1
MR/OE
1
Resets the output divide circuitry and serial
interface, tri-states all outputs
Enables all outputs - normal operation
PLL_EN
1
PLL bypass mode enabled. This is a test
mode in which the reference clock is provided
to the output dividers in place of the VCO
output.
PLL enabled - normal operation
STOP_CLK
1
QA[4:0], QB[4:0] and QC[3:0] outputs disabled Outputs enabled, normal operation
in Low state.
CLK_SEL
VCO_SEL
0
0
CLK0 selected as PLL reference
VCO ÷ 2
CLK1 selected
VCO ÷ 4
TABLE 7: BANK OUTPUT DIVIDER CONTROLS
INPUT
OUTPUT
QA[4:0]
÷4
INPUT
OUTPUT
INPUT
OUTPUT
QC[3:0]
÷8
VC0_SEL
FSEL_A
VCO_SEL
FSEL_B
QB[4:0]
÷4
VC0_SEL
FSEL_C
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
÷8
÷8
÷12
÷8
÷8
÷16
÷16
÷16
÷24
TABLE 8: FEEDBACK DIVIDER CONTROL
VCO_SEL
FSEL_FB1
FSEL_FB0
QFB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷8
÷16
÷12
÷24
÷16
÷32
÷24
÷48
7
XRK69774
PRELIMINARY
1:14 LVCMOS PLL CLOCK GENERATOR
REV.P1.0.1
FIGURE 4. OUTPUT-TO-OUTPUT SKEW t
SK(O)
VCC
VCC÷2
GND
VCC
VCC÷2
GND
tSK(O)
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device.
FIGURE 5. PROPOGATION DELAY (t , STATIC PHASE OFFSET) TEST REFERENCE
(Ø)
VCC
CCLKx
VCC÷2
GND
VCC
VCC÷2
GND
FB_IN
t(Ø)
FIGURE 6. OUTPUT DUTY CYCLE (DC)
VCC
VCC÷2
GND
tp
T0
DC=tP/T0 x 100%
The time from the PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
FIGURE 7. I/O JITTER
CCLKx
FB_IN
TJIT(I/O) = |T0-T1mean |
The deviation in t0 for a controlled edge with respect to a t0 mean in a random
sample of cycles
8
PRELIMINARY
XRK69774
REV. P1.0.1
1:14 LVCMOS PLL CLOCK GENERATOR
FIGURE 8. CYCLE-TO-CYCLE JITTER
TJIT(CC)= |TN-TN+1
|
TN+1
TN
The variation in cycle time of a signal between adjacent cycles, over a random
sample of adjacent cycle pairs
FIGURE 9. PERIOD JITTER
T0
TJIT(Per)= |TN-1/f0 |
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
FIGURE 10. OUTPUT TRANSITION TIME TEST REFERENCE
VCC=3.3V
2.4
0.55
OtF
OtR
9
XRK69774
PRELIMINARY
1:14 LVCMOS PLL CLOCK GENERATOR
REV.P1.0.1
PACKAGE DIMENSIONS
52 LEAD LOW-PROFILE QUAD FLAT PACK
(10 mm x 10 mm X 1.4 mm LQFP, 1.0 mm Form)
Rev. 1.00
Note: The control dimension is in millimeters.
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.063
0.006
0.057
0.014
0.009
0.480
0.398
MIN
1.40
0.05
1.35
0.25
0.11
11.80
9.90
MAX
1.60
0.15
1.45
0.35
0.23
12.20
10.10
A
A1
A2
B
C
D
0.055
0.002
0.053
0.010
0.004
0.465
0.390
D1
e
0.0256 BSC
0.65 BSC
L
α
0.029
0°
0.041
7°
0.73
0°
1.03
7°
α
10
PRELIMINARY
XRK69774
REV. P1.0.1
1:14 LVCMOS PLL CLOCK GENERATOR
REVISION HISTORY
REVISION #
DATE
DESCRIPTION
P1.0.0
P1.0.1
April 7, 2006 Initial release
April 10, 2006 General Description edit last line to: ...input frequency range of 4.16MHz to 62.5MHz.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2006 EXAR Corporation
Datasheet April 2006.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
11
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EXAR
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