XRK39351 [EXAR]
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER; 3.3V或2.5V ， 9路输出PLL时钟驱动器
| 型号： | XRK39351 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER |
| 文件： | 总10页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PRELIMINARY
XRK39351
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
FEBRUARY 2006
REV. P1.0.0
input is pulled low. This is a test mode intended for
system debug purposes.
GENERAL DESCRIPTION
The XRK39351 is a low voltage PLL based clock
driver designed for high speed clock distribution
applications.
The XRK39351 has an output/input frequency range
of 25MHz to 200MHz with the PLL enabled and an
input frequency range of 2MHz to 300MHz when the
PLL is disabled (test mode).
The XRK39351 has two reference clock inputs, one
LVPECL and the other LVCMOS. The REF_SEL
input selects clock input to be used as the PLL’s
reference source.
FEATURES
• 9 LVCMOS Outputs (4 banks)
• 25 - 200 MHz output frequency range
• Fully Integrated PLL
The XRK39351 uses PLL technology to frequency
lock its outputs to the clock reference input. The
divider in the feedback path will determine the
frequency of the VCO. The XRK39351 provides 9
LVCMOS outputs that are separated into 4 banks.
Each of the separate output banks can individually
divide down the VCO output frequency. This allows
the XRK39351 to generate a variety of output-to-input
frequency ratios (1:1, 1:2, 1:4, 2:1 and 4:1). All
outputs provide LVCMOS compatible levels while
driving 50Ω terminated transmission lines.
• 2.5V or 3.3V Operation
• Selectable reference clock input, LVCMOS or
LVPECL
• 150ps max output to output skew
• Pin compatible with MPC9351
• Industrial temp range: -40°C to +85°C
• 32-Lead TQFP Packaging
The input reference clock can be directly applied to
the output dividers bypassing the PLL when PLL_EN
FIGURE 1. BLOCK DIAGRAM OF THE XRK39351
REF_SEL
÷ 2
0
1
QA
QB
TCLK
1
0
0
1
Ref
FB
4
8
÷
÷
PECL
PECL
PLL
FB_IN
0
1
VDD
PLL_EN
SELA
SELB
SELC
SELD
0
1
QC0
QC1
QD0
QD1
QD2
QD3
QD4
0
1
OE
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRK39351
PRELIMINARY
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
REV. P1.0.0
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
XRK39351IQ
32-Lead TQFP
-40°C to +85°C
FIGURE 2. PIN OUT OF THE XRK39351
32 31 30 29 28 27 26 25
AVCC
FB_IN
SELA
SELB
SELC
SELD
AGND
PECL
1
2
3
4
5
6
7
8
24
QC0
23
22
21
20
19
18
17
VCCQC
QC1
GND
XRK39351
QD0
VCCQD
QD1
GND
9
10 11 12 13 14 15 16
2
PRELIMINARY
XRK39351
REV. P1.0.0
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
PIN DESCRIPTIONS
NUMBER
NAME
AVCC
FB_IN
SELA
SELB
SELC
SELD
AGND
PECL
PECL
OE
TYPE
DESCRIPTION
1
2
Power
Input
Input
Input
Input
Input
Power
Input
Input
Input
Power
Output
Power supply for PLL
pull-down External PLL feedback clock input
pull-down Selects divider value for Bank A output
pull-down Selects divider value for Bank B output
pull-down Selects divider value for Bank C outputs
pull-down Selects divider value for Bank D outputs
PLL ground
3
4
5
6
7
8
LVPECL - pos differential reference clock
LVPECL - neg differential reference clock
pull-down Output enable/disable and device reset
Power supply for core, inputs and bank A output clock
Bank D clock outputs
9
10
11
VCC
12, 14, 16,
18, 20
QD[4:0]
13, 17, 21,
25, 29
GND
Power
Ground
15, 19
20, 22
23
VCCQD
QC[1:0]
VCCQC
QB
Power
Output
Power
Output
Power
Output
Input
Power supply for bank D output clocks
Bank C clock outputs
Power supply for bank C output clocks
Bank B clock output
26
27
VCCQB
QA
Power supply for bank B output clock
Bank A clock output
28
30
TCLK
pull-down LVCMOS reference clock input
31
PLL_EN
REF_SEL
Input
pull-up
Selects PLL or PLL-bypass (test mode) operation
32
Input
pull-down Selects primary reference clock source
3
XRK39351
PRELIMINARY
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
REV. P1.0.0
TABLE 1: CONTROL INPUT FUNCTION TABLE
PIN NAME
REF_SEL
PLL_EN
0
1
DEFAULT
PECL clock inputs selected as reference
TCLK input selected as reference
0
1
PLL is bypassed. Test Mode. TCLK refer-
ence source drives the divider select blocks
PLL enabled. Normal operation. VCO out-
put drives the divider select blocks
SELA
SELB
SELC
SELD
OE
Bank A divider = 2
Bank B divider = 4
Bank C divider = 4
Bank D divider = 4
Outputs enabled
Bank A divider = 4
Bank B divider = 8
Bank C divider = 8
Bank D divider = 8
0
0
0
0
0
Outputs tri-stated, VCO running at minimum
frequency
DC CHARACTERISTICS (V = 3.3 + 5%, T = -40°C TO +85°C)
CC
A
SYMBOL
CHARACTERISTICS
MIN
TYP
MAX
UNIT
CONDITION
a
PECL Clock inputs common mode range
1.2
V
-0.9
V
CC
V
CMR
V
PECL Clock peak-to-peak input voltage
Input voltage high
500
2.0
1000
mV
V
PP
V
VCC+0.3
0.8
IH
V
Input voltage low
V
IL
a
V
2.4
V
I
=-24mA
OH
Output High Voltage
OH
a
V
0.55
0.30
V
V
I
I
=24mA
=12mA
OL
Output Low Voltage
OL
OL
Z
Output Impedance
14-17
3.0
Ω
OUT
I
Input leakage current
+150
5.0
4
μΑ
V
=V or V =GND
IN CC IN
IN
I
Maximum PLL supply current
Maximum Quiescent supply current
Output Termination Voltage
mA AV pin
CC
CC_PLL
I
mA All V
pins
CCQX
CC
V
V
÷2
CC
V
TT
a. VCMR is the cross point of the differential input signal.
4
PRELIMINARY
XRK39351
REV. P1.0.0
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
.
AC CHARACTERISTICS (V = 3.3 + 5%, T = -40°C TO +85°C) a
CC
A
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
CONDITION
f
VCO Frequency
200
400
MHz
VCO
f
Input Reference Frequency
÷2 feedback
÷4 feedback
÷8 feedback
PLL Bypass
100
50
25
2
200
100
50
MHz
PLL_EN = 1
PLL_EN = 1
PLL_EN = 1
PLL_EN = 0
ref
300
f
Max Output Frequency
÷2 feedback
÷4 feedback
÷8 feedback
100
50
200
100
50
MHz
MAX
25
t /t
Input Rise/Fall time
1.0
75
ns
%
0.8 to 2.0V
ir if
f
Input Clock duty cycle
25
refDC
t
Propagation Delay - (SPO, Input clock to FB)
TCLK to FB_IN
pd
-50
-25
150
325
ps
ps
PLL Locked
PLL Locked
PECL to FB_IN
t
Output-to-Output Skew
150
22
ps
ps
skew
t
Cycle-to-Cycle Jitter (RMS)
Period Jitter (RMS)
÷4 feedback
÷4 feedback
10
8
All outputs set
to ÷4
JIT(CC)
t
15
ps
ps
All outputs set
to ÷4
JIT(PER)
t
I/O Phase Jitter (RMS)
PLL bandwidth
4 - 17
JIT(I/O)
BW
÷2 feedback
÷4 feedback
÷8 feedback
9.0-20.0
3.0-9.5
1.2-2.1
MHz
MHz
MHz
DC
Output duty cycle
÷2 feedback
÷4 feedback
÷8 feedback
45
50
50
50
55
%
%
%
100 - 200MHz
50 - 100MHz
25 - 50MHz
47.5
48.75
52.5
51.75
t
Maximum PLL Lock Time
Output Rise/Fall time
Output Disable Time
Output Enable Time
1.0
1000
10
ms
ps
ns
ns
LOCK
t /t
100
0.55 to 2.4V
or of
t
t
PLZ,HZ
PHZ,LZ
10
a. AC characteristics apply for parallel output termination of 50Ω to V
.
TT
5
XRK39351
PRELIMINARY
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
REV. P1.0.0
DC CHARACTERISTICS (V = 2.5 + 5%, T = -40°C TO +85°C)
CC
A
SYMBOL
CHARACTERISTICS
MIN
TYP
MAX
UNIT
CONDITION
a
PECL Clock inputs common mode range
1.2
V
-0.6
V
CC
V
CMR
V
PECL Clock peak-to-peak input voltage
Input voltage high
500
1.7
1000
mV
V
PP
V
VCC+0.3
0.7
IH
V
Input voltage low
V
IL
V
1.8
V
I =-15mA
OH
OH
Output High Voltage
V
0.6
V
I
=15mA
OL
OL
Output Low Voltage
Output Impedance
Z
17-20
3.0
Ω
OUT
I
Input leakage current
+150
5.0
1
μΑ
V
=V or V =GND
IN CC IN
IN
I
Maximum PLL supply current
Maximum Quiescent supply current
Output Termination Voltage
mA AV pin
CC
CC_PLL
I
mA
V
All V
pins
CCQX
CC
V
V
÷2
CC
TT
a. VCMR is the cross point of the differential input signal.
6
PRELIMINARY
XRK39351
REV. P1.0.0
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
.
AC CHARACTERISTICS (V = 2.5 + 5%, T = -40°C TO +85°C) a
CC
A
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
CONDITION
f
VCO Frequency
200
400
MHz
VCO
f
Input Reference Frequency
÷2 feedback
÷4 feedback
÷8 feedback
PLL Bypass
100
50
200
100
50
MHz
PLL_EN = 1
PLL_EN = 1
PLL_EN = 1
PLL_EN = 0
ref
25
f
Max Output Frequency
÷2 feedback
÷4 feedback
÷8 feedback
100
50
200
100
50
MHz
MAX
25
t /t
Input Rise/Fall time
1.0
75
ns
%
0.7 to 1.7V
ir if
f
Input Clock duty cycle
25
refDC
t
Propagation Delay - (SPO, Input clock to FB)
TCLK to FB_IN
pd
-100
0
100
300
ps
ps
PLL Locked
PLL Locked
PECL to FB_IN
t
Output-to-Output Skew
150
22
ps
ps
skew
t
Cycle-to-Cycle Jitter (RMS)
Period Jitter (RMS)
÷4 feedback
÷4 feedback
10
8
All outputs set
to ÷4
JIT(CC)
t
15
ps
ps
All outputs set
to ÷4
JIT(PER)
t
I/O Phase Jitter (RMS)
PLL bandwidth
6 - 25
JIT(I/O)
BW
÷2 feedback
÷4 feedback
÷8 feedback
4.0-15.0
2.0-7.0
0.7-2.0
MHz
MHz
MHz
DC
Output duty cycle
÷2 feedback
÷4 feedback
÷8 feedback
45
50
50
50
55
%
%
%
100 - 200MHz
50 - 100MHz
25 - 50MHz
47.5
48.75
52.5
51.75
t
Maximum PLL Lock Time
Output Rise/Fall time
Output Disable Time
Output Enable Time
1.0
1000
12
ms
ps
ns
ns
LOCK
t /t
100
0.55 to 2.4V
or of
t
t
PLZ,HZ
PHZ,LZ
12
a. AC characteristics apply for parallel output termination of 50Ω to V
.
TT
7
XRK39351
PRELIMINARY
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
REV. P1.0.0
a
ABSOLUTE MAXIMUM RATINGS
SYMBOL
CHARACTERISTICS
MIN
MAX
UNIT
CONDITION
V
Supply Voltage
-0.3
4.6
V
CC
V
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
-0.3
-0.3
V
V
+0.3
V
V
IN
CC
CC
V
+0.3
OUT
I
+20
mA
mA
°C
IN
I
+50
150
OUT
T
Storage Temperature
-55
S
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
GENERAL SPECIFICATIONS
SYMBOL
CHARACTERISTICS
MIN
TYP
MAX
UNIT
CONDITION
V
Output termination voltage
V
÷2
V
TT
CC
MM
HBM
LU
ESD Protection (Machine model)
ESD Protection (Human body model)
Latch-up immunity
200
2000
200
V
V
mA
pF
C
Input Capacitance
4.0
Inputs
IN
θ
Thermal resistance junction to ambient
JESD 51-3, single layer test board
Natural convection
JA
62.0
°C/W
JESD 51-6, multi layer test board
Thermal resistance junction to case
47
14
°C/W
°C/W
θ
JC
Operating junction temperature
115
°C
8
PRELIMINARY
XRK39351
REV. P1.0.0
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
PACKAGE DIMENSIONS
32 LEAD THIN QUAD FLAT PACK
(7 x 7 x 1.4 mm TQFP)
rev. 2.00
D
D1
24
17
16
25
32
D
D1
9
1
8
B
e
A
2
C
A
α
Seating Plane
A
1
L
[
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
MAX
SYMBOL
MIN
MIN
MAX
1.60
0.15
A
0.055
0.002
0.063
0.006
1.40
0.05
A
1
A
0.053
0.012
0.004
0.346
0.272
0.057
0.018
0.008
0.362
0.280
1.35
0.30
0.09
8.80
6.90
1.45
0.45
0.20
9.20
7.10
2
B
C
D
D
1
e
L
α
0.0315 BSC
0.80 BSC
0.018
0.030
0.45
0.75
0°
7°
0°
7°
9
XRK39351
PRELIMINARY
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
REV. P1.0.0
REVISION HISTORY
REVISION #
DATE
DESCRIPTION
P1.0.0
February 2006 Initial release.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2006 EXAR Corporation
Datasheet February 2006.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
10
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