XRK39653 [EXAR]
3.3V, 8-OUTPUT ZERO DELAY BUFFER; 3.3V ， 8输出的零延迟缓冲器
| 型号： | XRK39653 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 3.3V, 8-OUTPUT ZERO DELAY BUFFER |
| 文件： | 总7页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PRELIMINARY
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
FEBRUARY 2006
REV. P1.0.0
XRK39653 GENERAL DESCRIPTION
use. The second is a full bypass mode that has the PLL
and divider operation removed (BYPASS=0). In this mode
the reference clock directly sources the outputs drivers.
The XRK39653 is a low voltage high performance PLL
based zero delay buffer/clock generator designed for high
speed clock distribution applications. It provides 9 low
skew, low jitter outputs ideal for networking, computing and
telecom applications.
FEATURES
• 8 LVCMOS Clock Outputs
The PLL based design allows the 9 outputs (8 clock outputs
and 1 feedback output) to be phase aligned to the input ref-
erence clock. The outputs source LVCMOS compatible lev-
els and can drive 50Ω transmission lines. If series
termination is used, each output can drive up to 2 lines pro-
viding effectively a fanout of 1:16. The XRK39653’s refer-
ence input accepts a LVPECL clock source.
• 1 Feedback Output
• LVPECL reference clock input
• 25-200 MHz input/output frequency range
■ Input/Output range (÷4): 50-125MHz
■ Input/Output range (÷8): 25-62.5MHz
• 150ps max output to output skew
• Two bypass test mode options
• Fully Integrated PLL
• 3.3V Operation
• Pin compatible with MPC9353
For normal operation (PLL used to source the outputs), the
feedback output (QFB) is connected to the feedback input
(FB_IN). The VCO range of operation is 200 to 500MHz.
This means that the input/output ranges are determined by
the divider setting. If ÷4 is used, the input/output range is 50
to 125MHz (high range), if ÷8 is used the input/output range
is 25 to 62.5MHz (low range).
• Industrial temp range: -40°C to +85°C
For testing purposes two PLL bypass modes are provided.
The first simply replaces the PLL output with the reference
clock (PLL_EN=0, BYPASS=1). The dividers are still in
• 32-Lead TQFP Packaging
FIGURE 1. BLOCK DIAGRAM OF THE XRK39653
VDD
QFB
Q0
PECL
PECL
0
1
0
1
Ref
0
1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
÷ 4
PLL
FB
÷ 2
FB_IN
VDD
PLL_EN
VCO_SEL
BYPASS
OE
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
PRELIMINARY
REV. P1.0.0
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER
XRK39653IQ
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
32-Lead TQFP
32-Lead TQFP "Lead Free"
-40°C to +85°C
-40°C to +85°C
XRK39653IQ-F
FIGURE 2. PIN OUT OF THE XRK39653
32 31 30 29 28 27 26 25
AVDD
FB_IN
NC
1
2
3
4
5
6
7
8
24
Q1
23
22
21
20
19
18
17
VDD
Q2
NC
GND
Q3
XRK39653
NC
NC
VDD
Q4
AGND
PECL
GND
9
10 11 12 13 14 15 16
2
PRELIMINARY
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
REV. P1.0.0
PIN DESCRIPTIONS
NUMBER
NAME
AVDD
FB_IN
NC
TYPE
DESCRIPTION
1
Power
Input
Power supply for PLL
2
pull-up
External PLL feedback clock input
3, 4, 5, 6
7
8
AGND
PECL
PECL
OE
Power
Input
PLL ground
LVPECL - pos differential reference clock
LVPECL - neg differential reference clock
9
Input
10
Input
pull-down Output enable/disable and device reset
Power supply
11,15, 19,
23, 27,
VDD
Power
12, 14, 16,
18, 20, 22,
24, 26
Q[7:0]
GND
Output
Power
Clock outputs
13, 17, 21,
25, 29
Ground
28
30
31
32
QFB
Output
Input
Input
Input
Feedback output for PLL
PLL_EN
BYPASS
VCO_SEL
pull-up
pull-up
pull-up
PLL enable/disable select
PLL and output divider bypass select
VCO divider select
TABLE 1: CONTROL INPUT FUNCTION TABLE
Pin Name
VCO_SEL
PLL_EN
0
1
Default
System Divide = 4 of VCO output
System Divide = 8 of VCO output
1
1
PLL is bypassed and disabled. The PECL
clock reference source drives the outputs
through the divider blocks
PLL enabled. Normal operation. VCO out-
put drives the outputs through the divider
blocks
BYPASS
OE
Complete bypass of the PLL and divider
blocks. PECL reference clocks the outputs.
Normal operation. Dividers selected.
1
0
Outputs enabled
Outputs tri-stated and device reset. VCO
running at minimum frequency
3
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
PRELIMINARY
REV. P1.0.0
DC CHARACTERISTICS (V = 3.3 + 5%, T = -40°C TO +85°C)
CC
A
SYMBOL
CHARACTERISTICS
MIN
TYP
MAX
UNIT
CONDITION
a
PECL Clock inputs common mode range
1.0
V
-0.6
V
LVPECL
V
DD
CMR
V
PECL Clock peak-to-peak input voltage
Input voltage high
300
2.0
1000
mV LVPECL
PP
V
V
+0.3
DD
V
V
V
LVCMOS
LVCMOS
IH
V
Input voltage low
0.8
IL
a
V
2.4
I
=-24mA
OH
Output High Voltage
OH
a
V
0.55
0.30
V
V
I
I
=24mA
=12mA
OL
OL
Output Low Voltage
OL
Z
Output Impedance
14-17
5.0
Ω
OUT
I
Input leakage current
+200
10.0
10.0
μΑ
V
=V or V =GND
IN DD IN
IN
I
Maximum PLL supply current
Maximum Quiescent supply current
Output Termination Voltage
mA AV pin
DD
CC_PLL
I
mA All V pins, OE=1
CCQ
DD
V
V
÷2
CC
V
TT
a. VCMR is the cross point of the differential input signal.
AC CHARACTERISTICS (V = 3.3 + 5%, T = -40°C TO +85°C) a
.
CC
PARAMETER
A
SYMBOL
MIN
TYP
MAX
UNIT
CONDITION
f
VCO Frequency
200
500
MHz
VCO
f
Input Reference Frequency
Max Output Frequency
÷4 feedback
÷8 feedback
PLL Bypass
50
25
0
125
62.5
200
MHz
MHz
PLL locked
PLL locked
ref
bypass mode
f
÷4 feedback
÷8 feedback
50
25
125
PLL locked
PLL locked
MAX
62.5
V
PECL Clock peak-to-peak input voltage
PECL input Common Mode range
450
1.2
2
1000
mV
V
LVPECL
LVPECL
PP
V
V
-0.75
DD
CMR
t
Input Reference Clock Minimum Pulse Width
ns
ps
PW Min
t
Propagation Delay - Static Phase Offset (PECL
to FB_IN)
-75
125
PLL locked
SPO
t
Propagation Delay - PLL Bypassed
Bypass mode 1 (BYPASS = 0)
PD
1.2
3.0
3.3
7.0
ns
ns
Bypass mode 2, (BYPASS = 1, PLL_EN = 0)
t
Output-to-Output Skew
150
1.5
ps
ns
ps
skew(O)
t
Part to Part Skew (bypass PLL & divider)
Cycle-to-Cycle Jitter
BYPASS=0
skew(PP)
t
100
JIT(CC)
4
PRELIMINARY
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
REV. P1.0.0
AC CHARACTERISTICS (V = 3.3 + 5%, T = -40°C TO +85°C) a
CC
PARAMETER
A
SYMBOL
MIN
TYP
MAX
UNIT
CONDITION
t
Period Jitter
100
ps
JIT(PER)
t
I/O Phase Jitter (RMS)
PLL bandwidth
25
ps
JIT(I/O)
BW
÷4 feedback
÷8 feedback
0.8 - 4
MHz
MHz
0.5 - 1.3
DC
Output duty cycle
45
50
55
%
PLL locked
0.55 to 2.4V
t
Maximum PLL Lock Time
10.0
ms
LOCK
t /t
Output Rise/Fall time
Output Disable Time
Output Enable Time
100
1000
ps
ns
ns
or of
t
t
7
6
PLZ,HZ
PHZ,LZ
a. AC characteristics apply for parallel output termination of 50Ω to V
.
TT
a
MAXIMUM RATINGS
SYMBOL
CHARACTERISTICS
MIN
MAX
UNIT
CONDITION
V
Supply Voltage
-0.3
3.9
V
V
DD
V
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
-0.3
-0.3
V
V
+0.3
IN
DD
DD
V
+0.3
V
OUT
I
+20
mA
mA
°C
IN
I
+50
125
OUT
T
Storage Temperature
-65
S
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
GENERAL SPECIFICATIONS
SYMBOL
CHARACTERISTICS
MIN
TYP
MAX
UNIT
CONDITION
V
Output termination voltage
V
÷2
V
TT
CC
MM
HBM
LU
ESD Protection (Machine model)
ESD Protection (Human body model)
Latch-up immunity
200
2000
200
V
V
mA
pF
C
Input Capacitance
4.0
Inputs
IN
5
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
PRELIMINARY
REV. P1.0.0
PACKAGE DIMENSIONS
32 LEAD THIN QUAD FLAT PACK
(7 x 7 x 1.4 mm TQFP)
rev. 2.00
D
D1
24
17
16
25
32
D
D1
9
1
8
B
e
A2
C
A
α
Seating Plane
A1
L
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
MAX
SYMBOL
MIN
MIN
MAX
1.60
0.15
A
0.055
0.002
0.063
0.006
1.40
0.05
A
1
A
0.053
0.012
0.004
0.346
0.272
0.057
0.018
0.008
0.362
0.280
1.35
0.30
0.09
8.80
6.90
1.45
0.45
0.20
9.20
7.10
2
B
C
D
D
1
e
L
α
0.0315 BSC
0.80 BSC
0.018
0.030
0.45
0.75
0°
7°
0°
7°
6
PRELIMINARY
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
REV. P1.0.0
REVISION HISTORY
REVISION #
DATE
DESCRIPTION
P1.0.0
February 2006 Initial release.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2006 EXAR Corporation
Datasheet February 2006.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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