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VT8601 Apollo ProMedia

REVISION HISTORY

Document Release

Date

Revision

Initials

0.92

12/9/98 Initial internal release based on Apollo MVP4 data sheet revision 0.92

Added preliminary pin diagram based on engineering ballout rev 0.3 11/10/98

Added Slot-1 pinouts from Apollo Pro Plus Data Sheet

DH

Replaced feature list, overview, and vblock diagram from product brief

0.93

0.94

1.0

12/16/98 Updated pinouts to match engineering rev 0.5 document dated 12/1/98

1/20/99 Updated pinouts to match engineering rev 0.8 document dated 12/22/98

DH

6/4/99

Added 133 MHz Support to Feature Bullets

Updated / Fixed Pin Descriptions:

Fixed description of strap options on MA2, MA8, and MA11-14

Removed Auxiliary Memory Port

Added REQ/GNT[4-7]#

Added GND & VCC3 pins to increase pin count to 510 (updated mech spec)

Fixed definitions of RESET# & CRSTI# and changed CRSTI# to CPURSTD#

Removed PWRGD function from SERR#

Fixed definitions of SRAS#, SCAS#, and SWE#

Added note to PLLTST description

Updated Device 0 Registers Rx50-53, 68[4], 69, 6B[5-1], 6C[7-4], 70[3,0,

72[0], 76[7], 79[1-0], 7A (added)

Updated Device 1 Registers Rx41[0], 42[0]

1.1

6/23/99 Updated feature bullets & overview and fixed misc formatting problems

Fixed REQ/GNT4# pinouts and CKE & DQM naming polarity

Device 0 Bus 0 updated Rx2-3 Device ID, 69[7-6], 6D[6-5], 76[6]

Device 0 Bus 0 added Rx2C-D, 2E-F, 50[1], 51[5], 53[2], removed 6E-6F

Device 0 Bus 1 updated Rx0-3 Vendor & Device ID, Rx7-6[7]

Removed AC timing specs

DH

1.11

1.2

7/8/99

Fixed pin descriptions of CPURSTD# and SUSP

DH

8/23/99 Fixed typo in device 0 Rx50[7] description; added comment about default state

Fixed system frequency divider settings (MA pin descriptions, Dev 0 Rx68[1-0])

1.3

9/8/99

Fixed strap options on MA2-6 and MA13 pin descriptions

Fixed Device 0 Rx52[7] strap option and removed (reserved) Device 0 Rx52[5]

Removed “VIA Confidential” watermark

DH

Revision 1.3 September 8, 1999

-i-

Revision History

VT8601 Apollo ProMedia

TABLE OF CONTENTS

REVISION HISTORY........................................................................................................................................................................I

TABLE OF CONTENTS..................................................................................................................................................................II

LIST OF FIGURES..........................................................................................................................................................................IV

LIST OF TABLES ...........................................................................................................................................................................IV

APOLLO PROMEDIA...................................................................................................................................................................... 1

SYSTEM OVERVIEW...................................................................................................................................................................... 6

APOLLO PROMEDIA CORE LOGIC OVERVIEW ............................................................................................................................ 7

APOLLO PROMEDIA GRAPHICS CONTROLLER OVERVIEW ........................................................................................................ 8

Capability Overview............................................................................................................................................................... 8

System Capabilities................................................................................................................................................................. 9

High Performance 64-bit 2D GUI.......................................................................................................................................... 9

Highly Integrated RAMDAC^TM& Clock Synthesizer......................................................................................................... 9

Full Feature High Performance 3D Engine.......................................................................................................................... 9

Video Processor..................................................................................................................................................................... 10

Video Capture and DVD ...................................................................................................................................................... 10

Versatile Frame Buffer Interface ........................................................................................................................................ 10

Hi-Res and Hi-Ref Display Support.................................................................................................................................... 10

CRT Power Management (VESA DPMS) .......................................................................................................................... 11

Flat Panel Interface .............................................................................................................................................................. 11

Video Capture Interface....................................................................................................................................................... 11

Complete Hardware Compatibility..................................................................................................................................... 11

PINOUTS.......................................................................................................................................................................................... 12

PIN DESCRIPTIONS...................................................................................................................................................................... 15

REGISTERS..................................................................................................................................................................................... 23

REGISTER OVERVIEW ................................................................................................................................................................. 23

REGISTER SUMMARY TABLES..................................................................................................................................................... 23

MISCELLANEOUS I/O................................................................................................................................................................... 33

CONFIGURATION SPACE I/O ....................................................................................................................................................... 33

REGISTER DESCRIPTIONS............................................................................................................................................................ 34

Device 0 Bus 0 Header Registers - Host Bridge.................................................................................................................. 34

Device 0 Bus 0 Host Bridge Registers ................................................................................................................................. 36

CPU Interface Control .......................................................................................................................................................................... 36

DRAM Control ..................................................................................................................................................................................... 38

PCI Bus Control.................................................................................................................................................................................... 44

GART / Graphics Aperture Control ...................................................................................................................................................... 48

AGP Control ......................................................................................................................................................................................... 50

Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge .................................................................................................... 52

Device 1 Bus 0 PCI-to-AGP Bridge Registers .................................................................................................................... 54

AGP Bus Control .................................................................................................................................................................................. 54

Device 0 Bus 1 Header Registers - Graphics Accelerator.................................................................................................. 55

Device 0 Bus 1 Graphics Accelerator Registers ................................................................................................................. 58

Graphics Accelerator PCI Bus Master Registers................................................................................................................................... 59

VGA Standard Registers - Introduction ................................................................................................................................................ 65

Capture / ZV Port Registers.................................................................................................................................................................. 66

DVD Registers...................................................................................................................................................................................... 67

Revision 1.3 September 8, 1999

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Table of Contents

VT8601 Apollo ProMedia

VGA Registers....................................................................................................................................................................... 70

Attribute Controller Registers (AR)...................................................................................................................................................... 70

VGA Status / Enable Registers ............................................................................................................................................................. 70

VGA Sequencer Registers (SR) ............................................................................................................................................................ 71

VGA RAMDAC Registers.................................................................................................................................................................... 71

VGA Graphics Controller Registers (GR)............................................................................................................................................. 72

VGA CRT Controller Registers (CR) .................................................................................................................................................. 73

VGA Extended Registers...................................................................................................................................................... 74

VGA Extended Registers – Non-Indexed I/O Ports.............................................................................................................................. 74

VGA Extended Registers – Sequencer Indexed.................................................................................................................................... 75

VGA Extended Registers – Graphics Controller Indexed..................................................................................................................... 85

VGA Extended Registers – CRT Controller Indexed............................................................................................................................ 91

VGA Extended Registers – CRTC Shadow ........................................................................................................................................ 105

3D Graphics Engine Registers ........................................................................................................................................... 106

Operational Concept ........................................................................................................................................................................... 106

Drawing............................................................................................................................................................................................... 107

Geometry Primitives............................................................................................................................................................................ 108

Synchronization .................................................................................................................................................................................. 111

Functional Blocks ............................................................................................................................................................................... 111

Bus Interface ....................................................................................................................................................................................... 111

Span Engine......................................................................................................................................................................... 112

Graphics Engine Core ........................................................................................................................................................ 113

Graphics Engine Organization ............................................................................................................................................................ 116

Setup Engine Registers ....................................................................................................................................................................... 117

Vertex Registers.................................................................................................................................................................................. 118

Rasterization Engine Registers............................................................................................................................................................ 119

Pixel Engine Registers ........................................................................................................................................................................ 126

Texture Engine Registers .................................................................................................................................................................... 132

Memory Interface Registers ................................................................................................................................................................ 134

Data Port Area..................................................................................................................................................................................... 134

FUNCTIONAL DESCRIPTIONS ................................................................................................................................................ 135

SYSTEM CONFIGURATION ......................................................................................................................................................... 135

DFP Interface Configuration............................................................................................................................................. 135

GRAPHICS CONTROLLER POWER MANAGEMENT ................................................................................................................... 136

Power Management States................................................................................................................................................. 136

Power Management Clock Control................................................................................................................................... 136

Power Management Registers ........................................................................................................................................... 136

ELECTRICAL SPECIFICATIONS............................................................................................................................................. 137

ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................... 137

DC CHARACTERISTICS.............................................................................................................................................................. 137

AC TIMING SPECIFICATIONS.................................................................................................................................................... 137

MECHANICAL SPECIFICATIONS........................................................................................................................................... 138

Revision 1.3 September 8, 1999

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Table of Contents

VT8601 Apollo ProMedia

LIST OF FIGURES

FIGURE 1. VT8601 BALL DIAGRAM (TOP VIEW) ................................................................................................................ 12

FIGURE 2. VT8601 PIN LIST (NUMERICAL ORDER) – USING DFP, TVOUT, & VIDEO CAPTURE PORTS ............ 13

FIGURE 3. VT8601 PIN LIST (ALPHABETICAL ORDER) .................................................................................................... 14

FIGURE 4. GRAPHICS APERTURE ADDRESS TRANSLATION ......................................................................................... 48

FIGURE 5. PHYSICAL REGION DESCRIPTOR TABLE FORMAT..................................................................................... 60

FIGURE 6. PCI BUS MASTER ADDRESS TRANSLATION ................................................................................................... 60

FIGURE 7. FRAME BUFFER PARAMETERS.......................................................................................................................... 98

FIGURE 8. LIVE VIDEO DISPLAY PARAMETERS................................................................................................................ 98

FIGURE 9. MECHANICAL SPECIFICATIONS - 510-PIN BALL GRID ARRAY PACKAGE......................................... 138

LIST OF TABLES

TABLE 1. VT8601 PIN DESCRIPTIONS .................................................................................................................................... 15

TABLE 2. REGISTER SUMMARY.............................................................................................................................................. 23

TABLE 3. SYSTEM MEMORY MAP.......................................................................................................................................... 38

TABLE 4. MEMORY ADDRESS MAPPING TABLE ............................................................................................................... 39

TABLE 5. VGA/MDA MEMORY/IO REDIRECTION.............................................................................................................. 54

TABLE 6. SUPPORTED PCI COMMAND CODES................................................................................................................... 55

TABLE 7. INTERRUPT SOURCES AND CONTROLS ............................................................................................................ 57

TABLE 8. GRAPHICS CLOCK FREQUENCIES – 14.31818 MHZ REFERENCE................................................................ 77

TABLE 9. DPMS SEQUENCE - HARDWARE TIMER MODE............................................................................................... 88

TABLE 10. DPMS SEQUENCE - HARDWARE MODE IN SIMULTANEOUS DISPLAY MODE ..................................... 88

TABLE 11. HARDWARE CURSOR PIXEL OPERATION ...................................................................................................... 95

TABLE 12. PCI POWER MANAGEMENT STATES .............................................................................................................. 136

TABLE 13. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................... 137

TABLE 14. DC CHARACTERISTICS....................................................................................................................................... 137

TABLE 15. AC TIMING MIN / MAX CONDITIONS.............................................................................................................. 137

Revision 1.3 September 8, 1999

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Table of Contents

VT8601 Apollo ProMedia

VIA VT8601

APOLLO PROMEDIA

66 / 100 / 133 MHz

Single-Chip Slot-1 / Socket-370 PCI North Bridge,

With Integrated AGP 2D / 3D Graphics Accelerator

and Advanced Memory Controller

supporting PC100 / PC133 and VCM SDRAM

For Desktop PC Systems

• General

−

510 BGA Package (35mm x 35mm )

2.5 Volt core with 3.3V CMOS I/O

Supports GTL+ I/O buffer Host interface

Supports separately powered 5.0V tolerant interface to PCI bus and Video interface

2.5V, 0.25um, high speed / low power CMOS process

PC98 / 99 compatible using VIA VT82C686A (352-pin BGA) south bridge chip for Desktop and Mobile

applications

−

66 / 100 / 133 MHz CPU Front Side Bus (FSB) Operation

• High Integration

−

Single chip implementation for 64-bit Slot-1 and Socket-370 CPUs, 64-bit system memory, 32-bit PCI with

integrated 2D / 3D GUI accelerator

−

Apollo ProMedia Chipset: VT8601 system controller and VT82C686A PCI to ISA bridge

Chipset includes dual UltraDMA-33/66 EIDE, AC-97 link, 4 USB ports, integrated Super-I/O, hardware monitoring,

keyboard / mouse interfaces, and RTC / CMOS

• High Performance CPU Interface

−

Supports Slot-1Intel Pentium II^TM/ Pentium III^TMand Socket-370 Celeron^TMprocessors

66 / 100 / 133 MHz CPU Front Side Bus (FSB)

Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions

Five outstanding transactions (four In-Order Queue (IOQ) plus one input latch)

Supports WC (Write Combining) cycles

Dynamic deferred transaction support

Sleep mode support

System management interrupt, memory remap and STPCLK mechanism

CPU

DRAM

GUI Core Internal AGP

PCI

Comments

133 MHz 133 MHz 100 MHz

133 MHz 100 MHz 100 MHz

100 MHz 133 MHz 100 MHz

100 MHz 100 MHz 100 MHz

66 MHz

33 MHz Synchronous (DRAM uses CPU clock)

33 MHz Pseudo-synchronous (DRAM uses GUI clock)

33 MHz Synchronous (DRAM uses CPU clock)

33 MHz Pseudo-synchronous (DRAM uses GUI clock)

33 MHz Synchronous (DRAM uses CPU clock)

100 MHz 66 MHz

66 MHz 100 MHz 100 MHz

66 MHz 66 MHz 66 MHz

66 MHz

Revision 1.3 September 8, 1999

-1-

Features

VT8601 Apollo ProMedia

• Internal Accelerated Graphics Port (AGP) Controller

−

AGP v1.0 compliant

Pipelined split-transaction long-burst transfers up to 533 MB/sec

Eight level read request queue

Four level posted-write request queue

Thirty-two level (quadwords) read data FIFO (128 bytes)

Sixteen level (quadwords) write data FIFO (64 bytes)

Intelligent request reordering for maximum AGP bus utilization

Supports Flush/Fence commands

Graphics Address Relocation Table (GART)

One level TLB structure

Sixteen entry fully associative page table

LRU replacement scheme

Independent GART lookup control for host / AGP / PCI master accesses

Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport driver support

• Concurrent PCI Bus Controller

−

PCI bus is synchronous / pseudo-synchronous to host CPU bus

33 MHz operation on the primary PCI bus

Supports up to five PCI masters

Peer concurrency

Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time

Zero wait state PCI master and slave burst transfer rate

PCI to system memory data streaming up to 132Mbyte/sec

PCI master snoop ahead and snoop filtering

Six levels (double-words) of CPU to PCI posted write buffers

Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities

Enhanced PCI command optimization (MRL, MRM, MWI, etc.)

Forty-eight levels (double-words) of post write buffers from PCI masters to DRAM

Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters

Supports L1/L2 write-back forward to PCI master read to minimize PCI read latency

Supports L1/L2 write-back merged with PCI master post-write to minimize DRAM utilization

Delay transaction from PCI master reading DRAM

Read caching for PCI master reading DRAM

Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)

Symmetric arbitration between Host/PCI bus for optimized system performance

Complete steerable PCI interrupts

PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs

Revision 1.3 September 8, 1999

-2-

Features

VT8601 Apollo ProMedia

• Advanced High-Performance DRAM Controller

−

DRAM interface synchronous or pseudosynchronous with CPU FSB speed of 66 / 100 / 133 MHz

DRAM interface may be faster than CPU by 33 MHz to allow use of PC100 with 66 MHz Celeron CPU or use of

PC133 with 100 MHz Pentium II or Pentium III CPU

−

DRAM interface may be slower than CPU by 33 MHz to allow use of older memory modules with a newer CPU

Concurrent CPU, AGP, and PCI access

Supports FP, EDO, SDRAM and VCM-SDRAM memory types

Different DRAM types may be used in mixed combinations

Different DRAM timing for each bank

Dynamic Clock Enable (CKE) control for SDRAM power reduction in high speed systems

Mixed 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs

6 banks DRAMs supported up to 1GB (256Mb DRAM technology)

Flexible row and column addresses

64-bit data width only

3.3V DRAM interface with 5V-tolerant inputs

Programmable I/O drive capability for MA, command, and MD signals

Two-bank interleaving for 16Mbit SDRAM support

Two-bank and four bank interleaving for 64Mbit SDRAM support

Supports maximum 8-bank interleave (i.e., 8 pages open simultaneously); banks are allocated based on LRU

Independent SDRAM control for each bank

Seamless DRAM command scheduling for maximum DRAM bus utilization

(e.g., precharge other banks while accessing the current bank)

Four cache lines (16 quadwords) of CPU to DRAM write buffers

Four cache lines of CPU to DRAM read prefetch buffers

Read around write capability for non-stalled CPU read

Speculative DRAM read before snoop result

Burst read and write operation

x-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM from CPU or from DRAM controller

x-1-1-1-1-1-1-1 back-to-back accesses for SDRAM

BIOS shadow at 16KB increment

Decoupled and burst DRAM refresh with staggered RAS timing

CAS before RAS or self refresh

−

Revision 1.3 September 8, 1999

-3-

Features

VT8601 Apollo ProMedia

• General Graphic Capabilities

−

64-bit Single Cycle 2D/3D Graphics Engine

Supports 2 to 8 Mbytes of Frame Buffer

Real Time DVD MPEG-2 and AC-3 Playback

Video Processor

I²C Serial Interface

Integrated 24-bit 230MHz True Color DAC

Extended Screen Resolutions up to 1600x1200

Extended Text Modes 80 or 132 columns by 25/30/43/60 rows

DirectX 6 and OpenGL ICD API

• Graphics Performance

−

Sustained 1M polygons/second and 100M pixels/second

30fps DVD playback of 9.8Mbps MPEG-2 video with 30% headroom

Host Based AC-3 decode at only 8% utilization

• High Performance rCADE3D™ Accelerator

−

32 entry command queue, 32 entry data queue

4Kbyte texture cache with over 90% hit rates

Pipelined Single Cycle Setup/Texturing/Rendering Engines

DirectDraw™ acceleration

Multiple buffering and page flipping

Setup Engine

−

32-bit IEEE floating point input data

Slope and vertex calculations

Back facing triangle culling

1/16 sub-pixel positioning

Rendering Engine

−

High performance single pass execution

Diffused and specula lighting

Gouraud and flat shading

Anti-aliasing including edge, scene, and super-sampling

OpenGL compliant blending for fog and depth-cueing

16-bit Z-buffer

8/16/32 bit per pixel color formats

Texturing Engine

−

1/2/4/8-bits per pixel compact palletized textures

16/32-bits per pixel quality non-palletized textures

Pallet formats in ARGB 565, 1555, or 444

Tri-linear, bi-linear, and point-sampled filtering

Mip-mapping with multiple Level-Of-Detail (LOD) calculations and perspective correction

Color keying for translucency

2D GUI Engine

−

8/15/16/24/32-bits per pixel color formats

256 Raster Operations (ROPs)

Accelerated drawing: BitBLTs, lines, polygons, fills, patterns, clipping, bit masking

Panning, scrolling, clipping, color expansion, sprites

32x32 and 64x64 Hardware Cursor

DOS graphics and text modes

Revision 1.3 September 8, 1999

-4-

Features

VT8601 Apollo ProMedia

• DVD

−

Hardware-Assisted MPEG-2 Architecture for DVD with AC-3

Simultaneous motion compensation and front-end processing (parsing, decryption and decode)

Supports full DVD 1.0, VCD 2.0 and CD-Karaoke

Microsoft DirectShow 3.0 native support, backward compatible to MCI

No additional frame buffer requirements

Sub-picture hardware eliminates Run-Length-Decoder and Alpha Blending overhead

Dynamic frame and field de-interlace filtering for high quality playback on VGA monitors (Bob and Weave)

Tamper-proof software CSS implementation

Freeze, Fast-Forward, Slow Motion, Reverse

Pan-and-Scan support for 16:9 sequence

• Video Processor

−

On-chip Color Space Converter (CSC)

Anti-tearing via two frame buffer based capture surfaces

Minifier for video stream compression and filtering

Horizontal/vertical interpolation with edge recovery

Dual frame buffer apertures for independent memory access for graphics and video

YUV 4:2:2/4:1:1/4:2:0 and RGB formats

Video Module Interface (VMI) to MPEG and video decoder

Vertical Blank Interval for Intercast™

Overlay differing video and graphic color depths

Minifier Video Module Interface (VMI) to MPEG and video decode

Display two simultaneous video streams from both internal AGP and VMI

Two scalers and Color Space Converters (CSC) for independent windows

• Flat Panel Interface

−

85MHz Flat Panel interface supports 1024x768 panels

Support for TFT, STN & DSTN panel technologies

Allows external LVDS or TMDS transmitter for advanced panel interfaces

• Power Management Support

−

Dynamic power down of SDRAM (CKE)

Independent clock stop controls for CPU / SDRAM, AGP, and PCI bus

PCI and AGP bus clock run and clock generator control

VTT suspend power plane preserves memory data

Suspend-to-DRAM and Self-Refresh operation

EDO self-refresh and SDRAM self-refresh power down

8 bytes of BIOS scratch registers

Low-leakage I/O pads

• Testability

−

Build-in NAND-tree pin scan test capability

Revision 1.3 September 8, 1999

-5-

Features

VT8601 Apollo ProMedia

SYSTEM OVERVIEW

The Apollo ProMedia is a PC Slot-1 system logic North Bridge with integrated 2D/3D Graphics accelerator. The core logic

portion of the chip is based on the VIA Apollo Pro133 with integrated graphics accelerator provided by an industry leading

Graphics supplier. The combination of the two leading edge technologies provides a stable, cost-effective, and high performance

solution to both the Desktop and Mobile personal computer markets. As shown in Figure 1 below, the Apollo ProMedia will

interface to:

•

Slot-1 Front-Side Bus (66 – 133 MHz)

PC66 / PC100 / PC133 SDRAM Memory Interface

PCI Bus (30 - 33 MHz)

Analog RGB Monitor with DDC

Various Flat Panels or Digital Monitor Transmitters (TMDS or LVDS)

Video Capture / Playback CODECs

Celeron or

Pentium-II / III

Processor

CNTLs

Apollo

ProMedia

D

R

A

M

MD[63:0]

TDMS/LVDS

510 BGA

MA[13:0]

TV Encoder

VMI

TV Signal

Figure 1: Apollo ProMedia High Level System Diagram

Revision 1.3 September 8, 1999

-6-

System Overview

VT8601 Apollo ProMedia

Apollo ProMedia Core Logic Overview

Apollo ProMedia – System Media Accelerated North Bridge (SMA) – is a high performance, cost-effective and energy efficient

solution for the implementation of Integrated 2D / 3D Graphics - PCI - ISA desktop and notebook personal computer systems

from 66 MHz to 133 MHz based on 64-bit Slot-1 Intel Pentium II, Pentium III, and Celeron processors. The complete solution

consists of the Apollo ProMedia controller / “north bridge” (510 BGA) and either the VT82C596B (324 BGA) or the VT82C686A

(352 BGA) PCI-to-ISA south bridge. Both south bridges are PC98 / PC99 compliant with integrated UltraDMA-33 / 66 IDE, 4

USB ports, and a complete power management feature set. The VT82C686A also integrates HW monitoring, Super-I/O functions

(floppy disk drive interface and serial / parallel ports), and AC-97 link supporting digital audio and HSP modem functions.

Apollo ProMedia supports six banks of DRAMs up to 1GB. The DRAM controller supports standard Fast Page Mode (FP)

DRAM, EDO-DRAM, Synchronous DRAM (SDRAM), and Virtual Channel Synchronous DRAM (VC-SDRAM) in a flexible

mix / match manner. The Synchronous DRAM interface allows zero wait state bursting between the DRAM and the data buffers

at 100 MHz. The six banks of DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs.

The DRAM Controller is optimized to run synchronous with the CPU Front Side Bus (FSB) frequency of 66 MHz, 100 MHz, or

133 MHz.

The Apollo ProMedia also supports full AGP v1.0 capability with the internal 2D/3D Graphics Engine for maximum software

compatibility. An eight level request queue plus a four level post-write request queue with thirty-two and sixteen quadwords of

read and write data FIFO’s respectively are included for deep pipelined and split AGP transactions. A single-level GART TLB

with 16 full associative entries and flexible CPU/AGP/PCI remapping control is also provided for operation under protected mode

operating environments. Both Windows-95 VXD and Windows-98 / NT5 miniport drivers are supported.

The Apollo ProMedia supports one 32-bit 3.3 / 5V system bus (PCI) that is synchronous / pseudo-synchronous to the CPU bus.

The chip also contains a built-in AGP bus-to-PCI bus bridge to allow simultaneous concurrent operations on each bus. Five levels

(doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation, forty-

eight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for concurrent

PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI bus commands such as Memory-Read-Line, Memory-

Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, advanced features are supported

such as snoop ahead, snoop filtering, L1 / L2 write-back forward to PCI master, and L1 / L2 write-back merged with PCI post

write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are

also implemented for further improvement of overall system performance.

For sophisticated notebook implementations, the Apollo ProMedia provides independent clock stop control for the CPU /

SDRAM, PCI, and AGP buses and Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is

implemented for the SDRAM control signals for Suspend-to-DRAM operation. Coupled with the 324-pin Ball Grid Array VIA

VT82C596A south bridge chip, a complete notebook PC main board can be implemented with no external TTLs.

Revision 1.3 September 8, 1999

-7-

System Overview

VT8601 Apollo ProMedia

Apollo ProMedia Graphics Controller Overview

The Apollo ProMedia Graphics Controller is a highly integrated display control device that incorporates a 64-bit 3D/2D graphic

engine and video accelerator with advanced DVD video and optional TV output capability. It provides a flexible and high

performance solution for graphics and video playback acceleration for various color depth and resolution modes.

The Apollo ProMedia Graphics Controller supports a video capture port to import captured live MPEG 1 or MPEG 2 video

streams, or DVD decompressed video streams to be overlaid with a graphics stream of mixed color depth displays. In supporting

dual live videos, the Apollo ProMedia Graphics Controller offers independent dual video windows ready for videoconferencing

and with linear scaling capability.

Integrating the programmable phase lock loop with high speed LUT DACs, the Apollo ProMedia Graphics Controller is a true

price/performance solution for the modern multimedia based entertainment PC.

Capability Overview

The Apollo ProMedia Graphics Controller is a fully integrated CRT and TV 64-bit 2D/3D Accelerator. The high performance

graphics engine offers high speed 3D image processing in full compliance and compatibility with IBM® VGA and VESA™

extended VGA. As an integrated controller, it allows unprecedented cost and performance advantages by eliminating the need for

an external frame buffer while at the same time gaining local access to a larger amount of memory. Many functions can now be

eliminated that previously consumed large amounts of bandwidth.

The Apollo ProMedia Graphics Controller, equipped with a single-cycle 3D GUI Engine, pipelines 3D rendering process

architecture in hardware, providing real-time interactions with solid 3D models in CAD/CAM, 3D modeling, and 3D games. It

supports all key 3D rendering operations, including: Gouraud shading for smooth object surfaces, texture mapping for realistic

object textures, 16-bit hardware Z-buffering for fast 3D depth calculations, and Alpha Blending for transparency effects.

The Apollo ProMedia Graphics Controller’s highly innovative design, a full 64-bit memory interface with a high performance

graphics engine which can support a RAMDAC™ running up to 230MHz, dramatically improves GUI functions and significantly

promotes overall system operation.

The Apollo ProMedia Graphics Controller supports a full AGP implementation internally to remain compatible with existing

software and programming models. However, since the engine is integrated it enjoys a higher bandwidth and lower latency than is

possible with discrete solutions. AGP operations can include direct access of the system memory by the 2D/3D engine to provide

increased texture memory.

To meet the requirements of a PC99 graphics adapter in a multimedia PC, the Apollo ProMedia Graphics Controller supports

planar video format for MPEG-1, MPEG-2, and DVD-video playback. The dual video playback is capable of overlaying windows

for videoconferencing and multimedia displays. Advanced features of the Apollo ProMedia Graphics Controller, such as color

space conversion, video scaling, dual video windows, dual-view display, Video Module Interface (VMI), Vertical Blanking

Interleave (VBI), a 24-bit True Color DAC, and triple clock synthesizers allow performance at peak levels.

By using an extended 16-bit VMI port the Apollo ProMedia Graphics Controller can support DTV resolution. This port can

operate as either an input for Video Capture or as an output for Video display. The Apollo ProMedia Graphics Controller is

capable of supporting three simultaneous displays: CRT, Flat Panel & Video, each with a different “window” or desktop.

Apollo ProMedia Graphics Controller supports a rich featured flat panel interface that can be used to directly control a flat panel

device. Alternatively, it can drive an LVDS or TMDS transmitter to support the latest Flat Panel displays requiring these

interfaces.

Revision 1.3 September 8, 1999

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System Overview

VT8601 Apollo ProMedia

System Capabilities

The Apollo ProMedia Graphics Controller’s main system features include:

•

High Performance single cycle GUI

Highly Integrated RAMDAC™ and Triple Clock Synthesizer

Full Feature High Performance 3D Graphics Engine

High speed internal AGP Bus Mastering data bus supporting DVD video playback & 3D

Hardware implementation of motion compensation

Dual Video Windows for Videoconferencing

TrueVideo Processor

DirectDraw^TMand DirectVideo^TMHardware Support

Versatile Motion Video Capture/Overlay/Playback Support

Flexible Frame Buffer Memory Interface

Advanced Mobile Power Management

CRT Power Management (VESA™ DPMS)

PC99 Hardware Support

High Performance 64-bit 2D GUI

The 64-bit graphics engine of the Apollo ProMedia Graphics Controller significantly improves graphics performance through

specialized hardware that accelerates the most frequently used GUI operations and matches the high-speed requirements of CPUs.

Functions directly supported in hardware include: BitBLTs, image and text transfer, line draw, short stroke vector draw, rectangle

fills, and clipping. The graphics engine supports 256 Raster Operations (ROPs) for up to 32-bit packed pixel graphic modes. The

ROP3 Processor in the Apollo ProMedia Graphics Controller is able to perform Boolean functions which allow many additional

operations, including transparency, pattern masking, color expansion alignment, and pattern enhancement. Additionally, the

graphics engine features linear display memory addressing (up to 4GB memory space), accelerated color expansion modes for

graphics text procession, and memory-mapped I/O registers on the graphics engine for faster access time.

Graphic functions are optimized by a 64-bit internal data bus and a four-color hardware cursor/pop-up icon, operating up to a

128x128x2 pixel image, which offloads the CPU. The hardware cursor mechanism can also be used to display patterns stored in

the system memory. This pop-up icon is very useful to display user friendly information instantly through simple hot key

operations. This advanced function combination allows significant performance increases over standard Super VGA designs and

provides outstanding graphics acceleration on GUIs, such as Microsoft Windows 98 .

Highly Integrated RAMDAC^TM& Clock Synthesizer

The highly integrated design of the Apollo ProMedia Graphics Controller offers a “no TTL” solution for cost-effective, high-

performance multimedia subsystem designs for the PC and compatible notebooks. The 64-bit memory data bus supporting

SDRAM and SGRAM memory provides faster data transfer rates for improved system throughput. The Apollo ProMedia

Graphics Controller has a built-in, high speed RAMDAC^TM. The RAMDAC^TMis composed of one 256x24 and one 256x18 color

lookup table and a triple loop frequency synthesizer, providing the read/write timing control for the Frame Buffer Memory and the

refresh of the TV/CRT display.

The integrated frequency synthesizer provides a 125MHz memory clock for high speed DRAM access and a 230MHz video clock

which supports various refresh rates up to 85Hz at 1280x1024.

Full Feature High Performance 3D Engine

The Apollo ProMedia Graphics Controller is equipped with an advanced Graphics Drawing, Single Cycle 3D Graphics Engine

that performs premium 3D functions at a high level of more than 1M triangles per second. The 3D engine supports Microsoft

Direct3D. The 3D Engine is set up to off-load the CPU from major 3D tasks including slope calculation, sub-pixel positioning,

and Tri-striping. By balancing the 3D pipeline and reducing parameter passing, the Apollo ProMedia Graphics Controller

provides very high levels of performance. The 3D engine is integrated with a triangle set-up engine that sets up triangles

according to vertex input data and accomplishes various functions for 3D rendering. Gouraud shading provides smooth shading

for colors across surfaces, perspective correction texture mapping to correct texture data based on the perspective, bi-linear texture

filtering for interpolating, alpha blending to compensate colors for the opacity of two colors blended, Z-buffering (16-bit/24-bit),

video texturing to overlay 2D video play-back onto 3D images, fogging to simulate weather effects, palletized texture mapping (1-

Revision 1.3 September 8, 1999

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System Overview

VT8601 Apollo ProMedia

, 4-, or 8-bit) for memory and bandwidth reduction, and anti-aliasing to reduce or eliminate jaggies resulted from alias rendering.

The 3D engine also works with the APM system, conserving power while 3D operations are suspended.

Video Processor

Video processor features include: on-chip hardware Color Space Conversion (CSC) for faster data conversion on the fly,

Horizontal/Vertical (H/V) scaling with interpolation, edge recovery algorithm logic, gamma correction, and overlay control with

different color depths from graphics. The Apollo ProMedia Graphics Controller also includes a fully integrated GUI accelerator,

read cache, and command FIFO that optimize memory bandwidth and maximize graphics performance.

The Apollo ProMedia Graphics Controller, with an integrated Video Display and a Capture Engine, supports dual apertures on the

PCI bus which enables independent graphic and video data to be transported simultaneously to and from different memory areas

and greatly accelerates the performance of both DirectDraw^TMand DirectVideo^TM. The Apollo ProMedia Graphics Controller can

provide dual video windows that display different images from different video sources (from the PCI bus and from the capture

port) on the same screen. The video image is stored in off-screen memory and is retrieved by the Video Display Processing block

for video processing. With the help of DirectDraw™ acceleration for sprites, page flipping, double buffering, and color keying,

video processing is performed by utilizing a proprietary edge recovery algorithm for sharper line visibility, de-interlacing, anti-

tearing, multitap horizontal filtering, dithering, and scaling operations with bilinear interpolation in both horizontal and vertical

directions. Linear scaling permits zoom in/out to any size without any restrictions. In addition, the on-chip hardware Color Space

Conversion (CSC) accelerates conversion for 16 bit YUV pixels into linear true color 32 bit RGB pixels on the fly. The additional

X and Y minifiers are capable of shrinking video images to any linear fractions, which saves bus bandwidth and memory space.

The YUV planar logic of the Apollo ProMedia Graphics Controller supports a YUV 420 format that can eliminate redundant

video stream decoding procedures. The load of the CPU is reduced while performing software MPEG or software video

conferencing. The color and luminance control provided by the Apollo ProMedia Graphics Controller offers color compensations

to prevent color distortion for display devices such as a CRT or TV with Gamma correction and hue adjustment control.

The Video Conferencing feature allows remote and local video images to be displayed simultaneously on the same screen.

Video Capture and DVD

The Apollo ProMedia Graphics Controller has a Video Module Interface (VMI) and advanced hardware interface logic allowing it

to be directly connected to many MPEG and video decoders such as the C-Cube CL450/480, SGS 3400/3500, Philips 7110/1 and

Brooktree BT819/817/827/829.

The Apollo ProMedia Graphics Controller, integrated with a DVD video hardware block for motion compensation, gives existing

PCs the ability to play DVD video in MPEG-2 format at high bandwidths with very good video quality.

A new industry standard is being set for transmission of non-video data over a TV broadcast signal during vertical blanking dead

time. This technology is referred to as Intercast. The Apollo ProMedia Graphics Controller has the ability to take the entire video

stream over the video port, sending the visible video stream to the display memory for display in a window, stripping the VBI data

from the stream, and then sending this data to the CPU for processing using PCI Bus Mastering.

Versatile Frame Buffer Interface

The Apollo ProMedia Graphics Controller features a versatile frame buffer interface apperature into main system memory.

Optimized performance can be achieved with the single cycle memory bus interface using programmable DRAM timing. The

display queue has been increased to reduce the frequency of memory bus requests, optimizing memory bus efficiency for the

graphic controller.

With the support of the internal AGP apperature, the Apollo ProMedia Graphics Controller has access to system memory through

the GART. In the execute mode, the Apollo ProMedia Graphics Controller is able to use both the dedicated graphics portion and

the general portion of system memory for graphics operations. As a result, DVD and 3D rendering performance and quality are

greatly enhanced.

Hi-Res and Hi-Ref Display Support

Apollo ProMedia Graphics Controller display enhancements dramatically improve CRT resolution. These enhancements include

support of non-interlaced 1280x1024x64K, 1024x768x16M, 800x600x16M, and 640x480x16M colors for “full spectrum” color.

Extended text modes of 80 or 132 columns by 25, 30, 43, or 60 rows provide an extended graphics area frequently used in many

spreadsheet and database applications. Extended graphics and text modes are supported by software drivers that provide a “ready-

to-go” solution, minimizing the need for additional driver development.

Revision 1.3 September 8, 1999

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System Overview

VT8601 Apollo ProMedia

A virtual screen can be created with the Apollo ProMedia Graphics Controller . When this function is enabled, a selected portion

of a large image can be shown on a smaller display. The image can also be moved across the whole screen, either up or down.

The Apollo ProMedia Graphics Controller is able to automatically detect DDC monitors with I²C signaling.

CRT Power Management (VESA DPMS)

The Apollo ProMedia Graphics Controller conforms to the standard power management schemes defined by VESA™ for CRTs.

The Apollo ProMedia Graphics Controller supports four states of VESA™ Display Power Management Signaling (DPMS), which

decrease monitor power consumption after timeout periods. VESA™ DPMS power down states (ready, standby, suspend, and

off) specify HSYNC and VSYNC signals to control the monitor power down state.

Flat Panel Interface

The Apollo ProMedia Flat Panel interface is designed to support industry standard TFT and STN panels. It can also be used to

drive external TMDS or LVDS transmitters. The interface supports both 18-bit and 24-bit display modes. Optionally, an 18+18

panel can be supported utilizing external latches.

24 Bit

Mode

18 Bit

Mode Notes

PD[23]

PD[22]

PD[21]

PD[20]

PD[19]

PD[18]

PD[17]

PD[16]

PD[15]

PD[14]

PD[13]

PD[12]

PD[11]

PD[10]

PD[9]

B0

B1

G0

G1

R0

R1

B2

B3

G2

G3

R2

R3

B4

B5

B6

B7

G4

G5

G6

G7

R4

R5

R6

R7

S2

S1

S2 used for external 18+18

S1 used for external 18+18

B0

B1

G0

G1

R0

R1

B2

B3

B4

B5

G2

G3

G4

G5

F2

PD[8]

PD[7]

PD[6]

PD[5]

PD[4]

PD[3]

PD[2]

R3

R4

R5

PD[1]

PD[0]

Video Capture Interface

The Video Module Interface (VMI) is supported for video devices such as MPEG1 and MPEG2. Additionally, the zero-wait state

host write buffer, read cache, and memory mapped I/O increase operating speeds and contribute to peak performance levels. All

I/O interfaces are 5V tolerant, capable of interfacing with external devices operating at 5V, even though the Apollo ProMedia

Graphics Controller runs at 2.5V. Graphics system throughput is further enhanced by a command FIFO, allowing maximum bus

transfer speed for applications such as Windows™ or AutoCAD™ that directly access video memory.

Complete Hardware Compatibility

The Apollo ProMedia Graphics Controller is fully compliant with the VESA™ DDC and VAFC standards. The Apollo ProMedia

Graphics Controller is 100% VGA compatible at both the BIOS and Driver level, allowing full compatibility with virtually any

VGA application software. The Apollo ProMedia Graphics Controller provides hardware support to DirectDraw™, offering high

speed game graphics on Windows 98 . The Apollo ProMedia Graphics Controller meets the requirements of PC99 as well,

supporting a unique ID for each customer and a unique ID for each model.

Revision 1.3 September 8, 1999

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System Overview

VT8601 Apollo ProMedia

Figure 2. VT8601 Pin List (Numerical Order) – Using DFP, TVout, & Video Capture Ports

Pin #

A01

A02 IO NC

A03 IO NC

A04 IO NC

A05 IO NC

A06 IO HD62

A07 IO HD57

A08 IO HD63

Pin Name Pin #

Pin Name

Pin #

Pin Name

LP

VCC3

HCLK

HLOCK#

Pin #

N26 IO MD06

P01 GND

P02 IO VD09

P03 IO VD10

P04 IO VD11

P05 IO VD08

P06

P21

Pin Name

Pin #

Pin Names

Pin #

AC26

AD01 IO REQ7#

AD02 IO GNT5#

AD03 IO GNT6#

AD04

AD05

AD06 IO AD28

AD07 IO CBE3#

Pin Name

MA05 / strap

P

GNDRGB

D02

D03

D04

A

P

BLUE

GRN

GND

G05

G06

G21

G22

G23

O

P

I

Y22

Y23

Y24

Y25

Y26

AA01

AA02

AA03 IO NC

O

RAS4# / CS4#

RAS3# / CS3#

RAS2# / CS2#

RAS1# / CS1#

RAS0# / CS0#

O

P

D05 IO HD61

D06 IO HD53

D07 IO HD54

D08 IO HD47

D09 IO HD42

I

REQ3#

REQ1#

G24 IO HIT#

G25 IO HTRDY#

G26

P

A

GNDV2

VLF2

P

GND

I

HITM#

A09

P

GND

D10 IO HD37

D11 IO HD36

D12 IO HD29

D13 IO HD25

D14 IO HD23

H01

H02

H03

H04

H05

O

PD02

PD01

DE

PD05

EVEE /

P22 IO MD12

P23 IO MD08

P24 IO MD41

P25 IO MD09

P26 IO MD40

AA04 IO NC

AD08 P GND

A10 IO HD45

A11 IO HD38

A12 IO HD34

A13 IO HD31

AA05 IO NC

AD09 IO CBE2#

AD10 IO TRDY#

AD11 IO AD14

AD12 IO AD09

AA06

AA07

P

GND

VCC3

AA08 IO AD16

A14 IO HD16

A15 IO HD13

A16 IO HD03

A17 IO HD12

D15 IO HD07

D16 IO HD11

D17 IO HD08

D18 IO HD06

D19 IO HD15

D20 IO HA30

D21 IO HA17

H06

H21

H22

H23 IO RS0#

H24 GND

H25 IO RS2#

H26 IO DBSY#

P

VCC3

VCCA

R01 IO VD06

R02 IO VD04

R03 IO VD07

R04 IO VD05#

R05 IO VD03#

R06 IO VD00#

R22 IO MD44

AA09

AA10

AA13

AA14

AA15

AA17

AA18

P

VCCI

VCC3

GND

VCC3

VCCI

AD13

AD14

AD15

AD16 IO MD61

AD17 IO MD27

AD18 IO MD57

P

GND

PWROK

PGNT#

I

O

A18

A19

P

O

GND

CPURST#

P

A20 IO HA18

AD19 P GND

A21 IO HA20

A22 IO HA22

A23 IO HA10

A24 IO HA28

D22 IO HA12

J01

J02

J03

J04

J05

J06

J21

J22

O

P

O

PD04

PD03

PD08

PD07

R23 IO MD10

R24 IO MD43

R25 IO MD11

R26 IO MD42

T01 IO VD02

T02 IO VD01

T03 IO VHS

AA19 IO MD58

AD20 IO MD21

AD21 IO MD50

AD22 IO MD16

D23

P

GND

AA20

AA21

AA22

AA23

AA24

AA25

AA26

P

O

VCC3

D24 IO HA04

D25 IO HA14

D26 IO BNR#

GND

VSUS2

MA00 / strap

SRASA#

SRASB# / CKE5 AD26

AD23

AD24

AD25

O

CAS6# / DQM6

MA11 / strap

MA09 / strap

MA08 / strap

A25 IO HA03

PD11

A26

B01

B02

P

GND

GNDS

GND

E01

E02

E03

E04

O

A

VSYNC

HSYNC

IRSET

VCCI

MCLKO

T04

T05

T06

T21

P

O

P

VCC3

TVD4

TVD6

GND

SRASC# / CKE4 AE01 IO GNT7#

B03 IO NC

B04 IO NC

B05 IO NC

B06 IO HD50

COMP

J23 IO DRDY#

J24 IO ADS#

J25

J26

AB01 IO NC

AB02 IO NC

AB03 IO NC

AB04 IO NC

AE02

AE03

AE04

O

I

GNT4#

GNT3#

REQ2#

E05 IO HD56

E06 IO HD58

E07 IO HD46

O

P

BREQ0#

GND

T22 IO MD15

AE05 IO LOCK#

B07 IO HD59

B08 IO HD48

B09 IO HD51

B10 IO HD44

E08 IO HD40

E09 IO HD27

E10 IO HD39

K01

K02

K03

K04

O

PD12

PD10

PD13

PD20

T23 IO MD13

T24 IO MD46

T25 IO MD14

T26 IO MD45

AB05

O

GNT0#

AE06 IO AD27

AE07 IO AD20

AE08 IO AD19

AE09 IO FRAME#

AB06 IO AD30

AB07 IO AD25

AB08 IO AD21

E11

P

VTT

B11 IO HD22

B12 IO HD32

B13 IO HD33

B14 IO HD19

B15 IO HD24

B16 IO HD02

B17 IO HD10

B18 IO HD01

B19 IO HA26

B20 IO HA29

B21 IO HA23

B22 IO HA25

E12

P

GTLREF

K05

K06

K21

K22

K23 IO RS1#

K24

K25 IO MD01

K26 IO MD32

L01

L02

L03

L04

O

P

I

PD16

U01 IO VVS

AB09 IO DEVSEL#

AE10 IO STOP#

AE11 IO AD13

AE12 IO AD08

AE13 IO AD02

AE14 IO AD01

E13 IO HD35

E14 IO HD21

E15 IO HD30

E16 IO HD14

E17 IO HD18

E18 IO HD17

E19 IO HD00

E20 IO HA24

PD06

U02

O TVD7

AB10 IO PAR

VCC3

MCLKI

U03 IO VCLK

AB11 IO CBE1#

AB12 IO AD10

AB13 IO AD07

AB14 IO AD05

U04

U05

U06

U21

U22

O

P

O

TVD5

TVD2

VCC5

VCC3

SCASA#

PLLTST

AE15

I RESET#

AB15

I

PCLK

AE16 IO MD30

AE17 IO MD59

AE18 IO MD26

AE19 IO MD55

AE20 IO MD22

AE21 IO MD19

AB16 IO MD63

AB17 IO MD29

AB18 IO MD56

O

P

PD17

PD15

PD18

VCC3

U23 IO MD47

E21

E22

P

O

GTLREF

CPURSTD#

U24

U25

U26

O

SWEA#/MWEA#

SWEB#/MWEB# / CKE2 AB19 IO MD54

SWEC#/MWEC# / CKE0 AB20 IO MD20

E23 IO HA07

B23 IO HA21

B24 IO HA13

B25 IO HA05

E24 IO HREQ0#

E25 IO HREQ4#

E26 IO BPRI#

L05

L06

L21

O

P

PD09

PD14

GNDA

V01

V02

V03

V04

V05

V06

V21

V22

O

P

TVD0

TVD1

TVD3

TVCLK

TVHS

VCCI

VSUS3

AB21 IO MD18

AE22 IO MD48

AB22

AB23

AB24

AB25

AB26

P

O

VSUS3

AE23

AE24

O

CAS3# / DQM3

MA12 / strap

MA01 / strap

MA04 / strap

MA03 / strap

MA02 / strap

B26 IO HA06

F01

O

EVDD

L22

P

GNDA

AE25

AE26

AF01

AF02

AF03

O

P

I

MA13 / strap

MA10 / strap

GND

REQ4#

GNT2#

C01

C02

P

A

VCCS

RED

F02 IO SDA

F03 IO SCL

L23 IO MD33

L24 IO MD35

L25 IO MD03

L26 IO MD02

C03 IO NC

C04 IO NC

F04

F05

I

ETST#

SUSP

AC01 IO NC

AC02 IO REQ5#

O

C05 IO NC

C06 IO HD60

C07 IO HD55

F06

F07

P

GND

M01

M02

M03

M04

M05

M06

M21

M22 IO MD34

M23 IO MD00

M24 IO MD05

M25 IO MD36

M26 IO MD04

O

I

PD23

IMIO

IMIIN

PD21

PD22

PD19

GND

V23

V24

V25

V26

W01

W02

W03

W04

W05

W06

W21

W22

O

P

O

P

O

P

CAS0# / DQM0

SCASC# / CKE1

SCASB# / CKE3

GND

VCCD

VCCV1

TVVS

XLTO

INTA#

VCC3

RAS5# / CS5#

VSUS3

AC03 IO REQ6#

AF04

O

GNT1#

VCC3

AC04

P

GND

AF05 IO AD31

AF06 IO AD26

AF07 IO AD22

AF08 IO AD18

F08 IO HD52

F09

AC05

I

REQ0#

C08

P

GND

P

VCCI

O

AC06 IO AD29

C09 IO HD41

C10 IO HD49

C11 IO HD43

C12 IO HD28

C13 IO HD26

F10

F12

F13

F14

F16

F17

F18

F19

P

VCC3

GND

VCC3

VCCI

VTT

O

P

AC07 IO AD24

AC08 IO AD23

AC09 IO AD17

AC10 IO IRDY#

AC11 IO AD15

AC12 IO AD11

AC13 IO AD06

AC14 IO AD04

AF09 P GND

AF10 IO SERR#

AF11 IO AD12

AF12 IO CBE0#

AF13 IO AD03

AF14 IO AD00

AF15 IO PCKRUN#

C14

P

GND

C15 IO HD20

C16 IO HD09

C17 IO HD05

F20

P

VCC3

N01 IO VD14

W23

W24

W25

W26

O

CAS1# / DQM1

AC15

I

PREQ#

AF16 IO MD62

C18 IO HD04

F21

P

GND

N02 IO VD13

P

GND

AC16 IO MD31

AC17 IO MD60

AC18 IO MD25

AF17 IO MD28

C19

P

GND

F22 IO HA15

F23 IO HREQ1#

N03

P

GND

O

CAS5# / DQM5

CAS4# / DQM4

AF18 P GND

AF19 IO MD24

C20 IO HA27

N04 IO VD15

C21 IO HA31

C22 IO HA19

C23 IO HA16

F24 IO HREQ2#

F25 IO HREQ3#

F26 IO DEFER#

N05 IO VD12

Y01

Y02

Y03

P

A

GNDV1

VCCV2

VLF1

AC19 IO MD23

AC20 IO MD52

AC21 IO MD49

AF20 IO MD53

AF21 IO MD51

AF22 IO MD17

N06

N21

P

GND

C24 IO HA09

C25 IO HA11

C26 IO HA08

G01

G02

G03

O

EBLT

PD00

FLM

N22 IO MD39

N23 IO MD37

N24 IO MD07

Y04

I

XLTI

AC22

AC23

AC24

I

P

O

SUST#

AF23

AF24

AF25

O

CAS7# / DQM7

CAS2# / DQM2

MA14 / strap

Y05 IO NC

GND

Y06

P

VCC3

MA07 / strap

D01

P

VCCR

G04

O

SCLK

N25 IO MD38

Y21

P

VCC3

AC25

O

MA06 / strap

AF26

P

GND

Center GND Pins (28 pins): L11, L13-14, L16, M12-15, N11-16, P11-16, R12-15, T11, T13-14, T16

Center VCC3 Pins (8 pins): L12, L15, M11, M16, R11, R16, T12, T15

Revision 1.3 September 8, 1999

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Pinouts

VT8601 Apollo ProMedia

Figure 3. VT8601 Pin List (Alphabetical Order)

Pin #

AF14 IO AD00

AE14 IO AD01

Pin Name

Pin #

M21

N03

Pin Name Pin #

GND

Pin Name Pin #

Pin Names

NC

Pin #

U25

U26

Pin Name

SWEB#/MWEB# / CKE2

SWEC#/MWEC# / CKE0

D17 IO HD08

AC25

AC24

O

MA06 / strap

MA07 / strap

B03

B04

-

O

P

C16 IO HD09

GND

AE13 IO AD02

AF13 IO AD03

AC14 IO AD04

AB14 IO AD05

AC13 IO AD06

AB13 IO AD07

AE12 IO AD08

B17 IO HD10

D16 IO HD11

A17 IO HD12

A15 IO HD13

E16 IO HD14

D19 IO HD15

A14 IO HD16

AD26

AD25

AE26

AD24

AE24

AE25

AF25

O

MA08 / strap

MA09 / strap

MA10 / strap

MA11 / strap

MA12 / strap

MA13 / strap AA03

MA14 / strap AA04

B05

C03

C04

C05

Y05

-

NC

AD10 IO TRDY#

N06

N21

P01

P06

P21

T21

V26

P

GND

V04

V01

V02

U05

V03

T05

O

TVCLK

TVD0

TVD1

TVD2

TVD3

TVD4

AD12 IO AD09

AB12 IO AD10

E18 IO HD17

E17 IO HD18

K22

J22

I

O

MCLKI

MCLKO

AA05

AB01

-

NC

U04

T06

O

TVD5

TVD6

W24

AA06

P

GND

AC12 IO AD11

AF11 IO AD12

AE11 IO AD13

B14 IO HD19

C15 IO HD20

E14 IO HD21

M23 IO MD00

K25 IO MD01

L26 IO MD02

AB02

AB03

AB04

-

NC

U02

V05

W03

O

TVD7

TVHS

TVVS

AA13

AA14

AA15

P

GND

AD11 IO AD14

AC11 IO AD15

AA08 IO AD16

AC09 IO AD17

B11 IO HD22

D14 IO HD23

B15 IO HD24

D13 IO HD25

L25 IO MD03

M26 IO MD04

M24 IO MD05

N26 IO MD06

AC01

AB10 IO PAR

AF15 IO PCKRUN#

AB15

-

NC

AA21

AC04

AC23

AD08

P

GND

F07

F10

F12

F17

P

VCC3

I

PCLK

AF08 IO AD18

AE08 IO AD19

AE07 IO AD20

AB08 IO AD21

AF07 IO AD22

AC08 IO AD23

C13 IO HD26

E09 IO HD27

C12 IO HD28

D12 IO HD29

E15 IO HD30

A13 IO HD31

N24 IO MD07

P23 IO MD08

P25 IO MD09

R23 IO MD10

R25 IO MD11

P22 IO MD12

G02

H02

H01

J02

J01

H04

O

PD00

PD01

PD02

PD03

PD04

PD05

AD13

AD19

AF01

AF09

AF18

AF26

P

GND

F20

G06

G21

H06

K21

L04

P

VCC3

AC07 IO AD24

AB07 IO AD25

B12 IO HD32

B13 IO HD33

T23 IO MD13

T25 IO MD14

K06

J04

O

PD06

PD07

L21

L22

P

GNDA

T04

U21

P

VCC3

AF06 IO AD26

AE06 IO AD27

AD06 IO AD28

AC06 IO AD29

AB06 IO AD30

AF05 IO AD31

A12 IO HD34

E13 IO HD35

D11 IO HD36

D10 IO HD37

A11 IO HD38

E10 IO HD39

T22 IO MD15

AD22 IO MD16

AF22 IO MD17

AB21 IO MD18

AE21 IO MD19

AB20 IO MD20

J03

L05

K02

J05

K01

K03

O

PD08

PD09

PD10

PD11

PD12

PD13

A01

B01

Y01

AA01

AB05

AF04

P

O

GNDRGB

GNDS

W06

Y06

Y21

AA07

AA10

AA17

P

VCC3

GNDV1

GNDV2

GNT0#

GNT1#

J24 IO ADS#

AF03

AE03

AE02

AD02

O

GNT2#

GNT3#

GNT4#

GNT5#

E08 IO HD40

C09 IO HD41

D09 IO HD42

C11 IO HD43

AD20 IO MD21

AE20 IO MD22

AC19 IO MD23

AF19 IO MD24

L06

L02

K05

L01

O

PD14

PD15

PD16

PD17

AA20

U06

H21

H22

P

VCC3

VCC5

VCCA

D02

A BLUE

D26 IO BNR#

E26 IO BPRI#

J25

V23

W23

AF24

AE23

O

BREQ0#

CAS0# / DQM0 AE01

CAS1# / DQM1

CAS2# / DQM2

CAS3# / DQM3

AD03

O

A

P

GNT6#

GNT7#

GRN

GTLREF

B10 IO HD44

A10 IO HD45

E07 IO HD46

D08 IO HD47

B08 IO HD48

AC18 IO MD25

AE18 IO MD26

AD17 IO MD27

AF17 IO MD28

AB17 IO MD29

L03

M06

K04

M04

M05

O

PD18

PD19

PD20

PD21

PD22

W01

F09

F18

J06

J21

P

VCCD

VCCI

D03

E12

E21

P

W26

W25

AD23

AF23

AF12 IO CBE0#

AB11 IO CBE1#

AD09 IO CBE2#

AD07 IO CBE3#

E04

A19

E22

O

CAS4# / DQM4

CAS5# / DQM5

CAS6# / DQM6

CAS7# / DQM7

A25 IO HA03

D24 IO HA04

B25 IO HA05

B26 IO HA06

E23 IO HA07

C26 IO HA08

C24 IO HA09

A23 IO HA10

C25 IO HA11

D22 IO HA12

B24 IO HA13

C10 IO HD49

B06 IO HD50

B09 IO HD51

F08 IO HD52

D06 IO HD53

D07 IO HD54

C07 IO HD55

E05 IO HD56

A07 IO HD57

E06 IO HD58

B07 IO HD59

AE16 IO MD30

AC16 IO MD31

K26 IO MD32

L23 IO MD33

M22 IO MD34

L24 IO MD35

M25 IO MD36

N23 IO MD37

N25 IO MD38

N22 IO MD39

P26 IO MD40

M01

AD15

K24

AC15

AD14

Y26

Y25

Y24

Y23

O

PD23

PGNT#

PLLTST

PREQ#

V06

V21

AA09

AA18

D01

C01

W02

Y02

P

VCCI

VCCR

VCCS

VCCV1

VCCV2

I

PWROK

O

RAS0# / CS0#

RAS1# / CS1#

RAS2# / CS2#

RAS3# / CS3#

RAS4# / CS4#

RAS5# / CS5#

A

O

COMP

CPURST#

CPURSTD#

U03 IO VCLK

R06 IO VD00

T02 IO VD01

Y22

W21

H26 IO DBSY#

H03 DE / GMD11

D25 IO HA14

F22 IO HA15

C23 IO HA16

D21 IO HA17

A20 IO HA18

C22 IO HA19

A21 IO HA20

B23 IO HA21

A22 IO HA22

C06 IO HD60

D05 IO HD61

A06 IO HD62

A08 IO HD63

P24 IO MD41

R26 IO MD42

R24 IO MD43

R22 IO MD44

T26 IO MD45

T24 IO MD46

U23 IO MD47

AE22 IO MD48

AC21 IO MD49

C02

A

I

RED

T01 IO VD02

R05 IO VD03

R02 IO VD04

R04 IO VD05

R01 IO VD06

R03 IO VD07

P05 IO VD08

P02 IO VD09

P03 IO VD10

O

AC05

AD05

AE04

AD04

AF02

AC02

AC03

AD01

REQ0#

REQ1#

REQ2#

REQ3#

REQ4#

REQ5#

REQ6#

REQ7#

F26 IO DEFER#

AB09 IO DEVSEL#

J23 IO DRDY#

I

G24 IO HIT#

G01

O

EBLT

G26

G23

I

HITM#

HLOCK#

F04

F01

H05

I

O

ETST#

EVDD

EVEE

E24 IO HREQ0#

F23 IO HREQ1#

G03

O

FLM

B21 IO HA23

E20 IO HA24

B22 IO HA25

B19 IO HA26

C20 IO HA27

A24 IO HA28

B20 IO HA29

D20 IO HA30

C21 IO HA31

F24 IO HREQ2#

F25 IO HREQ3#

E25 IO HREQ4#

AD21 IO MD50

AF21 IO MD51

AC20 IO MD52

AF20 IO MD53

AB19 IO MD54

AE19 IO MD55

AB18 IO MD56

AD18 IO MD57

AA19 IO MD58

AE17 IO MD59

AC17 IO MD60

AD16 IO MD61

AE15

I

RESET#

P04 IO VD11

N05 IO VD12

N02 IO VD13

N01 IO VD14

N04 IO VD15

T03 IO VHS

AE09 IO FRAME#

H23 IO RS0#

K23 IO RS1#

H25 IO RS2#

U22

V25

V24

G04

F03 IO SCL

F02 IO SDA

AF10 IO SERR#

AA24

AA25

AA26

A09

A18

A26

B02

C08

C14

C19

D04

D23

F06

F13

F14

F16

F21

H24

J26

P

GND

E02

O HSYNC

G25 IO HTRDY#

O

SCASA#

M02

M03

W05

O

I

O

IMIO

IMIIN

INTA#

SCASB# / CKE3

SCASC# / CKE1

SCLK

Y03

AA02

AA22

V22

W22

AB22

E01

A

P

O

P

VLF1

VLF2

AC10 IO IRDY#

E03 IRSET

AE05 IO LOCK#

VSUS2

VSUS3

VSYNC

VTT

G22

I

HCLK

A

E19 IO HD00

B18 IO HD01

B16 IO HD02

A16 IO HD03

C18 IO HD04

C17 IO HD05

D18 IO HD06

D15 IO HD07

G05

O

LP

O

SRASA#

SRASB# / CKE5

SRASC# / CKE4

AA23

AB23

AB26

AB25

AB24

AC26

MA00 / strap AF16 IO MD62

MA01 / strap AB16 IO MD63

MA02 / strap

MA03 / strap

MA04 / strap

MA05 / strap

E11

F19

A02

A03

A04

A05

-

NC

AE10 IO STOP#

VTT

F05

AC22

U24

I

O

SUSP

SUST#

SWEA# / MWEA#

U01 IO VVS

Y04

W04

I

O

XLTI

XLTO

Center GND Pins (28 pins): L11, L13-14, L16, M12-15, N11-16, P11-16, R12-15, T11, T13-14, T16

Center VCC3 Pins (8 pins): L12, L15, M11, M16, R11, R16, T12, T15

Revision 1.3 September 8, 1999

-14-

Pinouts

VT8601 Apollo ProMedia

PIN DESCRIPTIONS

Table 1. VT8601 Pin Descriptions

CPU Interface

Signal Name

HA[31:3]#

Pin #

I/O Signal Description

see pin list IO

Connect to the address bus of the host CPU. These pins are inputs

Host Address Bus.

during CPU cycles, but are driven by the VT8601 during cache snooping operations.

see pin list IO

These signals are connected to the CPU data bus.

. The CPU asserts ADS# in T1 of the CPU bus cycle.

HD[63:0]#

ADS#

BNR#

Host CPU Data.

Address Strobe

J24

IO

D26

. Used to block the current request bus owner from issuing new

Block Next Request

requests. This signal is used to dynamically control the processor bus pipeline depth.

E26

IO

. The owner of this signal will always be the next bus owner.

BPRI#

Priority Agent Bus Request

This signal has priority over symmetric bus requests and causes the current symmetric

owner to stop issuing new transactions unless the HLOCK# signal is asserted. The

VT82C693 drives this signal to gain control of the processor bus.

H26

F26

IO

. Used by the data bus owner to hold the data bus for transfers requiring

more than one cycle.

Defer

. The VT8601 uses a dynamic deferring policy to optimize system performance. The

DBSY#

Data Bus Busy

DEFER#

VT8601 also uses the DEFER# signal to indicate a processor retry response.

J23

G24

IO

. Asserted for each cycle that data is transferred.

DRDY#

HIT#

Data Ready

Hit

Also driven in conjunction with HITM# by the target to extend the snoop window.

. Asserted by the CPU to indicate that the address presented with the last

. Indicates that a cacheing agent holds an unmodified version of the requested line.

G26

G23

I

HITM#

Hit Modified

assertion of EADS# is modified in the L1 cache and needs to be written back.

. All CPU cycles sampled with the assertion of HLOCK# and ADS# until the

HLOCK#

Host Lock

negation of HLOCK# must be atomic.

J25

O

BREQ0#

Bus Request 0.

Bus request output to CPU.

E25, F25,

F24, F23,

E24

IO

HREQ[4:0]#

Request Command

. Asserted during both clocks of the request phase. In the first clock,

the signals define the transaction type to a level of detail that is sufficient to begin a snoop

request. In the second clock, the signals carry additional information to define the complete

transaction type.

G25

IO

. Indicates that the target of the processor transaction is able to enter

the data transfer phase.

. Indicates the type of response per the table below:

RS[2:0]# Response type

HTRDY#

RS[2:0]#

Host Target Ready

H25, K23,

H23

Response Signals

000

001

010

Idle State

Retry Response

Defer Response

Reserved

011

100

Hard Failure

101

110

111

Normal Without Data

Implicit Writeback

Normal With Data

Reset output to CPU

A19

E22

O

CPURST#

CPURSTD#

CPU Reset.

CPU Reset Delayed.

CPU Reset output delayed by 2T.

Note: Clocking of the CPU and cache interfaces is performed with HCLK; see the clock pin group at the end of the pin

descriptions section for descriptions of the clock input pins.

Note: All signals above require 4.7K pullups to VCC3 except EADS#, HITM#, AHOLD, HA, and HD.

Note: All signals above connect directly to the host CPU except HA and HD which connect directly to the L2 cache SRAMs and

connect to the host CPU through 22 ohm series resistors (see the “Apollo ProMedia Design Guide” for more information).

Revision 1.3 September 8, 1999

-15-

Pinouts

VT8601 Apollo ProMedia

DRAM Interface

Signal Name

MD[63:0]

Pin #

I/O Signal Description

see pin list

IO

These signals are connected to the DRAM data bus.

Memory Data.

Note: MD0 is internally pulled up for use in EDO memory type

detection.

AF25, AE25, O / I

AE24, AD24,

AE26, AD25,

AD26, AC24,

AC25, AC26,

AB24, AB25,

AB26, AB23,

AA23

DRAM address lines. These pins are also used for

Memory Address.

power-up strapping options (sampled on the rising edge of RESET#):

MA14,12 Rx68[1-0] CPU FSB Freq (0=66, 1=100, 2=auto, 3=133)

MA[14:0]

/ Strap Options

MA13

MA11

MA10-9

MA8, 6

MA7

Rx52[7] GTL I/O Buffer Pullup (0=Disable, 1=Enable)

In-order Queue Depth (0=1-level, 1=4-level)

North Bridge Clock Delay (0-3 Clocks)

Graphics Clock Select (0=Normal, 1-3=Test)

Graphics Test Mode (0=Normal, 1=Test)

LCD Output (0=Off, 1=On)

MA5

MA4-2

MA1-0

Panel Type (0-3=TFT, 4-7=DSTN)

Graphics Clock Delay (0-3 Clocks)

All pins have internal pull-downs for default low (0).

Strap 1 using 4.7KΩ TO VCC3.

AA25,

AA26,

V25,

U25,

V24,

IO

Clock enables 5-0 may be connected to the

SDRAM Clock Enable.

DRAM modules in any order. Each DRAM module requires 2 clock

enables.

CKE5# / SRASB#,

CKE4# / SRASC#,

CKE3# / SCASB#,

CKE2# / SWEB#,

CKE1# / SCASC#,

CKE0# / SWEC#

RAS[5-0]# / CS[5-0]#

Note: These pins are powered by VSUS

U26

W21, Y22,

Y23, Y24,

Y25, Y26

O

Multifunction Pins

1. FPG/EDO DRAM: Row Address Strobe of each bank.

2. Synchronous DRAM: Chip select of each bank.

Note: These pins are powered by VSUS.

Multifunction Pins

1. FPG/EDO DRAM: Column Address Strobe of each byte lane.

2. Synchronous DRAM: Data mask of each byte lane.

Note: These pins are powered by VSUS.

AF23, AD23,

W25, W26,

AE23, AF24,

W23, V23

AA24,

CAS#[7:0] / DQM[7:0]

For support of up to three

SRASA#,

SRASB# / CKE5,

SRASC# / CKE4

Row Address Command Indicator.

AA25,

AA26

Synchronous DRAM DIMM slots (these are copies of the same logical

signal). “A” controls banks 0-1 (module 0), “B” controls banks 2-3

(module 1), and “C” controls banks 4-5 (module 2).

U22,

V25,

V24

For support of up to three

Column Address Command Indicator.

SCASA#,

SCASB# / CKE3

SCASC# / CKE1

Synchronous DRAM DIMM slots (these are copies of the same logical

signal). “A” controls banks 0-1 (module 0), “B” controls banks 2-3

(module 1), and “C” controls banks 4-5 (module 2).

U24,

U25,

U26

For support of up to three

SWEA# / MWEA#,

SWEB# / MWEB# / CKE2,

SWEC# / MWEC# / CKE0

Write Enable Command Indicator.

Synchronous DRAM DIMM slots (these are copies of the same logical

signal). Multifunction pins, used as MWE# pins for FPG/EDO

memory. “A” controls banks 0-1 (module 0), “B” controls banks 2-3

(module 1), and “C” controls banks 4-5 (module 2). Note: These pins

are powered by VSUS.

Note: Clocking of the memory subsystem uses memory clock (MCLK); see the clock pin group at the end of the pin descriptions

section for descriptions of the clock pins.

Note: Connect all memory interface pins except MD to the DRAM modules through 22Ω series resistors (see the Apollo ProMedia

Design Guide” for more specific connection details and PCB layout recommendations).

Revision 1.3 September 8, 1999

-16-

Pinouts

VT8601 Apollo ProMedia

PCI Bus Interface

Signal Name

AD[31:0]

Pin #

I/O Signal Description

see pin list

IO

The standard PCI address and data lines. The address is

Address/Data Bus.

driven with FRAME# assertion and data is driven or received in following

cycles.

AD7, AD9, AB11,

AF12

IO

Commands are driven with FRAME# assertion.

Byte enables corresponding to supplied or requested data are driven on

following clocks.

CBE[3:0]#

Command/Byte Enables.

AB10

AE9

IO

A single parity bit is provided over AD[31:0] and C/BE[3:0].

Assertion indicates the address phase of a PCI transfer. Negation

PAR

FRAME#

Parity.

Frame.

indicates that one more data transfer is desired by the cycle initiator. 10KΩ

pullup to VCC3.

AC10

AD10

AE10

AB9

IO

IRDY#

Asserted when initiator is ready for data transfer. 10KΩ

Initiator Ready.

pullup to VCC3.

Target Ready.

VCC3.

TRDY#

STOP#

Asserted when target is ready for data transfer. 10KΩ pullup to

Asserted by the target to request the master to stop the current

transaction. 10KΩ pullup to VCC3.

Stop.

This signal is driven by the ProMedia when a PCI initiator is

DEVSEL#

Device Select.

attempting to access main memory. It is an input when the ProMedia is acting

as a PCI initiator. 10KΩ pullup to VCC3.

AE5

AF10

AC15

AD15

IO

I

LOCK#

SERR#

Used to establish, maintain, and release resource lock. 10KΩ pullup to

Lock.

VCC3.

The ProMedia will pulse this signal when it detects a system

System Error.

error condition (10KΩ pullup to VCC3).

This signal comes from the South Bridge. PREQ# is

PREQ#

South Bridge Request.

the South Bridge request for the PCI bus. 10KΩ pullup to VCC3.

O

I

This signal driven by the ProMedia to grant PCI access

PGNT#

South Bridge Grant.

to the South Bridge. 10KΩ pullup to VCC3.

AD1, AC3, AC2, AF2,

AD4, AE4, AD5, AC5

AE1, AD3, AD2, AE2,

AE3, AF3, AF4, AB5

REQ[7:0]#

GNT[7:0]#

INTA#

PCI master requests for use of the PCI bus. 2.2KΩ

PCI Master Request.

pullup to VCC5.

O

Permission is given to the master to use the PCI bus.

PCI Master Grant.

2.2KΩ pullup to VCC3.

W5

INTA# is an asynchronous active low output used to

PCI Interrupt Out.

signal an event that requires handling. It is driven by the integrated graphics

controller.

Note: Clocking of the PCI interface is performed with PCLK; see the clock pin group at the end of the pin descriptions sectionfor

descriptions of the clock input pins.

Revision 1.3 September 8, 1999

-17-

Pinouts

VT8601 Apollo ProMedia

Clock / Reset Control

Signal Name

HCLK

Pin #

I/O

Signal Description

This pin receives the host CPU clock. This clock is used by all logic in

G22

I

Host Clock.

the host CPU domain. It is driven by the external clock synthesizer.

K22

J22

I

This clock is used by internal clock logic to maintain the proper

Memory Clock In.

phase relationship with MCLKO. It is driven by the external clock synthesizer.

Created on-chip from MCLKI and used by the memory controller

Memory Clock Out.

MCLKI

O

MCLKO

as a timing reference for creation of all memory timing sequences. It is connected to the

external clock chip for use in maintaining proper phase relationships.

AB15

I

This clock is used by all on-chip logic in the PCI clock domain. This input

PCI Clock.

PCLK

must be 33 MHz maximum to comply with PCI specification requirements and must be

synchronous with the host CPU clock (HCLK) with an HCLK:PCLK frequency ratio of

2:1 (66MHz CPU clock) or 3:1 (100 MHz CPU clock). The PCI clock needs to be

controlled to within 1.5 ± 0.5 nsec relative to the host CPU clock (CPU leads).

AF15

Y4

IO

I

. For implementation of PCI bus clock control for low-power PCI bus

PCI Clock Run

operation. Refer to the “PCI Mobile Design Guidelines” and “Apollo ProMedia Design

Guide” documents for additional information.

PCKRUN#

XLTI

14.31818 MHz for the video clock synthesizer reference. Connect to a

Crystal Input.

14.31818 MHz clock source if a crystal not used. Connect to main ground plane GND

with 10Pf if using a crystal.

W4

O

I

14.31818 MHz for the video clock synthesizer reference. Leave open

Crystal Output.

if a clock source is used instead of a crystal. Connect to main ground plane GND with

10Pf if using a crystal.

XLTO

AE15

Driven from the South Bridge PCIRST# signal. When asserted (low), this signal

Reset.

RESET#

resets the ProMedia and sets all register bits to the default value. This signal also

connects to the PCI bus (South Bridge RESET drives the ISA bus if implemented). The

rising edge of this signal is used to sample all power-up strap options (see memory

interface MA pins).

A19

E22

AD14

AC22

O

I

CPU Reset output to the host CPU.

CPURST#

CPURSTD#

PWROK

SUST#

CPU Reset.

Alternate CPU Reset output to the host CPU

Connect to South Bridge and Power Good circuitry.

CPU Reset Delayed 2T.

Power OK.

I

For implementation of the Suspend-to-DRAM feature. Input logic for

Suspend Status.

this pin is powered by VSUS. Connect to the South Bridge SUST# pin or to a 10KΩ

pullup to VSUS if not used.

F5

I

Used to put the integrated graphics controller into suspend state.. Input logic

Suspend.

SUSP

for this pin is powered by VSUS. Connect to South Bridge GPO pin or to a 10KΩ

pullup to VSUS if not used.

Miscellaneous

Signal Name

Pin #

I/O

Signal Description

F4

M2

M3

I

O

I

ETST#

IMIO

IMIIN

4.7KΩ pullup to VCC3 for normal operation.

Leave open.

IMI Out.

4.7KΩ pullup to VCC3.

Test Mode Enable.

IMI In.

Revision 1.3 September 8, 1999

-18-

Pinouts

VT8601 Apollo ProMedia

CRT Interface

Signal Name

RED

Pin #

I/O Signal Description

C2

A

Red analog output to the CRT. Connect 75Ω load resistor to GNDR (RGB Return)

Red.

and connect to VGA connector through a series ferrite bead and 10pF capacitors to GNDR

on both input and output sides of the bead (see “Apollo ProMedia Design Guide”).

D3

D2

E2

A

O

Green analog output to the CRT. Connect same as RED.

Green.

GRN

BLUE

HSYNC

Blue analog output to the CRT. Connect same as RED.

Blue.

Digital horizontal sync output to the CRT. Also used (with VSYNC)

Horizontal Sync.

to signal power management state information to the CRT per the VESA™ DPMS™

standard. Connect to VGA connector through a series 47Ω resistor and 120pF capacitor

to ground (see “Apollo ProMedia Design Guide”).

E1

F2

O

Digital vertical sync output to the CRT. Also used (with HSYNC) to

Vertical Sync.

VSYNC

SDA

signal power management state information to the CRT per the VESA™ DPMS™

standard. Connect to VGA connector through a series 47Ω resistor and 120pF capacitor

to ground (see “Apollo ProMedia Design Guide”).

IO

Serial I²C protocol for VESA™ DDC2B signaling to the CRT.

DDC Data/Address.

Connect this pin to VCC5 through a 4.7KΩ pullup. Connect to the VGA connector only

(pin 12 of the connector). Connect through a ferrite bead and 120pF capacitor to ground

(on the output side of the bead). Refer to the “Apollo ProMedia Design Guide” for

additional information.

F3

IO

Serial I²C protocol for VESA™ DDC2B signaling to the CRT. Connect this

SCL

DDC Clock.

pin to VCC5 through a 4.7KΩ pullup. Connect to the VGA connector only (pin 15 of the

VGA connector). Connect through a ferrite bead and 120pF capacitor to ground (on the

output side of the bead). Refer to the “Apollo ProMedia Design Guide” for additional

information.

DFP Interface

Signal Name

Pin #

I/O Signal Description

(see pin list)

O

Digital pixel data outputs to the panel.

Clock for transferring digital pixel data.

Indicates valid data on PD[23-0].

PD[23-0]

SCLK

DE

LP

FLM

EVDD

EVEE

EBLT

Panel Data.

Shift Clock.

Data Enable.

G4

H3

G5

G3

F1

Digital monitor equivalent of HSYNC.

Line Pulse.

Digital monitor equivalent of VSYNC.

First Line Marker.

Enable Panel VDD Power.

Enable Panel VEE Power.

Enable Panel Backlight.

H5

G1

Note: Connect SHFCLK, DE, LP, and FLM to external TMDS transmitters through series 22Ω resistors. See the “Apollo

ProMedia Design Guide” for DFP interface design examples and additional information.

Revision 1.3 September 8, 1999

-19-

Pinouts

VT8601 Apollo ProMedia

TV Input / Video Interface

Signal Name

VD[15-0]

Pin #

I/O Signal Description

N4, N1, N2, N5, P4, P3, P2, P5,

IO

Video Capture / Playback Data.

R3, R1, R4, R2, R5, T1, T2, R6

T3

U1

U3

IO

Connect to TV decoder if used.

Video Vertical Sync.

Connect to TV decoder through a series 22Ω resistor.

VHS

VVS

VCLK

Video Horizontal Sync.

Video Clock.

Note: Refer to the “Apollo ProMedia Design Guide” for video interface design examples.

TV Output Interface

Signal Name

Pin #

I/O Signal Description

U2, T6, U4, T5, V3, U5, V2, V1

O

Connect to TV encoder if used.

TV Output Data.

TVD[7-0]

TVHS

TVVS

V5

W3

V4

Connect to TV encoder if used.

TV Horizontal Sync.

Connect to TV encoder if used.

TV Vertical Sync.

Connect to TV encoder through a series 22Ω resistor.

TVCLK

TV Clock.

Note: Refer to the “Apollo ProMedia Design Guide” for TV interface design examples.

Revision 1.3 September 8, 1999

-20-

Pinouts

VT8601 Apollo ProMedia

Clock Power / Ground and Filtering

Signal Name

VCCA

Pin #

I/O Signal Description

H21, H22

P

for

(2.5V ±5%). Connect to VCCI through a

North Bridge Clock Circuitry

Power

ferrite bead and decouple to GNDA with 0.001Uf and 0.1Uf ceramic and 10Uf tantalum

capacitors (see “Apollo ProMedia Design Guide”).

L21, L22

W2

P

for

Connect to main ground plane GND

North Bridge Clock Circuitry.

GNDA

Ground

through a ferrite bead. (see “Apollo ProMedia Design Guide”).

for (2.5V ±5%). Connect to

VCCV1

Power

Video Clock Synthesizer 1 Analog Circuitry

VCCI through a ferrite bead and decouple to GNDV1 with 0.001Uf and 0.1Uf ceramic

and 10Uf tantalum capacitors (see “Apollo ProMedia Design Guide”).

Y1

Y3

Y2

P

A

P

for

Connect to main ground plane through a

Video Clock Synthesizer 1.

GNDV1

VLF1

Ground

ferrite bead.

Low Pass Filter Capacitor

through a 560Pf capacitor.

for

Connect to GNDV1

Video Clock Synthesizer 1.

for

(2.5V ±5%). Connect to

VCCV2

Power

Video Clock Synthesizer 2 Analog Circuitry

VCCI through a ferrite bead and decouple to GNDV2 with 0.001Uf and 0.1Uf ceramic

and 10Uf tantalum capacitors (see “Apollo ProMedia Design Guide”).

AA1

AA2

K24

P

for

Connect to main ground plane through a

Video Clock Synthesizer 2.

GNDV2

VLF2

Ground

ferrite bead.

Low Pass Filter Capacitor

through a 560Pf capacitor.

A

for

Connect to GNDV2

Video Clock Synthesizer 2.

Pull down with 4.7K resistor for normal operation.

PLL Test.

PLLTST

RAMDAC Output Power / Ground and Analog Control

Signal Name

VCCS

Pin #

I/O Signal Description

C1

P

for

(2.5V ±5%). Connect to VCCI

RAMDAC Current Source Circuitry

Power

through a ferrite bead and decouple to GNDS with 0.001uF and 0.1uF ceramic and 10uF

tantalum capacitors (see “Apollo ProMedia Design Guide”).

B1

E4

E3

A1

P

A

P

for Connect to main ground plane

RAMDAC Current Source Circuitry.

through a ferrite bead.

GNDS

Ground

RAMDAC analog control. Connect to VCCS using a 0.1

COMP

IRSET

Compensation Capacitor.

uF capacitor.

RAMDAC analog control. Connect to GNDS

RAMDAC Current Set Point Resistor.

through a 360Ω 1% resistor.

Connection point for the RGB load resistors. Also used

RGB Video Output Return.

GNDRGB

as a shield for the RGB video output traces to the VGA display connector. Connects to

RGB return pins 6, 7, and 8 of the VGA connector. Connect to main ground plane

through a ferrite bead. Refer to the “Apollo ProMedia Design Guide” for more specific

connection and PCB layout details.

Commonly Used Prefix / Suffix Letters in Signal Names:

I = Internal Logic

A = North Bridge Clock Synthesizer

M = Memory (SDRAM) Interface

H = Host CPU Interface

P = PCI Bus Interface

G = AGP Bus (internal in ProMedia)

GM = Graphics Memory Interface

U (or USB) = USB (Universal Serial Bus)

H (or HWM) = Hardware Monitoring

SUS = Suspend Power

V1 = Video Clock Synthesizer PLL1

V2 = Video Clock Synthesizer PLL2

D = Video Clocks Digital Data Path

R = RAMDAC Digital Data Path

S = RAMDAC Current Source

RGB = Analog Video Out Return

TV = TV Out

V = TV In / Video Capture

Revision 1.3 September 8, 1999

-21-

Pinouts

VT8601 Apollo ProMedia

Digital Power and Ground

Signal Name

VCC5

Pin #

I/O Signal Description

U6

P

for

(5V ±5%). Power for CRT

Display / Video Interfaces

Power

H/VSYNC, DFP interface, video interface, and TV interface. Used to

provide adequate output voltage swing for driving external video

devices. Also used to provide 5V input tolerance from those interfaces.

F7, F10, F12, F17, F20, G6,

P

for

(2.5V to 3.3V ±5%). Power for host

On-Board Interfaces

VCC3

Power

G21, H6, K21, L4,

M11, M16, R11, R16,

CPU / L2 Cache interface, PCI bus interface, and memory interface

(except pins listed below under VSUS).

L12, L15,

T4,

, U21, W6, Y6, Y21,

T12, T15

AA7, AA10, AA17, AA20

V22, W22, AB22

P

(3.3V ±5%). Power for memory interface signals

Suspend Power

VSUS3

SRASC#, SCASC#, SWEC#, SWEB#, RAS[5-0]#, CAS[7-0]#, and

MECC[7-0] as well as SUSTAT# and SUSCLK. Connect to VCC3 if

suspend functions are not implemented.

AA22

P

(2.5V ±5%). Connect to VCCI if suspend functions

are not implemented.

VSUS2

VCCI

Suspend Power

F9, F18, J6, J21, V6, V21,

for

(2.5V ±5%).

Power

On-Chip Internal Logic

AA9, AA18

W1

for

(2.5V ±5%).

Video Clock Synthesizer Digital Logic

VCCD

Connect to VCCI through a ferrite bead and decouple to main ground

plane GND with 0.001uF and 0.1uF ceramic and 10uF tantalum

capacitors (see “Apollo ProMedia Design Guide”).

D1

P

for

(2.5V ±5%).

RAMDAC Video Output Digital Logic

VCCR

Power

Connect to VCCI through a ferrite bead and decouple to main ground

plane GND with 0.001uF and 0.1uF ceramic and 10uF tantalum

capacitors (see “Apollo ProMedia Design Guide”).

E11, F19

E12, E21

P

(1.5V ±10%).

VTT

GTLREF

CPU Interface Termination Voltage

2/3 VTT ±2%. Derived

CPU Interface GTL+ Voltage Reference.

from the termination voltage to the pullup resistors. Determines the

noise margin for the host CPU interface signals. Internally connects to

+

the GTL sense amp on each GTL input or I/O pin.

Connect to primary PCB ground plane.

Ground.

A9, A18, A26, B2, C8, C14,

C19, D4, D23, F6, F13-F14,

P

GND

F16, F21, H24, J26,

L11, L13,

, M21,

L14, L16, M12-M15

N3, N6,

, N21, P1, P6,

N11-N16

, P21,

P11-P16

R12-R15, T11,

, T21, V26,

T13, T14, T16

W24, AA6, AA13-AA15,

AA21, AC4, AC23, AD8,

AD13, AD19, AF1, AF9,

AF18, AF26

A2-A5, B3-B5, C3-C5, Y5,

AA3-AA5, AB1-AB4, AC1

-

NC

No Connect.

Revision 1.3 September 8, 1999

-22-

Pinouts

VT8601 Apollo ProMedia

REGISTERS

Register Overview

Register Summary Tables

Table 2. Register Summary

The following tables summarize the configuration and I/O

registers of the ProMedia. These tables also document the

power-on default value (“Default”) and access type (“Acc”)

for each register. Access type definitions used are RW

(Read/Write), RO (Read/Only), “—” for reserved / used

(essentially the same as RO), and RWC (or just WC) (Read /

Write 1’s to Clear individual bits). Registers indicated as RW

may have some read/only bits that always read back a fixed

value (usually 0 if unused); registers designated as RWC or

WC may have some read-only or read write bits (see

individual register descriptions following these tables for

details). All offset and default values are shown in

hexadecimal unless otherwise indicated.

I/O Ports

Port # I/O Port

Default Acc

00 RW

0000 0000 RW

22 PCI / AGP Arbiter Disable

CFB-8 Configuration Address

CFF-C Configuration Data

Revision 1.3 September 8, 1999

-23-

Register Summary Tables

VT8601 Apollo ProMedia

Device 0 Bus 0 Registers - Host Bridge

PCI Configuration Registers

Device-Specific Configuration Registers (continued)

Offset Configuration Header

1-0 Vendor ID

3-2 Device ID

5-4 Command

7-6 Status

Default Acc

Offset PCI Bus Control

70 PCI Buffer Control

71 CPU to PCI Flow Control 1

72 CPU to PCI Flow Control 2

73 PCI Master Control 1

74 PCI Master Control 2

75 PCI Arbitration 1

76 PCI Arbitration 2

77 Chip Test (do not program)

78 PMU Control 1

79 PMU Control 2

7A Miscellaneous Control

7B-7D -reserved-

7E-7F DLL Test Mode (do not program)

80-FF -reserved-

Default Acc

1106

0601

0006

0290

nn

RO

RW

WC

RO

—

00

RW

—

8

9

Revision ID

Program Interface

Sub Class Code

Base Class Code

-reserved- (cache line size)

Latency Timer

00

A

B

C

D

E

F

00

06

00

RW

RO

Header Type

Built In Self Test (BIST)

13-10 Graphics Aperture Base

14-27 -reserved- (base address registers)

28-2B -reserved- (unassigned)

2D-2C Subsystem Vendor ID

2F-2E Subsystem ID

33-30 -reserved- (expan ROM base addr)

37-34 Capability Pointer

34-3B -reserved- (unassigned)

3C-3D -reserved- (interrupt line & pin)

3E-3F -reserved- (min gnt and max latency)

0000 0008 RW

RW

—

00

0000

00

—

RW

—

Offset GART/TLB Control

83-80 GART/TLB Control

84 Graphics Aperture Size

85-87 -reserved- (unassigned)

8B-88 Gr. Aperture Translation Table Base 0000 0000 RW

8C-8F -reserved- (unassigned)

Default Acc

0000 0000 RW

00

RW

—

0000 00A0 RO

00

—

00

—

Offset AGP Control

A0 AGP ID

A1 AGP Next Item Pointer

A2 AGP Specification Revision

A3 -reserved- (unassigned)

A7-A4 AGP Status

AB-A8 AGP Command

AC AGP Control

AD AGP Latency

Default Acc

Device-Specific Configuration Registers

02

00

10

00

RO

—

Offset CPU Interface Control

50 Request Phase Control

51 Response Phase Control

52 Dynamic Defer Timer

53 Miscellaneous

55-54 Non-Cacheable Region #1

57-56 Non-Cacheable Region #2

Default Acc

00

10

00

0000

RW

0700 0203 RO

0000 0000 RW

00

RW

—

AC-EF -reserved- (unassigned)

Offset DRAM Control

59-58 MA Map Type

5A-5F DRAM Row Ending Address:

Default Acc

Offset BIOS Scratch

F0-F7 BIOS Scratch

Default Acc

00 RW

0000

RW

5A

5B

5C

5D

5E

5F

Bank 0 Ending (HA[29:22])

Bank 1 Ending (HA[29:22])

Bank 2 Ending (HA[29:22])

Bank 3 Ending (HA[29:22])

Bank 4 Ending (HA[29:22])

Bank 5 Ending (HA[29:22])

01

00

EC

00

01

00

RW

—

Offset Miscellaneous Control

F8 DRAM Arbitration Timer 1

F9 DRAM Arbitration Timer 9

FA CPU Direct Access FB Base Address

FB Frame Buffer Conrol

Default Acc

00

RW

60 DRAM Type

Offset Back Door Control

FC Back Door Control 1

FD Back Door Control 2

FF-FE Back Door Device ID

Default Acc

61 ROM Shadow Control C0000-CFFFF

62 ROM Shadow Control D0000-DFFFF

63 ROM Shadow Control E0000-FFFFF

64 DRAM Timing for Banks 0,1

65 DRAM Timing for Banks 2,3

66 DRAM Timing for Banks 4,5

67 -reserved- (unassigned)

68 DRAM Control

69 DRAM Clock Select

6A DRAM Refresh Counter

6B DRAM Arbitration Control

6C SDRAM Control

6D DRAM Control Drive Strength

6E-6F -reserved- (unassigned)

00

RW

0000 0000 RW

Revision 1.3 September 8, 1999

-24-

Register Summary Tables

VT8601 Apollo ProMedia

Device 1 Bus 0 Registers - PCI-to-AGP Bridge

PCI Configuration Registers

Device-Specific Configuration Registers

Offset Configuration Header

1-0 Vendor ID

3-2 Device ID

5-4 Command

7-6 Status

Default Acc

Offset AGP Control

Default Acc

1106

8601

0007

0220

nn

00

04

RO

RW

WC

RO

—

40 CPU-to-AGP Flow Control 1

41 CPU-to-AGP Flow Control 2

42 AGP Master Control

00

RW

—

43-4F -reserved- (unassigned)

8

9

Revision ID

Program Interface

Sub Class Code

Base Class Code

-reserved- (cache line size)

Latency Timer

A

B

C

D

E

F

06

00

01

00

RW

RO

—

Header Type

Built In Self Test (BIST)

10-17 -reserved- (base address registers)

18 Primary Bus Number

19 Secondary Bus Number

1A Subordinate Bus Number

1B -reserved- (secondary latency timer)

1C I/O Base

00

RW

—

F0

00

0000

RW

RO

1D I/O Limit

1F-1E Secondary Status

21-20 Memory Base

FFF0 RW

0000

RW

FFF0 RW

23-22 Memory Limit (Inclusive)

25-24 Prefetchable Memory Base

27-26 Prefetchable Memory Limit

28-3D -reserved- (unassigned)

3F-3E PCI-to-AGP Bridge Control

0000

00

RW

—

00

RW

Revision 1.3 September 8, 1999

-25-

Register Summary Tables

VT8601 Apollo ProMedia

Device 0 Bus 1 Registers - 2D / 3D Graphics Accelerator

PCI Configuration Registers

AGP Registers (2300-23FF)

I/O Port AGP Configuration Regs

2303-2300 (See PCI Bus Master Regs)

2307-2304 Capability List

230F-2308 -reserved-

2323-2310 (See PCI Bus Master Regs)

2333-2324 -reserved-

2337-2334 Capability List Address

233F-2338 -reserved-

Offset Configuration Header

1-0 Vendor ID

3-2 Device ID

5-4 PCI Command

7-6 PCI Status

Default Acc

1023

8500

0003

0220

nn

R

—

RW

—

RW

R

8

9

A

B

Revision ID

—

RW

—

Register Level

Sub Class Code

Base Class Code

00

03

R

—

I/O Port

AGP Operation Registers

Default Acc

F-C -reserved-

—

2343-2340 FB Command List Start Addr

2347-2344 FB Command List Size

234B-2348 Ch 1 FB Start Addr / Pitch

234F-234C Ch 1 Frame Buffer Size

2353-2350 Ch 1 System Start Address

2357-2354 Ch 1 & 2 System Side Pitch

235B-2358 Ch 2 System Start Address

235F-235C Ch 2 FB Start Addr / Pitch

2363-2360 Ch 2 FB Size

2367-2364 Ch Arb Counter Threshold

236B-2368 Channel 1/0 Control

236F-236C Global & Channel 2 Control

2373-2370 Cmd List / Ch 0/1/2 Op Status

237F-2374 -reserved-

—

RW

—

13-10 Memory Base 0 (8MB display mem)

17-14 Memory Base 1 (128K mem map IO) E080 0000 RW

1B-18 Memory Base 2 (8MB video overlay) E040 0000 RW

E000 0000 RW

2B-1C -reserved-

—

2D-2C Subsystem Vendor ID

2F-2E Subsystem ID

33-30 Expansion ROM Base

3B-34 -reserved-

3C Interrupt Line

3D Interrupt Pin

3E-3F -reserved-

Offset Device-Specific Configuration

40-8F -reserved-

93-90 Power Management 1

97-94 Power Management 2

98-FF -reserved-

0000

RW

0000 0001 RW

—

0B

01

—

RW

R

—

Default Acc

—

RW

—

I/O Port

AGP Configuration Regs

Default Acc

2383-2380 Capability Identifier

2387-2384 AGP Status

238B-2388 AGP Command

23AF-238C -reserved-

—

RW

—

PCI Bus Master Registers (2204, 2300, 231x, 232x)

I/O Port PCI Bus Master Registers Default Acc

I/O Port

AGP Command Buffer Regs Default Acc

2207-2204 Master Status

2303-2300 Master Control

2313-2310 System Side Start Address

2315-2314 Master Height

2317-2316 Master Width

231B-2318 FB Start Address & Pitch

231D-231C System Side Pitch

231F-231E -reserved-

—

R

23B3-23B0 Command Buffer Start Addr

23B7-23B4 Command Buffer End Addr

23FF-23B8 -reserved-

—

RW

—

RW

—

2323-2320 Clear Data

RW

Revision 1.3 September 8, 1999

-26-

Register Summary Tables

VT8601 Apollo ProMedia

Capture Registers (2200)

Extended Registers – Non-Indexed I/O Ports

I/O Port

Capture Registers

Default Acc

I/O Port

Extended Non-Indexed Regs Default Acc

2203-2200 Capture Command

—

RW

3D8

3D9

3xB

Alt Destination Segment Addr

Alt Source Segment Address

Alt Clock Select

00

—

RW

DVD Registers (2280-22FF)

Note: 3xB notation indicates that these registers are accessible

at either 3BB or 3DB depending on the setting of the color /

mono bit.

I/O Port

DVD Registers

MC ID

MC Control

MC Frame Buffer Config

-reserved-

Default Acc

2280

2281

2282

2283

—

R

RW

—

2285-2284 MC Status

2287-2284 MC Command Queue

—

RW

228B-2288 MC Y-Reference Address

228F-228C MC U-Reference Address

2293-2290 MC V-Reference Address

—

RW

2297-2294 MC Display Y-Address Offset

229B-2298 MC Display U-Address Offset

229F-229C MC Display V-Address Offset

—

RW

22A0

22A1

22A2

22A3

MC H Macroblock Count

-reserved-

MC V Macroblock Count

-reserved-

—

RW

—

RW

—

22A5-22A4 MC Frame Buffer Y-Length

22A7-22A6 -reserved-

22AB-22A8 Color Palette Entries

22AF-22AC -reserved-

—

RW

—

RW

—

22B3-22B0 SP BUF0 Pixel Start Address

22B7-22B4 SP BUF1 Pixel Start Address

—

RW

22BB-22B8 SP BUF0 Cmd Start Address

22BF-22BC SP BUF1 Cmd Start Address

—

RW

22C1-22C0 SP Y Display Offset

22CF-22C2 -reserved-

—

RW

—

22D0

Digital TV Encoder Control

—

RW

—

22D3-22D1 Digital TV Encoder CFC

22FF-22D4 -reserved-

Revision 1.3 September 8, 1999

-27-

Register Summary Tables

VT8601 Apollo ProMedia

Standard VGA Registers

Standard VGA Registers – Graphics Controller (GR)

Port Index VGA Registers

Default Acc

Port Index Graphics Controller Regs

Default Acc

3CE

3CF

—

0

1

2

3

4

5

6

7

8

Index

Set / Reset

—

00

—

RW

3B4/5 0-18 CRT Controller (Mono Mode)

—

RW

R

RW

R

3BA

—

Input Status 1 (Mono Mode)

Enable Set / Reset

Color Compare

Data Rotate

Read Map Select

Graphics Mode

Miscellaneous

Color Don’t Care

Bit Mask

3C0/1 0-14 Attribute Controller

—

3C2

3C3

—

Input Status 0

Miscellaneous Output (Write)

Video Subsystem Enable

W

RW

W

R

RW

R

RW

R

RW

3C4/5 0-4 Sequencer

3C6

3C7

3C8

—

RAMDAC Pixel Mask

RAMDAC Read Index

RAMDAC Write Index

RAMDAC Index Readback

Standard VGA Registers – CRT Controller (CR)

Port Index CRT Controller Registers Default Acc

3C9 0-FF RAMDAC Palette Data

3CC Miscellaneous Output (Read)

—

3CE/F 0-8 Graphics Controller

3x4

3x5

—

0

1

2

3

4

5

6

7

Index

Horizontal Total

—

00

FF

00

RW

3D4/5 0-18 CRT Controller (Color Mode)

—

3DA

—

Input Status 1 (Color Mode)

Horizontal Display Enable

Horizontal Blanking Start

Horizontal Blanking End

Horizontal Retrace Start

Horizontal Retrace End

Vertical Total

46E8

—

Display Adapter Enable

Note: CRTC registers are accessible at either 3B4 / 3B5 or

3D4 / 3D5 (shorthand notation 3x4 / 3x5) depending on the

setting of the color / mono bit.

Standard VGA Registers – Attribute Controller (AR)

Overflow

8

9

Preset Row Scan

Maximum Scan Line

Cursor Start

Port Index Attribute Controller Regs

3C0 Index

Default Acc

—

RW

A

B

C

D

E

F

3C0/1 0-F Color Palette

Cursor End

3C0/1 10 Attribute Mode Control

3C0/1 11 Overscan Color

3C0/1 12 Color Plane Enable

3C0/1 13 Horizontal Pixel Panning

3C0/1 14 Color Select

Start Address High

Start Address Low

Cursor Location High

Cursor Location Low

10 Vertical Retrace Start

11 Vertical Retrace End

12 Vertical Display Enable End

13 Offset

14 Underline Location

15 Vertical Blanking Start

16 Vertical Blanking End

17 CRTC Mode Control

18 Line Compare

Standard VGA Registers – Sequencer (SR)

Port Index Sequencer Registers

Default Acc

3C4

3C5

—

0

1

2

3

Index

Reset

Clocking Mode

Map Mask

Character Map Select

Memory Mode

—

RW

4

Note: CRTC registers are accessible at either 3B4 / 3B5 or

3D4 / 3D5 (shorthand notation 3x4 / 3x5) depending on the

setting of the color / mono bit.

Revision 1.3 September 8, 1999

-28-

Register Summary Tables

VT8601 Apollo ProMedia

Extended Registers – VGA Sequencer Indexed

Port Index Extended Sequencer Regs

Default Acc

Port Index New Video Display Regs

Default Acc

3C5

8

9

Old-New Status

Graphics Controller Version

-reserved-

00

58

—

F3

B7

—

20

10

A8

40

BF

00

21

—

00

—

00

—

0E

—

00

—

R

3C5 82-80 W1 U FB Start Address

3C5 85-83 W1 V FB Start Address

—

RW

R

A

B

C

D

E

F

—

3C5 88-86 W2 FB Start Address

3C5 8A-89 W2 H Scaling Factor

3C5 8C-8B W2 V Scaling Factor

3C5 90-8D W2 Live Video Start

3C5 94-91 W2 Live Video End

—

00

RW

Version/Old-New Mode Ctrl

Configuration Port 1

Configuration Port 2

Old Mode Control 2

New Mode Control 2

Old Mode Control 1

New Mode Control 1

Power-up Mode 2

RW

—

RW

—

3C5

95 W2 Live Vid Line Buf Level

3C5

96 New Live Video Win Ctrl 0

97 New Live Video Win Ctrl 1

98 New Live Video Win Ctrl 2

99 New Live Video Win Ctrl 3

10 VESA™ Big BIOS Control

11 Protection

12 Threshold

3C5 9B-9A Vid Row Byte Off. (W1-UV)

3C5 9D-9C Vid Row Byte Offset (W2-Y)

—

RW

3C5 13-17 -reserved-

3C5

9E Line Buf Req Threshold

9F VBI Control

00

—

00

—

00

—

RW

—

RW

—

RW

—

3C5

18 VCLK1 Frequency Control 0

19 VCLK1 Frequency Control 1

1A VCLK2 Frequency Control 0

1B VCLK2 Frequency Control 1

3C5 A3-A0 VBI Frame Buffer Address

3C5 A7-A4 VBI Capture Start

3C5 AB-A8 VBI Capture End

3C5 AD-AC VBI V Interrupt Position

3C5 AF-AE Capture Row Byte Offset

3C5 B1-B0 Window 1 HSB Control

3C5 B3-B2 Window 2 HSB Control

3C5 B6-B4 2^ndDisplay Addr Select

3C5 1C-1F -reserved-

3C5

3C5 23-22 Signature Data

3C5

3C5 26-36 -reserved-

3C5

3C5 39-4F -reserved-

3C5 52-50 Playback Color Key Data

3C5

3C5 56-54 Playback Color Key Mask

3C5 57 Playback Vid Key Mode

3C5 58-59 -reserved-

20 Clock Syn / RAMDAC Setup

21 Signature Control

RW

R

RW

R

24 Power Management Ctrl

25 Monitor Sense

3C5

B7 Video Sharpness

—

3C5 BA-B8 2^ndCapture Addr Select

37 Video Key Mode

38 Feature Connector Control

RW

—

RW

—

RW

—

RW

—

3C5

BB -reserved-

BC Contrast Control

BD Dual View MUX Control

BE Miscellaneous Control Bits

—

53 -reserved-

3C5 BF-CD -reserved-

3C5

CE Window 2 Live Video Ctrl

CF -reserved-

3C5 D1-D0 Row Byte Offset (W2-UV)

3C5 D4-D2 W2 U-Frame Start Address

3C5 D7-D5 W2 V-Frame Start Address

3C5 D9-D8 Digital TV Interface Control

3C5 DB-DA W2 V Count Status

RW

R

RW

R

3C5 5A-5F Scratch Pad 0-5

3C5 62-60 2^ndPlayback Color Key Data

3C5

63 -reserved-

3C5 66-64 2^ndPlayback ColorKey Mask

3C5 67-7F -reserved-

—

RW

—

3C5 DD-DC Dual View Control

3C5 DF-DE W1 V Count Status

Port Index Reserved Registers

3C5 E0-FF -reserved-

Default Acc

RW

—

Revision 1.3 September 8, 1999

-29-

Register Summary Tables

VT8601 Apollo ProMedia

Extended Registers – VGA Graphics Controller Indexed

Port Index Extd Graphics Ctrlr Regs Default Acc

3CE/F

E

F

Old / New Src Segment Addr

Misc Extended Function Ctrl

00

—

RW

—

3CE/F 10-1F -reserved-

3CE/F 20-2F Power Management Regs

20 Standby Timer Control

21 Power Management Control 1

22 Power Management Control 2

23 Power Status

0xxx0000b RW

00

—

E0

FF

00

0000

—

RW

—

24 Soft Power Control

25 Power Control Select

26 DPMS Control

28-27 GPIO Control

29 -reserved-

2A Suspend Pin Timer

2B -reserved-

00

—

RW

—

2C Miscellaneous Pin Control

2D-2E -reserved-

00

—

RW

—

2F Miscellaneous Internal Ctrl

00

RW

3CE/F 30-5A -reserved-

3CE/F 5A-5F Scratch Pad 0-5

3CE/F 60-7F -reserved-

—

RW

—

Revision 1.3 September 8, 1999

-30-

Register Summary Tables

VT8601 Apollo ProMedia

Extended Registers – VGA CRT Controller Indexed

Port Index Extended CRTC Registers Default Acc

Port Index Extended CRTC Registers

Default Acc

3x5

0E CRT Module Test

00

RW

3x5 80-BF Video / Capture Engine

81-80 Horiz Scaling Factor (W1)

83-82 Vert Scaling Factor (W1)

85-84 -reserved-

3x5

19 CRT Interlace Control

1A Arbitration Control 1

1B Arbitration Control 2

1C Arbitration Control 3

—

00

—

00

—

0F

—

00

—

00

10

00

—

00

—

03

—

0000

00

82

00

RW

—

RW

RO

—

RO

RW

—

RW

—

RW

—

RW

—

RW

—

RW

—

RW

—

RW

89-86 Video Window Start (W1)

8D-8A Video Window End

8F-8E Video Display Engine Flag

91-90 Row Byte Offset (W1, W1-Y)

94-92 Vid Start Addr (W1-Y or W1)

95 Vid Win Line Buffer Thresh

96 Line Buf Lev Ctl (W1-Y, W1)

97 Video Display Engine Flag

9A-98 Capture Video Start Address

9B Video Display Status

3x5 1D-1E -reserved-

3x5

1F Software Programming

20 Command FIFO

21 Linear Addressing

22 CPU Latch Readback

23 -reserved-

24 VGA Attribute State

25 RAMDAC RW Timing

26 -reserved-

27 CRT High Order Start

28 -reserved-

29 RAMDAC Mode

2A In terface Select

2B Horiz. Parameter Overflow

2C -reserved-

—

RW

—

9C Capture Control 1

9D Capture Control 2

9E Capture Control 3

9F Capture Control 4

A1-A0 Capture Vertical Total

A3-A2 Capture Horizontal Total

A5-A4 Capture Vertical Start

A7-A6 Capture Vertical End

A9-A8 Capture Horizontal Start

AB- Capture Horizontal End

AC Capture Vert Sync Pulse

AD Capture Horiz Sync Pulse

AE Capture CRTC Control

AF Capture CRTC Control

B1-B0 Capture Horiz Minify Factor

B3-B2 Capture Vert Minify Factor

B5-B4 DST Pixel Width Count

B7-B6 DST Pixel Height Count

B8 Capture FIFO Control 1

B9 Capture FIFO Control 2

BB- Chromakey Comp Data 0 Lo

BD- Chromakey Comp Data 0 Hi

BE Capture Control

2D GE Timing Control

2E -reserved-

2F Performance Tuning

3x5 30-33 -reserved-

3x5 35-34 GE IO Linear Address Base

3x5

36 Graphics / Video Engine Ctrl

37 I²C Control

38 Pixel Bus Mode

39 PCI Interface Control

3A Physical Address Control

3B Clock and Tuning

3C Misc Control

0000000nb RW

00 RW

0n000001b RW

00

—

RW

—

3x5 3D-3F -reserved-

3x5 40-50 Hardware Cursor Registers

43-40 HW Cursor Position

45-44 HW Cursor Pattern Location

47-46 HW Cursor Offset

—

RW

4F-48 HW Cursor Color

50 HW Cursor Control

51 Bus Grant Termination Ctrl

52 Shared Frame Buffer Ctrl

BF Display Engine Flag 4

3x5 C0-CF -reserved-

3x5 D3-D0 VGA / Digital TV Sync Ctrl 1

3x5 D4-FF -reserved-

3x5

RW

—

000x0010b RW

3x5 53-54 -reserved-

—

0F

00

—

RW

—

3x5

55 PCI Retry Control

56 Display Pre-end Control

57 Display Pre-end Fetch Param.

Extended Registers – CRTC Shadow

Port Index CRTC Shadow Registers

Default Acc

3x5

00 Horizontal Total

—

RW

3x5 58-5D -reserved-

3x5

03 Horizontal Blanking End

04 Hoprizontal Retrace Start

05 Horizontal Retrace End

06 Vertical Total

5E Capture / ZV Port Control

5F Test Control

x0000000b RW

00

—

04

00

—

RW

—

RW

—

3x5 60-61 -reserved-

3x5

62 Enhancement 0

63 Enhancement 1

64 DPA Extra

07 Overflow

10 Vertical Retrace Start

11 Vertical Retrace End

16 Vertical Blanking End

3x5 65-7F -reserved-

Revision 1.3 September 8, 1999

-31-

Register Summary Tables

VT8601 Apollo ProMedia

3D Graphics Engine Registers

These registers are addressed at offsets from the Graphics

Engine Base Address (GEbase). All registers are 32-bit.

Offset Span Engine Registers

3-0 Parameter Source 1

7-4 Parameter Source 2

Default Acc

Offset Texture Engine Registers

A3-A0 Texture Control

A7-A4 Texture Color

AB-A8 Palette Data

AF-AC Texture Boundary

Offset Command List Control Registers

B3-B0 -reserved-

B7-B4 -reserved-

Offset Memory Interface Registers

BB-B8 Destination Stride & Buffer 0

BF-BC Destination Stride & Buffer 1

C3-C0 Destination Stride & Buffer 2

C7-C4 Destination Stride & Buffer 3

CB-C8 Source Stride & Buffer 0

CF-CC Source Stride & Buffer 1

D3-D0 Source Stride & Buffer 2

D7-D4 Source Stride & Buffer 3

DB-D8 Z Depth & Buffer

DF-DC Texture Base Level 0 (1:1 Map)

E3-E0 Texture Base Level 1

E7-E4 Texture Base Level 2

EB-E8 Texture Base Level 3

EF-EC Texture Base Level 4

F3-F0 Texture Base Level 5

F7-F4 Texture Base Level 6

FB-F8 Texture Base Level 7

FF-FC Texture Base Level 8 (mallest)

Offset Data Port Area

Default Acc

—

RW

—

RW

W

B-8 Parameter Destination 1

F-C Parameter Destination 2

Offset VGA Core Registers

13-10 Right View Display Base Addresses

17-14 Left View Display Base Addresses

1B-18 Block Write Start Address

1F-1C Block Write Area / End Address

23-20 GE Status

27-24 GE Control

2B-28 GE Debug

2F-2C Wait Mask

Offset Rasterization & Setup Engine Regs Default Acc

33-30 Primitive Attribute

37-34 -reserved-

3B-38 -reserved-

3F-3C Primitive Type

3F-3C Setup Engine Status

Offset Pixel Engine Registers

43-40 -reserved-

47-44 Drawing Command

4B-48 Raster Operation (ROP)

4F-4C Z-Function

53-50 Texture Function

57-54 Clipping Window 0

5B-58 Clipping Window 1

5F-5C -reserved-

63-60 Color 0

67-64 Color 1

RW

Default Acc

—

RW

R

W

R

RW

—

Default Acc

—

RW

—

RW

—

W

R

Default Acc

—

RW

—

RW

—

Default Acc

1xxxx Data Port Area

—

6B-68 Color Key

6F-6C Pattern and Style

73-70 Pattern Color

77-74 Pattern Foreground Color

7B-78 Pattern Background Color

7F-7C Alpha

83-80 Alpha Function

87-84 Bit Mask

8B-88 -reserved-

8F-8C -reserved-

93-90 -reserved-

97-94 -reserved-

9B-98 -reserved-

—

9F-9C -reserved-

—

Revision 1.3 September 8, 1999

-32-

Register Summary Tables

VT8601 Apollo ProMedia

Miscellaneous I/O

Configuration Space I/O

One I/O port is defined in the ProMedia: Port 22.

All registers in the ProMedia (listed above) are addressed via

the following configuration mechanism:

Port 22 – PCI /AGP Arbiter Disable ...............................RW

........................................ always reads 0

7-2 Reserved

Mechanism #1

1

AGP Arbiter Disable

These ports respond only to double-word accesses. Byte or

word accesses will be passed on unchanged.

0

Respond to GREQ# signal .....................default

1

Do not respond to GREQ# signal

0

PCI Arbiter Disable

Port CFB-CF8 - Configuration Address......................... RW

31 Configuration Space Enable

0

Respond to all REQ# signals..................default

1

Do not respond to any REQ# signals, including

PREQ#

0

1

Disabled................................................. default

Convert configuration data port writes to

configuration cycles on the PCI bus

This port can be enabled for read/write access by setting bit-7

of Device 0 Configuration Register 78.

........................................always reads 0

30-24 Reserved

23-16 PCI Bus Number

Used to choose a specific PCI bus in the system

15-11 Device Number

Used to choose a specific device in the system

(devices 0 and 1 are defined)

10-8 Function Number

Used to choose a specific function if the selected

device supports multiple functions (only function 0 is

defined).

7-2 Register Number (also called the "Offset")

Used to select

a

specific DWORD in the

configuration space

........................................always reads 0

1-0 Fixed

Port CFF-CFC - Configuration Data.............................. RW

Refer to PCI Bus Specification Version 2.2 for further details

on operation of the above configuration registers.

Revision 1.3 September 8, 1999

-33-

Register Summary Tables

VT8601 Apollo ProMedia

Device 0 Offset 7-6 - Status........................................... RWC

15 Detected Parity Error

Register Descriptions

Device 0 Bus 0 Header Registers - Host Bridge

0

1

No parity error detected......................... default

Error detected in either address or data phase.

This bit is set even if error response is disabled

(command register bit-6). ......write one to clear

All registers are located in PCI configuration space. They

should be programmed using PCI configuration mechanism 1

through CF8 / CFC with bus number, function number, and

device number equal to zero.

14 Signaled System Error (SERR# Asserted)

........................................always reads 0

13 Signaled Master Abort

Device 0 Offset 1-0 - Vendor ID........................................RO

0

1

No abort received .................................. default

Transaction aborted by the master ...................

....................................write one to clear

(reads 1106h to identify VIA Technologies)

15-0 ID Code

Device 0 Offset 3-2 - Device ID..........................................RO

(reads 0601h to identify the VT8601)

15-0 ID Code

Device 0 Offset 5-4 - Command........................................RW

........................................ always reads 0

12 Received Target Abort

0

1

No abort received .................................. default

Transaction aborted by the target......................

....................................... write 1 to clear

........................always reads 0

Target Abort never signaled

15-10 Reserved

........................RO

Fast back-to-back transactions only allowed to

the same agent ........................................default

Fast back-to-back transactions allowed to

different agents

9

Fast Back-to-Back Cycle Enable

11 Signaled Target Abort

0

10-9 DEVSEL# Timing

00 Fast

1

01 Medium....................................always reads 01

10 Slow

......................................................RO

8

SERR# Enable

0

1

SERR# driver disabled...........................default

SERR# driver enabled

11 Reserved

Data Parity Error Detected

8

(SERR# is used to report parity errors if bit-6 is set).

......................................RO

Address / Data Stepping

0

1

No data parity error detected ................. default

Error detected in data phase. Set only if error

response enabled via command bit-6 = 1 and

VT8601 was initiator of the operation in which

the error occurred. .................write one to clear

7

6

5

4

3

2

1

0

1

Device never does stepping....................default

Device always does stepping

........................................

Parity Error Response

RW

0

1

Ignore parity errors & continue..............default

Take normal action on detected parity errors

..............................................RO

Treat palette accesses normally..............default

Don’t respond to palette accesses on PCI bus

...............always reads 1

7

6

5

4

Fast Back-to-Back Capable

........................................always reads 0

Reserved

VGA Palette Snoop

..................................always reads 0

66MHz Capable

Supports New Capability list

0

1

.............always reads 1

........................................always reads 0

3-0 Reserved

..........RO

Memory Write and Invalidate Command

Device 0 Offset 8 - Revision ID......................................... RO

7-0 VT8601 Chip Revision Code

0

1

Bus masters must use Mem Write ..........default

Bus masters may generate Mem Write & Inval

....................................RO

Special Cycle Monitoring

Device 0 Offset 9 - Programming Interface..................... RO

0

1

Does not monitor special cycles.............default

Monitors special cycles

..........................................................RO

Never behaves as a bus master

Can behave as a bus master....................default

......................................................RO

Does not respond to memory space

Responds to memory space ....................default

...........................always reads 00

7-0 Interface Identifier

Bus Master

Device 0 Offset A - Sub Class Code.................................. RO

0

1

7-0 Sub Class Code .......reads 00 to indicate Host Bridge

Memory Space

Device 0 Offset B - Base Class Code................................. RO

0

1

7-0 Base Class Code.. reads 06 to indicate Bridge Device

..........................................................RO

Does not respond to I/O space ...............default

Responds to I/O space

I/O Space

Device 0 Offset D - Latency Timer.................................. RW

0

1

Specifies the latency timer value in PCI bus clocks.

7-3 Guaranteed Time Slice for CPU................default=0

2-0 Reserved (fixed granularity of 8 clks) .. always read 0

Bits 2-1 are writeable but read 0 for PCI specification

compatibility. The programmed value may be read

back in Offset 75 bits 5-4 (PCI Arbitration 1).

Revision 1.3 September 8, 1999

-34-

Device 0 Bus 0 Header Registers - Host Bridge

VT8601 Apollo ProMedia

Device 0 Offset E - Header Type.......................................RO

Device 0 Offset 2D-2C – Subsystem Vendor ID ............. RW

7-0 Header Type Code ............reads 00: single function

15-0 Subsystem Vendor ID.........................default = 0000

Device 0 Offset F - Built In Self Test (BIST)....................RO

Device 0 Offset 2F-2E – Subsystem ID............................ RW

7

BIST Supported ......reads 0: no supported functions

15-0 Subsystem ID ......................................default = 0000

6-0 Reserved

........................................ always reads 0

Device 0 Offset 37-34 - Capability Pointer ...................... RO

Device 0 Offset 13-10 - Graphics Aperture Base............RW

Contains an offset from the start of configuration space.

31-28 Upper Programmable Base Address Bits....... def=0

27-20 Lower Programmable Base Address Bits ...... def=0

These bits behave as if hardwired to 0 if the

corresponding Graphics Aperture Size register bit

(Device 1 Offset 84h) is 0.

31-0 AGP Capability List Pointer ........ always reads A0h

27 26 25 24 23 22 21 20 (This Register)

7

6

5

4

3

2

1

0

(Gr Aper Size)

RW RW RW RW RW RW RW RW 1M

RW RW RW RW RW RW RW 0

2M

RW RW RW RW RW RW 0

0

4M

8M

RW RW RW RW RW 0

0

RW RW RW RW 0

0

16M

32M

64M

128M

256M

RW RW RW 0

0

RW RW 0

0

RW 0

0

19-0 Reserved

................................ always reads 00008

Note: The locations in the address range defined by this

register are prefetchable.

Revision 1.3 September 8, 1999

-35-

Device 0 Bus 0 Header Registers - Host Bridge

VT8601 Apollo ProMedia

Device 0 Bus 0 Host Bridge Registers

CPU Interface Control

Device 0 Offset 51 – Response Phase Control (00h)....... RW

Device 0 Offset 50 – Request Phase Control (00h) .........RW

7

CPU Read DRAM 0WS for Back-to-Back Read

Transactions

7

CPU Hardwired IOQ (In Order Queue) Size

Default per strap on pin MA11 during reset. This

register bit can be written to 0 to restrict the chip to

one level of IOQ.

0

1

Disable................................................... default

Enable

Setting this bit enables maximum read performance

by allowing continuous 0-wait-state reads for

pipelined line reads. If this bit is not set, there will be

at least 1T idle time between read transactions.

CPU Write DRAM 0WS for Back-to-Back Write

Transactions

0

1

1-Level

4-Level ....... default if no external strap resistor

6

Read-Around-Write

0

1

Disable ...................................................default

Enable

6

5

4

Reserved

........................................ always reads 0

Defer Retry When HLOCK Active

0

1

Disable................................................... default

Enable

0

1

Disable ...................................................default

Enable

Setting this bit enables maximum write performance

by allowing continuous 0-wait-state writes for

pipelined line writes ands sustained 3T single writes.

If this bit is not set, there will be at least 1T idle time

between write transactions.

Note: always set this bit to 1

3-2 Reserved

........................................ always reads 0

1

Fast Speculative Read

0

1

Disable ...................................................default

Enable

5

4

3

2

1

0

DRAM Read Request Rate

0

1

3T

2T

.................................................... default

0

CPU / PCI Master Read DRAM Timing

0

1

Start DRAM read after snoop complete ...... def

Start DRAM read before snoop complete

Fast Response (HIT/HITM Sampled 1T Earlier)

0

1

Disable................................................... default

Enable

Non-Posted IOW

0

1

Disable................................................... default

Enable

CPU Read DRAM Prefetch Buffer Depth

0

1

1-level prefetch buffer ........................... default

4-level prefetch buffer

CPU-to-DRAM Post-Write Buffer Depth

0

1

1-level post-write buffer ........................ default

4-level post-write buffer

Concurrent PCI Master / Host Operation

0

1

Disable – the CPU bus will be occupied (BPRI

asserted) during the entire PCI operation.....def

Enable – the CPU bus is only requested before

ADS# assertion

Revision 1.3 September 8, 1999

-36-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 0 Offset 52 – Dynamic Defer Timer (10h)...........RW

Device 0 Offset 53 – Miscellaneous (00h)........................ RW

7

GTL I/O Buffer Pullup...........default = MA13 Strap

7

HREQ Function

0

1

Disable................................................... default

Enable

0

1

Disable

Enable

The default value of this bit is determined by a strap

on the MA13 pin during reset.

RAW Write Retire After 2 Writes

6

DRAM Frequency Higher Than CPU FSB

0

1

Disable................................................... default

Enable

6

5

Setting this bit enables the DRAM subsystem to run at

a higher frequency than the CPU FSB frequency.

When setting this bit, register bit Rx69[6] must also be

set and only SDRAM memory type DIMM modules

may be installed. An EDO / SDRAM mix in the

DRAM subsystem is not supported in this case.

AGP/PCI-to-CPU Master / CPU-to-PCI Slave

Concurrency

0

1

Disable ...................................................default

Enable

Reserved

........................................ always reads 0

4-0 Snoop Stall Count

00 Disable dynamic defer

01-1F Snoop stall count ........................ default = 10h

5

0

1

Disable................................................... default

Enable

4

3

2

HPRI Function

0

1

Disable................................................... default

Enable

P6Lock Function

0

1

Disable................................................... default

Enable

P6Lock

0

1

Disable................................................... default

Enable

1-0 Reserved

........................................always reads 0

Revision 1.3 September 8, 1999

-37-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 0 Offset 55-54 - Non-Cacheable Region #1 .........RW

DRAM Control

15-3 Base Address - A<28:16>........................... default=0

As noted below, the base address must be a multiple

of the region size.

These registers are normally set at system initialization time

and not accessed after that during normal system operation.

Some of these registers, however, may need to be

programmed using specific sequences during power-up

initialization to properly detect the type and size of installed

memory (refer to the VIA Technologies VT8601 BIOS

porting guide for details).

2-0 Range (Region Size)

000 Disable ...................................................default

001 64K

010 128K (Base Address A16 must be 0)

011 256K (Base Address A16-17 must be 0)

100 512K (Base Address A16-18 must be 0)

101 1M (Base Address A16-19 must be 0)

110 2M (Base Address A16-20 must be 0)

111 4M (Base Address A16-21 must be 0)

Table 3. System Memory Map

Space Start Size

Address Range

Comment

DOS 640K 00000000-0009FFFF Cacheable

0

VGA 640K 128K 000A0000-000BFFFF Used for SMM

BIOS 768K 16K 000C0000-000C3FFF Shadow Ctrl 1

BIOS 784K 16K 000C4000-000C7FFF Shadow Ctrl 1

BIOS 800K 16K 000C8000-000CBFFF Shadow Ctrl 1

BIOS 816K 16K 000CC000-000CFFFF Shadow Ctrl 1

BIOS 832K 16K 000D0000-000D3FFF Shadow Ctrl 2

BIOS 848K 16K 000D4000-000D7FFF Shadow Ctrl 2

BIOS 864K 16K 000D8000-000DBFFF Shadow Ctrl 2

BIOS 880K 16K 000DC000-000DFFFF Shadow Ctrl 2

BIOS 896K 64K 000E0000-000EFFFF Shadow Ctrl 3

BIOS 960K 64K 000F0000-000FFFFF Shadow Ctrl 3

Device 0 Offset 57-56 - Non-Cacheable Region #2 .........RW

15-3 Base Address MSBs - A<28:16>................ default=0

As noted below, the base address must be a multiple

of the region size.

2-0 Range (Region Size)

000 Disable ...................................................default

001 64K

010 128K (Base Address A16 must be 0)

011 256K (Base Address A16-17 must be 0)

100 512K (Base Address A16-18 must be 0)

101 1M (Base Address A16-19 must be 0)

110 2M (Base Address A16-20 must be 0)

111 4M (Base Address A16-21 must be 0)

Sys

Bus D Top

1MB

—

00100000-DRAM Top Can have hole

DRAM Top-FFFEFFFF

Init 4G-64K 64K FFFEFFFF-FFFFFFFF 000Fxxxx alias

Revision 1.3 September 8, 1999

-38-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 0 Offset 59-58 - DRAM MA Map Type...............RW

Device 0 Offset 60 – DRAM Type ................................... RW

15-13 Bank 5/4 MA Map Type (EDO/FPG)

000 8-bit Column Address

7-6 Reserved

........................................always reads 0

5-4 DRAM Type for Bank 5/4

00 Fast Page Mode DRAM (FPG).............. default

01 EDO DRAM (EDO)

001 9-bit Column Address

010 10-bit Column Address ..........................default

011 11-bit Column Address

10 Reserved

100 12-bit Column Address (64Mb)

101 Reserved

11x Reserved

11 SDRAM

3-2 DRAM Type for Bank 3/2.....................default=FPG

1-0 DRAM Type for Bank 1/0.....................default=FPG

Bank 5/4 MA Map Type (SDRAM)

0xx 16Mb SDRAM.......................................default

100 64/128Mb SDRAM (x4, x8, x16, 4-bank x32)

101 64Mb VC SDRAM(x4)

Table 4. Memory Address Mapping Table

EDO/FP DRAM

110 64/128Mb VC SDRAM (8Mx8 or 8Mx16)

111 128Mb VC SDRAM (16Mx8)

12 Bank 5/4 Virtual Channel Enable............. default=0

MA: 13 12 11 10

9

8

7

6

5

4

3

2

1

0

8-bit Col

(000)

9-bit Col

(001)

10-bit Col

(010)

11-bit Col

(011)

23 22 21 11 20 19 18 17 16 15 14 13 12 Row Bits

10 3 Col Bits

24 23 22 21 20 19 18 17 16 15 14 13 12 Row Bits

11 10 3 Col Bits

25 24 23 21 20 19 18 17 16 15 14 13 12 Row Bits

22 11 10 3 Col Bits

26 25 23 21 20 19 18 17 16 15 14 13 12 Row Bits

24 22 11 10 3 Col Bits

27 25 23 21 20 19 18 17 16 15 14 13 12 Row Bits

9

8

7

6

5

4

11-8 Reserved

........................................ always reads 0

9

8

7

6

5

4

7-5 Bank 1/0 MA Map Type (see above)

Bank 1/0 Virtual Channel Enable............. default=0

9

8

7

6

5

4

9

8

7

6

5

4

3-1 Bank 3/2 MA Map Type (see above)

Bank 3/2 Virtual Channel Enable............. default=0

12-bit Col

(100)

0

26 24 22 11 10

9

8

7

6

5

4

3 Col Bits

SDRAM

MA: 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Device 0 Offset 5A-5F – DRAM Row Ending Address:

All of the registers in this group default to 01h:

16Mb (0xx)

22 21 20 19 18 17 16 15 14 13 12 Row Bits

PC

11

24 23 10

9

8

7

6

5

4

3 Col Bits

64Mb (100) 24 13 12 22 21 20 19 18 17 16 15 14 11 23 x4: 10 col

PC

2/4 bank

x4, x8, x16;

4-bank x32

13 12

26 25 10

9

8

7

6

5

4

3 x8: 9 col

x16: 8 col

x32: 8 col

24

Offset 5A – Bank 0 Ending (HA[30:23]) ....................RW

Offset 5B – Bank 1 Ending (HA[30:23]).....................RW

Offset 5C – Bank 2 Ending (HA[30:23]) ....................RW

Offset 5D – Bank 3 Ending (HA[30:23]) ....................RW

Offset 5E – Bank 4 Ending (HA[30:23]).....................RW

Offset 5F – Bank 5 Ending (HA[30:23]).....................RW

VC SDRAM

Segment address {HA9,HA10,HA25,HA26} depends on VC

SDRAM configurations.

MA: 13 12 11 10 9

8 7 6 5 4 3 2 1 0

24 13 12 22 21 20 19 18 17 16 15 14 11 23

64M

VC SDRAM

(101) 6-bit Cola

2-bank

64M/128M

VC SDRAM

(110) 7-bit Cola

2-bank

64M: 4Mx16

(13x6)

PC

24 13 12

26 25 10 9 8 7 6 5 4 3

Note :BIOS is required to fill the ending address registers

for all banks even if no memory is populated. The

endings have to be in incremental order.

64M: 8Mx8

(13x7)

24 13 12 22 21 20 19 18 17 16 15 14 11 23

PC

128M: 8Mx16

(13x7)

24 13 12

26 25 10 9 8 7 6 5 4 3

128M

128M: 16Mx8

(13x8)

24 13 12 22 21 20 19 18 17 16 15 14 11 23

VC SDRAM

(111) 8-bit Cola

2-bank

PC

24 13 12

26 25 10 9

8 7 6 5 4 3

"PC" = "Precharge Control" (refer to SDRAM specifications)

16Mb 11x10, 11x9, and 11x8 configurations supported

64Mb x4: 12x10 4bank, 13x10 2bank

x8: 12x9 4bank, 13x9 2bank

x16: 12x8 4bank, 13x8 2bank

x32: 11x8 4bank

128Mb same as 64Mb

Revision 1.3 September 8, 1999

-39-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 0 Offset 61 - Shadow RAM Control 1 .................RW

7-6 CC000h-CFFFFh

Device 0 Offset 63 - Shadow RAM Control 3................. RW

7-6 E0000h-EFFFFh

00 Read/write disable..................................default

01 Write enable

10 Read enable

00 Read/write disable ................................. default

01 Write enable

10 Read enable

11 Read/write enable

5-4 C8000h-CBFFFh

5-4 F0000h-FFFFFh

00 Read/write disable..................................default

01 Write enable

10 Read enable

00 Read/write disable ................................. default

01 Write enable

10 Read enable

11 Read/write enable

3-2 C4000h-C7FFFh

3-2 Memory Hole

00 Read/write disable..................................default

01 Write enable

10 Read enable

00 None .................................................... default

01 512K-640K

10 15M-16M (1M)

11 Read/write enable

11 14M-16M (2M)

1-0 C0000h-C3FFFh

1-0 SMI Mapping Control

00 Disable SMI Address Redirection ......... default

01 Allow access to DRAM Axxxx-Bxxxx for both

normal and SMI cycles

00 Read/write disable..................................default

01 Write enable

10 Read enable

11 Read/write enable

10 Reserved

11 Allow SMI Axxxx-Bxxxx DRAM access

Device 0 Offset 62 - Shadow RAM Control 2 .................RW

Note: The A0000-BFFFF address range is reserved

for use by VGA controllers for system access to the

VGA frame buffer. Since frame buffer accesses are

normally directed to the system VGA controller (with

its separate memory subsystem), system DRAM

locations in the A0000-BFFFF range would normally

be unused. Setting the above bits appropriately

allows this block of system memory to be used by

directing Axxxx-Bxxxx accesses to corresponding

memory addresses in system DRAM instead of

directing those accesses to the PCI bus for VGA

frame buffer access.

7-6 DC000h-DFFFFh

00 Read/write disable..................................default

01 Write enable

10 Read enable

11 Read/write enable

5-4 D8000h-DBFFFh

00 Read/write disable..................................default

01 Write enable

10 Read enable

11 Read/write enable

3-2 D4000h-D7FFFh

00 Read/write disable..................................default

01 Write enable

10 Read enable

11 Read/write enable

1-0 D0000h-D3FFFh

00 Read/write disable..................................default

01 Write enable

10 Read enable

11 Read/write enable

Revision 1.3 September 8, 1999

-40-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 0 Offset 64 - DRAM Timing for Banks 0,1 .........RW

Device 0 Offset 65 - DRAM Timing for Banks 2,3 .........RW

Device 0 Offset 66 - DRAM Timing for Banks 4,5 .........RW

FPG / EDO Settings for Registers 64-66

Device 0 Offset 68 - DRAM Control ............................... RW

7

RAS Precharge Time

7

SDRAM Open Page Control

0

1

3T

4T

0

Always precharge SDRAM banks when

accessing EDO/FPG DRAMs................ default

SDRAM banks remain active when accessing

EDO/FPG banks

.....................................................default

6

RAS Pulse Width

1

0

1

4T

5T

.....................................................default

6

5

4

3

Bank Page Control

5-4 CAS Read Pulse Width

0

1

Allow only pages of the same bank active...def

Allow pages of different banks to be active

00 1T

01 2T

10 3T

EDO Pipeline Burst Rate

.....................................................default

0

1

X-2-2-2-2-2-2-2 ..................................... default

X-2-2-2-3-2-2-2

11 4T

Note: EDO will not automatically reduce the CAS

pulse width. For EDO type DRAMs, use 00 if CAS

width = 1 is to be used.

DRAM Data Latch Delay for EDO/FPG DRAM

0

1

Latch DRAM data at CCLK rising edge.....def.

Delay latch of DRAM data by ½ CCLK

3

2

1

0

CAS Write Pulse Width

EDO Test Mode

0

1

1T

2T

0

1

Disable................................................... default

Enable

.....................................................default

MA-to-CAS Delay

Note: MD0 is internally pulled up for EDO detection.

Burst Refresh

0

1

1T

2T

2

.....................................................default

0

1

Disable................................................... default

Enable (burst 4 times)

RAS to MA Delay

0

1

1T

2T

.....................................................default

........................................ always reads 0

1-0 System Frequency Divider...................................RO

00 CPU/PCI Frequency Ratio = 2x

01 CPU/PCI Frequency Ratio = 3x

(66 MHz)

(100 MHz)

Reserved

10 CPU/PCI Frequency Ratio Auto Detect

11 CPU/PCI Frequency Ratio = 4x

These bits are latched from MA[14, 12] at the rising

(133 MHz)

SDRAM Settings for Registers 64-66

7

Precharge Command to Active Command Period

edge of RESET#.

Without external strapping

0

1

T

^RP= 2T

resistors, the default setting of these bits is 00 (66

MHz).

T^RP= 3T ................................................default

6

Active Command to Precharge Command Period

0

1

T

^RAS= 5T

T^RAS= 6T ..............................................default

5-4 CAS Latency

00 1T

01 2T

10 3T

.....................................................default

11 Reserved

3

2

Reserved (Do Not Program).................... default = 0

ACTIVE Command to CMD Command Period

0

1

2T

3T

.....................................................default

1-0 Bank Interleave

00 No Interleave..........................................default

01 2-way

10 4-way

11 Reserved

Revision 1.3 September 8, 1999

-41-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 0 Offset 69 – DRAM Clock Select (00h)..............RW

Device 0 Offset 6A - Refresh Counter............................. RW

7-6 DRAM Operating Frequency Select ................. RW

7-0 Refresh Counter (in units of 16 CPUCLKs)

00 DRAM Refresh Disabled....................... default

01 32 CPUCLKs

Rx68[1-0] Rx69[7-6] CPU/DRAM

00

01

10

00

01

00

10

01

00

10

66/66

(default)

66/100

100/100

100/66

100/133

133/133

133/100

02 48 CPUCLKs

03 64 CPUCLKs

04 80 CPUCLKs

05 96 CPUCLKs

… …

The programmed value is the desired number of 16-

CPUCLK units minus one.

5

4

3

2

1

0

256M bit DRAM Support

0

1

Disable ...................................................default

Enable (DCLKRD becomes output)

DRAM Controller Command Register Output

Device 0 Offset 6B - DRAM Arbitration Control (01h) RW

0

1

Disable ...................................................default

Enable

7-6 Arbitration Parking Policy

00 Park at last bus owner............................ default

01 Park at CPU side

Fast DRAM Precharge for Different Bank

0

1

Disable ...................................................default

Enable

10 Park at AGP side

11 Reserved

DRAM 4K Pages (for 64Mbit DRAM)

0

1

Disable ...................................................default

Enable

5

4

Fast Read to Write Turnaround

0

1

Disable................................................... default

Enable

Registered DIMM Support

0

1

Disable ...................................................default

Enable

Memory Module Configuration..........................RO

0

1

Normal Operation.................................. default

Unused Outputs Tristated (RASB#, CASB#,

CKE, MAB, DCLKO)

Reserved

........................................ always reads 0

This bit is latched from MAB7# at the rising edge of

RESET#.

3

2

1

0

MD Bus Second Level Strength Control

0

1

Normal slew rate control........................ default

More slew rate control

CAS Second Level Strength Control

0

1

Normal slew rate control........................ default

More slew rate control

Virtual Channel-SDRAM

0

1

Disable................................................... default

Enable

Multi-Page Open

0

Disable (page registers marked invalid and no

page register update which causes non page-

mode operation)

1

Enable.................................................... default

Revision 1.3 September 8, 1999

-42-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 0 Offset 6C - SDRAM Control.............................RW

Device 0 Offset 6D - DRAM Drive Strength................... RW

7-5 Reserved

4

........................................ always reads 0

CKE Configuration

7

Reserved

........................................always reads 0

6-5 Delay DRAM Read Latch

0

Rx6B[4]=0 RASA = CSA, RASB = CSB,

CKE0=CKE0, CKE1 = CKE1

Rx6B[4]=1 RASA = CSA, RASB = Float,

CASB = Float, MAB = Float,

CKE0 = CKE0, CKE1 = CKE0

Rx6B[4]=0 RASA = CSA, RASB = CSB,

CKE3-2 = CSA7-6

00 Disable................................................... default

01 0.5 ns

10 1.0 ns

11 1.5 ns

x

4

3

MD Drive

1

0

1

6 mA .................................................... default

8 mA

CKE5-4 = CSB7-6

SDRAM Command Drive Strength

(SRAS#, SCAS#, SWE#)

CKE1 = GCKE (Global CKE)

CKE0 = FENA (FET Enable)

Fast AGP TLB lookup

0

1

16mA .................................................... default

24mA

3

0

1

Disable ...................................................default

Reduce the lookup time from 4T to 2T

2

1

0

MA[2:13] / WE# Drive Strength

0

1

16mA .................................................... default

24mA

2-0 SDRAM Operation Mode Select

000 Normal SDRAM Mode ..........................default

001 NOP Command Enable

CAS# Drive Strength

0

1

8 mA .................................................... default

12 mA

010 All-Banks-Precharge Command Enable

(CPU-to-DRAM cycles are converted

to All-Banks-Precharge commands).

011 MSR Enable

RAS# Drive Strength

0

1

16mA .................................................... default

24mA

CPU-to-DRAM cycles are converted to

commands and the commands are driven on

MA[13:0]. The BIOS selects an appropriate

host address for each row of memory such that

the right commands are generated on

MA[13:0].

100 CBR Cycle Enable (if this code is selected,

CAS-before-RAS refresh is used; if it is not

selected, RAS-Only refresh is used)

101 Reserved

11x Reserved

Rx6B[0] Rx64-66[1-0] Rx68[7-6] Remark

0

1

00

Non-page mode, every access starts

from precharge-active cmd

Only one page active at a time

(recommended setting)

Only allow sub-bank of a SDRAM

bank active at a time, # of subbank

depends on Rx64-66<1:0>

00

01 or 10

1

01 or 10

01

11

Allow mutliple sub-banks across

different SDRAM banks active, but

if EDO is accessed, all SDRAM

pages will be closed

Allow maximum 8 pages of

SDRAM, EDO opened

Revision 1.3 September 8, 1999

-43-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

PCI Bus Control

These registers are normally programmed once at system

initialization time.

Device 0 Offset 70 - PCI Buffer Control .........................RW

Device 0 Offset 71 - CPU to PCI Flow Control 1........... RW

7

CPU to PCI Post-Write

7

Dynamic Burst

0

1

Disable ...................................................default

Enable

0

1

Disable................................................... default

Enable (see note under bit-3 below)

6

PCI Master to DRAM Post-Write

6

Byte Merge

0

1

Disable ...................................................default

Enable

0

1

Disable................................................... default

Enable

5

4

Reserved

5

4

Reserved (do not program)........................default = 0

PCI I/O Cycle Post Write

PCI Master to DRAM Prefetch Disable

0

1

Enable.....................................................default

Disable

0

1

Disable................................................... default

Enable

3

CPU-to-PCI Buffer Available Cycle Reduction

3

PCI Burst

0

1

Normal operation ...................................default

Reduce 1 cycle when the CPU-to-PCI buffer

becomes available after being full (PCI and

AGP buses)

0

1

Disable................................................... default

Enable (bit7=1 will override this option)

bit-7 bit-3 Operation

0

1

Every write goes into the write buffer and no

PCI burst operations occur.

2

1

0

PCI Master Read Caching

0

1

Disable ...................................................default

Enable

0

If the write transaction is a burst transaction,

the information goes into the write buffer and

burst transfers are later performed on the PCI

bus. If the transaction is not a burst, PCI write

occurs immediately (after a write buffer flush).

Every write transaction goes to the write

buffer; burstable transactions will then burst

on the PCI bus and non-burstable won’t. This

is the normal setting.

Delay Transaction

0

1

Disable ...................................................default

Enable

Slave Device Stopped Idle Cycle Reduction

1

x

0

1

Normal Operation...................................default

Reduce 1 PCI idle cycle when stopped by a

slave device (PCI and AGP buses)

2

PCI Fast Back-to-Back Write

0

1

Disable................................................... default

Enable

1

0

Quick Frame Generation

0

1

Disable................................................... default

Enable

1 Wait State PCI Cycles

0

1

Disable................................................... default

Enable

Revision 1.3 September 8, 1999

-44-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 0 Offset 72 - CPU to PCI Flow Control 2.........RWC

Device 0 Offset 73 - PCI Master Control 1..................... RW

7

Retry Status

7

6

Reserved

........................................always reads 0

PCI Master 1-Wait-State Write

0

1

Retry occurred less than retry limit ........default

Retry occurred more than x times (where x is

0

1

Zero wait state TRDY# response........... default

One wait state TRDY# response

defined by bits 5-4) .................write 1 to clear

6

Retry Timeout Action

5

4

3

2

1

0

PCI Master 1-Wait-State Read

0

1

Retry Forever (record status only)..........default

Flush buffer for write or return all 1s for read

0

1

Zero wait state TRDY# response........... default

One wait state TRDY# response

5-4 Retry Limit

00 Retry 2 times ..........................................default

Disable Prefetch when Doing Delay Transaction

0

1

Enable.................................................... default

Disable

01 Retry 16 times

10 Retry 4 times

11 Retry 64 times

Clear Failed Data and Continue Retry

Assert STOP# after PCI Master Write Timeout

0

1

Disable................................................... default

Enable

3

2

0

1

Flush the entire post-write buffer ...........default

When data is posting and master (or target)

abort fails, pop the failed data if any, and keep

posting

Assert STOP# after PCI Master Read Timeout

0

1

Disable................................................... default

Enable

LOCK# Function

0

1

Disable................................................... default

Enable

CPU Backoff on PCI Read Retry Failure

0

1

Disable ...................................................default

Backoff CPU when reading data from PCI and

retry fails

PCI Master Broken Timer Enable

0

1

Disable................................................... default

Enable. Force into arbitration when there is no

FRAME# 16 PCICLK’s after the grant. Does

not apply to south bridge PREQ# input

1

0

Reduce 1T for FRAME# Generation

0

1

Disable ...................................................default

Enable

Reduce 1T for CPU Read of PCI Slave

Device 0 Offset 74 - PCI Master Control 2..................... RW

0

1

Disable ..................................................Default

Enable

7

PCI Master Read Prefetch by Enhance Command

0

1

Always Prefetch..................................... default

Prefetch only if Enhance command

6

PCI Master Write Merge

0

1

Disable................................................... default

Enable

5

4

Reserved

........................................always reads 0

Dummy Request Handling............Should be set to 1

0

1

As VP3................................................... default

Complete Fix

3

2

PCI Delay Transaction Time-Out

0

1

Disable................................................... default

Enable

Backoff CPU Immediately on CPU to AGP Retry

0

1

Disable................................................... default

Enable

1-0 CPU/PCI Master Latency Timer Control

00 AGP Master Reloads MLT timer........... default

01 Falling edge of AGP Master Request reloads

MLT timer

10 Rising Edge of AGP Master Request clears

MLT timer and falling edge reloads the timer

11 Reserved (illegal setting)

Revision 1.3 September 8, 1999

-45-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 0 Offset 75 - PCI Arbitration 1 ............................RW

Device 0 Offset 76 - PCI Arbitration 2............................ RW

7

Arbitration Mechanism

7

CPU-to-PCI Post-Write Retry Failed

0

1

PCI has priority ......................................default

Fair arbitration between PCI and CPU

0

1

Continue retry attempt ........................... default

Go to arbitration

6

Arbitration Mode

6

CPU Latency Timer Bit-0....................................RO

0

1

REQ-based (arbitrate at end of REQ#)...default

Frame-based (arbitrate at FRAME# assertion)

0

CPU has at least 1 PCLK time slot when CPU

has PCI bus............................................ default

CPU has no time slot

5-4 Latency Timer ........... read only, reads Rx0D bits 2:1

3-0 PCI Master Bus Time-Out

(force into arbitration after a period of time)

0000 Disable ...................................................default

0001 1x32 PCLKs

1

5-4 Master Priority Rotation Control

00 Disabled (arbitration per Rx75 bit-7)..... default

01 Grant to CPU after every PCI master grant

10 Grant to CPU after every 2 PCI master grants

11 Grant to CPU after every 3 PCI master grants

With setting 01, the CPU will always be granted

access after the current bus master completes, no

matter how many PCI masters are requesting. With

setting 10, if other PCI masters are requesting during

the current PCI master grant, the highest priority

master will get the bus after the current master

completes, but the CPU will be guaranteed to get the

bus after that master completes. With setting 11, if

other PCI masters are requesting, the highest priority

will get the bus next, then the next highest priority

will get the bus, then the CPU will get the bus. In

other words, with the above settings, even if multiple

PCI masters are continuously requesting the bus, the

CPU is guaranteed to get access after every master

grant (01), after every other master grant (10) or after

every third master grant (11).

0010 2x32 PCLKs

0011 3x32 PCLKs

0100 4x32 PCLKs

... ...

1111 15x32 PCLKs

3-2 High Priority REQ Select

00 REQ4 .................................................... default

01 REQ0

10 REQ1

11 REQ2

1

0

CPU-to-PCI QW High DW Read Access to PCI

Slave Allow Backoff

0

1

Disable................................................... default

Enable

High Priority Request Support

0

1

Disable................................................... default

Enable

Device 0 Offset 77 - Chip Test Mode............................... RW

7-6 Reserved (no function).......................always reads 0

5-0 Reserved (do not use).................................default=0

Revision 1.3 September 8, 1999

-46-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 0 Offset 78 - PMU Control 1 ................................RW

Device 0 Offset 7A – Miscellaneous Control .................. RW

7

I/O Port 22 Access

7

No Time-Out Arbitration for Consecutive Frame

Accesses

0

CPU access to I/O address 22h is passed on to

the PCI bus.............................................default

CPU access to I/O address 22h is processed

internally

0

1

Enable.................................................... default

Disable

1

6-4 Reserved

........................................always reads 0

6

Suspend Refresh Type

3

Background PCI-to-PCI Write Cycle Mode

0

1

CBR Refresh ..........................................default

Self Refresh

........................................ always reads 0

Dynamic Clock Control

0

1

Enable.................................................... default

Disable

5

4

Reserved

2-1 Reserved

........................................always reads 0

0

South Bridge PCI Master Force Timeout When

PCI Master Occupancy Timer Is Up

0

1

Normal (clock is always running)...........default

Clock to various internal functional blocks is

disabled when those blocks are not being used

0

1

Disable................................................... default

Enable

3

2

Reserved

........................................ always reads 0

AGPSTP# Control

0

1

Disable ...................................................default

Enable

Device 0 Offset 7E – PLL Test Mode.............................. RW

7-6 Reserved (status) ..................................................RO

5-0 Reserved (do not use).................................default=0

1

0

Reserved

........................................ always reads 0

Memory Clock Enable (CKE) Function

0

1

CKE Disable (pins used as MECC[2-0])..... def

CKE Enable (pins used for CKE[2-0]#)

Device 0 Offset 7F – PLL Test Mode .............................. RW

7-0 Reserved (do not use).................................default=0

Device 0 Offset 79 – PMU Control 2................................RW

7

CPU Interface Controller Dynamic Clock

Stopping

0

1

Disable ...................................................default

Enable

6

DRAM Controller Dynamic Clock Stopping

0

1

Disable ...................................................default

Enable

5

AGP Controller Dynamic Clock Stopping

0

1

Disable ...................................................default

Enable

4

3

2

PCI Interface Controller Dynamic Clock Stopping

0

1

Disable ...................................................default

Enable

Pseudo Power Good

0

1

Disable ...................................................default

Enable

South Bridge has High Priority

0

1

Disable ...................................................default

Enable

1-0 Reserved

........................................ always reads 0

Revision 1.3 September 8, 1999

-47-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

GART / Graphics Aperture Control

The function of the Graphics Address Relocation Table

(GART) is to translate virtual 32-bit addresses issued by an

AGP device into 4K-page based physical addresses for system

memory access. In this translation, the upper 20 bits (A31-

A12) are remapped, while the lower 12 address bits (A11-A0)

are used unchanged.

Since address translation using the above scheme requires an

access to system memory, an on-chip cache (called a

"Translation Lookaside Buffer" or TLB) is utilized to enhance

performance. The TLB in the 82C501 contains 16 entries.

Address "misses" in the TLB require an access of system

memory to retrieve translation data. Entries in the TLB are

replaced using an LRU (Least Recently Used) algorithm.

A one-level fully associative lookup scheme is used to

implement the address translation. In this scheme, the upper

20 bits of the virtual address are used to point to an entry in a

page table located in system memory. Each page table entry

contains the upper 20 bits of a physical address (a "physical

page" address). For simplicity, each page table entry is 4

bytes. The total size of the page table depends on the GART

range (called the "aperture size") which is programmable in

the VT8601.

Addresses are translated only for accesses within the

"Graphics Aperture" (GA). The Graphics Aperture can be any

power of two in size from 1MB to 256MB (i.e., 1MB, 2MB,

4MB, 8MB, etc). The base of the Graphics Aperture can be

anywhere in the system virtual address space on an address

boundary determined by the aperture size (e.g., if the aperture

size is 4MB, the base must be on a 4MB address boundary).

The Graphics Aperture Base is defined in register offset 10 of

device 0. The Graphics Aperture Size and TLB Table Base

are defined in the following register group (offsets 84 and 88

respectively) along with various control bits.

This scheme is shown in the figure below.

31

12 11

0

Virtual Page Address

TLB Base

Page Offset

index

Page Table

31

12 11

0

Physical Page Address

Page Offset

Figure 4. Graphics Aperture Address Translation

Revision 1.3 September 8, 1999

-48-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 0 Offset 83-80 - GART/TLB Control...................RW

31-16 Reserved

........................................ always reads 0

15-8 Reserved (test mode status).................................RO

Device 0 Offset 84 - Graphics Aperture Size.................. RW

7-0 Graphics Aperture Size

11111111 1M

11111110 2M

11111100 4M

7

Flush Page TLB

0

1

Disable ...................................................default

Enable

11111000 8M

11110000 16M

11100000 32M

11000000 64M

10000000 128M

00000000 256M

6-4 Reserved (always program to 0) ........................ RW

3

2

1

0

PCI Master Address Translation for GA Access

0

Addresses generated by PCI Master accesses

of the Graphics Aperture will not be translateddefault

PCI Master GA addresses will be translated

Offset 8B-88 - GA Translation Table Base..................... RW

31-12 Graphics Aperture Translation Table Base

Pointer to the base of the translation table in system

memory used to map addresses in the aperture range

(the pointer to the base of the "Directory" table).

1

AGP Master Address Translation for GA Access

0

Addresses generated by AGP Master accesses

of the Graphics Aperture will not be translateddefault

AGP Master GA addresses will be translated

11-3 Reserved

........................................always reads 0

1

2

One Cycle TLB Flush Command

CPU Address Translation for GA Access

0

1

Disable................................................... default

Enable................................... should be set to 1

0

Addresses generated by CPU accesses of the

Graphics Aperture will not be translated..... def

CPU GA addresses will be translated

1

Graphics Aperture Enable

1

0

1

Disable................................................... default

Enable Graphics Aperture Address [31:28]

AGP Address Translation for GA Access

0

Addresses generated by AGP accesses of the

Graphics Aperture will not be translated..... def

AGP GA addresses will be translated

Note: To disable the Graphics Aperture, set this bit

to 0 and set all bits of the Graphics Aperture Size to

0. To enable the Graphics Aperture, set this bit to 1

and program the Graphics Aperture Size to the

desired aperture size.

1

Note: For any master access to the Graphics Aperture range,

snoop will not be performed.

0

Reserved

........................................always reads 0

Note: If TLB miss, the TLB table is fetched by the address:

Gr Ap Trans Table Base [31:12] + A[27:22], A[21:12], 2’b00

Revision 1.3 September 8, 1999

-49-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

AGP Control

Device 0 Offset A3-A0 - AGP Capability Identifier ........RO

Device 0 Offset AC - AGP Control.................................. RW

31-24 Reserved

...................................... always reads 00

23-20 Major Specification Revision ..... always reads 0001

Major revision # of AGP spec device conforms to

19-16 Minor Specification Revision ..... always reads 0000

Minor revision # of AGP spec device conforms to

7

6

Reserved

...................................... always reads 0s

AGP Read Synchronization

0

1

Disable................................................... default

Enable (the CPU to AGP cycle will be delayed

if the CMFIFO contains a GART access)

5

4

AGP Read Snoop CMFIFO

15-8 Pointer to Next Item........ always reads 00 (last item)

0

1

Disable................................................... default

Enable (AGP read address will snoop the

CMFIFO; if hit, AGP read will be started after

the write is retired)

7-0 AGP ID

.. (always reads 02 to indicate it is AGP)

Device 0 Offset A7-A4 - AGP Status.................................RO

31-24 Maximum AGP Requests ................ always reads 07

Max # of AGP requests the device can manage (8)

AGP Master Request has Higher Priority if AGP

Controller is Parking at AGP Master

23-10 Reserved

.......................................always reads 0s

9

Supports SideBand Addressing ........ always reads 1

0

1

Disable................................................... default

Enable

8-2 Reserved

.......................................always reads 0s

1

2X Rate Supported

Value returned can be programmed by writing to

3

2

2X Rate Supported (read also at RxA4[1])

0

1

Not supported ........................................ default

Supported

RxAC[3]

........................................ always reads 1

0

1X Rate Supported............................. always reads 1

LPR In-Order Access (Force Fence)

0

Fence/Flush functions not guaranteed. AGP

read requests (low/normal priority and high

priority) may be executed before previously

issued write requests.............................. default

Force all requests to be executed in order

(automatically enables Fence/Flush functions).

Low (i.e., normal) priority AGP read requests

will never be executed before previously

issued writes. High priority AGP read requests

may still be executed prior to previously issued

write requests as required.

Device 0 Offset AB-A8 - AGP Command........................RW

31-24 Request Depth (reserved for target)...always reads 0s

23-10 Reserved

.......................................always reads 0s

9

SideBand Addressing Enable

1

0

1

Disable ...................................................default

Enable

8

AGP Enable

0

1

Disable ...................................................default

Enable

7-2 Reserved

.......................................always reads 0s

1

2X Mode Enable

1

0

AGP Arbitration Parking

0

1

Disable ...................................................default

Enable

0

1

Disable................................................... default

Enable (GGNT# remains asserted until either

GREQ# de-asserts or data phase ready)

0

1X Mode Enable

0

1

Disable ...................................................default

Enable

2T AGP to DRAM Request Generation

0

1

Disable................................................... default

Enable

Device 0 Offset AD – AGP Latency Register.................. RW

7-4 Reserved

...................................... always reads 0s

3-0 AGP Latency Timer(units of 16 GCLKs)

0000 Free Run ................................................ default

Revision 1.3 September 8, 1999

-50-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 0 Offset F7-F0 – BIOS Scratch Register .............RW

7-0 No Hardware Function

Device 0 Offset FC – Back Door Control 1..................... RW

7-2 Reserved

........................................always reads 0

1

Back-door MAX # of AGP Request Allowed

0

1

Read RXA7 will return 7....................... default

Read RxXA7 will have number programmed at

RxFD

Device 0 Offset F8 – DRAM Arbitration Timer 1..........RW

7-4 AGP Timer (units of 4 DRAM Clocks)

3-0 Host Timer (units of 4 DRAM Clocks)

0

Back-Door Device ID Enable

0

1

Use Rx3-2’s value for Rx3-2 read ......... default

Use the value in RxFE-FF

Device 0 Offset F9 – DRAM Arbitration Timer 2..........RW

7-4 VGA High Priority Timer (units of 16 DRAM

Clocks)

3-0 VGA Timer (units of 16 DRAM Clocks)

Device 0 Offset FD – Back Door Control 2..................... RW

7-3 Reserved

2-0 Back-Door Max # of AGP Requests the Device can

Handle

000 1-Request............................................... default

001 2-Requests

… …

111 8-Requests

Device 0 Offset FA – CPU Direct Access Frame Buffer

Base Address A[28:21]......................................................RW

7-0 A[28:21]

Device 0 Offset FF-FE – Back Door Device ID .............. RW

Device 0 Offset FB – Frame Buffer Control ...................RW

15-0 Back-Door Device ID................................default = 0

7

VGA Enable

0

1

Disable ...................................................default

Enable

6

VGA Reset ................................. (Write 1 to Reset)

5-4 Frame Buffer Size

00 None

.....................................................default

01 2M

10 4M

11 8M

3

CPU Direct Access Frame Buffer

0

1

Disable ...................................................default

Enable

2-0 CPU Direct Access Frame Buffer Base Address

<31:29>

Revision 1.3 September 8, 1999

-51-

Device 0 Bus 0 Host Bridge Registers

VT8601 Apollo ProMedia

Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge

Device 1 Offset 7-6 - Status (Primary Bus).................. RWC

15 Detected Parity Error ........................always reads 0

14 Signaled System Error (SERR#).......always reads 0

13 Signaled Master Abort

All registers are located in PCI configuration space. They

should be programmed using PCI configuration mechanism 1

through CF8 / CFC with bus number and function number

equal to zero and device number equal to one.

0

1

No abort received .................................. default

Transaction aborted by the master with

Master-Abort (except Special Cycles)..............

....................................... write 1 to clear

Device 1 Offset 1-0 - Vendor ID........................................RO

15-0 ID Code (reads 1106h to identify VIA Technologies)

12 Received Target Abort

Device 1 Offset 3-2 - Device ID..........................................RO

0

1

No abort received .................................. default

Transaction aborted by the target with Target-

Abort ....................................... write 1 to clear

15-0 ID Code (reads 8601h to identify the VT8601 PCI-

to-PCI Bridge device)

11 Signaled Target Abort........................always reads 0

10-9 DEVSEL# Timing

Device 1 Offset 5-4 - Command........................................RW

15-10 Reserved

........................................ always reads 0

00 Fast

9

Fast Back-to-Back Cycle Enable ........................RO

01 Medium....................................always reads 01

0

1

Fast back-to-back transactions only allowed to

the same agent ........................................default

Fast back-to-back transactions allowed to

different agents

10 Slow

11 Reserved

8

7

6

5

4

Data Parity Error Detected ...............always reads 0

Fast Back-to-Back Capable ...............always reads 0

User Definable Features.....................always reads 0

66MHz Capable..................................always reads 1

Supports New Capability list.............always reads 0

8

SERR# Enable......................................................RO

0

1

SERR# driver disabled...........................default

SERR# driver enabled

(SERR# is used to report parity errors if bit-6 is set).

Address / Data Stepping ......................................RO

3-0 Reserved

........................................always reads 0

7

6

5

Device 1 Offset 8 - Revision ID......................................... RO

0

1

Device never does stepping....................default

Device always does stepping

7-0 VT8601 Chip Revision Code (00=First Silicon)

Parity Error Response........................................RW

Device 1 Offset 9 - Programming Interface..................... RO

0

1

Ignore parity errors & continue..............default

Take normal action on detected parity errors

This register is defined in different ways for each Base/Sub-

Class Code value and is undefined for this type of device.

VGA Palette Snoop ..............................................RO

0

1

Treat palette accesses normally..............default

Don’t respond to palette writes on PCI bus

(10-bit decode of I/O addresses 3C6-3C9 hex)

7-0 Interface Identifier ...........................always reads 00

Device 1 Offset A - Sub Class Code.................................. RO

4

3

2

Memory Write and Invalidate Command..........RO

7-0 Sub Class Code .reads 04 to indicate PCI-PCI Bridge

0

1

Bus masters must use Mem Write ..........default

Bus masters may generate Mem Write & Inval

Device 1 Offset B - Base Class Code................................. RO

7-0 Base Class Code.. reads 06 to indicate Bridge Device

Special Cycle Monitoring ....................................RO

0

1

Does not monitor special cycles.............default

Monitors special cycles

Device 1 Offset D - Latency Timer................................... RO

7-0 Reserved

........................................always reads 0

Bus Master .........................................................RW

0

1

Never behaves as a bus master

Device 1 Offset E - Header Type ...................................... RO

Enable to operate as a bus master on the

primary interface on behalf of a master on the

secondary interface ................................default

7-0 Header Type Code.......... reads 01: PCI-PCI Bridge

Device 1 Offset F - Built In Self Test (BIST) ................... RO

1

0

Memory Space.....................................................RW

7

6

BIST Supported...... reads 0: no supported functions

Start Test .......... write 1 to start but writes ignored

0

1

Does not respond to memory space

Enable memory space access .................default

5-4 Reserved

........................................always reads 0

I/O Space .........................................................RW

3-0 Response Code..........0 = test completed successfully

0

1

Does not respond to I/O space

Enable I/O space access ........................default

Revision 1.3 September 8, 1999

-52-

Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge

VT8601 Apollo ProMedia

Device 1 Offset 18 - Primary Bus Number......................RW

Device 1 Offset 3F-3E – PCI-to-PCI Bridge Control..... RW

7-0 Primary Bus Number............................... default = 0

This register is read write, but internally the chip always uses

bus 0 as the primary.

15-4 Reserved

3

........................................always reads 0

VGA-Present on AGP

0

1

Forward VGA accesses to PCI Bus ....... default

Forward VGA accesses to AGP Bus

Note: VGA addresses are memory A0000-BFFFFh

and I/O addresses 3B0-3BBh, 3C0-3CFh and 3D0-

3DFh (10-bit decode). "Mono" text mode uses

B0000-B7FFFh and "Color" Text Mode uses B8000-

BFFFFh. Graphics modes use Axxxxh. Mono VGA

uses I/O addresses 3Bx-3Cxh and Color VGA uses

3Cx-3Dxh. If an MDA is present, a VGA will not

use the 3Bxh I/O addresses and B0000-B7FFFh

memory space; if not, the VGA will use those

addresses to emulate MDA modes.

Device 1 Offset 19 - Secondary Bus Number ..................RW

7-0 Secondary Bus Number........................... default = 0

Note: PCI#2 must use these bits to convert Type 1 to Type 0.

Device 1 Offset 1A - Subordinate Bus Number ..............RW

7-0 Primary Bus Number............................... default = 0

Note: PCI#2 must use these bits to decide if Type 1 to Type 1

command passing is allowed.

2

Block / Forward ISA I/O Addresses

0

Forward all I/O accesses to the AGP bus if

they are in the range defined by the I/O Base

and I/O Limit registers (device 1 offset 1C-1D)

.................................................... default

Do not forward I/O accesses to the AGP bus

that are in the 100-3FFh address range even if

they are in the range defined by the I/O Base

and I/O Limit registers.

Device 1 Offset 1C - I/O Base...........................................RW

7-4 I/O Base AD[15:12].......................... default = 1111b

3-0 I/O Addressing Capability....................... default = 0

Device 1 Offset 1D - I/O Limit..........................................RW

1

7-4 I/O Limit AD[15:12] ................................ default = 0

3-0 I/O Addressing Capability....................... default = 0

1-0 Reserved

........................................always reads 0

Device 1 Offset 1F-1E - Secondary Status........................RO

15-0 Reserved

.................................. always reads 0000

Device 1 Offset 21-20 - Memory Base..............................RW

15-4 Memory Base AD[31:20].................default = 0FFFh

3-0 Reserved

........................................ always reads 0

Device 1 Offset 23-22 - Memory Limit (Inclusive)..........RW

15-4 Memory Limit AD[31:20]........................ default = 0

3-0 Reserved

........................................ always reads 0

Device 1 Offset 25-24 - Prefetchable Memory Base .......RW

15-4 Prefetchable Memory Base AD[31:20].def = 0FFFh

3-0 Reserved

........................................ always reads 0

Device 1 Offset 27-26 - Prefetchable Memory Limit......RW

15-4 Prefetchable Memory Limit AD[31:20] ...................

.............................................. default = 0

3-0 Reserved

........................................ always reads 0

Revision 1.3 September 8, 1999

-53-

Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge

VT8601 Apollo ProMedia

Device 1 Bus 0 PCI-to-AGP Bridge Registers

Device 1 Offset 41 - CPU-to-AGP Flow Control 2...... RWC

7

Retry Status

AGP Bus Control

0

1

No retry occurred................................... default

Retry Occurred ........................write 1 to clear

Device 1 Offset 40 - CPU-to-AGP Flow Control 1 .........RW

6

Retry Timeout Action

7

6

5

4

3

CPU-AGP Post Write

0

1

No action taken except to record status .......def

Flush buffer for write or return all 1s for read

0

1

Disable ...................................................default

Enable

5-4 Retry Count

00 Retry 2, backoff CPU ............................ default

CPU-AGP Dynamic Burst

0

1

Disable ...................................................default

Enable

01 Retry 4, backoff CPU

10 Retry 16, backoff CPU

11 Retry 64, backoff CPU

Post Write Data on Abort

CPU-AGP One Wait State Burst Write

0

1

Disable ...................................................default

Enable

3

2

0

Flush entire post-write buffer on target-abort

or master abort....................................... default

Pop one data output on target-abort or master-

abort

AGP to DRAM Prefetch

0

1

Disable ...................................................default

Enable

1

AGP Master Allowed Before CPU-to-AGP Post

Write Buffer is Not Flushed

CPU Backoff on AGP Read Retry Timeout

0

1

Disable................................................... default

Enable

0

1

Disable ...................................................default

Enable

1-0 Reserved

........................................always reads 0

This option is always enabled for PCI

2

MDA Present on AGP

Device 1 Offset 42 - AGP Master Control ...................... RW

0

1

Forward MDA accesses to AGP.............default

Forward MDA accesses to PCI

7

6

5

4

Read Prefetch for Enhance Command

0

1

Always Perform Prefetch....................... default

Prefetch only if Enhance Command

Note: Forward despite IO / Memory Base / Limit

Note: MDA (Monochrome Display Adapter)

AGP Master One Wait State Write

addresses are memory addresses B0000h-B7FFFh

and I/O addresses 3B4-3B5h, 3B8-3BAh, and 3BFh

(10-bit decode). 3BC-3BE are reserved for printers.

Note: If Rx3E bit-3 is 0, this bit is a don't care (MDA

accesses are forwarded to the PCI bus).

0

1

Disable................................................... default

Enable

AGP Master One Wait State Read

0

1

Disable................................................... default

Enable

1

0

AGP Master Read Caching

Extend AGP Internal Master for Efficient

Handling of Dummy Request Cycles

0

1

Disable ...................................................default

Enable

0

1

Disable................................................... default

Enable

AGP Delay Transaction

0

1

Disable ...................................................default

Enable

This bit is normally set to 1.

AGP Delay Transaction Timeout

3

2

0

1

Disable................................................... default

Enable

Table 5. VGA/MDA Memory/IO Redirection

Prefetch During Delay Transaction

3E[3] 40[2] VGA MDA Axxxx, B0000 3Cx,

VGA MDA is

Pres. Pres. on

0

1

Enable.................................................... default

Disable

is B8xxx -B7FFF 3Dx 3Bx

on Access Access I/O I/O

1

0

Reserved

........................................always reads 0

0

1

-

0

1

PCI PCI

AGP AGP AGP

AGP PCI AGP

PCI

PCI PCI PCI

AGP AGP AGP

PCI AGP PCI

Reserved (do not use) ...............................default = 0

Revision 1.3 September 8, 1999

-54-

Device 1 Bus 0 PCI-to-AGP Bridge Registers

VT8601 Apollo ProMedia

Device 0 Bus 1 Header Registers - Graphics Accelerator

The Apollo ProMedia 2D / 3D Graphics Accelerator is fully

compliant with PCI bus interface protocol revision 2.2. The

controller implements slave functions of PCI to accept cycles

initiated by PCI masters targeted for its internal registers,

RAMDAC™, frame buffer, and/or BIOS. It will accept only

one data transaction for non-memory type transfers; however

burst read/write transfers for frame buffer accesses are also

implemented for performance enhancement. Bursting is

disabled when accessing memory mapped I/O. Data parity

will be generated for read cycles.

The PCI configuration space is fully implemented. Due to the

second memory base register, all I/O registers can be memory

mapped; which allows more than one graphics controller to be

installed within a system by mapping memory and I/O to

different locations.

All configuration registers are located in PCI configuration

space and should be programmed using PCI configuration

mechanism 1 through CF8 / CFC with bus number equal to

one and function number and device number equal to zero.

There are three memory base registers. The first defines the

memory base location for the graphics frame buffer. The

second defines the memory base for the memory mapped I/O

locations. The third defines the memory base for the second

video aperture. With this second aperture, graphics data and

video data can be sent to the ProMedia simultaneously.

To support the PC AT architecture, palette snooping is

supported. There are two different palette snooping modes:

(1) snooping due to PCI retry, and (2) snooping due to master

abort. Both modes are supported. The video BIOS will

automatically determine the correct snooping mode in a PCI

based system during power up. The ProMedia follows the

PCI 2.2 specification running at 33 MHz or lower system

clock frequencies. For packed pixel modes, if the first data

TRDY is not generated within 16 clocks, a retry will be

issued. During bursting, if successful data is not generated

within 8 clocks, a retry will also be issued.

The ProMedia supports the PCI Bus Master mode which can

send captured video data directly to system memory for

processing. The registers to control the PCI Bus Master are

defined in following sections (they are all in PCI configuration

space).

The table below lists the commands implemented by the

ProMedia graphics controller PCI interface. Note that codes

not listed (0000 interrupt acknowledge, 0001 special cycle,

0100, 0101, 1000, 1001 reserved, and 1101 dual address

cycle) are not decoded and DEVSEL# is not generated. No

action takes place inside the chip for these codes.

Offset 1-0 - Vendor ID (1023h)......................................... RO

15-0 ID Code

................................always reads 1023h

Offset 3-2 - Device ID (8500h) .......................................... RO

15-0 ID Code

................................always reads 8500h

Table 6. Supported PCI Command Codes

Command Code Command

0010

0011

0110

0111

1010

1011

1100

I/O Read

I/O Write

Memory Read

Memory Write

Configuration Read

Configuration Write

Memory Read Multiple

(treated as simple memory read)

Memory Read Line

(treated as simple memory read)

Memory Write and Invalid

(treated as simple memory write)

1110

1111

Revision 1.3 September 8, 1999

-55

Device 0 Bus 1 Header Registers - Graphics Accelerator

VT8601 Apollo ProMedia

Offset 5-4 - Command.......................................................RW

15-10 Reserved

........................................ always reads 0

Offset 7-6 - Status .......................................................... RWC

15 Detected Parity Error

0

1

No parity error detected......................... default

Error detected in either address or data phase.

This bit is set even if error response is disabled

(command register bit-6). ......write one to clear

9

Fast Back-to-Back Cycle Enable ........................RO

...........default set from inverse of MA??

0

1

Fast back-to-back transactions only allowed to

the same agent

Fast back-to-back transactions allowed to

different agents

14 Signaled System Error (SERR# Asserted)

........................................always reads 0

13 Signaled Master Abort (Bus Master Only)

8

SERR# Enable......................................................RO

0

1

No abort received .................................. default

Transaction aborted by the master ...................

....................................write one to clear

0

1

SERR# driver disabled...........................default

SERR# driver enabled

(SERR# is used to report parity errors if bit-6 is set).

12 Received Target Abort (Bus Master Only)

7

6

5

4

3

2

1

0

Address / Data Stepping ......................................RO

0

1

No abort received .................................. default

Transaction aborted by the target......................

....................................... write 1 to clear

0

1

Device never does stepping....................default

Device always does stepping

Parity Error Response.........................................RO

11 Signaled Target Abort........................always reads 0

Target Abort never signaled

0

1

Ignore parity errors & continue..............default

Take normal action on detected parity errors

0

10-9 DEVSEL# Timing

VGA Palette Snoop .............................................RW

00 Fast

0

1

Treat palette accesses normally..............default

Don’t respond to palette accesses on PCI bus

01 Medium....................................always reads 01

10 Slow

11 Reserved

Memory Write and Invalidate Command..........RO

0

1

Bus masters must use Mem Write ..........default

Bus masters may generate Mem Write & Inval

8

7

Data Parity Error Detected (Bus Master Only)

0

1

No data parity error detected .....always reads 0

Error detected in data phase

Special Cycle Monitoring ....................................RO

0

1

Does not monitor special cycles.............default

Monitors special cycles

Fast Back-to-Back Capable

0

1

Not capable............................................ default

Capable

Bus Master .........................................................RW

0

1

Never behaves as a bus master ...............default

Can behave as a bus master

6

5

4

Reserved

........................................always reads 0

66MHz Capable..................................always reads 1

Supports New Capability list.............always reads 0

Memory Space.....................................................RW

0

1

Does not respond to memory space

Responds to memory space ....................default

3-0 Reserved

........................................always reads 0

I/O Space .........................................................RW

0

1

Does not respond to I/O space

Responds to I/O space ...........................default

Revision 1.3 September 8, 1999

-56

Device 0 Bus 1 Header Registers - Graphics Accelerator

VT8601 Apollo ProMedia

Offset 8 - Revision ID.........................................................RO

8-0 VT8601 Graphics Controller Revision Code

Offset 3C – Interrupt Line............................................... RW

7-0 Interrupt Line...................................... default = 0Bh

Offset 9 - Programming Interface.....................................RO

Offset 3D – Interrupt Pin.................................................. RO

7-0 Interface Identifier........................... always reads 00

7-0 Interrupt Pin....................always reads 01h (INTA#)

Offset A - Sub Class Code..................................................RO

7-0 Sub Class Code................................. always reads 00

Interrupts

There are several interrupt sources and their corresponding

controls in the ProMedia as shown in the following table:

Offset B - Base Class Code ................................................RO

7-0 Base Class Code

Table 7. Interrupt Sources and Controls

Reads 03 to indicate Graphics Controller

Source

Capture³

Mask

Clear

Status

CR9B[7] CR9B[6]¹CR9B[4]

2

Capture VSYNC

Capture Even Field

Capture Odd Field

Capture Blank

GE⁴

Offset 13-10 - Graphics Memory Base 0 .........................RW

2

31-0 Graphics Memory Base 0 .........default = E000 0000

Defines an 8MB space for display memory

Offset 17-14 - Graphics Memory Base 1 .........................RW

2122[7] 2122[7] 2120[4]

CR11[5] CR11[4]

VGA⁵

31-0 Graphics Memory Base 0 .........default = E080 0000

Defines a 128KB space for memory mapped I/O

1) Write 0 to clear.

2) Selected by CR9E[7:6]

Offset 1B-18 - Graphics Memory Base 2.........................RW

3) Video capture logic can generate an interrupt which is

selected from one of four sources determined by

CR9E.[7:6]. This interrupt is enabled by CR9B[7]. To

clear this bit write 0 to CR9B[6]. Whether an interrupt is

generated can be determined from CR9B[4].

31-0 Graphics Memory Base 0 .........default = E040 0000

Defines an 8MB space for off-screen video overlay

4) The GE interrupt is similar to the capture interrupt.

5) The VGA interrupt is similar to the capture interrupt except

that there is no status bit.

Offset 2D-2C – Subsystem Vendor ID.............................RW

15-0 Subsystem Vendor ID ............................ default = 00

Offset 2F-2E - Subsystem ID ............................................RW

15-0 Subsystem ID.......................................... default = 00

Offset 33-30 –Graphics ROM Base..................................RW

31-0 Graphics ROM Base................. default = 0000 0001

Revision 1.3 September 8, 1999

-57

Device 0 Bus 1 Header Registers - Graphics Accelerator

VT8601 Apollo ProMedia

Device 0 Bus 1 Graphics Accelerator Registers

Offset 93-90 – Power Management 1................................RO

Offset 97-94 – Power Management 2 .............................. RW

31-27 Reserved

........................................ always reads 0

31-24 Reserved

........................................always reads 0

PME# not supported

Power dissipation reporting not supported

26 D2 State (Suspend) Supported.......... always reads 1

The D2 state is supported

25 D1 State (Standby) Supported .......... always reads 1

The D1 state is supported

23-16 Reserved

........................................always reads 0

15 D3 Cold Supported.............................always reads 0

D3 cold not supported

14-13 Data Scale ........................................always reads 0

Power dissipation reporting not supported

24-22 Reserved

........................................ always reads 0

21 Device Specific Initialization............. always reads 1

12-9 Power Consumed / Dissipated ...........always reads 0

Power dissipation reporting not supported

Special DSI is required from the video BIOS

20 Reserved

Auxiliary power source not supported

19 Reserved

........................................ always reads 0

8

Reserved

........................................always reads 0

PME# for D3 cold not supported

7-2 Reserved

........................................always reads 0

PME# generation not supported

1-0 Power State

00 Fully On................................................. default

01 Standby

10 Suspend

18-16 PCI PM Version #........................ always reads 001b

15-8 Next Item Pointer............................... always reads 0

7-0 PCI PM Capable............................ always reads 01h

This device is PCI PM capable

11 D3hot, similar to suspend

Revision 1.3 September 8, 1999

-58

Device 0 Bus 1 Graphics Accelerator Registers

VT8601 Apollo ProMedia

Graphics Accelerator PCI Bus Master Registers

Port 2300 – Graphics Bus Master Control..................... RW

31-16 Reserved

........................................always reads 0

15 PCI Master Read Data to GE SRCQ

Disable................................................... default

Enable

14-11 Bytes in DW to be Cleared

When enabling block transfer with clear, one bits

define which byte(s) in the DW will be cleared

10 Enable Bit with Clear

The ProMedia PCI Bus Master controller supports both

read/write and scatter/gather. Software can take advantage of

this feature to transfer data between system memory and the

frame buffer. After software sets the proper registers and

commands, the PCI master begins to transfer data

automatically between system memory and the frame buffer.

This allows the CPU to do other jobs at the same time, thus

increasing performance.

0

1

0

1

Disable................................................... default

Enable

Invert C / Z Position

Software should use the PCI Bus Master functionality to

transfer big chunks of data such as video capture data for

video conferencing applications or texture data for 3-D

applications. For small chunks of data, direct CPU access to

the Frame Buffer is the preferred method.

9

8

0

1

Hardware assumes C is located in bits 15:0 and

Z in bits 31:16........................................ default

Hardware assumes C is located in bits 31:16

and Z in bits 15:0

The software sequence used to control bus master operation is

as follows: Software first sets registers such as the system

memory starting address, page table starting address / height /

width, and frame buffer starting address and line offset.

Software finally sets the bus master control register where

either bit 1 (for reads) or bit 2 (for writes) is set as the

command bit. After the command bit is set, the hardware will

begin to transfer data automatically based on the parameters

specified. After the transfer is finished, the hardware will

issue an interrupt. Software can then poll the status bit to get

the transfer status. The hardware will clear the command bit

after the transfer is finished. Software cannot issue new

commands until the previous command is completed.

Enable Z Stripping

0

1

Disable................................................... default

Enable

........................................always reads 0

Bus Master Interrupt

Disable................................................... default

Enable

Master Latency

Disable................................................... default

Enable

Write Command ........................................default =0

Writing this bit to 1 will trigger the hardware to begin

a write operation. After finishing the operation,

hardware will automatically clear this bit.

7-5 Reserved

4

3

2

0

1

0

1

All Registers are memory mapped. The memory address base

is defined in PCI configuration register “Memory Base 1”

(offset 17h-14h).

1

0

Read Command ........................................default =0

Writing this bit to 1 will trigger the hardware to begin

a read operation. After finishing the operation,

hardware will automatically clear this bit.

Port 2204 – Graphics Bus Master Status .........................RO

Scatter / Gather

31-3 Reserved

2

1

........................................ always reads 0

Bus Master Interrupt Status

End of Transfer

0

1

Disable................................................... default

Enable

0

1

Still processing.......................................default

End of Transfer (Idle)

0

Bus Master Error Status

0

1

Normal ...................................................default

Error Detected

This error is ususlly detected because the total page

table size is less than the size defined in the

“Graphics Bus Master Height” register at index

2314h.

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Port 2310 – Graphics Bus Master System Start Addr ...RW

Port 2314 – Graphics Bus Master Height....................... RW

31-0 System Start Address

15-10 Reserved

........................................always reads 0

If scatter / gather is enabled, bits 31:12 point to the

physical region translation table (the page starting

address must be aligned on 4KB address boundaries)

and bits 11:0 are the offset within a page.

9-0 Source Data Height

Port 2316 – Graphics Bus Master Width........................ RW

15-12 Reserved

........................................always reads 0

11-0 Source Data Width (in bytes)

Physical Region Descriptor Table

While system memory is allocated in a non-contiguous space,

software needs to provide a physical region description table

in system memory and pass the table's starting address to

hardware.

Port 2318 – Graphics Bus Master FB Start Addr/Pitch RW

31-22 Frame Buffer Line Offset (FB pitch) in quadwords

21-20 Reserved

........................................always reads 0

19-0 Frame Buffer Start Address (quadword aligned)

The table size must less than or equal to 4K bytes and the

table cannot cross the 4K boundary.

Port 231C – Graphics Bus Master System Pitch............ RW

15-12 Reserved

........................................always reads 0

11-0 System Row Byte Offset (pitch) in bytes

Figure 5. Physical Region Descriptor Table Format

BYTE3

|

BYTE2

|

BYTE1

|

BYTE0

|EOT

Page 0 physical address

Page 1 physical address

......

Port 2320 – Graphics Bus Master Clear Data................ RW

31-0 Clear Data Value

Page n physical address

|EOT

Used as the “clear” value for “block transfer with

clear”

EOT = End of Table

Each table entry is 4 bytes in length. Hardware assumes that

the physical page is always 4K. Bits 31:2 indicate the

physical page starting address. Bit 0 of the first byte indicates

the end of the table. Bus Master operation terminates when

the last descriptor has been retired.

Figure 6. PCI Bus Master Address Translation

System Start Address

Register at 2210

31 ................ 12 11 ...... 0

Physical Region

Description Table

Physical Memory

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Graphics Accelerator AGP Registers

Command List Format

The command list is stored in AGP memory in groups. Each

group has the following format:

The default base I/O address for the AGP registers is 2300h.

The AGP control unit has 3 channels. These channels can

work independently and in parallel. Each channel has its own

capabilities:

Bit

63 48 32

Data 0

Bit

31 16

QuadWord

0

Header

Channel 0: Execution mode texture access.

1

2

…

Data 2

Data 4

…

Data 1

Data 3

…

Channel 1: Command List Operation. Executes command

lists from AGP memory.

n / 2 + 1

Pad/Data n-1

Data n – 1/2

Channel 2: Data Move. Moves data from AGP memory to

frame buffer or to the Capture/MPEG2 FIFO.

Also moves data from the frame buffer to AGP

memory.

The header is a 32-bit word that contains information about

this group, such as the amount of useful data in the group. A

group is always padded to a quadword boundary. Padding

DWORDs are discarded by the channel. The format of the

header is as follows:

Graphics AGP Configuration Registers

31 Consecutive Addressing

0

Disabled (all data in this group will be written

to the register with the destination address

specified in the “ADDR” field in bits 29-8)

Enabled (All data in this group will be written

to registers ADDR, ADDR+4, … ADDR+4 *

(LEN-1) sequentially

Port 2304 – Graphics AGP Capability List.....................RW

31-0 xx

Port 2334 – Graphics AGP Capability List Address......RW

31-0 xx

1

30 Wait

0

Don’t Wait (send data to the Graphics Engine

as long as it can receive it)

Graphics AGP Operation Registers

1

Wait (until the GE is idle, then send data)

Port 2340 – Graphics AGP FB Command List Start .....RW

29-8 Register Address of the First Data (ADDR)

15-0 Number of DWORDs of Data in this Group (LEN)

31-19 Reserved

........................................ always reads 0

18-0 Frame Buffer Command List Start Address

Port 2344 – Graphics AGP FB Command List Size.......RW

31-19 Reserved

........................................ always reads 0

18-3 Frame Buffer Command List Size (in quadwords)

Value programmed is the desired size minus one

2-0 Reserved

........................................ always reads 0

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Port 2348 – Graphics AGP Channel 1 FB Start/Pitch ...RW

Port 2364 –Channel Arbitration Counter Threshold.... RW

31-22 Frame Buffer Line Offset (in quadwords)

31-28 Reserved

........................................always reads 0

21-19 Reserved

........................................ always reads 0

18-0 Frame Buffer Starting Address

26-24 Channel 2 System Arbitration Threshold

23-20 Channel 2 System Arbitration Threshold

19-16 Channel 2 System Arbitration Threshold

Port 234C – Graphics AGP Channel 1 FB Size..............RW

15-12 Reserved

11-8 ??

........................................always reads 0

31-13 X Direction (in quadwords minus one)

12-10 Reserved

........................................ always reads 0

7-0 ??

9-0 Y Direction (in pixels minus one)

Port 2368 – Graphics AGP Channel I/O Control .......... RW

31-27 Reserved

26 Reserved (Do not Program).......................must be 0

25 Reserved

........................................always reads 0

24 Reserved (Do not Program).......................must be 0

23-22 Reserved

........................................always reads 0

Port 2350 – Graphics AGP Channel 1 System Start ......RW

31-3 Channel 1 System Memory Start Address

(quadword aligned)

2-1 Reserved

........................................ always reads 0

21-20 Reserved (Do not Program).....................must be 01

19 Channel 1 Read Enable

0

Command List Operation Trigger

This bit is the same as bit-19 of register 2368h

(Channel 1 Read Enable). It is used to trigger

command list operation and force bit-17 of register

2368h (Channel 1 Destination Select) to 1 (to select

the GE Command FIFO).

0

1

Disable................................................... default

Enable

18 Channel 1 Interrupt Enable

0

1

Disable................................................... default

Enable

17 Channel 1 Destination Select

0

1

Frame Buffer.......................................... default

GE Command FIFO

Port 2354 – Graphics AGP Chan 1/2 System Pitch........RW

31-27 Reserved

........................................ always reads 0

26-16 Ch 2 System Memory Line Offset (in quadwords)

15-11 Reserved

........................................ always reads 0

16 Channel 1 Enable

0

1

Disable................................................... default

Enable

15-1 Reserved

........................................always reads 0

10-0 Ch 1 System Memory Line Offset (in quadwords)

0

Channel 0 Enable

0

1

Disable................................................... default

Enable

Port 2358 – Graphics AGP Channel 2 System Start ......RW

31-3 Channel 2 System Memory Start Address

(quadword aligned)

2-0 Reserved

........................................ always reads 0

Port 235C – Graphics AGP Channel 2 FB Start/Pitch .RW

31-22 Frame Buffer Line Offset (in quadwords)

21-19 Reserved

........................................ always reads 0

18-0 Frame Buffer Starting Address

Port 2360 – Graphics AGP Channel 2 FB Size...............RW

31-27 Reserved

26-16 Ch 2 System Memory Line Offset (in quadwords)

15-11 Reserved

........................................ always reads 0

10-0 Ch 1 System Memory Line Offset (in quadwords)

........................................ always reads 0

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Port 236C – Graphics AGP Global & Chan 2 Control..RW

31-26 Reserved

........................................ always reads 0

Port 2370 –AGP Status..................................................... RW

31-18 Reserved

........................................always reads 0

25-24 Sideband Address (SBA) Standby Latency Timer

23 High Priority Command Enable

17 Channel 2 Interrupt Status

0

1

No interrupt pending.............................. default

Interrupt Pending

0

1

Disable ...................................................default

Enable

16 Channel 2 Busy Status

22 Long Read Command Enable

0

1

Idle .................................................... default

Busy

0

1

Disable ...................................................default

Enable

15-10 Reserved

........................................always reads 0

21 System Side Channel 2 Priority

20 System Side Channel 1 Priority

19 System Side Channel 0 Priority

9

Channel 1 Interrupt Status

0

1

No interrupt pending.............................. default

Interrupt Pending

18 Reserved

........................................ always reads 0

8

Channel 1 Busy Status

17 Frame Buffer Channel 2 Priority

16 Frame Buffer Channel 1 Priority

0

1

Idle .................................................... default

Busy

15-5 Reserved

........................................ always reads 0

7-2 Reserved

........................................always reads 0

4-3 Channel 2 Read Operation Select

00 Disabled .................................................default

01 Read from Frame Buffer to AGP

10 Write from AGP to Capture / MPEG / FB

11 -reserved-

1

Channel 0 Interrupt Status

0

1

No interrupt pending.............................. default

Interrupt Pending

0

Channel 0 Busy Status

0

1

Idle .................................................... default

Busy

2

Channel 2 Interrupt Enable

0

1

Disable ...................................................default

Enable

1-0 Channel 2 Write Target Select

00 Write to Frame Buffer............................default

01 Write to Capture / MPEG / FB

1x -reserved-

Graphics AGP Configuration Registers

Port 2380 – Graphics AGP Capability Identifier........... RW

31-0 xx

Port 2384 – Graphics AGP Status................................... RW

31-0 xx

Port 2388 – Graphics AGP Command............................ RW

31-0 xx

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Graphics Accelerator PCI Bus Master Registers

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Command List Operation

Port 23B0 –Command Buffer Start Address.................. RW

31-30 Command List Mode

The ProMedia implements an internal block called the

“Command List Control Unit” to process command lists.

Command list operation is invisible to software. After

initialization of the Command List Control Unit, software can

set registers as if there is no Command List Control Unit. If

an engine is idle and there are no pending commands in the

command buffer, data will be passed to the corresponding

register directly. Otherwise, address and data will be stored

into the command buffer to be processed later. When the

engine is idle, the Command List Control Unit will fetch

commands from the command buffer which is located in

video memory and send it to the engine. There are two

registers that determine the lower and upper bounds of the

command buffer, the Command Buffer Start and Command

Buffer End registers. The Command List Control Unit uses

the command buffer in a round robin fashion, i.e., the address

is wrapped around when it passes the end of the buffer.

00 Disable Command Buffer ...................... default

01 Enable Command Buffer

10 Flush Command Buffer Then Disable (after

first completing any commands in the existing

command buffer)

11 -reserved-

29-24 Reserved

........................................always reads 0

23-0 Command Buffer Start Address

Starting address of the command buffer in bytes

(quadword aligned). Writing to this register will set

the internal buffer start and end pointers to this

address.

Port 23B0 –Command Buffer End Address ................... RW

31-24 Reserved

........................................always reads 0

23-0 Command Buffer End Address

End address of the command buffer in bytes

(quadword aligned).

programmed to one more than the address of the last

byte of the command buffer.

This address should be

Registers in the Setup Engine, Rasterization Engine, Pixel

Engine, Memory Interface, and data from the host CPU and

the drawing environment can be buffered by the Command

List Control Unit. Command List Control registers and VGA

extension registers cannot be buffered. Every entry in the

command buffer is 64-bit with the lower 32 bits for the

register address and the higher 32 bits for register data. In

order to optimize memory bandwidth usage, the Command

List Control Unit maintains one read and one write FIFO in its

interface to memory in order to burst information from the

read/write command list.

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Graphics Accelerator PCI Bus Master Registers

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VGA Standard Registers - Introduction

where extended functions are provided in all indexed register

groups except the Attribute Controller (due to the unusual

nature of Attribute Controller indexing using a single I/O port

which makes access to this register group more cumbersome).

This document will detail the functions of all the standard

VGA registers first. All extended functions will then be

separately documented in following sections.

The standard VGA register set consists of five sets of indexed

registers plus several individually addressed registers. All

VGA registers are addressed at specific I/O port addresses

defined by the VGA legacy standard.

The non-indexed registers (also called the “Status / Enable”

registers) are:

Regarding notation used in this document, indexed registers

(including extended registers) may be referenced using a 2-

letter mnemonic from the following table followed by the

index number:

Input Status Register 0 Read at 3C2

Input Status Register 1 Read at 3BA or 3DA

Miscellaneous Register Read at 3CC, Write at 3C2

Video Subsystem Enable Read/Write at 3C3

Display Adapter Enable Read/Write at 46E8

Attribute Controller

Graphics Controller

CRT Controller

Sequencer

AR

GR

CR

SR

The indexed register sets each control different functional

blocks inside the hardware VGA logic. These register sets

are:

For example, index register 26h of the 3CE / 3CFh indexed

register group could also be referred to as GR26. Bit-7 if this

register, using this notation, would be GR26[7].

Attribute Controller

Sequencer

Graphics Controller

CRT Controller

RAMDAC

21 registers (0-14h) at 3C0/1

5 registers (0-4h) at 3C4/5

9 registers (0-8h) at 3CE/F

25 registers (0-18h) at 3x4/5

256 24-bit registers at 3C7-3C9

Register groups, for the most part, are included in this

document in order by I/O port address. Some registers are

included out of order with other registers in the same

functional block. Refer to the table of contents and the

register summary tables at the beginning of the register section

of this document for further information and help in finding

descriptive information for a specific register.

Indexed registers typically require two sequential port

addresses, the first of which is the index and the second of

which is the data. In other words, the index is written to the

first port address and then the data corresponding to that

indexed register is read from or written to the second port

address. The exceptions to this are the Attribute Controller

and the RAMDAC. For the Attribute Controller, the index is

written at 3C0 as expected. Data reads (but not writes) can be

performed from port 3C1 in the standard way. However,

generally most data read and all data write operations use the

same 3C0 port as used for the index. Data and address are

accessed on alternate operations to 3C0 with an internal flag

to keep track of where the next operation is to be performed

(reads from 3BA or 3DA reset the flag to point at the index

register). The other exception to the 2-port index/data

structure is the RAMDAC which uses three port addresses. In

this case, there are two locations provided for the index, 3C7

and 3C8, with the data at 3C9. There is actually only one

index register, but automatic pre / post incrementation is

performed differently depending on whether the index is

written at the “Read” address (3C7) or the “Write” address

(3C8). The current index value may be read at 3C8. Refer to

the RAMDAC register group for further explanation of the

operation of the index registes and sequential access to the

three data bytes of each indexed data location.

For standard VGA registers, primarily only the bit definitions

are provided here. Since the operation of these bits was

standardized long ago, full explanation of the operation of

these bits is not provided in this document. Detailed

explanation of these bits is provided by many fine indiustry

publications (check your local computer book store or the

internet for further information).

The number of registers listed above for each indexed register

group is the number of registers defined by the VGA standard.

The operation of these “base” registers will always be exactly

the same from one vendor’s implementation of the VGA to

another. Typically, however, there are additional non-

standard

/ extended functions implemented in higher

numbered index values. That is the case for this chip as well,

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Capture / ZV Port Registers

Port 2200 – Capture / ZV Port Command ......................RW

31-28 Reserved

27-24 Address 1

23-20 Reserved

19-16 Address 0

15-8 Data 1

........................................ always reads 0

7-0 Data 0

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Graphics Accelerator PCI Bus Master Registers

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DVD Registers

Port 2280 – MC Version ID...............................................RO

7-0 Version ID

Port 2282 – MC Frame Buffer Configuration................ RW

7

6

Interlaced Display

TV Flicker Filter Bypass

Port 2281 – MC Control...................................................RW

0

1

Use TV CRTC ....................................... default

Use VGA CRTC

7

6

5

4

3

Debug Mode

0

1

Disable ...................................................default

Enable

5

4

3

2

Request Threshold of Display Command Queue

Request Threshold of PBF

Request Threshold of PFF

MC Completion Interrupt

0

1

Disable ...................................................default

Enable

Hardware SP RL-Decode Disable

0

1

Enable.................................................... default

Disable

VO Completion Interrupt

0

1

Disable ...................................................default

Enable

1-0 Frame Buffer Configuration

00 4-frame................................................... default

01 3.5-frame

Host Bus Identification

0

1

AGP .....................................................default

PCI

10 3.5-frame HHR

11 3-frame

Decode Overwrite

0

1

Enable.....................................................default

Disable

2-1 IDCT Data Format

00 -reserved-................................................default

01 9 bits

10 8 bits

11 16 bits

MC Mode

0

1

Disable ...................................................default

Enable

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Graphics Accelerator PCI Bus Master Registers

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Port 2287-2284 – MC Command Queue .........................RW

31-12 Page Table Address

Port 2285-2284 – MC Status............................................ RW

15 Task Pop Out Done Status

14-12 FIFO Status

11 SP Command Present

11 MC Decode Done Status

0

1

SP Command is Absent..........................default

SP Command is Present

10-9 Video Output Display Fields

00 -reserved-............................................... default

01 Top

10-9 Video Output Display Fields

00 -reserved-................................................default

01 Top

10 Bottom

11 Both

8-6 Video Output Display Buffer

000 F0

001 F1

010 F2

011 F3

100 H0

101 H1

110 H2

.................................................... default

000 F0

001 F1

010 F2

011 F3

100 H0

101 H1

110 H2

.....................................................default

111 -reserved-

5-4 MC Buffer 2

Bit-1 = 1

111 -reserved-

5-4 MC Buffer 2

Bit-1 = 1

Bit-1 = 0

top

bottom

both

Bit-1 = 0

top

bottom

both

00

01

10

H0

H1

H2

00

01

10

H0

H1

H2

11 No Buf 2

3-2 MC Buffer 1

Bit-1 = 1

n/a

11 No Buf 2

3-2 MC Buffer 1

Bit-1 = 1

n/a

Bit-1 = 0

00

01

10

11

H0

H1

H2

n/a

F0

F1

F2

F3

00

01

10

11

H0

H1

H2

n/a

F0

F1

F2

F3

1

0

MC Buffer is Field

1

0

MC Buffer is Field

0

1

Not Field................................................ default

Field

0

1

Not Field ................................................default

Field

MC Status

MC Command in Queue

0

1

Not in progress....................................... default

In Progress

0

1

Disable ...................................................default

Enable

The bit definitions above are valid only when bit-0 is equal to

1. When hardware clears bit-0, bit definitions revert to those

defined by the “MC Command Queue” register defined in the

left hand column of this page.

This register changes definition when written with bit-0 = 1.

This address then becomes “MC Status” with the definition of

the bits matching the following bit definitions until MC-Status

bit-0 is cleared by hardware.

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Port 228B-2288 – MC Y-Reference Address ..................RW

31-20 Reserved

........................................ always reads 0

Port 22AB-22A8 – Color Palette Entries........................ RW

19-0 Y-Reference Start Address (quadword aligned)

Port 22B3-22B0 – SP BUF0 Pixel Start Address ........... RW

Port 22B7-22B4 – SP BUF1 Pixel Start Address ........... RW

Port 228F-228C – MC U-Reference Address..................RW

31-20 Reserved

........................................ always reads 0

19-0 U-Reference Start Address (quadword aligned)

Port 2293-2290 – MC V-Reference Address...................RW

31-20 Reserved

........................................ always reads 0

19-0 V-Reference Start Address (quadword aligned)

Port 22BB-22B8 – SP BUF0 Command Start Address . RW

Port 22BF-22BC – SP BUF1 Command Start Address. RW

Port 2297-2294 – MC Display Y-Address Offset............RW

31-20 Reserved

19-0 Y Address Offset

Y address offset (quadword aligned) of first display

........................................ always reads 0

Port 22C1-22C0 – SP Y Display Offset........................... RW

pixel relative to the first pixel (top left hand corner)

of the picture.

Port 22D0 – Digital TV Encoder Control....................... RW

Port 22D3-22D1 – Digital TV Encoder CFC.................. RW

Port 229B-2298 – MC Display U-Address Offset ...........RW

31-20 Reserved

19-0 U Address Offset

U address offset (quadword aligned) of first display

........................................ always reads 0

pixel relative to the first pixel (top left hand corner)

of the picture.

Port 229F-229C – MC Display V-Address Offset...........RW

31-20 Reserved

19-0 V Address Offset

V address offset (quadword aligned) of first display

........................................ always reads 0

pixel relative to the first pixel (top left hand corner)

of the picture.

Port 22A0 – MC H Macroblock Count ...........................RW

7-0 Number of Horizontal Macroblocks

Port 22A2 – MC V Macroblock Count............................RW

7-0 Number of Vertical Macroblocks

Port 22A5-22A4 – MC Frame Buffer Y Length .............RW

15-0 Number of Pixels in a Y Frame

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VGA Status / Enable Registers

Port 3C2 – VGA Input Status 0........................................ RO

Vertical Retrace Interrupt Pending

VGA Registers

Attribute Controller Registers (AR)

7

6-5 Reserved

........................................always reads 0

For this indexed register group, the index is accessed at 3C0

as expected. However, although data operations can be

performed using port 3C1 in the standard way, data is

generally accessed at 3C0 as well. In other words, data and

address are accessed on alternate operations to 3C0 with an

internal flag to keep track of where the next operation is to be

performed. The state of the internal flag may be read back in

the extended registers (see CR24). To set the internal flag to

select the index (i.e., to set the flag so that the next access to

port 3C0h points to the index register), read port 3BAh or

3DAh (depending on the state of the color / mono bit in the

4

Switch Sense

3-0 Reserved

........................................always reads 0

Port 3xA – VGA Input Status 1........................................ RO

This register is accessible at either 3BA or 3DA (shorthand

notation 3xA) depending on the setting of Miscellaneous

Output Register at 3C2[0].

7-6 Reserved

5-4 Diagnostic

3

2-1 Reserved

0

........................................always reads 0

Vertical Retrace

........................................always reads 0

Display Enable (Inverted)

Miscellaneous Output Register at 3C2[0]).

Attribute

Controller register data may be read at 3C1 (the internal flag is

not toggled) but must be written at 3C0.

Port 3C0 – VGA Attribute Controller Index..................RW

Port 3C2 – VGA Miscellaneous Output Register (Write)WO

Port 3CC – VGA Miscellaneous Output Register (Read)RO

7-6 Reserved

........................................ always reads 0

5

Palette Address Source

7

6

5

4

Vertical Sync Polarity

Horizontal Sync Polarity

Page Bit for Odd / Even

4-0 Attribute Controller Index

Only the lower 5 bits are implemented to allow access

to Attribute Controller registers 0-14h.

Reserved

........................................always reads 0

Port 3C0/3C1 Index 0-F – Attr Ctrlr Color Palette .......RW

3-2 Clock Select

7-6 Reserved

5-0 Color Value

........................................ always reads 0

1

0

Enable RAM

I/O Address Select

0

1

CRTC registers at 3Bx, Input Status 1 at 3BA

CRTC registers at 3Dx, Input Status 1 at 3DA

Port 3C0/3C1 Index 10 – Attr Ctrlr Mode Control .......RW

7

6

5

4

3

2

1

0

P5 / P4 Select

Pixel Width

Pixel Panning Compatibility

Port 3C3 – VGA Video Subsystem Enable ..................... RW

7-1 Reserved

........................................always reads 0

Video Subsystem Enable

Reserved

........................................ always reads 0

Select Background Intensity or Enable Blink

Enable Line Graphics Character Mode

Display Type

0

Port 46E8h – VGA Display Adapter Enable .................. RW

Graphics / Text Mode

7-4 Reserved

........................................always reads 0

Port 3C0/3C1 Index 11 – Attr Ctrlr Overscan Color.....RW

7-0 Overscan Color

3

Display Adapter Enable

2-0 Reserved

........................................always reads 0

Port 3C0/3C1 Index 12 – Attr Ctrlr Color Plane Ena ...RW

7-6 Reserved

........................................ always reads 0

5-4 Video Status Mux

3-0 Color Plane Enable for Color Planes 3-0

Port 3C0/3C1 Index 13 – Attr Ctrlr H Pixel Panning....RW

7-4 Reserved

........................................ always reads 0

3-0 Horizontal Pixel Pan

Port 3C0/3C1 Index 14 – Attr Ctrlr Color Select...........RW

7-4 Reserved

........................................ always reads 0

3-0 Color Select Bits 7-4

Revision 1.3 September 8, 1999

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VGA Registers

VT8601 Apollo ProMedia

VGA Sequencer Registers (SR)

VGA RAMDAC Registers

Port 3C4 – VGA Sequencer Index ...................................RW

Port 3C6 – VGA RAMDAC Pixel Mask......................... RW

7-0 Palette Address Mask

7-0 Sequencer Index

Only the lower 3 bits are implemented in a standard

VGA to point to Sequencer registers 0-4. However,

all 8 bits are implemented here to allow for extended

registers up to index FF.

Port 3C6 – VGA RAMDAC Command.......................... RW

This register is a non-standard VGA register (“extension

register”) located at the same port address as the VGA

Port 3C5 Index 0 – Sequencer Reset................................RW

RAMDAC Pixel Mask register.

In order to maintain

7-2 Reserved

1

0

........................................ always reads 0

Synchronous Reset

Asynchronous Reset

compatibility with standard VGA operations, access to this

register is restricted: access is enabled by performing four

successive accesses to the Pixel Mask register at 3C6 (i.e.,

read 3C6 four times).

Port 3C5 Index 1 – Sequencer Clocking Mode...............RW

7-6 Reserved

........................................ always reads 0

7-4 Color Mode Select

5

4

3

2

1

0

Screen Off

Shift 4

Dot Clock

Shift Load

Reserved

0000 Pseudo-Color Mode............................... default

0001 Hi-Color Mode (15-bit direct interface)

0010 Muxed Pseudo-Color Mode (16-bit pixel bus)

0011 XGA Color Mode (16-bit direct interface)

01xx -reserved-

........................................ always reads 0

8/9 Dot Clocks

10xx -reserved-

1100 -reserved-

1101 True Color Mode (24-bit direct interface)

111x -reserved-

Port 3C5 Index 2 – Sequencer Map Mask ......................RW

7-4 Reserved

........................................ always reads 0

Enable Map 3

Enable Map 2

3

2

1

0

3

2

Reserved

........................................always reads 0

DAC Disable

Enable Map 1

Enable Map 0

0

1

DAC On (if SR20[0] = 1)...................... default

DAC Off

1

0

Reserved

........................................always reads 0

RAMDAC Enable

Port 3C5 Index 3 – Sequencer Character Map Select....RW

7-6 Reserved

........................................ always reads 0

Character Map Select A

Character Map Select B

0

1

Disable (Bypass) RAMDAC.................. default

Enable RAMDAC

5

4

3-2 Character Map Select A

1-0 Character Map Select B

Port 3C7 – VGA RAMDAC Read Index ........................WO

Port 3C8 – VGA RAMDAC Write Index .......................WO

Port 3C5 Index 4 – Sequencer Memory Mode................RW

7-4 Reserved

........................................ always reads 0

3

2

1

0

Chain 4

Odd / Even

Port 3C8 – VGA RAMDAC Index Readback ................. RO

7-0 RAMDAC Index

Extended Memory

Reserved

........................................ always reads 0

Port 3C9 Index 0-FF – RAMDAC Color Palette ........... RW

7-0 RAMDAC Color Data

There are 768 data entries in the palette consisting of 256

three-byte entries. R, G, and B 8-bit values are accessed on

successive operations to this port with the index

autoincremented after every 3 accesses. Refer to a VGA

programmers guide for further information.

Revision 1.3 September 8, 1999

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VGA Registers

VT8601 Apollo ProMedia

VGA Graphics Controller Registers (GR)

Port 3CE – VGA Graphics Controller Index..................RW

Port 3CF Index 5 – Graphics Controller Mode ............. RW

7

Reserved

........................................ always reads 0

6-0 Graphics Controller Index

7

6

5

4

3

2

Reserved

........................................always reads 0

256 Color Mode ........................................default = 0

Shift Register ............................................default = 0

Odd / Even ..............................................default = 0

Read Mode ..............................................default = 0

Only the lower 4 bits are implemented in a standard

VGA to allow access to Graphics Controller registers

0-8. However, 7 bits are implemented here to allow

for extended registers up to index 7F.

Reserved

........................................always reads 0

1-0 Write Mode ..............................................default = 0

Port 3CF Index 0 – Graphics Controller Set / Reset......RW

Port 3CF Index 6 – Graphics Controller MiscellaneousRW

7-4 Reserved

........................................ always reads 0

3-0 Set / Reset Planes 3-0

7-4 Reserved

........................................always reads 0

3-2 Memory Map

Port 3CF Index 1 – Graphics Controller Set / Reset EnaRW

1

0

Chain Odd Maps to Even

Graphics Mode

7-4 Reserved

........................................ always reads 0

3-0 Enable Set / Reset Planes 3-0

Port 3CF Index 7 – Graphics Ctrlr Color Don’t Care .. RW

7-4 Reserved

........................................always reads 0

Port 3CF Index 2 – Graphics Controller Color CompareRW

7-4 Reserved

........................................ always reads 0

3-0 Color Don’t Care Planes 3-0

3-0 Color Compare Planes 3-0

Port 3CF Index 8 – Graphics Controller Bit Mask........ RW

7-0 Bit Mask

Port 3CF Index 3 – Graphics Controller Data Rotate ...RW

7-4 Reserved

........................................ always reads 0

3

Function Select

2-0 Rotate Count

Port 3CF Index 4 – Graphics Ctrlr Read Map Select....RW

7-2 Reserved

........................................ always reads 0

1-0 Map Select

Revision 1.3 September 8, 1999

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VGA Registers

VT8601 Apollo ProMedia

VGA CRT Controller Registers (CR)

Port 3x5 Index A – VGA CRTC – Cursor Start ............ RW

CRTC registers are accessible at either 3B4 / 3B5 or 3D4 /

3D5 (shorthand notation 3x4 / 3x5) depending on the setting

of Miscellaneous Output Register 3C2 bit-0

7-6 Reserved

5

........................................always reads 0

Cursor On/Off ..........................................default = 0

4-0 Cursor Row Scan Start............................default = 0

Port 3x5 Index B – VGA CRTC – Cursor End .............. RW

Port 3x4 – VGA CRT Controller Index ..........................RW

7

Reserved

........................................always reads 0

7-0 CRT Controller Index

6-5 Cursor Skew..............................................default = 0

4-0 Cursor Row Scan End..............................default = 0

Only the lower 5 bits are implemented in a standard

VGA to allow access to CRTC registers 0-18h.

However, all 8 bits are implemented here to allow for

extended registers up to index FF.

Port 3x5 Index C / D – VGA CRTC Start Addr Hi/Lo.. RW

..............................................default = 0

Port 3x5 Index 0 – VGA CRTC – H Total ......................RW

Port 3x5 Index E / F – VGA CRTC Cursor Loc Hi/Lo . RW

7-0 Horizontal Total....................................... default = 0

..............................................default = 0

Port 3x5 Index 1 – VGA CRTC – H Display Ena End...RW

Port 3x5 Index 10 – VGA CRTC – V Retrace Start ...... RW

7-0 Horizontal Display Enable End .............. default = 0

7-0 Vertical Retrace Pulse Start....................default = 0

Port 3x5 Index 2 – VGA CRTC – H Blank Start............RW

Port 3x5 Index 11 – VGA CRTC – V Retrace End........ RW

7-0 Horizontal Blanking Start....................... default = 0

7

6

5

4

CR0-7 Write Protect ................................default = 0

Reserved

........................................always reads 0

Vertical Interrupt Enable ........................default = 0

Vertical Interrupt Clear ..........................default = 0

Port 3x5 Index 3 – VGA CRTC – H Blank End .............RW

7

Reserved

........................................ always reads 0

6-5 Display Enable Skew................................ default = 0

4-0 Horizontal Blanking End......................... default = 0

3-0 Vertical Retrace Pulse End......................default = 0

Port 3x5 Index 12 – VGA CRTC – V Display Ena End RW

Port 3x5 Index 4 – VGA CRTC – H Retrace Start.........RW

7-0 Vertical Display Enable End ...................default = 0

7-0 Horizontal Retrace Pulse Start.........default = 0FFh

Port 3x5 Index 13 – VGA CRTC – Offset....................... RW

Port 3x5 Index 5 – VGA CRTC – H Retrace End ..........RW

7-0 Display Screen Logical Line Width ........default = 0

7

Horizontal Blanking End......................... default = 0

6-5 Horizontal Retrace Delay........................ default = 0

4-0 Horizontal Retrace Pulse End................. default = 0

Port 3x5 Index 14 – VGA CRTC – Underline Location RW

7

6

5

Reserved

........................................always reads 0

Port 3x5 Index 6 – VGA CRTC – V Total.......................RW

Double Word Mode..................................default = 0

Count By 4 .............................................default = 0

7-0 Vertical Total ........................................... default = 0

4-0 Underline Location...................................default = 0

Port 3x5 Index 7 – VGA CRTC – Overflow....................RW

Port 3x5 Index 15 – VGA CRTC – V Blank Start ......... RW

7

6

5

4

3

2

1

0

Vertical Retrace Start Bit-9 .................... default = 0

Vertical Display Enable End Bit-9.......... default = 0

Vertical Total Bit-9 .................................. default = 0

Line Compare Bit-8 ................................. default = 0

Vertical Blank Start Bit-8 ....................... default = 0

Vertical Retrace Start Bit-8 ................... default = 0

Vertical Display Enable End Bit-8.......... default = 0

Vertical Total Bit-8 .................................. default = 0

7-0 Vertical Blanking Start............................default = 0

Port 3x5 Index 16 – VGA CRTC – V Blank End........... RW

7-0 Vertical Blanking End..............................default = 0

Port 3x5 Index 17 – VGA CRTC – Mode Control......... RW

7

6

5

4

Hardware Rese .........................................default = 0

Word / Byte Mode ....................................default = 0

Address Wrap...........................................default = 0

VSYNC Update Select (VGA Extended Capability)

Port 3x5 Index 8 – VGA CRTC – Preset Row Scan.......RW

Reserved

........................................ always reads 0

7

0

1

Base may only be updated during Vsync.....def

Base address may be updated during Hsync

6-5 Byte Panning ............................................ default = 0

4-0 Preset Row Scan....................................... default = 0

3

2

1

0

Count By 2 ..............................................default = 0

Horizzontal Retrace Select ......................default = 0

Select Row Scan Counter.........................default = 0

Compatibility Mode Support...................default = 0

Port 3x5 Index 9 – VGA CRTC – Max Scan Line..........RW

7

6

5

200 to 400 Line Conversion..................... default = 0

Line Compare Bit-9 ................................. default = 0

Vertical Blank Start Bit-9 ....................... default = 0

Port 3x5 Index 18 – VGA CRTC – Line Compare ........ RW

4-0 Maximum Scan Line................................ default = 0

7-0 Line Compare ...........................................default = 0

Revision 1.3 September 8, 1999

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VGA Registers

VT8601 Apollo ProMedia

VGA Extended Registers

Port 3xB – Alternate Clock Select................................... RW

VGA Extended Registers – Non-Indexed I/O Ports

3xB notation indicates that this register is accessible at either

3BB or 3DB depending on the setting of the color / mono bit.

7-5 New Mode Control Register Bits 3-1 ..........def = 00

These bits have the same function as SRD[3-1]

Port 3D8 – Alternate Destination Segment Addr ...........RW

7

Reserved

........................................ always reads 0

6-0 Alternative Destination Segment Address . def = 00

Read / write of this register is enabled by GRF[2].

This register becomes active when GR6[3-2] are not 00.

4-2 Reserved

........................................always reads 0

1-0 Video Clock Select........................................def = 00

Port 3D9 – Alternate Source Segment Address ..............RW

7

Reserved

........................................ always reads 0

6-0 Alternative Source Segment Address......... def = 00

Read / write of this register is enabled by GRF[2].

This register becomes active when GR6[3-2] are not 00.

Revision 1.3 September 8, 1999

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VGA Extended Registers

VT8601 Apollo ProMedia

VGA Extended Registers – Sequencer Indexed

SR8 – Old / New Status......................................................RO

SRD – Mode Control 2 (Old)........................................... RW

7

6

Old / New Status (see SRB, SRC, SRD, SRE, GRE)

7-6 Reserved

........................................always reads 0

...................................... always reads 1

........................................always reads 0

0

1

Old .....................................................default

New

5

4

3

Reserved

Interlace Scan Field

CPU Bandwidth Select

0

1

Odd .....................................................default

Even

0

1

Normal................................................... default

Non-interrupted CPU access during VBLANK

........................................always reads 0

5

4

Reserved

........................................ always reads 0

2-0 Reserved

Command FIFO Empty

SRD – Mode Control 2 (New).......................................... RW

0

1

Empty.....................................................default

Not Empty

........................................ always reads 0

7-4 Display FIFO Memory Request Threshold Ctrl

0000 Empty 0 level

3-0 Reserved

0001 Empty 4 level......................................... default

0010 Empty 8 lrevel

0011 Empty 12 level

0100 Empty 16 level

0101 Empty 20 level

SR9 – Graphics Controller Version..................................RO

7-0 Version Number ............................. always reads 58h

0110 Empty 24 level

0111 Empty 28 level

1000 Empty 32 level

1001 Empty 36 level

1010 Empty 40 level

1011 Empty 44 level

1100 Empty 48 level

SRB – Version / Old-New Mode Control ........................RW

7-0 Graphics Controller Version #...... always reads F3h

A write to this register will change the Old / New Mode

Control registers (SRD, SRE, and GRE) to the “old”

definition. A read from this register will change the Old / New

Mode Control registers to the “new” definition.

1101 Empty 52 level

1110 Empty 56 level

1111 Empty 60 level

SRC – Configuration Port 1.............................................RW

3

Reserved

2-1 Video Clock Divide

00 Divide by 1 ............................................ default

........................................always reads 0

Access to this register is enabled by SRE_Old[5] = 1 (“Select

Configuration Port 1”) and writes are enabled by SRE_New[7]

= 1 (“Configuration Port Write Enable”).

01 Divide by 2

10 Divide by 4

11 Divide by 1.5

7

6

Reserved

.......................................always reads 1

Memory Bus Width

0

1

32-bit Memory Bus ................................default

64-bit Memory Bus

0

Reserved

........................................always reads 0

Note: Although the ProMedia integrated graphics

controller does not control memory directly (the

system memory controller is used to access graphics

memory as a portion of system memory), some

functional blocks in the graphics controller (such as

video) use this bit to manage their data bus widths.

5

4

Reserved

.......................................always reads 1

Video Subsystem Enable

0

1

46E8

3C3 .....................................................default

3

Video BIOS Size

0

1

64K .....................................................default

32K

2-0 Reserved

.................................always reads 111b

SRC – Configuration Port 2.............................................RW

Access to this register is enabled by SRE_Old[5] = 0 (“Select

Configuration Port 2”) and writes are enabled by SRE_New[7]

= 1 (“Configuration Port Write Enable”).

7-0 Reserved for BIOS

Revision 1.3 September 8, 1999

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VGA Extended Registers

VT8601 Apollo ProMedia

SRE – Mode Control 1 (Old)............................................RW

SRF – Power-up Mode 2 .................................................. RW

.......................................always reads 1

IRQ Polarity Select

Active High ............................................default

Active Low

Configuration Port (SR0C) Select

This register is write protected by SRE_New[7].

7

6

Reserved

7

6

Reserved

BIOS Control

...................................... always reads 1

0

1

0

1

Disabled................................................. default

Enabled

5

0

1

Select Port 2

Select Port 1 ..........................................default

5

4

Palette Mode

0

1

Master Abort Mode

Intel Retry Mode................................... default

4

3

Reserved

........................................ always reads 0

Memory Bus .........................................................RO

Linear / Bank Addressing Control

0

1

8-bit

0

1

Linear Only

Linear / Bank ........................................ default

16-bit .......................................always reads 1

2-1 256K Bank Select

00 Bank 0 ....................................................default

3-0 Reserved for BIOS ............................default = 1111

01 Bank 1

10 Bank 2

11 Bank 3

SR10 – VESA™ Big BIOS Control................................. RW

7

Extended VESA™ Big BIOS Enable

Note: an inverted value will be written to bit-1

These bits (and 3C2[5]) are write enabled when

GR06[3-2] = 00. 3C2[5] is used as a page select to

select one of the two 64KB pages.

RAMDAC Pixel Clock Invert

0

1

Disabled ................................................ default

Enabled

6-5 Video Address Select........................................... RO

00 A0000-A7FFF ....................................... default

01 -reserved-

0

1

Normal ...................................................default

Invert pixel clock to RAMDAC

10 B0000-B7FFF

11 B8000-BFFFF

These bits are decoded from GR6[3-2]

4-1 Reserved

Page Select

........................................always reads 0

0

SRE – Mode Control 1 (New)...........................................RW

0

1

Select the original C0000-C7FFF access.....def

Select extended access defined by bits 6-5

7

Configuration Port Write Enable........... default = 0

0

1

Write Protect

Write Enable

Bit-0 of this register is write protected by SRE_New[7].

Ports effected: SRC, SRF, CR28-2A, SRE_New[6-4]

(this register), and SR10[0]

6

CPU Bandwidth Select for Text Mode

SR11 – Protection ........................................................ RW

0

1

132-Column Text

Other Text .............................................default

7-0 Register Protection Enable....................default = 00

87 Unprotect all extended registers except those

which may still be protected by SRE_New[7]

92 Unprotect all extended registers independent

of SRE_New[7]

5-0 64K Bank Select ....................................... default = 0

Bit-1 should be inverted when performing writes

These bits are enabled when GR06[3-2] are written

with any value other than 00.

If any value other than the ones listed above is

programmed into this register, all extended registers

will be write protected.

SR12 – Threshold

........................................................ RW

7-4 Queue Threshold Playback and Capture .....def = 2

Threshold of the display queue when both playback

and capture are enabled (for definition see SRD.new).

3-0 Queue Threshold Playback or Capture........def = 1

Threshold of the display queue when either playback

or capture are enabled (for definition see SRD.new)

The old threshold is used when neither playback nor capture is

enabled. All three thresholds cannot be set to 0. Other

definitions are the same as the original.

Revision 1.3 September 8, 1999

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VGA Extended Registers

VT8601 Apollo ProMedia

Graphics Clock Synthesizer Control

SR18 – VCLK1 Frequency Control 0..............................RW

SR20 – Clock Synthesizer / RAMDAC Setup................. RW

7-0 VCLK1 Frequency Generator Numerator .... def=0

7

6

Reserved

........................................always reads 0

Multiplex Mode Sync Mechanism

SR19 – VCLK1 Frequency Control 1..............................RW

0

1

Normal Mode......................................... default

Enable synchronization in multiplexed mode

for high VCLK tracking

7-6 VCLK1 Frequency Generator K-Factor ....... def=0

5-0 VCLK1 Frequency Generator Denominator. def=0

5

4

3

2

Simultaneous VAFC and Playback

0

1

Simultaneous VAFC / playback display default

Playback only

SR1A – VCLK2 Frequency Control 0.............................RW

VAFC and Playback Display Overlay

7-0 VCLK2 Frequency Generator Numerator .... def=0

0

1

VAFC is on top...................................... default

Playback is on top

SR1B – VCLK2 Frequency Control 1.............................RW

DAC Test Mode

7-6 VCLK2 Frequency Generator K-Factor ....... def=0

5-0 VCLK2 Frequency Generator Denominator. def=0

0

1

Disable................................................... default

Enable

Video Mode

0

1

Disable................................................... default

Enable

1-0 Video Mode Select

x0 5-5-5 Hi-color..................................default = 0

x1 5-6-5 XGA-color

0x Video Playback, True-color

1x Video Playback, 256-color

Table 8. Graphics Clock Frequencies – 14.31818 MHz Reference

Denominator Numerator

Actual

Frequency

Expected

Frequency

Error %

Value

N

M

K

88

89

88

83

85

84

43

46

42

43

4A

48

46

44

42

44

04

07

02

03

05

3E

4F

5D

30

4A

42

43

48

1B

33

18

21

23

63

53

43

33

34

22

39

3B

42

44

4A

22

3C

19

22

3A

4B

5A

62

79

93

48

74

66

67

72

27

51

24

33

35

99

83

67

51

52

34

57

59

66

68

74

34

60

25

34

58

75

90

8

9

8

3

5

4

3

6

2

3

10

8

6

4

2

4

7

2

3

5

2

1

0

25.057

28.311

36.153

40.091

41.932

44.148

44.744

47.727

50.114

52.798

57.273

58.705

61.568

63.835

65.148

67.116

70.398

71.591

75.170

77.557

79.943

88.295

90.682

97.841

100.227

108.182

118.125

120.273

135.000

169.773

200.455

25.175

28.322

36.000

40.000

42.000

44.000

44.900

48.000

50.350

52.800

57.270

58.800

61.600

64.000

65.000

67.200

70.400

72.000

75.000

77.000

80.000

88.000

90.000

98.000

100.000

108.000

118.000

120.000

135.000

170.000

200.000

-0.0047

-0.0004

0.0043

0.0023

-0.0016

0.0034

-0.0035

-0.0057

-0.0047

0.0000

-0.0016

-0.0005

-0.0026

0.0023

-0.0012

0.0000

-0.0057

0.0023

0.0072

-0.0007

0.0034

0.0076

-0.0016

0.0023

0.0017

0.0011

0.0023

0.0000

-0.0013

0.0023

The clock frequency can be derived by multiplying the reference frequency times (N+8) / [(M+2) x 2^K]

Revision 1.3 September 8, 1999

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VGA Extended Registers

VT8601 Apollo ProMedia

Graphics Signature Analyzer Registers

Graphics Connector Control Registers

SR25 – Monitor Sense ....................................................... RO

7-3 Reserved

........................................always reads 0

SR21 – Signature Control.................................................RW

7

6

Signature Generator Enable

0

1

Disable (readback 0 indicates done).......default

Enable (readback 1 indicates busy)

2-0 Monitor Sense Result: [red, green, blue]

SR37 – Video Key Mode .................................................. RW

Signature Source Select

7

6

Feature Connector Input Clock Polarity

0

1

TV / CRT ...............................................default

LCD

0

1

Normal................................................... default

Inverted

5-0 Bit Select .............................................. default = 0

Signal Output (AFC Processing)

SR23-22 – Signature Data .................................................RO

15-0 Signature Data

0

1

Signal output is sent before AFC processingdef

Signal output is sent after AFC processing

5-4 Feature Connector Input Pixel Clock Tuning

00 0 ns .................................................... default

01 4 ns

Graphics Power Management Control Registers

10 8 ns

11 12 ns delay of pixel clock with respect to data

3-0 Overlay Key Type

SR24 – Power Management Control ...............................RW

7

6

RAMDAC Clock During RAMDAC Powerdown

0000 VGA Port Only...................................... default

0001 Color Key & Video Key

0010 Color Key & not Video Key

0011 Color Key

0100 Not Color Key & Video Key

0101 Video Key

0110 Color Key XOR Video Key

0111 Color Key | Video Key

1000 Not Color Key & Not Video Key

1001 Color Key XNOR Video Key

1010 Not Video Key

1011 Color Key | Not Video Key

1100 Not Color Key

1101 Not Color Key | Video Key

1110 Not Color Key | Not Video Key

1111 Video Port Only

0

1

14.318 MHz ..........................................default

14.31818 MHz divided by 2

Enable VCLK2 VCO Directly

(without warmup sequence)

0

1

Enable

Don’t Enable ..........................................default

5-4 Clock Input Divisor

Divisor for 14.318 MHz clock input to MCLK to

drive DRAM refresh cycles in power managed

modes.

00 1

01 2

10 4

11 8

.....................................................default

3

2

Power Management Slow MCLK

0

1

Use divided MCLK during standby & suspend

Use MCLK during standby & suspend........ def

SR38 – Advanced Feature Connector (AFC) Control... RW

Enable MCLK VCO Directly

7

6

Reserved

........................................always reads 0

DCLK Rate (set after other bits for syncronization)

(without warmup sequence)

0

1

Enable

0

1

PCLK .................................................... default

PCLK / 2

Don’t Enable .........................................default

1

0

Enable MCLK VCO Directly

(without warmup sequence)

5

4

3

DCLK Phase Select (if bit-6 = 1)

0

1

180 degree phase shift ........................... default

In phase

0

1

Enable

Don’t Enable .........................................default

DCLK Output Polarity

DAC Power

0

1

Normal when bit-6 = 0........................... default

Inverted

0

1

Off .....................................................default

On

VCLK Input Polarity

0

1

Normal................................................... default

Inverted

2-1 Reserved

........................................always reads 0

0

Pixel Data Bus Output Enable Control

0

1

Disable Output Drive............................. default

Disable drive only when EVIDEO# is low

Revision 1.3 September 8, 1999

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VGA Extended Registers

VT8601 Apollo ProMedia

Graphics Playback Control Registers

Graphics Second Playback Control Registers

SR52-50 – Playback Color Key Data...............................RW

SR62-60 – 2^ndPlayback Color Key Data ........................ RW

23-16 Playback Color Key for True Color Mode

15-8 Playback Color Key for High Color Mode

7-0 Playback Color Key for 256 Color Mode

23-16 Playback Color Key for True Color Mode

15-8 Playback Color Key for High Color Mode

7-0 Playback Color Key for 256 Color Mode

SR56-54 – Playback Color Key Mask .............................RW

SR66-64 – 2^ndPlayback Color Key Mask....................... RW

23-16 Playback Color Key Mask for True Color Mode

15-8 Playback Color Key Mask for High Color Mode

7-0 Playback Color Key Mask for 256 Color Mode

23-16 Playback Color Key Mask for True Color Mode

15-8 Playback Color Key Mask for High Color Mode

7-0 Playback Color Key Mask for 256 Color Mode

SR57 – Playback Video Key Mode Function ..................RW

7-0 Overlay Key Type

Defines all 256 defferent types of mixing among

VGA Color Key, Playback Window Key, and Video

Chroma Key (very similar to ROP3 code). Below

are some common combinations:

00 VGA Port Only

F0 Color Key Only

CC Playback Key Only

AA Chromakey Only

88 Playback Key & Chromakey

C0 Colorkey & Playback Key

80 Colorkey & Playback key & Chromakey

FF Video Port Only

Graphics BIOS Scratch Pad Registers

SR5A – Scratch Pad 0.......................................................RW

SR5B – Scratch Pad 1 .......................................................RW

SR5C – Scratch Pad 2.......................................................RW

SR5D – Scratch Pad 3.......................................................RW

SR5E – Scratch Pad 4 .......................................................RW

SR5F – Scratch Pad 5 .......................................................RW

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Graphics Video Display Registers

SR82-80 – Window 1 U-Plane FB Start Address............RW

SR8C-8B – Window 2 Vertical Scaling Factor .............. RW

15 W2 Vertical Minify / Zoom Select

23-20 Reserved

........................................ always reads 0

0

1

Zoom .................................................... default

Minify

19-0 W1 U-Plane FB Start Address

When operating in planar mode, this field defines the

frame buffer starting address for the U-plane for the

first live video window

14 W2 Vertical Filtering

0

1

Off .................................................... default

On

SR85-83 – Window 1 V-Plane FB Start Address............RW

Zoom Selected (Bit-15 = 0)

13-0 W2 Vertical Zoom Factor

Same format as for the first live video window as

defined in CR82 and CR83

23-20 Reserved

........................................ always reads 0

19-0 W1 V-Plane FB Start Address

When operating in planar mode, this field defines the

frame buffer starting address for the V-plane for the

first live video window

Minify Selected (Bit-15 = 1)

13-10 Reserved

9-0 W2 Vertical Minify Factor

SR88-86 – Window 2 Frame Buffer Start Address ........RW

23-20 Reserved

........................................ always reads 0

SR90-8D – Window 2 Live Video Start .......................... RW

19-0 Window 2 Frame Buffer Start Address

Frame buffer starting address for the second live

video window (packed YUV format only)

31-28 Reserved

........................................always reads 0

27-16 W2 Vertical Starting Point

15-12 Reserved

........................................always reads 0

11-0 W2 Horizontal Starting Point

SR8A-89 – Window 2 Horizontal Scaling Factor...........RW

15 W2 Horizontal Minify / Zoom Select

SR94-91 – Window 2 Live Video End............................. RW

0

1

Zoom .....................................................default

Minify

31-30 W2 Line Buffer Level Bits 8-7 (see SR95)

29-28 Reserved

........................................always reads 0

27-16 W2 Vertical Ending Point

........................................always reads 0

11-0 W2 Horizontal Ending Point

Zoom Selected (Bit-15 = 0)

14 Reserved

13-0 W2 Horizontal Zoom Factor

Same format as for the first live video window as

defined in CR80 and CR81

15-12 Reserved

SR95 – Window 2 Live Video Line Buffer Level ........... RW

7

Reserved

........................................always reads 0

6-0 W2 Line Buffer Level Bits 6-0 (see SR91[31-30])

Minify Selected (Bit-15 = 1)

14-13 W2 Tap

12-10 W2 Horizontal Minify Integer (Inverter)

9-0 W2 Horizontal Minify Factor

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SR96 – New Live Video Window Control 0....................RW

SR98 – New Live Video Window Control 2 ................... RW

7

W2 Horizontal Interpolation

7-6 Two Live Window Chroma Key Select

00 Chroma key only.................................... default

01 Window 1 & chroma key

0

1

Interpolation...........................................default

Duplication

6

W1 Vertical Interpolation U and V Components

10 Window 2 & chroma key

0

1

Enable.....................................................default

Disable

11 (Window 1 | Window 2) & chroma key

5-4 W1 Anti-Flicker Removal

This bit is effective only if window 1 vertical Y

interpolation is enabled (CR8E[12] = 1)

00 Disable................................................... default

01 One field is shifted up 1 line

5

4

Reserved

656

........................................ always reads 0

10 One field is shifted up 2 lines

11 One field is shifted up 3 lines

0

1

Disable ...................................................default

Enable

3

W1 Anti-Flicker Removal Field Selection

0

1

Odd field is shifted up ........................... default

Even field is shifted up

3

W2 Color Space Converter (CSC) Bypass

0

1

Disable ...................................................default

Enable

2-1 W2 Anti-Flicker Removal

00 Disable................................................... default

01 One field is shifted up 1 line

2

1

Reserved

........................................ always reads 0

10 One field is shifted up 2 lines

11 One field is shifted up 3 lines

W2 Anti-Flicker Removal Field Selection

MC Even / Odd Inverter

0

1

Disable ...................................................default

Enable

0

1

Odd field is shifted up ........................... default

Even field is shifted up

0

MC Interlace Display

0

1

Disable ...................................................default

Enable

SR99 – New Live Video Window Control 3 ................... RW

SR97 – New Live Video Window Control 1....................RW

7

6

Reserved

........................................always reads 0

Capture Addres Swap Enable

Disable................................................... default

Enable

Capture Address Swap

7

6

Reserved

........................................ always reads 0

Planar Mode X (Horizontal) Y/UV Ratio

0

1

0

1

2x

4x

.....................................................default

5

0

1

No swap................................................. default

Swap

5-4 Planar Mode Y (Vertical) Y/UV Ratio

00 2x (Yp420).............................................default

01 4x (Yp410)

4-2 W2 HDE Delay Adjust.............................default = 0

........................................always reads 0

1x 1x (Yp422)

1-0 Reserved

3

Reserved

........................................ always reads 0

2-0 Window Mode .................................... default = 000b

Format

000 YUV422

001 Planar

01x YUV

100 MPEG2 YUV422 H-V

101 MPEG2 Planar

11x YUV422

Interpolation Line Buffers

SR9B-9A – Window 1 UV Video Row Byte Offset........ RW

15-14 Reserved

........................................always reads 0

13-0 W1 UV Plane Video Row Byte Offset (the bytes in

H-V

FIFO H

(96+48) x 64

96 x 64

a row)

2x(96+48)x64

H-V

SR9D-9C – Window 2 Y Video Row Byte Offset........... RW

H-V (V-YUV) 2x(96+48)x64

15-14 Reserved

........................................always reads 0

For 1xx, only one h/w overlay window is supported

13-0 W2 Y Plane Video Row Byte Offset (the bytes in a

row)

SR9E – Line Buffer Request Threshold.......................... RW

7

Reserved

........................................always reads 0

6-0 Line Buffer Request Threshold Level...........def = 0

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SR9F – VBI Control .........................................................RW

SRAD-AC – VBI Vertical Interrupt Position................. RW

7

6

5

4

3

VBI Interrupt Status............................................RO

15 Reserved

14-12 Dithering Mode

000 Bypass dithering .................................... default

........................................always reads 0

Reserved

........................................ always reads 0

VBI Bit-8

VBI IV Bit-8

VBI Interrupt

001 -reserved-

010 24 bpp dither to 16 bpp

011 24 bpp chop to 16 bpp

100 24 bpp dither to 15 bpp

101 24 bpp chop to 15 bpp

110 24 bpp dither to RGB8

111 24 bpp chop to RGB8

0

1

Disable ...................................................default

Enable

2

VBI Enable

0

1

Disable ...................................................default

Enable

1-0 VBI Data Format in Frame Buffer

00 Every field data overwrite ......................default

01 Data in even/odd format

11 Capture CSC

Disable................................................... default

Enable

10-0 VINST[10-0]

0

1

10 Every two field data write contiguous

11 -reserved-

SRA3-A0 - VBI Frame Buffer Address...........................RW

31-20 VBI Row Byte Offset

19-0 VBI Start Address

SRA7-A4 – VBI Capture Start.........................................RW

31-27 Reserved

........................................ always reads 0

26-16 VBI Vertical Start

15-11 Reserved

........................................ always reads 0

10-0 VBI Horizontal Start

SRAB-A8 – VBI Capture End..........................................RW

31-27 Reserved

........................................ always reads 0

26-16 VBI Vertical End

15-11 Reserved

........................................ always reads 0

10-0 VBI Horizontal End

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SRAF-AE – Capture Row Byte Offset ............................RW

15 Reserved

........................................ always reads 0

SRBD – Dual View Mux Control .................................... RW

7-3 Reserved

........................................always reads 0

14 Capture Address Initial Control

13-0 Capture Row Byte

2-0 CRT / TV View Multiplexing Control

00x Color key 1 determines top window (1=W1)def

010 Video window 1 overlay

011 Video window 2 overlay

10x Window key defines window 1 on top

11x Window key defines window 2 on top

SRB1-B0 – Window 1 HSB Control ................................RW

15-10 Brightness

9-5 Sin(Hue) * Saturation * 8 (bit-9 is the sign bit)

4-0 Cos(Hue) * Saturation * 8 (bit-4 is the sign bit)

Hue range is 0-360 degrees (default = 0)

Saturation range is 0-1.875 (default = 1)

SRBE – Miscellaneous Control Bits................................ RW

7

Planar Capture

0

1

Off .................................................... default

On

SRB3-B2 – Window 2 HSB Control ................................RW

15-10 Brightness

6-5 Capture Start Address W/R Control (CR98[19-

9-5 Sin(Hue) * Saturation * 8 (bit-9 is the sign bit)

4-0 Cos(Hue) * Saturation * 8 (bit-4 is the sign bit)

Hue range is 0-360 degrees (default = 0)

Saturation range is 0-1.875 (default = 1)

0])

0x W/R Y address....................................... default

10 W/R U address

11 W/R V address

4

Video Engine Power Saving Mode

0

1

On

.................................................... default

........................................always reads 0

SRB6-B4 – Second Display Address Select .....................RW

3

2

Reserved

Interpolation Bypass

23-20 Reserved

........................................ always reads 0

19-0 Second Display Address for Double Buffering

Second display address for double buffering instead

of capture address

0

1

Interpolation .......................................... default

Bypass

1

0

Window 2 HSCB Enable

0

1

Bypass ................................................... default

Enable

Window 1 HSCB Enable

SRB7 – Video Sharpness...................................................RW

7-0 Video Sharpness Factor

0

1

Bypass ................................................... default

Enable

SRBA-B8 – Second Capture Address Select...................RW

SRCE – Window 2 Live Video Control .......................... RW

23-20 Reserved

........................................ always reads 0

7

6

Reserved

........................................always reads 0

W2 Vertical Interpolation

19-0 Second Capture Address for Double Buffering

Second capture address for double buffering instead

of display address

0

1

Disable................................................... default

Enable

5

Planar Mode X (Horizontal) Y/UV Ratio

0

1

2x

4x

.................................................... default

SRBC – Contrast Control.................................................RW

7-4 Window 2 Contrast

3-0 Window 1 Contrast

4-3 Planar Mode Y (Vertical) Y/UV Ratio

00 2x (Yp420) ............................................ default

01 4x (Yp410)

1x 1x (Yp422)

2-0 Window Mode ....................................default = 000b

Format

000 YUV422

001 Planar

01x YUV

Interpolation Line Buffers

H-V

(96+48) x 64

96 x 64

FIFO H

100 MPEG2 YUV422 H-V

2x(96+48)x64

101 MPEG2 Planar

11x YUV422

H-V

H-V (V-YUV) 2x(96+48)x64

For 1xx, only one h/w overlay window is supported

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SRD1-D0 – Window 2 UV Row Byte Offset ...................RW

15-14 Reserved

........................................ always reads 0

SRDB-DA – Window 2 V-Count Status........................... RO

15-0 W2 V Count Status

13-0 W2 UV Plane Video Row Byte Offset (the bytes in

SRDD-DC – Dual View Control...................................... RW

a row)

15-11 Reserved

........................................always reads 0

10-9 Dual View Control - SHIF

8

7

6

5

4

3

2

1

0

Dual View Control – G Window Enable

SRD4-D2 – Window 2 U-Frame Start Address ..............RW

Dual View Control – W2 Double Buffer Enable

Dual View Control – W1 Double Buffer Enable

Dual View Control – W2 Address Trans Enable

Dual View Control – W1 Address Trans Enable

Dual View Control – Digital TV Enable

Dual View Control – Digital Video LUT Write

Dual View Control – Digital Video LUT Read

Dual View Control – Digital Video CRT

23-20 Reserved

........................................ always reads 0

19-0 W2 U-Frame Start Address

SRD7-D5 – Window 2 V-Frame Start Address ..............RW

23-20 Reserved

........................................ always reads 0

19-0 W2 V-Frame Start Address

SRD9-D8 – Digital TV Interface Control........................RW

SRDF-DE – Window 1 V-Count Status........................... RO

(see also CRD0, VGA / Digital TV Sync Control)

15-13 Reserved

12 DVV Sync

........................................always reads 0

15-14 Reserved

........................................ always reads 0

11-0 W1 V Count Status

13 DIVS I/O Control

12 DTVI Signal Output Control, except DIVS

(Vsync)

11 Dual View Clock Inversion Control

10 Dual View Clock Control for DTVI

9

8

7

DICLK Inversion Control

DIVS Inversion Control

DIHS Inversion Control

6-5 YUV Order Inversion Control

4, 1 Data Out Control

00 VGA / Video Overlay Data

x1 TV Data

10 Data Direct from Video Engine

3-0 HS / VS / CLK Control

0000 VGAHS, VGAVS, and PCLK

x100 VGAHS, VGAVS, and SPKTV

1000 VGAHS, VGAVS, and PCLK x 2

xxx1 DVHS, DVVS, and LCDCLK

xx10 TVHS, TVVS, and TVCLK

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VGA Extended Registers

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VGA Extended Registers – Graphics Controller Indexed

GRE – Old Source Segment Address...............................RW

GRF – Miscellaneous Extended Function Control ........ RW

7-3 Reserved

2-1 Source Segment Address Select .............. default = 0

Reserved

........................................ always reads 0

7

6

Reserved

........................................always reads 0

Character Clock Division Control Bit-1 (see bit-3)

00 No division ............................................ default

01 Divide by 2

0

10 Divide by 3

11 -reserved-

Symmetric / Asymmetric DRAM Address

GRE – New Source Segment Address..............................RW

Reserved

........................................ always reads 0

5

4

7

0

1

Symmetric.............................................. default

Asymmetric

6-0 Source Segment Address Select .............. default = 0

Bit-1 is written inverted

Compressed Chain 4 Mode for CPU Path

0

1

Disable................................................... default

Enable

3

2

Character Clock Division Control Bit-0 (see bit-6)

Alternate Bank & Clock Select

0

1

Disable 3D8, 3D9, and 3xB................... default

Enable 3D8, 3D9, and 3xB

1

0

Compressed Chain 4 Mode Display Path

0

1

Disable................................................... default

Enable

Source Segment Address Register Enable

0

1

Disable GRE.......................................... default

Enable GRE

All bits except 2 and 0 are write protected by SRE_New[7]

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Power Management Registers

GR20 – Standby Timer Control.......................................RW

GR22 – Power Management Control 2........................... RW

7

Timer Initialize & Enable

7

Timer Test Mode

0

1

Enable Timer..........................................default

Initialize and hold standby and DPMS timer

0

1

Disable................................................... default

Enable

6-4 Timer Testing .......................................................RO

3-0 Reserved

........................................ always reads 0

6

Refresh Clock Select

0

1

Crystal input or external clock (XMCLK)

provides refresh clock during suspend... default

REFCLK is used as refresh clock during

suspend for 64ms refresh (ignore “Suspend

DRAM Refresh Mode” bits 5-4 below)

GR21 – Power Management Control 1 ...........................RW

Power Management Pin Polarity

7

6

5

4

3

2

1

0

1

Active High ............................................default

Active Low

5-4 Suspend DRAM Refresh Mode

00 No refresh.............................................. default

01 Self refresh

PCI Power Management

0

1

Disable ...................................................default

Enable

10 Crystal clock provides rate for 8ms refresh

11 Crystal clock provides rate for 64ms refresh

Disable GPIO

Suspend Mode

0

1

Normal mode..........................................default

Enter Suspend Mode

3

0

1

Allow GPIO 7-0 pins to drive data in.... default

Suspend Input Pin

Disable GPIO 7-0 pins (and their shared

functions) from driving data. Tristates input

buffers on pins so no power is consumed if

GPIO pins are set to input mode.

0

1

Disable ...................................................default

Enable

D3 to D0 Reset

0

1

Disable ...................................................default

Enable

2

1

Reserved

........................................always reads 0

Hardware / Software Oscillator Select

Standby Input Pin

0

1

Software controls oscillator off with bit-0

(prevents automatic oscillator shutdown

without direct software control of the

“Oscillator Disable” bit) .............................. def

Hardware controls oscillator off (allow

oscillator shutdown when power states are

entered using hardware mechanisms)

0

1

Disable ...................................................default

Enable

CLKRUN# Mechanism

0

1

Disable ...................................................default

Enable

Consistent Standby / Suspend

0

The bits in the PCI PM configuration registers

will be OR’ed with bits 5 and 3 of this register

for connection to the internal PM state

machine ..................................................default

The bits in the PCI PM configuration registers

will be the same as bits 5 and 3 of this register

to allow software coherency

0

Oscillator Disable

0

1

Enable normal function.......................... default

Disable (oscillator off)

1

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GR23 – Power Status ........................................................RW

Power Management Pin Polarity (see GR21[7])

GR24 – Software Power Control..................................... RW

7

6

5

VCLK

0

1

Disable

Enable................................................... default

6-5 Chip Power Status

00 Ready

01 Standby

10 Suspend

11 -reserved-

MCLK

0

1

Disable

Enable................................................... default

4

LCD Power Sequence Status

CPU & DRAM Data Bus

0

1

LCD power sequencing is not occurring at this

time

LCD power sequencing is occurring at this

time

0

1

Disable

Enable................................................... default

4

3

Reserved

........................................always reads 0

ENPBLT (Panel and/or Backlight Enable)

3-2 Panel Power Sequencing

00 Fast panel power sequencing..................default

Control

Software Power Control

01 -reserved-

10 -reserved-

0

1

Drive ENPBLT Low.............................. default

Drive ENPBLT High

11 Slow panel power sequencing

Hardware Power Control (timers, pin, register bit)

1-0 DPMS Power Status

0

1

ENPBLT is active low........................... default

ENPBLT is active high

00 On Mode (CRT interface is active and

RAMDAC is full on)..............................default

01 Standby Mode (Hsync disabled, Vsync active,

DAC off, RAMDAC color palette lookup

table (LUT) video data path is off but LUT

I/O is allowed)

10 Suspend Mode (Vsync disabled, Hsync active,

RAMDAC is off but contents are retained)

11 Off Mode (Hsync and Vsync disabled, DAC

LUT is full off)

2

1

0

Panel VDD

0

1

Disable................................................... default

Enable

Panel Interface Signals

0

1

Disable................................................... default

Enable

Panel VEE

0

1

Disable................................................... default

Enable

In hardware mode, these bits indicate the status of

CRT Hsync and Vsync as well as the internal

RAMDAC power state (the “off” mode state can be

read only in CRT only mode). In software mode,

these bits control the state of the CRT Hsync and

Vsync signals but not the power state of the internal

RAMDAC. In simultaneous display modes, the

power state of the RAMDAC is not controlled by the

DPMS Power State (bits 1-0), but by the Chip Power

State (bits 6-5).

GR25 – Power Control Select.......................................... RW

When any of bits 7-6 or 3-0 are set to 1, the corresponding

power control bit reads back the logic state of the internal

power management engine. For all bits below, 0 selects

hardware power control and 1 selects software power control.

7

6

5

4

Power Control for VCLK..............................def = 1

Power Control for MCLK ............................def = 1

Power Control for the Data Bus ...................def = 1

Power Control for the RAMDAC ................def = 1

The RAMDAC is software enabled in GR26[7-6]

Power Control for Panel Enable / Backlight def = 1

(see GR24[3])

3

2

1

0

Power Control for Panel VDD .....................def = 1

Power Control for Panel Interface Signals .def = 1

Power Control for Panel VEE ......................def = 1

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GR26 – DPMS Control.....................................................RW

DPMS Control Modes

7-6 RAMDAC Internal Power Control

00 Normal ...................................................default

01 DAC off (used in LCD only mode)

10 Standby (DAC off, LUT in low power mode,

I/O allowed to LUT). May be used in LUT

bypass mode.

DPMS Software Control Mode

In simultaneous display mode, the software control mode can

be used to control DPMS low power states independent of the

chip power states. In CRT display mode, software mode

gives total DPMS control to software. Pseudo-standby may

be controlled by bits 7 and 6, as well as BLANK# timing.

11 Suspend (DAC off, LUT access disallowed

but LUT contents are preserved)

DPMS Hardware Control Mode

5-4 Reserved

........................................ always reads 0

3

DPMS Control

Table 9. DPMS Sequence - Hardware Timer Mode

0

Software Control Mode: DPMS controlled by

GR23[1-0] in simultaneous display and CRT-

only modes (may be used to decouple the

power modes of the CRT and LCD during

simultaneous display) ..........................default

Hardware Control Mode: DPMS controlled

by internal power states.

Power Level

DPMS Mode

High - Activity detected

Moderate - 16 min inactivity

Low - 32 min inactivity

On

Standby

Suspend

Off

1

Lowest - 64 min inactivity

2-0 Reserved

........................................ always reads 0

DPMS hardware timer mode is defined as CRT only mode

with the DPMS control mode bit set to hardware (bit 3 =1).

Activity detection is set by register GR21[2:0]. Status is

indicated in bits 1 and 0. The timer may be controlled by

software from GR20[7].

Table 10. DPMS Sequence - Hardware Mode in

Simultaneous Display Mode

Power Level

DPMS Mode

High - Chip on state

Moderate - Chip standby

Low - Chip suspend

On

Off

Lowest - Chip off state

In simultaneous display mode with hardware DPMS

set, DPMS states are sequenced by the timer, pin, and

register bits that control the chip power states.

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GR28-27 – GPIO Control.................................................RW

15-8 GPIO Direction 7-0

GR2F – Miscellaneous Internal Control......................... RW

7

PCLK Control

0

1

Read .....................................................default

Write

0

1

VGA Compatible................................... default

PCLK equals VCLK

........................................always reads 0

Hsync Skew Control

7-0 GPIO Data 7-0.......................................... default = 0

6

5

Reserved

0

1

One skew in graphics, two skew in text. default

No skew

GR2A – Suspend Pin Timer .............................................RW

4-3 Reserved

........................................always reads 0

7

Motion Video Port Suspend

2

1

0

Double Logical Line Width

0

1

Disable ...................................................default

Enable

0

1

Disable................................................... default

Enable

6-0 Reserved

........................................ always reads 0

Text Mode Display FIFO Prefetch Cycles Select

0

1

Multiple of 8.......................................... default

Multiple of 4

Enable Display FIFO Threshold Control

GR2C – Miscellaneous Pin Control.................................RW

0

1

Disable................................................... default

Enable (can also be enabled by AR10[0])

7

6

Reserved

........................................ always reads 0

Use PDINV pin as GPIO5

0

1

Disable ...................................................default

Enable

5-4 Reserved

........................................ always reads 0

3

2

1

0

Use INT# pin as PSTATUS

0

1

Disable ...................................................default

Enable

Tristate P35-0, DE, SFCLK, LP, FLM

0

1

Tristate ...................................................default

Enable

Tristate ENPVEE, ENPVDD, ENPBLT

0

1

Tristate ...................................................default

Enable

Reserved

........................................ always reads 0

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Scratch Pad Registers

These registers are reserved for use by software.

GR5A – Scratch Pad 0 ......................................................RW

GR5B – Scratch Pad 1 ......................................................RW

GR5C – Scratch Pad 2 ......................................................RW

GR5D – Scratch Pad 3 ......................................................RW

GR5E – Scratch Pad 4 ......................................................RW

GR5F – Scratch Pad 5.......................................................RW

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VGA Extended Registers – CRT Controller Indexed

CRE – CRT Module Test..................................................RW

CR1A – Arbitration Control 1 ........................................ RW

7

6

5

Extended Memory Access Above 256KB

7-0 Display Queue Kill Counter ....................default = 0

Controls how many requests can be accepted by the

arbiter before changing the owner to another agent

(00 disables the counter).

0

1

Disable ...................................................default

Enable

VGA Misc Output Register (3C2) Write Protect

0

1

Writes to 3C2 Allowed...........................default

Write Protect 3C2

CR1B – Arbitration Control 2......................................... RW

7-0 High Priority Arbiter Kill Counter ........default = 0

Controls how many requests can be accepted by the

arbiter before changing the owner to another agent

(00 disables the counter).

CRT Start Address Bit-16

....................................... alwatys reads 0

Interlaced Mode

4-3 Reserved

2

0

1

Disable ...................................................default

Enable

CR1C – Arbitration Control 3 ........................................ RW

1-0 Reserved for Test (Do Not Program) .... default = 0

7-0 Low Priority Arbiter Kill Counter .........default = 0

Controls how many requests can be accepted by the

arbiter before changing the owner to another agent

(00 disables the counter).

CR19 – CRT Interlace Control........................................RW

7-0 Interlaced Vsync Adjust Value

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CR1F – Software Programming ......................................RW

7-4 Reserved

........................................ always reads 0

CR29 – RAMDAC Mode ................................................. RW

7

External DAC

0

1

Disable.................................................... defaul

Enable

3-0 Display Memory Size

0011 1MB

0111 2MB

6

Reserved

........................................always reads 0

1111 4MB

5-4 CRTC Offset[9:8] for High or True Color Modes

0100 8MB

3

GE I/O Decode

0

1

Disable.................................................... defaul

Enable

All other codes are reserved

Memory size is automatically detected during system setup.

2

RAMDAC

CR20 – Command FIFO...................................................RW

0

1

External .................................................. defaul

Internal

7-6 Reserved

........................................ always reads 0

5

Write Buffer

1-0 RS[3-2] for RAMDAC (if register access definition

is selected)

This register is write protected by SRE_New[7]

0

1

Disable ....................................................defaul

Enable

4

16-Bit Planar Mode

CR2A – Interface Select................................................... RW

0

1

Disable ....................................................defaul

Enable

7

6

Reserved

........................................always reads 0

Internal Data Path Width

3-0 Reserved

........................................ always reads 0

0

1

8/16-bit ................................................... defaul

32-bit

CR21 – Linear Addressing ...............................................RW

7-6 Reserved

........................................ always reads 0

5

4

Reserved

Power Down Mode Using ROMCS#

...................................... always reads 1

5

Linear Memory Access

0

1

Disable ....................................................defaul

Enable

0

1

Enable..................................................... defaul

Disable

4-0 Reserved

........................................ always reads 0

This register is write protected by SRE_New[7].

3-0 Reserved

........................................always reads 0

This register is write protected by SRE_New[7]

CR22 – CPU Latch Readback...........................................RO

7-0 Latched Data

Pointed to by GR4 (VGA Read Map Select Register

)

CR24 – VGA Attribute State.............................................RO

7

VGA Attribute State

0

1

Index ......................................................defaul

Data

6-0 Reserved

CR25 – RAMDAC Read/Write Timing...........................RW

PCLK / P[7-0] BufferTristate Control

........................................ always reads 0

7

0

1

Enable......................................................defaul

Disable

6-4 Reserved

........................................ always reads 0

3-0 RAMDAC Read / Write Wait States..... def =1111b

CR27 – CRT High Order Start Address.........................RW

7

6

5

4

3

Vertical Total Bit-10 ................................ default = 0

Vertical Blanking Start Bit-10 ............... default = 0

Vertical Retrace Start Bit-10 ................. default = 0

Vertical Display Enable End Bit-10 ....... default = 0

Line Compare Bit-10 .............................. default = 0

2-0 Start Address Bits 19-17 ......................... default = 0

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VT8601 Apollo ProMedia

CR2B – Horizontal Parameter Overflow........................RW

7-5 Reserved

........................................ always reads 0

CR35-34 – Graphics Engine I/O Linear Address Base . RW

15-0 Graphics Engine Linear Address Base...default = 0

4

3

2

1

0

Horizontal Blank Start Bit-8................... default = 0

Horizontal Retrace Start Bit-8 ............... default = 0

Horizontal Interlace Parameter Bit-8 ... default = 0

Horizontal Display Enable Bit-8 ............ default = 0

Horizontal Total Bit-8 ............................ default = 0

CR36 – Graphics Engine / Video Engine Control.......... RW

7

6

5

Graphics Engine

0

1

Disable................................................... default

Enable

CR2D – GE Timing Control.............................................RW

7-5 Reserved

........................................ always reads 0

PCI Video Minifier

0

1

Bypass ................................................... default

Go through minifier

4-3 GE Sample Clock Delay Selection .......... default = 0

2-0 GE Frame Buffer Read Delay Cycles..... default = 0

Video Aperture

CR2F – Performance Tuning ...........................................RW

0

1

Disable................................................... default

Enable

7

6

Reserved

........................................ always reads 0

DRAM Refresh Cycle Control Bit-1

(Bit-0 is CR11[6])

4

3

Graphics Engine Software Reset

Writing a one to this bit resets the graphics engine

Graphics Engine I/O

00 3 refresh cycles per horizontal line

01 5 refresh cycles per horizontal line

10 1 refresh cycles per horizontal line

11 2 refresh cycles per horizontal line

Blank TimingSelect

0

1

Disable................................................... default

Enable

2

String Write

0

1

Disable................................................... default

Enable

5

4

0

1

Normal blank..........................................default

Blank is the inverse of display enable

1-0 Graphics Engine Register Mapping

00 I/O mapped at 21xxh ............................. default

01 Memory mapped at B7Fxxh

Display FIFO Depth Control

0

1

32 deep...................................................default

8 deep

10 Memory mapped at BFFxxh

11 Memory mapped using the GE base register

3-2 Memory Read Ready Control

00 -reserved.................................................default

01 Fast read cycle (same as 10)

10 Fast read cycle (same as 01)

11 Normal read cycle

CR37 – I²C / SMB Control .............................................. RW

7

6

SMBCLK Buffer is Open Drain........always reads 1

1

Clock Source

I²C SMBCLK Status............................................RO

0

1

VCLK2

5-4 Reserved

........................................always reads 0

VCLK1 ..................................................default

3

I²C Operation

0

Pin Scan (Test Only) ................................ default = 1

0

1

Read .................................................... default

Write

2

1

Reserved

........................................always reads 0

I²C SMBCLK Signal

0

1

Low

High ................................................... default

0

I²C SMBDAT Signal

0

1

Low .................................................... default

High

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VT8601 Apollo ProMedia

CR38 – Pixel Bus Mode ....................................................RW

CR3A – Physical Address Control .................................. RW

7-6 Reserved

........................................ always reads 0

Packed 24-Bit True-Color Mode

Disable ...................................................default

Enable

Standard VGA Mode in 64-Bit Configuration

Disable ...................................................default

Enable

True Color Mode

Disable ...................................................default

Enable

High Color Mode

7

6

Reserved

........................................always reads 0

AGP / PCI Select

5

4

3

2

0

1

0

1

PCI .................................................... default

AGP

5

4

Both IO

0

1

0

1

Disable................................................... default

Enable

Memory Address Linearization

Disable................................................... default

Enable

........................................always reads 0

AGP Software Reset

Normal................................................... default

Reset

PCI Configuration Subsystem ID Write

Disable................................................... default

Enable

Enhanced Register I/O Scheme

0

1

0

1

3

2

Reserved

0

1

Disable ...................................................default

Enable

........................................ always reads 0

16-Bit Pixel Bus

0

1

0

Reserved

1

0

1

Disable ...................................................default

Enable

This register is protected by SRE_New[7]

0

1

0

1

Disable................................................... default

Enable

CR39 – PCI Interface Control .........................................RW

CR3B – Clock and Tuning............................................... RW

Observe Clock Source

7

Pixel Data Format

7

0

1

Little Endian...........................................default

Big Endian

0

1

VCLK1 .................................................. default

VCLK2

6-5 Memory Data with Big Endian Format

00 Pass Through (PT) .................................default

01 Word Swap (WS)

10 Half Swap (HS)

11 Full Swap (FS)

4-3 BE[3-0]# With Big Endian Format

00 Pass Through (PT) .................................default

01 Word Swap (WS)

6-4 Clock Source Mode Select

0xx Internal Clock Chip

000 V/MCLK test mode, observe MCLK

001 V/MCLK test mode, observe VCLK1

010 V/MCLK test mode, observe VCLK2

011 Normal operation

1xx External Clock Chip

Bit 6 default is set from MA?? inverted

Bits 5-4 default to 00

10 Half Swap (HS)

11 Full Swap (FS)

3

Clock Control

2

1

0

PCI Burst Write

0

1

When bits 6-4 = 00x, clock is normal.... default

When bits 6-4 = 00x, clock is divided by 2

0

1

Disable ...................................................default

Enable

2-1 Reserved

........................................always reads 0

PCI Burst Read

0

Vertical Retrace Memory Refresh

0

1

Disable ...................................................default

Enable

0

1

Disable

Enable................................................... default

MMIO Control.....default set from Inverted MA??

This register is protected by SRE_New[7]

0

1

Disable

CR3C – Miscellaneous Control ....................................... RW

Enable (64KB VGA I/O space can be memory

mapped within the 4GB memory space)

7-3 Same Definition as GRF[7-3]...................default = 0

This register is protected by SRE_New[7]

2

1

0

Reserved

........................................always reads 0

Same Definition as GRF[1]......................default = 0

Mode Select 1............................................default = 0

0

This register has no function.................. default

The original GRF[7-0] bits are used

1

GRF[7-3, 1] accessed via this register only

GRF[2, 0] accessed at original register only

Original GRF[3] is R/W but has no function

This register is protected by SRE_New[7]

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VGA Extended Registers

VT8601 Apollo ProMedia

Hardware Cursor Registers

CR50 – Hardware Cursor Control ................................. RW

7

6

5

4

Hardware Cursor Enable

The ProMedia supports a Windows® compatible hardware

cursor. The hardware cursor operates only in extended planar

and packed pixel modes. The cursor size can be selected

between 32x32 and 64x64. Two 2-bits-per-pixel images

define the cursor shape. The table below shows how these

two bits operate on each pixel. The hardware cursor pattern

is stored in off-screen memory.

0

1

Disable .................................................. default

Enable

Hardware Cursor Mode

0

1

MS Windows™ Compatible ................. default

X11 Compatible

Hardware Cursor Color Control 3

0

1

Disable .................................................. default

Enable

Table 11. Hardware Cursor Pixel Operation

Hardware Cursor Color Control 2

0

1

Disable................................................... default

Enable

Plane 0 Plane 1 Pixel Operation

Pixel Operation

(X11)

(AND) (XOR)

(Windows®)

3-2 Reserved

1-0 Hardware Cursor Size

00 128x128 ................................................ default

........................................always reads 0

1

0

1

0

Transparent

Cursor BG Color

VGA Data Inversion Cursor FG Color

01 64x64

10 32x32

11 -reserved-

Cursor FG Color

Cursor BG Color

Transparent

CR43-40 – Hardware Cursor Position ............................RW

31-28 Reserved

........................................ always reads 0

27-16 Hardware Cursor Position Y Dimension

15-12 Reserved

........................................ always reads 0

11-0 Hardware Cursor Position X Dimension

CR45-44 – Hardware Cursor Pattern Location.............RW

15-12 Reserved

........................................ always reads 0

11-0 Hardware Cursor Map Mask Storage Location

1KB aligned in the frame buffer

CR47-46 – Hardware Cursor Offset................................RW

15 Reserved

14-8 Hardware Cursor Position Y-Offset

Reserved

........................................ always reads 0

7

6-0 Hardware Cursor Position X-Offset

CR4F-48 – Hardware Cursor Color................................RW

63-56 Reserved

........................................ always reads 0

55-32 Hardware Cursor Background Color

31-24 Reserved

........................................ always reads 0

23-0 Hardware Cursor Foreground Color

Revision 1.3 September 8, 1999

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Additional CRTC Extended Registers

CR51 – Bus Grant Termination Control.........................RW

CR5E – Capture / ZV Port Control ................................ RW

7-0 Bus Grant Termination Position

7

6

Capture Idle......................................................... RO

Capture Command Port

This regiester is active if CR52[6] = 1

0

1

Disable................................................... default

Enable new command port (2203-2200h)

CR52 – Shared Frame Buffer Control ............................RW

7, 5 Shared Frame Buffer (SFB)

5-3 Reserved

........................................always reads 0

00 Disable ...................................................default

01 Enable SFB slave mode 1 (8ma I/O buffer)

10 Enable SFB master mode

11 Enable SFB slave mode 2 (16ma I/O buffer)

Bus Grant Termination Position Control

2

1

0

PCI I/O Write Retry

0

1

Disable................................................... default

Enable

PCI I/O Read Retry

6

4

0

1

Disable................................................... default

Enable

0

1

Disable ...................................................default

Enable

Capture Interface

Reserved

........................................ always reads 0

0

1

Disable................................................... default

Enable

3-0 Bus Grant Low Pulse (MCLKs) ...........def = 0010b

This bit is protected by SRE_New[7]

CR5F – Test Control ........................................................ RW

7 Internal Control Test Output

CR55 – PCI Retry Control...............................................RW

7

6

PCI Retry in Memory Write Command

0

1

Disable ...................................................default

Enable

0

1

Normal................................................... default

Internal control signals are output to P15-0

P15 GEREQ

PCI Retry in Memory Read Command

0

1

Disable ...................................................default

Enable

P14 GEBUSY

5-0 Number of PCICLKs * 2 for STOP#....... def = 0Fh

Number of PCICLKs, multiplied by 2, for generating

STOP# during the first data phase

P13 CMDIN

P12 GEWAIT

P11 CMATCH

P10 KGECYC

CR56 – Display Pre-end Fetch Control...........................RW

P9

P8

P7

P6

P5

P4

P3

P2

P1

P0

WBMT

GERTRY

BLANKTV

WRSTY

WRSTU

WRSTV

WRST1

Y0EN

7-2 Reserved

........................................ always reads 0

1

Display Queue Pre-end Fetch

0

1

Disable ...................................................default

Enable

0

Display Queue Pre-end Fetch Parameter Bit-8

Used with CR57......................................... default = 0

CR57 – Display Pre-end Fetch Parameter ......................RW

UEN

YUVEN

7-0 Display Queue Pre-end Fetch Parameter Bit-8

Used with CR56[0] .....................................default n/a

6

Capture Input Interrupt Polarity Select

0

1

Normal................................................... default

Test data is output to pixel bus P15-0

5-1 Reserved

........................................always reads 0

0

Stop DISPQ REQ Test

0

1

Normal................................................... default

Stop DISPQ REQ

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VT8601 Apollo ProMedia

CR62 – Enhancement 0.....................................................RW

CR63 – Enhancement 1.................................................... RW

7

6

5

4

Pause GE Operation (GEPAUSE)

7-6 Reserved

5-4 Memory Folding Control

00 Normal................................................... default

........................................always reads 0

0

1

Normal GE Operation ............................default

Pause GE Operation

PCI Retry for GE (ENGERTRY)

01 FOLD6

10 FOLD7

11 -reserved-

0

1

Disable ...................................................default

Enable

Short Command (ENSHRT)

3-2 Reserved

........................................always reads 0

1-0 Extended FIFO Latency Control (LATV[5-4])

0

1

Disable ...................................................default

Enable

Combined with CR30

Direct Read Even if GE is Busy (ENDIRRD)

0

1

Disable ...................................................default

Enable

CR64 – DPA Extra ........................................................ RW

3

2

Reserved

Low Priority Arbitration Policy

........................................ always reads 0

7

DPA On/Off

0

1

On

Off

.................................................... default

0

1

Fixed Priority

Round Robin .........................................default

6

DPA Bypass

1

0

High Priority Arbitration Policy

0

1

Normal................................................... default

Bypass

0

1

Fixed Priority .........................................default

Round Robin

5-3 Reference Feedback Clock Delay

Maximum 2ns.............................................default = 0

2-0 Reference Internal Clock Delay

Frame Buffer Memory Size Select

0

1

8MB .....................................................default

4MB

Maximum 2ns.............................................default = 0

Revision 1.3 September 8, 1999

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VGA Extended Registers

VT8601 Apollo ProMedia

Video Display and Capture Engine Registers

used. If W1 is in planar mode, then W1-Y is the first live

video Y-component storage area, and W1-U (V) is the first

live video U (V) -component storage area. In the following

register definitions, a register with W1 (W2) indicates that

this parameter is applicable to the first (second) live video

window only.

The ProMedia integrates video display and capture engines,

which support YUV 4:2:2, YUV12 (planar) or YUV 4:1:1

data formats to accelerate software playback and video

capture functions. Video images can be captured through a

special video capture port or the PCI bus. Dual apertures on

the PCI bus enable graphics and video data to be transported

simultaneously without any software involvement. The video

image can be smoothed through a programmable multi-tap

filter to reduce the jig-jag effect after minification. The video

data can be minified to save bus bandwidth or memory space

and written into offscreen memory. The video display engine

fetches YUV 4:2:2 or planar video data from offscreen

memory and can be scaled up with linear interpolation in both

X and Y directions. The video data stream is converted into a

True Color RGB24 data stream and multiplexed with the

graphics data. Two live video windows can be supported.

The graphics data and video data can be handled smoothly in

different color depths with color key support. A hardware

anti-tear mechanism prevents the tearing effect due to frame

buffer update and eases the burden of software to flip the

page. Since the hardware synchronizes the capture or PCI

video address pointer with the playback VSYNC, the built-in

algorithm ensures the playback frame buffer is free from the

frame update. For the parameters defined here, refer to the

following figures.

Note that W1’ is defined for the anti-tearing function. W1 is

the first live video storage area and W2 is the second live

video storage area. W1 could be in either packed pixel or

planar format, while W2 can only be packed pixel mode. If

W1 is in packed pixel mode, then W1-U and W1-V are not

Figure 7. Frame Buffer Parameters

1: CR92-CR91, 2: 3X58E-CR8D, 3: CR8B-CR8A, 4: CR87-CR86, 5: CR89-CR88, 6: CR8D-CR8C, 7: SR90-SR8F, 8: SR94-SR93

Figure 8. Live Video Display Parameters

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VGA Extended Registers

VT8601 Apollo ProMedia

CR81-80 – Window 1 Horizontal Scaling Factor ...........RW

15 Horizontal Minify / Zoom Enable

CR89-86 – Window 1 Video Window Start.................... RW

31-28 Reserved

........................................always reads 0

0

1

Horizontal Zoom Enable ........................default

Horizontal Minify Enable

27-16 Video Window Vertical Start

In pixel delays from the edge of VSYNC

15-12 Reserved

........................................always reads 0

Minify Enabled:

14-13 Tap 1

11-0 Video Window Horontal Start

In pixel delays from the rising edge of HSYNC

12-10 Horizontal Minify Integer (Inverter), Hsrc/Hdst – 1

9-0 Horizontal Minify Factor, (Hdst/Hsrc) * 1024

CR8D-8A – Video Window End...................................... RW

Zoom Enabled:

13-0 Horizontal Zoom Factor, (Hdst/(Hsrc-2)-1) * 1024

31-28 Reserved

........................................always reads 0

27-16 Video Window Vertical End

In pixel delays from the edge of VSYNC

CR83-82 – Window 1 Vertical Scaling Factor................RW

15 Vertical Minify / Zoom Enable

15-12 Reserved

........................................always reads 0

11-0 Video Window Horontal End

In pixel delays from the rising edge of HSYNC

0

1

Vertical Zoom Enable ............................default

Vertical Minify Enable

14 Vertical Filtering

0

1

Disable ...................................................default

Enable

13-10 Reserved

........................................ always reads 0

9-0 Vertical Minify / Zoom Factor (Vdst/Vsrc) * 1024

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VGA Extended Registers

VT8601 Apollo ProMedia

CR8F-8E – Video Display Engine Flags..........................RW

15 Planar Capture Mode

CR95 – Video Window Line Buffer Threshold.............. RW

7

Line Buffer Level Bit-8 (used with CR96)

0

1

Planar 420 Capture.................................default

Planar 422 Capture

6-0 W1 / W2 Line Buffer Request Threshold Value

When the line buffer is less than this value, a memory

request will be issued. The value programmed in this

register must be less than the line buffer level (see bit-

7 and CR96).

14 VSYNC Test / Graphics Engine Reset

0

1

Disable ...................................................default

Enable

13 Edge Recovery Algorithm Control

CR96 – Window 1 / W1-Y Line Buffer Level Control .. RW

0

1

Disable ...................................................default

Enable

7-0 Line Buffer Levels (bit-8 is in CR95[7])

RGB8: (pixel # + 2) / 8 rounded up

12 Window 1 Vertical Interpolation

YUV 4:2:2: (Pixel # + 2) / 4 rounded up

For W1-U or W1-V, the level is this value divided by

4 or 16, depending on the panar format (YUV12 or

YUV9)

0

1

Disable ...................................................default

Enable

11 Window 1 Horizontal Interpolation

0

1

Disable ...................................................default

Enable

CR97 – Video Display Engine Flags................................ RW

10 CSC / Bypass Select

7

Start Address Reload Control

0

1

CSC .....................................................default

Bypass

0

1

x

CR94[4]=0 address can be reloaded any time

CR94[4]=0 only reloaded during Vsync

CR94[4]=1 address not reloaded

9

Line Toggle for Line Buffer

0

1

Normal ...................................................default

Toggle (Reversed)

6

Video Start Reference Select

0

1

HSYNC / VSYNC................................. default

Use fixed signals (fixed relationship with HDE

and VDE) as video start reference

8

Reserved

........................................ always reads 0

7-5 Window 1 HDEO Delay Adjust.............. default = 4

4

Video Window 1

5

4

Address Point Invert

0

1

Disable ...................................................default

Enable

0

1

Normal................................................... default

Invert

3

CCIR-/ DTV Input Video Data Control

Odd / Even Invert (Anti-tearing)

0

1

CCIR Format..........................................default

DTV Format

0

1

Normal................................................... default

Invert

2-1 W1 / W2 Line Buffer Page Break Level Control

00 8 levels ...................................................default

01 16 levels

3

2

Playback Test Mode Select (RGB Data Select)

Playback Test Mode

0

1

Disable................................................... default

Enable

1x 32 levels

Video Window 2

0

1

0

Anti-tearing Sync Select

0

1

Disable ...................................................default

Enable

0

1

VGA Vsync ........................................... default

Playback Vsync

CR91-90 – Window 1 / W1-Y Row Byte Offset..............RW

15-14 Reserved

........................................ always reads 0

13-0 Video Row Byte Offset

Anti-tearing

0

1

Disable................................................... default

Enable

This bit is automatically disabled if there is only one

video stream and dual live video mode is enabled. In

this mode, the even field is used for one live video

stream and the odd field is used for the other live

video stream.

Programmed with the number of bytes in a row

CR94-92 – Window 1 / W1-Y Video Start Address........RW

23-21 Reserved

........................................ always reads 0

20 Used with CR97 bit-7

19-0 Video Start Addres (in bytes)

CR9A-98 – Capture Video Start Address....................... RW

23-20 Reserved

........................................always reads 0

19-0 Capture Video Start Address

Controlled by SRBE (3C5 index BE).

Revision 1.3 September 8, 1999

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VGA Extended Registers

VT8601 Apollo ProMedia

CR9B – Video Display Status........................................RWC

CR9C – Capture Control 1.............................................. RW

7

Capture Interrupt

7-6 Frame Capture Control

00 Interlace Capture.................................... default

01 Even/odd 60fps capture

0

1

Disable ...................................................default

Enable

6

5

4

3

2

1

0

Capture Interrupt Clear..................Write 1 to Clear

VGA Vertical Blank.............................................RO

Capture Interrupt Status.....................................RO

Display Double Buffer Status..............................RO

VDQ (Capture FIFO) Empty..............................RO

Capture VSYNC Status.......................................RO

Capture Video Display Enable (VDE) Status....RO

10 Even field 30fps capture

11 Odd field 30fps capture

External HDE Select

5

4

3

2

1

0

1

Use Internal HDE .................................. default

Use External HDE

Capture Enable

0

1

Disable................................................... default

Enable

Genlock Enable

0

1

Disable................................................... default

Enable

Motion Effect Algorithm

0

1

Skip 2 lines ............................................ default

Skip 1 line

Capture Hsync Polarity

0

1

Normal................................................... default

Invert

Capture Vsync Polarity

0

1

Normal................................................... default

Invert

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VT8601 Apollo ProMedia

CR9D – Capture Control 2...............................................RW

Capture DTV / CCIR Format Select

CR9F – Capture Control 4 .............................................. RW

7

7-6 Capture Interrupt Source

00 Capture vsync ........................................ default

01 Capture even field

0

1

CCIR .....................................................default

DTV

6-4 Horizontal Filter Tap

0xx Bypass ....................................................default

10 Capture odd field

11 Capture blank

100 2 Tap

101 3Tap

110 5 Tap

111 9 Tap

UV Swap

5

4

IBM MPEG2 Mode Enable

0

1

Normal................................................... default

IBM MPEG2 Mode

Production Test Mode for Capture

0

1

Normal................................................... default

For test purposes, the ESYNC# pin is used

instead of capture Vsync and EDCLK# is used

instead of external CLK

3

2

1

0

1

Normal ...................................................default

Swap

YUV Swap

0

1

Normal ...................................................default

Swap

3-1 Capture Clock Divide Factor Select

Capture clock divide factor when the internal pixel

clock is source:

Philips 9051 Format Select

0

1

Normal ...................................................default

UV9051 Format

000 Divide by 1 ............................................ default

001 Divide by 2

010 Divide by 3

TV 8-Bit Control

0

1

16-bit capture input ................................default

8-bit capture input

011 Divide by 4

100 Divide by 5

101 Divide by 6

110 Select 14.318 MHz Clock

111 Select 28.636 MHz Clock

CR9E – Capture Control 3...............................................RW

7-6 Capture Input Data Mode

00 YUV 4:2:2..............................................default

01 YUV 4:1:1

0

Capture Clock Select

0

1

Use external capture clock..................... default

Use internal pixel clock divided by the factor

above

10 RGB 565

11 -reserved-

5

4

CGS Clock Double

0

1

Normal ...................................................default

Double

Capture Clock Polarity

0

1

Normal ...................................................default

Invert

3-2 Capture Clock Delay Select

00 No delay.................................................default

01 3 ns

10 6 ns

11 9 ns

1

0

Hsync Delay

0

1

Normal ...................................................default

Delay

PCI Frame Start and Busy

0

1

PCI Video Not Busy...............................default

PCI Video Busy

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VT8601 Apollo ProMedia

CRA1-A0 – Capture Vertical Total.................................RW

15-11 Reserved

........................................ always reads 0

10-0 Capture Vertical Total

CRAE – Capture CRTC Control .................................... RW

7

6

5

Time Base

0

1

One Time Base ...................................... default

Two Time Base

CRA3-A2 – Capture Horizontal Total ............................RW

Frame Reset

15-9 Reserved

........................................ always reads 0

0

1

Field reset .............................................. default

Frame reset

8-0 Capture Horizontal Total

Capture Clock Divide by 2

0

1

Select original capture clock.................. default

Select inverted capture clock before divide by

two

CRA5-A4 – Capture Vertical Start .................................RW

15-11 Reserved

........................................ always reads 0

4

3

2

1

0

Odd / Even Field Invert

10-0 Capture Vertical Start

0

1

Normal................................................... default

Invert

CRA7-A6 – Capture Vertical End...................................RW

CRTC Hsync Load

15-11 Reserved

........................................ always reads 0

0

1

Enable.................................................... default

Disable

10-0 Capture Vertical End

CRTC Vsync Load

0

1

Enable.................................................... default

Disable

CRA9-A8 – Capture Horizontal Start.............................RW

CRTC Horizontal Reset

15-10 Reserved

........................................ always reads 0

0

1

Enable.................................................... default

Disable

9-0 Capture Horizontal Start

CRAB-AA – Capture Horizontal End.............................RW

CRTC Vertical Reset

0

1

Enable.................................................... default

Disable

15-10 Reserved

........................................ always reads 0

9-0 Capture Horizontal End

CRAF – Capture CRTC Control .................................... RW

7

Video Exist Select

CRAC – Capture Vertical Sync Pulse Width .................RW

0

1

Video exist capture ................................ default

Always capture

7-4 Reserved

........................................ always reads 0

3-0 Capture Vertical Sync Pulse Width

6

Capture Sync and Direct

0

1

Input .................................................... default

Output

CRAD – Capture Horizontal Sync Pulse Width.............RW

7-6 Reserved

........................................ always reads 0

5

4

Reserved

Capture CRTC Input Clock Mode

........................................always reads 0

5-0 Capture Horizontal Sync Pulse Width

0

1

Normal................................................... default

Clock divided by 2 when in 8-bit pixel bus

mode

3

2

1

0

External CRTC Input Clock Mode

0

1

Clock devided by 1................................ default

Clock devided by 2

External Pixel Clock Mode

0

1

Clock devided by 1................................ default

Clock devided by 2

CRTC Mode

0

1

Targa Mode ........................................... default

XPCV Mode

MPEG2 Vsync Select

0

1

Original Vsync....................................... default

Field ID

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CRB1-B0 – Capture Horizontal Minify Factor..............RW

15 Reserved

........................................ always reads 0

CRBB-BA – Chromakey Comp Data 0 Low .................. RW

15-0 Chromakey Compare Data 0 (Lower Threshold

14-10 Planar Capture FIFO Level (for both U and V)

9-0 Capture Horizontal Minify Factor

CRBD-BC – Chromakey Comp Data 0 High ................. RW

15-0 Chromakey Compare Data 0 (Higher Threshold

CRB3-B2 – Capture Vertical Minify Factor...................RW

15 Reserved

........................................ always reads 0

14-10 Planar Capture FIFO Threshold (for both U & V)

9-0 Capture Vertical Minify Factor

CRBE – Capture Control ................................................ RW

7-6 Reserved

........................................always reads 0

5

Video WBUF Status ............................................ RO

0

1

Empty .................................................... default

Not empty

CRB5-B4 – DST Pixel Width Count................................RW

4

Second Aperture Direct Access (bypass video

capture)

15-12 Reserved

........................................ always reads 0

11-0 DST Pixel Width Count

3

2

Interpolation Control

Video Engine Clock Enable

CRB7-B6 – DST Pixel Height Count...............................RW

15-11 Reserved

........................................ always reads 0

0

1

Off

On

.................................................... default

10-0 DST Pixel Height Count

1

0

Flicker-Free Function

0

1

Disable................................................... default

Flicker-free when input is in interlace mode

........................................always reads 0

CRB8 – Capture FIFO Control 1 ....................................RW

Reserved

7-6 Capture FIFO Page Break

00 8 level.....................................................default

01 16 level

CRBF – Display Engine Flags 4 ...................................... RW

Video Line Buffer Read Reset Select......default = 0

7

1x 32 level

6-4 Window 2 Video Data Format

000 YUV 422 ............................................... default

001 -reserved-

5

Interlace Double Buffering

0

1

Disable ...................................................default

Enable

010 RGB 16

011 -reserved-

1xx -reserved-

Interpolation Bypass 1 ............................default = 0

4-0 Capture FIFO Level Control

0

1

Targa Mode............................................default

XPCV Mode

3

2-0 Window 1 Video Data Format

000 YUV 422 ............................................... default

001 -reserved-

CRB9 – Capture FIFO Control 2 ....................................RW

7

6

ENNENZOOM

Planar 422 Display

010 RGB 16

011 -reserved-

1xx -reserved-

0

1

Disable ...................................................default

Enable

5

Planar Mode Window Indicator

Indicate which window is in planar mode

4-0 Capture FIFO Request Threshold Control

0

1

Targa Mode............................................default

XPCV Mode

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Digital TV Control Registers

VGA Extended Registers – CRTC Shadow

Read/Write of Shadow registers is controlled by extended

register GR30[6] (port 3CE/3CF index 30h). If GR30[6]=1,

read/write operations to CRTC indices 0, 3-7, 10-11, and 16

are performed to the shadow registers instead of to the normal

registers. Bit definitions for these registers are identical to the

standard CRTC register set.

CRD3-D0 – VGA / Digital TV Sync Control 1................RW

31-27 Reserved

........................................ always reads 0

26-16 Vertical Data Load

15 VGA Slave Mode for DTV

0

1

Disable ...................................................default

Enable

14 H/V Data Load

CR00 – Shadow Horizontal Total ................................... RW

CR03 – Shadow Horizontal Blank End .......................... RW

CR04 – Shadow Horizontal Retrace Start...................... RW

CR05 – Shadow Horizontal Retrace End ....................... RW

CR06 – Shadow Vertical Total........................................ RW

CR07 – Shadow Overflow................................................ RW

CR10 – Shadow Vertical Retrace Start .......................... RW

CR11 – Shadow Vertical Retrace End............................ RW

CR16 – Shadow Vertical Blanking End.......................... RW

0

1

Disable ...................................................default

Enable

13 Digital Hsync Direction

0

1

Input .....................................................default

Output

12-9 Reserved

........................................ always reads 0

8-0 Horizontal Data Load

(see also CRD8, Digital TV Interface Control)

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3D Graphics Engine Registers

Operational Concept

This section describes how to program the ProMedia graphics

engine for different operations. When the Setup Engine is to

be used, the following steps should be taken to perform the

drawing functions:

From a programmer’s point of view, operations that can be

applied to the ProMedia fall into the following categories:

•

Reset: This operation resets the GE to default status.

Status: This operation returns the GE status.

Drawing Environment: The operations set environment

for drawing.

•

Software sets up the drawing environment.

Software issues a drawing command.

Software continuously sends triangles to Setup engine.

Software sends a triangle with last flag set or a null

triangle to Setup engine to signal end of operation.

•

Frame Buffer Control: The operations set control for the

frame buffer.

•

Drawing: Draw an object.

Geometry Primitives: Describe a geometry primitive.

Drawing Environment defines a set of conditions that decide

the operations to be applied to each pixel. Drawing

Environment operations are straight-forward. There is a

group of registers that defines the drawing environment. By

directly setting these registers, a program can control the

drawing environment.

Frame Buffer Control decides how to access the frame buffer.

Like the Drawing Environment, there is a group of registers

that define the frame buffer access. By directly setting these

registers, a program can control frame buffer access.

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Drawing

Bitblt - Frame Buffer to Frame Buffer

A Note on CPU as the Source of Operation

Blt operation may involve a pattern. If it does, and the pattern

is stored in the frame buffer, the pattern parameters (P1, P2,

P3) must also be set. The following registers must be set to

provide the source and destination rectangles of blt: Ps1, Pd1,

Ps2, and Pd2. These registers can be set in any order. If a

register is set several times, only the last one is effective.

After all the registers are set, the program starts blting by

writing a blt command to Command Register.

Any operation that uses the CPU as the source of operation

(such as the Blt shown in section x) requires the host CPU to

feed data into data registers III and IV (BA+56 and 60). Since

the ProMedia is using the 64-bit internal data path, any data

(32-bit) from the CPU will be packed into 64-bit before use.

Therefore, there are two registers for the CPU to write. These

two registers are arranged as shown in the following diagram.

Bitblt - CPU to Frame Buffer

The operation for blting from the CPU is similar to the blting

from the frame buffer except that Ps1 and Ps2 are not needed

and the data from the CPU must immediately follow the

setting of the Command Register.

Writing to Data Register IV triggers data in both registers to

be sent to the engine for processing. However, the hardware

may expose the two registers as a mapped space to save

software from toggling between the two registers.

For all commands that require data from the CPU, the

command and data are considered atomic; i.e., the data should

follow the command immediately and no other command or

parameter can be placed in between. The data can be written

to Data Register III and IV. Alternatively, it can be written to

a memory-mapped space designated by ProMedia apertures.

The same rule applies to drawing text from the CPU to the

frame buffer.

Geometry Primitive

To draw a geometry primitive, the host must issue a drawing

command by writing to the Command Register first and then

set up the geometry as described in later in this document.

Text

Text glyph can be from the CPU or the frame buffer. When

the glyph is from the CPU, the registers to be set are Pd1 and

Pd2 for text location. When the glyph is stored in the frame

buffer, the registers to be set are Ps1, Ps2, Pd1, and Pd2 to

provide both the glyph and text locations. These registers can

be set in any order. If a register is set several times, only the

last one is effective. After all the registers are set, the program

starts blting by writing a text command to Command Register.

The major difference between text and Blt is that a text source

data is 8-bit aligned while the bitblt is 64-bit aligned. That is,

for text, each new line starts at the byte boundary, while for a

bitblt, at the 64-bit boundary.

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Geometry Primitives

The ProMedia supports the following geometry primitives:

line, and polygon. Each geometry primitive can be further

modified for 3D, shading, and texture mapping. A different

mechanism, called sequential loading, performs the geometry

primitive set up operation.

Loading Mechanism

There are two ways to set up a geometry primitive, random

loading and sequential loading. Like the random access, the

order is not important in random loading, but the address is.

Writing to a certain address in the register space causes a

certain pre-determined action. On the other hand, like

sequential access, the order decides the data semantics in

sequential loading. The ProMedia uses sequential loading in

the Rasterization Engine and the Setup Engine.

In the ProMedia, parameters don’t have to be the fixed

addresses. ProMedia parameters are treated as a data stream

and interpreted based on the type of primitive. Parameters

must be set in a stream as follows:

P1 is the number of bytes for parameter 1, P2-P1 for

parameter 2, etc.

For the Rasterization Engine, there are 9 kinds of parameters:

Bresenham Edge, DDA Edge, Z, Texture, Perspective, Color,

Specular/fog Start, Specular, and Fog. Parameters must

appear in the following order:

Edge(Major), Texture, Perspective, Color, Specular/fog Start,

Specular, Fog, Z, Edge(Minor)

There are two kinds of edges and only one kind can appear in

a parameter stream. Bresenham Edge can only appear in 2D

primitives (without values for iterators).

For the Setup Engine, there is only one kind of parameter:

vertex. However, each primitive could have one or three

vertices. The size of each vertex is variable depending on

triangle attribute.

Only polygon and line primitives can use this sequential

loading feature. In the following sections, each primitive is

addressed in detail.

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Polygon

General polygons can only be drawn by directly using the

Rasterization Engine. In the ProMedia, all polygons must be

Y-monolithic, meaning, when walking from the vertex with

minimal Y to the vertex with maximum Y, the Y coordinates

of the vertices are monolithically increased. A polygon is

drawn by drawing a series of segments:

The following example shows how to draw two shaded

polygons.

Sequence Content

0

1

Drawing Command

Full Segment including

Primitive Type: Re-loading, Major & minor edge, color

Major edge L1

Sequence Content

Color Parameter for L1

Minor edge L2

0

1

Drawing Command (Polygon)

Full Polygon Segment

2

3

Partial Segment including

Primitive Type: minor edge

Minor Edge L3

Full Segment including

Primitive Type: Major edge, color

Major Edge L4

2

Polygon Segment (Full or Partial)

….

3

….

n

Color for L4

Polygon Segment (Full or Partial) or a Null Primitive

4

5

Partial Segment including

Primitive Type: Minor edge

Minor Edge L5

Full Segment including:

Primitive Type: Major & minor edge, color, negative scan

direction

Major edge L6

Color Parameter for L6

Minor edge L7

A partial segment consists of only one primitive type and one

minor edge parameter. A full segment consists of one

primitive type, edge parameter(s), and interpolation

parameters (Z, color, texture, etc.). The rule is whenever a

new major edge is in the segment a full segment must be used,

otherwise a partial segment has to be used.

6

Partial Segment including:

Primitive Type: Minor edge, “Last”

Minor Edge L8

Most bit fields in primitive type define the data to be loaded to

Rasterization Engine. If the “Re-load” bit is set, they also

define the data set to be passed to Pixel Engine. The primitive

type of the first and only the first segment must have the “Re-

load” bit set to signal Rasterization Engine the data set to be

passed to Pixel Engine. The primitive type of the last and

only the last segment must have the “Last” bit set to signal the

end of the sequence. The last of the primitive can be a Null

primitive (others must be polygon). Null primitive has no

parameter.

This mechanism can be used to draw a single polygon, as well

as multiple polygons with the same attributes (e.g. 3D texture

mapped). All that is required is that somewhere in the

sequence we pass a full segment with starting edges of a new

polygon.

The following sections are about complete segments (a full

segment with both major and minor edges) with different

attributes. A normal full segment may not have the minor

edge parameter. A partial segment has no other parameters

except the minor edge.

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2-D

3-D Shaded

Sequence Content

0

1

2

Primitive Type

Major Edge Parameter

Minor Edge Parameter

0

1

2

3

4

5

Primitive Type

Major Edge Parameter

Z Parameter

Color Parameter

Alpha Parameter (optional)

Minor Edge Parameter

3-D

Sequence Content

0

1

2

Primitive Type

Major Edge Parameter

Minor Edge Parameter

Texture Mapped Shaded

Without perspective correction:

Sequence Content

Texture Mapped

0

1

2

3

Primitive Type

Major Edge Parameter

Texture Coordinate Parameter

Optional Auxiliary Texture Data Parameter for

linear interpolation

Without perspective correction:

Sequence Content

0

1

2

3

Primitive Type

Major Edge Parameter

Texture Coordinate Parameter

Optional Auxiliary Texture Data Parameter for

linear interpolation

4

5

Color Parameter

Minor Edge Parameter

With perspective correction:

Sequence Content

4

Minor Edge Parameter

With perspective correction:

Sequence Content

0

1

2

3

4

5

6

7

Primitive Type

Major Edge Parameter

Texture Coordinate Parameter

Auxiliary Texture Data Parameter

Perspective Factor Parameter

Color Parameter

0

1

2

3

4

5

Primitive Type

Major Edge Parameter

Texture Coordinate Parameter

Auxiliary Texture Data Parameter

Perspective Factor Parameter

Minor Edge Parameter

Alpha Parameter (optional)

Minor Edge Parameter

Shaded

Sequence Content

3-D Texture Mapped Shaded

Without perspective correction:

Sequence Content

0

1

2

3

4

Primitive Type

Major Edge Parameter

Color Parameter

Alpha Parameter

Minor Edge Parameter

0

1

2

3

4

Primitive Type

Major Edge Parameter

Z Parameter

Texture Coordinate Parameter

Optional Auxiliary Texture Data Parameter for

linear interpolation

3-D Texture Mapped

Without perspective correction:

Sequence Content

5

6

7

Color Parameter

Alpha Parameter (optional)

Minor Edge Parameter

0

1

2

3

4

Primitive Type

Major Edge Parameter

Z Parameter

Texture Coordinate Parameter

Optional Auxiliary Texture Data Parameter for

linear interpolation

With perspective correction:

Sequence Content

0

1

2

3

4

5

6

7

Primitive Type

Major Edge Parameter

Z Parameter

Texture Coordinate Parameter

Auxiliary Texture Data Parameter

Perspective Factor Parameter

Color Parameter

5

Minor Edge Parameter

With perspective correction:

Sequence Content

0

1

2

3

4

5

Primitive Type

Major Edge Parameter

Z Parameter

Texture Coordinate Parameter

Auxiliary Texture Data Parameter

Minor Edge Parameter

Alpha Parameter (optional)

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Triangle

Synchronization

Triangles can be drawn using the Polygon Mechanism

described above. Additionally, triangles can also be drawn by

using the Setup Engine if they meet certain criteria. Triangles

and polygons can also be freely mixed in a drawing sequence.

The ProMedia supports stand-alone triangles as well as a

triangle list in a sequence as follows:

Reset and status operations can be performed in any order and

at any time including in the middle of another operation.

However, be aware of the consequence (reset) and what to

expect (status).

Generally, Drawing Environment and Frame Buffer Control

operations should be performed before the drawing operation

to take effect.

Sequence Content

0

1

2

3

…

1

Drawing Command (Polygon)

Triangle primitive

…

The primitive operation is considered atomic; i.e., no other

operation (except for status and reset) can be performed inside

a Geometry Primitive operation.

Functional Blocks

Triangle primitive

The ProMedia hardware is divided into 6 major functional

blocks. They are:

Each primitive consists of a triangle attribute and one or three

vertices. The order of the data in each primitive is: Triangle

Attribute, Vertex 0, Vertex 1 (optional), Vertex 2 (optional).

Whether vertices 1 and 2 are to be loaded depends on the

Triangle Attribute. Writing to BA+192 triggers a loading

sequence in the Setup Engine. The order of the data in a

vertex is: Z, RGBA, UV, W, XY. Not every one has to appear

in every vertex. Whether a particular item is present in a

vertex is decided by the Triangle Attribute. For example, the

Data in a stream for a texture mapped triangle strip may look

like: Triangle Attribute, U0V0, X0Y0.

•

Bus Interface (BI)

VGA core (VGA)

Setup Engine (SE)

Rasterization Engine (RE)

Pixel Engine (PE)

Memory Interface (MI)

Each functional block conceptually works independently of

other blocks. The term "Graphics Engine (GE)” indicates the

combination of the Setup Engine, the Rasterization Engine,

and the Pixel Engine.

Due to the limited precision of the setup engine, only triangles

smaller than a certain size will be passed. Software will only

pass triangles smaller than 64x128 or 128x64 to the hardware.

Also, delta values of RGBAUVZ across a triangle will be less

than 128. There is no limitation on the delta of W since it is

impossible to exceed 1.

Bus Interface

The bus interface block connects the AGP bus on one side and

the GE and VGA on the other side.

Line

Parameters for line primitives are very similar to their polygon

counter-parts. The differences are as follows:

There are only major edge parameters.

All the dXm values (dRm, dUm, etc.) are ignored.

The following example shows these differences for a texture

mapped primitive:

Sequence Polygon Content

Line Content

0

1

2

3

4

Drawing Command

Primitive Type

Major Edge

Texture Parameter

Minor Edge

Drawing Command

Primitive Type

Major Edge

Texture Parameter

Using the same mechanism for multiple polygons, multiple

lines can also be drawn by issuing one drawing command.

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Span Engine

PS1, PS2, PD1, and PD2 are used in blt and text operations to

define source and destination rectangles.

GEbase + 0 - Parameter Source 1 ....................................RW

GEbase + 8 - Parameter Destination 1............................ RW

31-28 Reserved

........................................ always reads 0

31-28 Reserved

........................................always reads 0

27-16 Y-coordinate Parameter Source 1 Start

High 12 bits of parameter source 1 starting address in

Y coordinate

27-16 Y-coordinate Parameter Destination 1 Start

High 12 bits of parameter destination 1 starting

address in Y coordinate

15-12 Reserved

........................................ always reads 0

15-12 Reserved

........................................always reads 0

11-0 X-coordinate Parameter Source 1 Start

Low 12 bits of parameter source 1 starting address in

X coordinate

11-0 X-coordinate Parameter Destination 1 Start

Low 12 bits of parameter destination 1 starting

address in X coordinate

GEbase + 4 - Parameter Source 2 ....................................RW

GEbase + C - Parameter Destination 2........................... RW

31-28 Reserved

........................................ always reads 0

31-28 Reserved

........................................always reads 0

27-16 Y-coordinate Parameter Source 2 Start

High 12 bits of parameter source 2 starting address in

Y coordinate

27-16 Y-coordinate Parameter Destination 2 Start

High 12 bits of parameter destination 2 starting

address in Y coordinate

15-12 Reserved

........................................ always reads 0

15-12 Reserved

........................................always reads 0

11-0 X-coordinate Parameter Source 2 Start

Low 12 bits of parameter source 2 starting address in

X coordinate

11-0 X-coordinate Parameter Destination 2 Start

Low 12 bits of parameter destination 2 starting

address in X coordinate

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Graphics Engine Core

GEbase + 10 - Right View Display Base Address ...........RW

31 Right View Active

GEbase + 18 – Block Write Start Address...................... RW

31 Linear Mode

0

Inactive (use VGA style for display start

address) ..................................................default

Active (use the base register address in this

register for the display starting address)

0

1

Fill a rectangle area................................ default

Fill a linear area

1

30-24 Reserved

23-0 Starting Address (in multiples of 64 bytes)

........................................always reads 0

30-24 Reserved

........................................ always reads 0

23-0 Right View Display Starting Address

Writing to this register sets Status Register bit-21 to 0. Later

when the address is used to display a frame, the status bit is

changed to 1.

GEbase + 1C – Block Write Area / End Address........... RW

Rectangle Area Fill Mode

31-28 Reserved

........................................always reads 0

27-16 Height of the Area

15-12 Reserved

........................................always reads 0

11-0 Width of the Area (in bytes)

Stride is Destination Stride in port 21C0h

GEbase + 14 - Left View Display Base Address..............RW

31 Left View Active

0

Disable (only Right View Display Starting

Address is used) .....................................default

Enable (Right View Display Starting Address

is used for the right view and this register for

the left view; hardware will use these two

addresses alternately)

Linear Area Fill Mode

31-0 End Address (in multiples of 64 bytes inclusive)

1

Writing to this register triggers a Memory Set operation.

Color for this operation is specified in the Foreground register.

30-24 Reserved

........................................ always reads 0

23-0 Left View Display Starting Address

Writing to this register sets Status Register bit-20 to 0. Later

when the address is used to display a frame, the status bit is

changed to 1.

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GEbase + 20 – Graphics Engine Status ............................RO

There are two input FIFOs to buffer data and commands from

the host, the Command FIFO (8 levels deep) and the

Bresenham FIFO (2 levels deep). Drawing commands,

Drawing Environment, and Frame Buffer Control are routed

through the Command FIFO. Primitive Type and Geometry

Primitives are routed through the Bresenham FIFO.

Commands in the Command FIFO don’t take effect until a

prior command is executed or the task in progress is finished.

Parameters in the Bresenham FIFO don’t take effect until a

prior parameter is phased out (reaches the end of an edge).

Writing to this register resets the GE.

31 Bresenham Engine Status

0

1

Idle

Busy

30 Setup Engine Status

0

1

Idle

Busy

29 SP / DPE Status

0

1

Idle

Busy

28 Memory Interface Status

0

1

Idle

Busy (access for screen refresh doesn’t count)

27 Command List Processing Status

0

1

Idle

Busy

26 Block Write Status

0

1

Idle

Busy

25 Command Buffer Status

0

1

Not full

Full

24 Reserved

........................................ always reads 0

23 PCI Write Buffer Status

0

1

Empty

Not empty

22 Z Check Status

0

Engine busy: All Z tests performed so far have

failed in the command being executed.

Engine idle: All Z tests performed in the last

command have failed.

1

Otherwise

Logically, this bit is the OR of all Z test results

performed in the latest command

21 Effective Status

0

1

Current display base register is not yet

effective (the frame is not displayed)

It is effective

20 Left View Status

0

1

Current display base register is not yet

effective (the frame is not displayed)

It is effective

19 Last View Displayed / Being Displayed

0

1

Right View

Left View

18-11 Reserved

........................................ always reads 0

10-0 Scan Line Currently Being Displayed

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GEbase + 24 – Graphics Engine Control ....................... WO

GEbase + 2C – Graphics Engine Wait Mask ................. RW

7

Reset

31-0 Wait Mask

0

1

Normal operation ...................................default

Reset all internal registers and pointers. Reset

is performed by setting this bit to 1 and then

back to 0.

When writing to this register, hardware will monitor

the value of M (Wait Mask & Status). If M is not 0,

the Graphics Engine (including the RE, SE, PE, and

MI) will not accept new registers from the host CPU

or AGP bus. This register is cleared by the hardware

when M = 0. Only bits 31-28, 26, 23, and 21-20 are

effective (all other bits are ignored).

6-4 Reserved

3-0 Debug Module Select ............................... default = 0

........................................ always reads 0

Module to Debug

000 None

GE Register 28

undefined

001 Setup Engine

SE Status

010 Rasterization Engine

011 Pixel Engine

RE Status

PE Status

100 Memory Interface

101 Cmd List Ctrl Unit

110 Cmd List Ctrl Unit

111 -reserved-

MI Status

Cmd List Start Address

Cmd List End Address

n/a

GEbase + 28 – Graphics Engine Debug............................RO

31-0 Engine Module Status

(See register 24 bits 3-0 above)

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Graphics Engine Organization

The ProMedia Graphics Engine consists of the following

units: Setup Engine, Rasterization Engine, and Pixel Engine.

These units are organized as follows:

When the Setup Engine is to be used, the following steps

should be taken to perform drawing functions:

•

S/W sets up the drawing environment.

S/W issues a drawing command.

S/W continuously sends triangles to the Setup Engine (or

primitives to the Rasterization Engine).

A G P

Setup Engine

•

S/W sends a triangle with last flag set or a null triangle to

the Setup Engine to signal the end of the operation (or its

equivalent to the Rasterization Engine).

Rasterization Engine

Triangles sent to the Setup Engine can be interleaved with

primitives sent to the Rasterization Engine in step 3 above.

Pixel Engine

The Setup Engine uses the same sequential loading

mechanism as in the Rasterization Engine. The order of

loading is: Triangle Attribute, Vertex 0, Vertex 1 (optional),

Vertex 2 (optional). Whether vertex 1 and 2 are to be loaded

depends on the Primitive Type. Writing to BA+4Ch triggers a

loading sequence to the Setup Engine. The order of data in a

vertex is: RGBA, SrgbF, W, UV, Z, XY. Not every one will

appear in every vertex. Whether a particular item will be

present in a vertex is decided by the Triangle Attribute. For

example, the data in a stream for a texture mapped triangle

strip may look like: Triangle Attribute, U0V0, X0Y0.

Memory Interface

The interfaces among the components are:

•

AGP to Pixel Engine: Set drawing environment registers.

AGP to Rasterization Engine: Set primitives: edge

walking, slopes.

AGP or Setup Engine: Set vertices, culling info.

Setup Engine to Rasterization Engine: Set primitives:

edge walking, slopes.

Rasterization Engine to Pixel Engine: Pixel Data,

addresses and coordinates.

Pixel Engine to Memory Interface: Addresses and

coordinates, pixel data.

•

GEbase + 2C – Setup Engine Status................................. RO

Each unit performs the following functions:

31-0 Overflow Status

This register records setup engine overflow status. For every

triangle, the entire register is shifted left one bit with bit-0 then

set to reflect whether the triangle has slope overflow. This

register is usefuil for debugging purposes. This register

resides in the VGA address space and is not decoded by the

setup engine.

•

Setup Engine: Back face culling, slope calculation.

Rasterization Engine: Edge walking, color interpolation,

Z, texture coordinates, perform perspective correction.

Pixel Engine: Generate addresses and coordinate for all

memory accesses: read/write Z, read texture, read

source/destination, write destination (draw buffer), 2-D

functions, bi/tri-linear interpolation, blending and

modulation, ROP, Z test, alpha test, transparency, etc.

•

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Setup Engine Registers

GEbase + 30 – Setup Engine Primitive Attribute...........RW

31 Z Parameter

6

5

Z Normalization (Setup Engine Only)

0

1

Absent ....................................................default

Present (Setup Engine calculates Z slope)

0

1

Disable................................................... default

Enable

30 Texture Parameter

Flat Mode (applies to diffuse color, alpha, specular

0

1

Absent ....................................................default

Present (SE calculates Z slope)

color, and fog)

0

1

Smooth color or no color....................... default

Flat color. SE sends only starting values to RE

29 Perspective Factor Parameter

0

1

Absent ....................................................default

Present (SE calculates W slope)

4

Full Vertex Info

0

1

Disable................................................... default

28 Color Parameter

Enable. Indicates that all vertex data are

needed for the triangle. Software still needs to

set bits 31-25. However in this case, the data

order in a vertex is: X, Y, Z, W, RGBA,

SrgbF, U, V. Even though the vertex actually

contains all the data, software doesn’t

necessarily set this bit. When this bit is not

set, hardware decodes vertex data as described

in the Vertex Register descriptions.

0

1

Absent ....................................................default

Present (SE calculates color slope)

27 Specular Color Parameter

0

1

Absent ....................................................default

Present (SE calculates specular slope)

26 Fog Parameter

0

1

Absent ....................................................default

Present (SE calculates fog slope)

25 Step Mode

3

2

1

Sub-Pixel Precision (Rasterization Engine Only)

0

1

Disable ...................................................default

0

1

Disable................................................... default

Enable

Enable (SE will process the next primitive only

when it finishes the current primitive. There is

no parallelism between primitives)

Anti-Aliasing (RE Only)

0

1

Disable (walk at pixel precision) ........... default

Enable (walk at sub-pixel precision)

24-20 Reserved

19-15 LOD Adjust .............................................. default = 0

........................................ always reads 0

Auto Direction for Scan Line Ends (RE Only)

3.2 signed # to be added to calculate the LOD value

0

1

Disable................................................... default

Enable. Bits 31-2 must be 0. Scan order is

passed to the Pixel Engine based on the

comparison result of two end points instead of

the bit in the Primitive Type register. Software

should only use this bit for 2D polygons with

Bresenham edge walking.

14-7 Reserved

........................................ always reads 0

0

Bresenham Edge Walking (RE Only)

0

1

Use DDA to walk through edges ........... default

Use Bresenham algorithm to walk through

edges

This register is decoded by the Setup Engine and passed to the

Rasterization Engine by the Setup Engine. This register and

its equivalent part in the Rasterization Engine are “partially”

pipelined in the sense that there are only two levels of pipe for

this register in both engines while there are many levels for

other data. The two levels are the decoding level and the

execution level. Both the Rasterization Engine and the Setup

Engine use this register to decide what kind of operation to

perform and what kind of data stream to expect. It must be set

before any parameter can be loaded.

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GEbase + 3C –Setup Engine Primitive Type ................. WO

Vertex Registers

Writing to this register signals the Graphics Engine to begin

sequential loading. The engine will interpret the contents of

this register and the Primitive Attribute register to decide the

amount and types of parameters to expect. Like vertices, there

is a FIFO for Triangle Attributes. The queue has three entries.

Writing to this register adds it to the queue. The Setup Engine

starts working whenever a triangle attribute is received and

stops after it is finished processing a triangle with L = 1.

Inside the setup engine, one set of registers is provided to

store the three vertices is is currently working on and an

additional set is provided to store three pending vertices. Note

that it doesn’t always require 3 vertices to define a triangle

(depending on the Triangle Attribute Register, it may be either

1 or 3 vertices).

Vertex information includes coordinate, texture, color, and

depth. Some may be absent in a data stream. If any appear in

a vertex, they must be present in the following order: Color,

Specular Color, W, U, V, Z, X, Y. The formats are shown

below:

31-30 Loading Target

00 Rasterization Engine. Send bits 19-0 to the

RE. Sequential loading data will also be sent

to the RE.................................................default

01 Setup Engine. Send bits 29-0 to the SE.

Sequential loading data will also be sent to the

SE. Internally, a flag is set to prevent the SE

from decoding the data and sending it to the

RE. The SE will clear this flag when it is idle.

1x -reserved-

Vertex Register 1 - Color Value

31-24 Alpha Value

23-16 Red Value

15-8 Green Value

7-0 Blue Value

29 Null Primitive

Vertex Register 2 - Specular Color Value

0

1

Regular Primitive ...................................default

Null Primitive

31-24 Fog Value

23-16 Specular Red Value

15-8 Specular Green Value

7-0 Specular Blue Value

28 Last Primitive

0

1

Regular Primitive ...................................default

Last Primitive

27-26 Culling Attribute (Setup Engine Target Only)

00 No culling...............................................default

01 Clockwise culling

Vertex Register 3 - W Value

31-0 Texture W Coordinate. 32-bit floating # in (0, 1.0)

Vertex Register 4 - U Value

10 Counter-clockwise culling

11 No culling

31-0 Texture U Coordinate. 32-bit floating number

25 Reserved

........................................ always reads 0

Vertex Register 5 - V Value

24 (V2, V0) Edge Anti-Aliasing Flag........... default = 0

23 (V1, V2) Edge Anti-Aliasing Flag .......... default = 0

22 (V1, V1) Edge Anti-Aliasing Flag .......... default = 0

21 Full Vertices Information

31-0 Texture V Coordinate. 32-bit floating number

Vertex Register 6 - Z Value

31-0 Z Coordinate. 32-bit floating number

0

Partial Vertices Information. Two of the

vertices are from the previous triangle. Only

one vertex is to be loaded from the vertex

queue to the working registers................default

All vertices are new. All three working

registers are to be loaded from the vertex

queue.

Vertex Register 7 - X Value

31-0 X Coordinate. 32-bit floating number

1

Vertex Register 8 - Y Value

31-0 Y Coordinate. 32-bit floating number

20-19 Working Vertex Index

Floating Point Number Format

Index of the working vertex that is to be replaced.

This field is always 0 if F = 1.

All floating point numbers are converted by on-chip hardware

into internal fixed point integer format. All floating point

numbers are specified in IEEE 32-bit floating point number

format (shown below):

18-3 Reserved

........................................ always reads 0

2

Debug Control

0

1

Discard triangle on overflow..................default

Draw triangle on overflow

31 Sign

30-23 Exponent (excess-127 format)

22-0 Mantissa (fractional part of a number in “1.nn”

format where the integer part is always 1)

1-0 Flat Color Vertex Index

Vertex index for flat color (Index of vertex whose

color is passed to the RE as the starting color)

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Rasterization Engine Registers

The major responsibilities of the Rasterization Engine are:

Both Rasterization and Setup Engines share one interface to

the AGP Write Buffer. The first reason is that both

Rasterization Engine and Setup Engine use stream decoding to

receive data from the host. Once they are inside a stream,

they must act quickly to grab data to prevent other

components from taking the data. Having two stream

decoders in the graphics engine is a potential source for

problems. The second reason is that both the Rasterization

Engine and Setup Engine handle the same types of data.

Coupling them tightly makes the design easier and reduces

problems that arise from synchronization. The third reason is

for better synchronization between the two engines.

•ꢀ ^{Receive data from host: Set registers, sequential loading}

of parameters.

•ꢀ ^{Edge walking: Generate end points of polygon edges or}

pixels on a line.

•ꢀ ^{Interpolation:}

Calculate values such as texture

coordinates on a polygon / line.

•

Perspective correction: Perform perspective correction.

In the ProMedia, the Rasterization Engine performs color

(including alpha) interpolation, texture coordinate (perspective

corrected) generation, Z coordinate interpolation, and texture

gradient (perspective corrected) calculations.

The engine interfaces to the host through both random access

registers and sequential loading. There are two random access

registers: Primitive Attribute and Primitive Type. The

Primitive Attribute register consists of most parameter

information from the Rasterization Engine’s Primitive Type

and the Setup Engine’s Triangle Attribute register.

Host access to the Rasterization Engine is by sequential writes

to minimize AGP bandwidth requirements. This is not needed

for the Setup Engine to access the Rasterization Engine. In

addition, if sequential parameters were used to interface

between the Setup Engine and the Rasterization Engine, it

would incur extra cost for the Setup Engine to pack data and

would also reduce performance. Therefore, the Setup Engine

accesses working registers in the Rasterization Engine

directly. To synchronize operation, hardware must wait until

the Setup Engine becomes idle to accept data from the host to

the Rasterization Engine.

The address space that can be used by sequential loading

parameters is from Base Address + 40h to Base Address +

FFh. Software should not use addresses outside this space for

parameters. Sequential loading must use the address in this

space starting at 0x40H in ascending order. For example,

the first address must be 40h, the next must be 44h, etc. In

order to give time to notify the other component to stop

decoding, address 40h is exclusively reserved for sequential

loading.

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GEbase + 30 – RE Primitive Attribute............................RW

31 Z Parameter

0

1

Absent ....................................................default

Present (Rasterization Engine calculates Z

slope)

6

5

Z Normalization (Setup Engine Only)

0

1

Disable................................................... default

Enable

30 Texture Parameter

Flat Mode (applies to diffuse color, alpha, specular

color, and fog)

0

1

Absent ....................................................default

Present (RE calculates texture info)

0

1

Smooth color or no color....................... default

Flat color. RE forces deltas to 0.

29 Perspective Factor Parameter

0

1

Absent ....................................................default

Present (RE performs perspective correction)

4

Full Vertex Info

0

1

Disable................................................... default

28 Color Parameter

Enable. Indicates that all vertex data are

needed for the triangle. Software still needs to

set bits 31-25. However in this case, the data

order in a vertex is: X, Y, Z, W, RGBA,

SrgbF, U, V. Even though the vertex actually

contains all the data, software doesn’t

necessarily set this bit. When this bit is not

set, hardware decodes vertex data as described

in the Vertex Register descriptions.

0

1

Absent ....................................................default

Present (RE calculates Gouraud color

(RGBA))

27 Specular Color Parameter

0

1

Absent ....................................................default

Present (RE calculates specular color)

26 Fog Parameter

0

1

Absent ....................................................default

Present (RE calculates fog)

3

2

1

Sub-Pixel Precision (Rasterization Engine Only)

25 Step Mode

0

1

Disable................................................... default

Enable

0

1

Disable ...................................................default

Enable (RE will process the next primitive

only when it finishes the current primitive. No

parallelism exists between primitives)

Anti-Aliasing (RE Only)

0

1

Disable (walk at pixel precision) ........... default

Enable (walk at sub-pixel precision)

24-20 Reserved

19-15 LOD Adjust .............................................. default = 0

3.2 signed # to be added to calculate the LOD value

14-7 Reserved

........................................ always reads 0

Auto Direction for Scan Line Ends (RE Only)

0

1

Disable................................................... default

Enable. Bits 31-2 must be 0. Scan order is

passed to the Pixel Engine based on the

comparison result of two end points instead of

the bit in the Primitive Type register. Software

should only use this bit for 2D polygons with

Bresenham edge walking.

........................................ always reads 0

0

Bresenham Edge Walking (RE Only)

0

1

Use DDA to walk through edges ........... default

Use Bresenham algorithm to walk through

edges

This register is decoded by the Setup Engine and passed to the

Rasterization Engine by the Setup Engine. This register and

its equivalent part in the Rasterization Engine are “partially”

pipelined in the sense that there are only two levels of pipe for

this register in both engines while there are many levels for

other data. The two levels are the decoding level and the

execution level. Both the Rasterization Engine and the Setup

Engine use this register to decide what kind of operation to

perform and what kind of data stream to expect. It must be set

before any parameter can be loaded.

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GEbase + 3C – RE Primitive Type ................................. WO

Writing to this register signals the Graphics Engine to begin

sequential loading, but doesn’t cause anything to be drawn..

The engine will interpret the contents of this register and

decide the amount and types of parameters to expect.

31-30 Loading Target

00 Rasterization Engine. Send bits 19-0 to the

RE. Sequential loading data will also be sent

to the RE.................................................default

01 Setup Engine. Send bits 29-0 to the SE.

Sequential loading data will also be sent to the

SE. Internally, a flag is set to prevent the SE

from decoding the data and sending it to the

RE. The SE will clear this flag when it is idle.

1x -reserved-

29 Null Primitive

0

1

Regular Primitive ...................................default

Null Primitive

28 Last Primitive

0

1

Regular Primitive ...................................default

Last Primitive

27-26 Operation Code (RE Target Only)

00 Line .....................................................default

01 Polygon

1x -reserved-

25 Major Edge Parameter

0

1

Parameter is Absent (parameter stream doesn’t

include values for the iterators)..............default

Parameter is Present (parameter stream also

includes values for the iterators)

24 Major Edge Anti-Aliasing

0

1

Don’t anti-alias major edge ....................default

Anti-alias major edge (effective only if E = 1)

23 Minor Edge Parameter

0

1

Absent ....................................................default

Present

22 Minor Edge Anti-Aliasing

0

1

Don’t anti-alias minor edge....................default

Anti-alias minor edge (effective only if M = 1)

21 Scan Direction

0

1

Positive (Major edge = left edge)...........default

Negative (Major edge = right edge)

........................................ always reads 0

20-16 Reserved

15-0 End Coordinate.......................................default -= 0

End coordinate of the primitive (inclusive). 12.4

signed integer.

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Bresenham Edge Parameters

DDA Edge Parameters

Bresenham Edge parameters describe an edge of a primitive or

a line.

DDA Edge parameters describe an edge of a primitive or a

line.

DoubleWord 0 – Start Coordinates

31-16 Start YS1

Starting coordinate of the line in the Y direction

(signed 12.4 number). The fractional part must be 0.

This parameter is ignored in minor edges.

15-0 Start XS1

Starting coordinate of the line in the Y direction

(signed 12.4 number). The fractional part must be 0.

This parameter is ignored in minor edges.

15-0 Start XS1

Starting coordinate of the line in the X direction

(signed 12.4 number). The fractional part must be 0.

Starting coordinate of the line in the X direction

(signed 12.4 number). The fractional part must be 0.

DoubleWord 1 – Drawing Direction / Bresenham Constant

31 YS Drawing Direction

DoubleWord 1 – Drawing Direction / Edge Slope

31 YS Drawing Direction

0

1

Positive

Negative

0

1

Positive

Negative

30 XS Drawing Direction

0

Positive

0

Positive

1

Negative

1

Negative

29 Swap

0

1

Normal (X / Y not swapped)

X / Y swapped

0

1

Normal (X / Y not swapped)

X / Y swapped

28-16 Bresenham (or Modified) Constant

28-26 Reserved

25-0 Edge Slope

...................................................ignored

15-13 Reserved

................................................... ignored

12-0 Bresenham (or Modified) Constant

12.14 signed number

When a DDA edge is used as a polygon boundary, the

fractional bits should round up to the next integer.

Interpolation values should be adjusted accordingly. DDA

edge walking shares the same logic as Bresenham edge

walking by using an error advance method. In DDA walking,

fractional bits should be rounded up to the next integer.

Rounding up is performed by changing drawing convention

according to whether the fractional parts are 0 as follows:

DoubleWord 2 – Error Term / Strip Length

31-29 Reserved

...........................must be written as zero

28-16 Initial Error Term

15-12 Reserved

...........................must be written as zero

11-0 Strip Length

Strip length of modified Bresenham line.

•

Left fractional is 0: Left inclusive.

Left fractional is not 0: Left exclusive.

Right fractional is 0: Right exclusive.

Right fractional is not 0: Right inclusive.

Because the error advance method is used for DDA walking,

the fractional part is always one step ahead of the coordinate.

For the starting point of a line, the fractional part is assumed

to be 0.

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Color Parameters

Z Value Parameters

Color parameters are used for Gouraud shading. They consist

of starting values, incremental along the X and Y axis. In flat

color mode, this parameter only has the starting value.

To the Rasterization Engine, the Z value is always a 25.8

signed integer internally regardless of Z buffer depth. It

always passes a 24-bit unsigned integer to the Pixel Engine. It

is the Pixel Engine’s responsibility to scale Z to the depth of

the Z buffer. Z parameters are used to calculate depth

information. Z values consist of starting values, incremental

along the X and Y axis.

DoubleWord 0 – Initial Values

31-24 Initial Alpha Value

Initial Alpha value on main edge (left edge of

trapezoid or long edge of triangle). Unsigned integer.

23-16 Initial Red Value

DoubleWord 0 – Initial Z Value

Initial Red value on main edge (left edge of trapezoid

or long edge of triangle). Unsigned integer.

15-8 Initial Green Value

31-0 Initial Z Value

Initial Z value on main edge (left edge of trapezoid or

long edge of triangle). Signed 25.7 integer.

Initial Green value on main edge (left edge of

trapezoid or long edge of triangle). Unsigned integer.

7-0 Initial Blue Value

DoubleWord 1 – X-Axis Z Gradient

Initial Blue value on main edge (left edge of

trapezoid or long edge of triangle). Unsigned integer.

31-0 X-Axis Z Gradient

Gradient of Z along the X axis over the primitive

surface. Signed 25.7 number.

DoubleWord 1 – X-Axis Blue Gradient

31-0 X-Axis Blue Gradient

DoubleWord 2 – Y-Axis Z Gradient

Gradient of Blue along the X axis over the primitive

surface. Signed 20.12 number.

31-0 Y-Axis Z Gradient

Gradient of Z along the Y axis over the primitive

surface. Signed 25.7 number.

DoubleWord 2 – Y-Axis Blue Gradient

31-0 Y-Axis Blue Gradient

Gradient of Blue along the Y axis over the primitive

surface. Signed 20.12 number.

DoubleWord 3 – Minimum Z Threshold

31-24 Reserved

...................................................ignored

23-0 Minimum Z Threshold

DoubleWord 3 – X-Axis Green Gradient

31-0 X-Axis Green Gradient

Minimum of Z threshold. Unsigned 24-bit integer.

Gradient of Green along the X axis over the primitive

surface. Signed 20.12 number.

DoubleWord 4 – Maximum Z Threshold

31-24 Reserved

...................................................ignored

DoubleWord 4 – Y-Axis Green Gradient

23-0 Maximum Z Threshold

31-0 Y-Axis Green Gradient

Maximum of Z threshold. Unsigned 24-bit integer.

Gradient of Green along the Y axis over the primitive

surface. Signed 20.12 number.

DoubleWord 5 – X-Axis Red Gradient

31-0 X-Axis Red Gradient

Gradient of Red along the X axis over the primitive

surface. Signed 20.12 number.

DoubleWord 6 – Y-Axis Red Gradient

31-0 Y-Axis Red Gradient

Gradient of Red along the Y axis over the primitive

surface. Signed 20.12 number.

DoubleWord 7 – X-Axis Alpha Gradient

31-0 X-Axis Alpha Gradient

Gradient of Alpha along the X axis over the primitive

surface. Signed 20.12 number.

DoubleWord 8 – Y-Axis Alpha Gradient

31-0 Y-Axis Alpha Gradient

Gradient of Alpha along the Y axis over the primitive

surface. Signed 20.12 number.

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Texture Coordinate Parameters

Perspective Factor Parameters

Texture parameters are used for texture mapping. They

consist of starting values, incremental along the X and Y axis.

Perspective factor parameters are used for perspective

corrected texture mapping. They consist of W starting values

incremental along the X and Y axis.

DoubleWord 0 – Initial U Value

DoubleWord 0 – Initial W Value

31-0 Initial U Value

Initial U value on main edge (left edge of trapezoid or

long edge of triangle). Signed 16.16 integer.

31-0 Initial W Value

Initial W value on main edge (left edge of trapezoid

or long edge of triangle). Signed 4.28 integer.

DoubleWord 1 – Initial U Value

31-0 Initial U Value

Initial U value on main edge (left edge of trapezoid or

long edge of triangle). Signed 16.16 integer.

DoubleWord 1 – X-Axis W Gradient

31-0 X-Axis W Gradient

Gradient of W along the X axis over the primitive

surface. Signed 4.28 number.

DoubleWord 2 – X-Axis U Gradient

DoubleWord 2 – Y-Axis W Gradient

31-0 X-Axis U Gradient

Gradient of U along the X axis over the primitive

surface. Signed 16.16 number.

31-0 Y-Axis W Gradient

Gradient of W along the Y axis over the primitive

surface. Signed 4.28 number.

DoubleWord 3 – Y-Axis U Gradient

31-0 Y-Axis U Gradient

Gradient of U along the Y axis over the primitive

surface. Signed 16.16 number.

DoubleWord 4 – X-Axis V Gradient

31-0 X-Axis V Gradient

Gradient of V along the X axis over the primitive

surface. Signed 16.16 number.

DoubleWord 5 – Y-Axis V Gradient

31-0 Y-Axis V Gradient

Gradient of V along the Y axis over the primitive

surface. Signed 16.16 number.

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Specular / Fog Start Value

Fog Parameters

The specular / fog start value is used for specular shading or

fogging.

Fog parameters are used for fogging. These parameters are

not present in flat color mode and consist of starting values

incremental along the X and Y axis.

DoubleWord 0 – Start Value

DoubleWord 0 – X-Axis Fog Gradient

31-24 Initial Fog Value

Initial Fog value on main edge (left edge of trapezoid

or long edge of triangle). Unsigned integer.

23-16 Initial Red Value

31-0 X-Axis Fog Gradient

Gradient of Fog along the X axis over the primitive

surface. Signed 20.12 number.

Initial Red value on main edge (left edge of trapezoid

or long edge of triangle). Unsigned integer.

15-8 Initial Green Value

Initial Green value on main edge (left edge of

trapezoid or long edge of triangle). Unsigned integer.

7-0 Initial Blue Value

DoubleWord 1 – Y-Axis Fog Gradient

31-0 Y-Axis Fog Gradient

Gradient of Fog along the Y axis over the primitive

surface. Signed 20.12 number.

Initial Blue value on main edge (left edge of

trapezoid or long edge of triangle). Unsigned integer.

Specular Parameters

Specular parameters are used for specular shading. These

parameters are not present in flat color mode and consist of

starting values incremental along the main direction ((dx, dy) =

(M1, 1)), and incremental along the X axis.

DoubleWord 0 – X-Axis Blue Gradient

31-0 X-Axis Blue Gradient

Gradient of Blue along the X axis over the primitive

surface. Signed 20.12 number.

DoubleWord 1 – Y-Axis Blue Gradient

31-0 Y-Axis Blue Gradient

Gradient of Blue along the Y axis over the primitive

surface. Signed 20.12 number.

DoubleWord 2 – X-Axis Green Gradient

31-0 X-Axis Green Gradient

Gradient of Green along the X axis over the primitive

surface. Signed 20.12 number.

DoubleWord 3 – Y-Axis Green Gradient

31-0 Y-Axis Green Gradient

Gradient of Green along the Y axis over the primitive

surface. Signed 20.12 number.

DoubleWord 4 – X-Axis Red Gradient

31-0 X-Axis Red Gradient

Gradient of Red along the X axis over the primitive

surface. Signed 20.12 number.

DoubleWord 5 – Y-Axis Red Gradient

31-0 Y-Axis Red Gradient

Gradient of Red along the Y axis over the primitive

surface. Signed 20.12 number.

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Pixel Engine Registers

Data from the Host

The major responsibilities of the Pixel Engine are to perform

per-pixel operations and to control data flow and its sequence.

The Pixel Engine can accept data from the host through either

the 32-bit data port register at 9Ch or data in the 1xxxh

Software passes only enough DWORDs to

Software doesn’t pack data to 64-bit

address space.

hardware.

The Pixel engine interfaces to the Rasterization Engine and

the host to accept data. It also interfaces to the Memory

Interface to access video memory. Inside the Pixel Engine,

there are several blocks: the Span Engine, the Data Path, and

the Texture Engine. Operation of the Data Path and the

Texture Engine are under control of the Span Engine. The

Memory Interface accepts memory access requests from the

Pixel Engine, translates the address into a linear address, and

executes the requests.

boundaries. It only packs to 32-bit boundaries.

For bitblts,

packing is done per-scanline. I.e., for every scanline, the host

will send just enough DWORDs to the engine. For text,

packing is done per-command. I.e., the scanline may be

broken inside a DWORD. For a string of texts, the number of

DWORDs of data passed to the Graphic Engine can be odd

numbers except for the last character. For the last character,

software should pass either an even number of DWORDs (by

padding a garbage DWORD as necessary) or by setting a

drawing environment register after all data is sent.

AGP

Rasterization

Data Path

D

Texture Engine

Span

A

D

Memory Interface

The 0 - FFh “Engine” register address space is partitioned

into six sections:

0 - 0Fh

10 - 2Fh

30 - 3Fh

44 - 9Fh

A0 – AFh

B0 – BFh

C0 – FFh

Span Engine

VGA core

Unified Rasterization and Setup Engines

Pixel Engine

Texture Engine

Command List Control Unit

Memory Interface

Addresses 40h - FFh are also used for sequential loading

overlapping with other registers in this space. Addresses

10000

-

1FFFFh are used as

a

data port area.

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3D Graphics Engine Registers

VT8601 Apollo ProMedia

GEbase + 44 – Drawing Command..................................RW

Writing to the Drawing Command register starts a drawing

operation. When this register is set, the drawing environment

registers and memory interface registers are locked in. Any

change to these registers will not affect this drawing

operation. Furthermore, the Pixel Engine will not accept any

data from the host or from the Rasterization Engine without a

drawing command. After a drawing command is issued, the

Pixel Engine will selectively accept data from the host or

Rasterization Engine depending on the command.

Specifically, the Pixel Engine only accepts data from the host

if the command is text or blt and the BS field indicates the

source is from the host. The Pixel Engine only accepts data

(scanlines, Z, color, etc.) from the Rasterization Engine if the

command is line or polygon.

20 Source Color Expansion

0

1

Disable

Enable (bits 26-21 must be 0)

19 Source Color

0

1

Transparent (applies to mono source and

constant color line)

Opaque (should be enabled for any operation

with a “solid Source”, such as Gouraud

shading, constant color fill, color to screen blt,

texture mapping, etc.)

18-17 Source Surface ID

16-15 Destination Surface ID

14-12 Source Offset

Mono source pixel offset. Bit-19 must be 1.

11 Double Specular Color

31-28 Operation Code

0000 Null Command .......................................default

0001 -reserved-

0

1

Disable

Enable. Specular color (RGB) is doubled

before being added to diffuse color.

0010 Line

0011 -reserved-

01xx -reserved-

10 Texture Transparency

0

1

Disable texture color key

Enable texture color key

1000 Bit-Blt (see note below)

1001 Text (see note below)

1010 (See BitBlt)

1011 Trapezoid / Polygon

1100 (See Bit Blt)

1101 (See Text)

1110 Trapezoid / Polygon

1111 -reserved-

9

8

Lit-Texture

0

Disable

1

Enable

Dither

0

1

Disable

Enable. Use 4x4 dither matrix (including fog

and alpha)

7

6

5

4

Source Color Key

Note: for Text and BitBlt opcodes, bit 29 indicates

whether the PE can accept data from the host

while bit-30 indicates whether the PE can

accept data from the RE.

27 Line Style

0

1

Disable

Enable (Key is FG)

Destination Color Key

0

1

Disable

Enable

0

No style, solid line, or other operation (blt,

Bit Mask

polygon, text)

Style line

0

Disable

1

ROP

0

Enable

26 Z Operations

0

1

Disable Z operations (must be 0 for text, blt)

Enable Z operations

Disable

Enable

1

25 Alpha Test

3-2 Blt Source or Constant Color Line or Polygon

00 Source from host (bits 26-20 must be 0 for blt)

01 Source from frame buffer

0

1

Disable (must be 0 for text)

Enable

24 Texture Function

10 Source is constant (FG). Includes constand

line and constant polygon.

11 Block write fill

0

1

Disable (must be 0 for blt, text)

Enable

23 Alpha Blending

This field must be set to 00 for text / line / polygon.

0

1

Disable (must be 0 for text)

Enable

1

0

Blt Direction (BLT Only)

0

1

Positive direction in X and Y

Negative direction in X and Y

22 Specular Color

0

1

Disable (must be 0 for blt, text)

Enable

Must be set to 0 for polygons, lines, and text.

Clipping

21 Fog

0

1

Disable

Enable

0

1

Disable (must be 0 for blt, text)

Enable

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3D Graphics Engine Registers

VT8601 Apollo ProMedia

GEbase + 48 – Raster Operation (ROP) .........................RW

GEbase + 4C – Z Function............................................... RW

31 Z-Bias

31-8 Reserved

........................................ always reads 0

0

1

Disable

Enable

7-0 ROP3 Code

30-17 Reserved

........................................always reads 0

16-7 Z-Bias Value

6

Test Alpha

0

1

Disable

Enable

5

Z-Buffer Write

0

1

Disable

Enable

4-3 Reserved

2-0 Z-Buffer Compare

000 Compare False. Z and RGB values will not be

........................................always reads 0

written to memory.

001 Compare Less Than. Z and RGB values will

be written to memory if the current Z value is

less than the Z value in memory.

010 Compare Equal. Z and RGB values will be

written to memory if the current Z value is

equal to the Z value in memory.

011 Compare Less Than or Equal. Z and RGB

values will be written to memory if the current

Z value is less than the Z value in memory.

100 Compare Greater Than. Z and RGB values

will be written to memory if the current Z

value is greater than the Z value in memory.

101 Compare Not Equal. Z and RGB values will

be written to memory if the current Z value is

not equal to the Z value in memory.

110 Compare Greater Than or Equal. Z and RGB

values will be written to memory if the current

Z value is greater than or equal to the Z value

in memory.

111 Compare True. Z and RGB values will be

written to memory.

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3D Graphics Engine Registers

VT8601 Apollo ProMedia

GEbase + 50 – Texture Function......................................RW

GEbase + 60 – Color 0 (Foreground).............................. RW

31-0 Foreground Color Value

31-22 Maximum U

21-12 Minimum U

GEbase + 64 – Color 1 (Background) ............................. RW

31-0 Background Color Value

11-5 Reserved

........................................ always reads 0

4

Mask

0

1

Disable

Enable

Note: In 16- and 8- bit modes, the color must be duplicated to

fill an entire 32-bit word. 32-bit color is in ARGB format

(i.e., Alpha, Red, Green, and Blue in bytes 3-0 respectively)

and 16-bit color is in RGB 565 format (5 bits of Red, 6 bits of

Green, and 5 bits of Blue).

3-2 Texture Alpha

00 Texel alpha

01 Source alpha

10 Modulated alpha: texel alpha x source alpha

11 -reserved-

1-0 Texture Color

00 Texel color

GEbase + 68 – Color Key................................................. RW

01 Source color

10 Modulated color: texel color x source color

11 -reserved-

31-26 Reserved

........................................always reads 0

25 Destination Polarity

0

1

Draw on Equal

24 Source Polarity

0

1

Draw on Equal

GEbase + 54 – Clipping Window 0..................................RW

31-28 Reserved

27-16 Clipping Window Top ............................. default = 0

15-12 Reserved

........................................ always reads 0

23-0 Destination Color Key Color

Unlike foreground and background, the color is not

replicated in 16-bit or 8-bit modes.

11-0 Clipping Window Left ............................ default = 0

GEbase + 58 – Clipping Window 1..................................RW

31-28 Reserved

27-16 Clipping Window Bottom........................ default = 0

15-12 Reserved

........................................ always reads 0

11-0 Clipping Window Right .......................... default = 0

........................................ always reads 0

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3D Graphics Engine Registers

VT8601 Apollo ProMedia

GEbase + 6C – Pattern and Style.....................................RW

31 Pattern Color Expansion

GEbase + 74 – Pattern Foreground Color...................... RW

31-0 Foreground Color Value..........................default = 0

0

1

Disable ...................................................default

Enable

GEbase + 78 – Pattern Background Color ..................... RW

31-0 Background Color Value .........................default = 0

30 Pattern Transparency

0

1

Opaque ...................................................default

Transparent

Note: In 16- and 8- bit modes, the color must be duplicated to

fill an entire 32-bit word. 32-bit color is in ARGB format

(i.e., Alpha, Red, Green, and Blue in bytes 3-0 respectively)

and 16-bit color is in RGB 565 format (5 bits of Red, 6 bits of

Green, and 5 bits of Blue).

29 Pattern Size

0

1

8 x 8 pixels .............................................default

32 x 32 pixels (mono only)

28 Pattern Register Segment

0

1

Low Segment..........................................default

High Segment

Note: The pattern cache is divided into two segments

for double pattern purposes. This bit serves two

purposes: First as the starting segment for loading a

pattern into the pattern cache, the corresponding

address is latched into an internal register which will

automatically increase by one when data is loaded.

Second as the segment base of the current pattern

when applying a pattern.

27-24 Reserved

........................................ always reads 0

23-16 Pattern Style Step

The # of pixels each mask bit should be mapped to:

00 1 Pixel per mask bit................................default

01 2 pixels per mask bit

02 3 pixels per mask bit

… …

FF 256 pixels per mask bit

15-0 Pattern Style Mask

Determines the line drawing style (e.g., dotted line).

Bit-0 maps to the first pixel. Writing to the low byte

of ths register (GEbase + 6C) causes the internal style

count to be reset to 0. When 3D operations are

enabled (smooth shading, texture, Z), style line must

be transparent and style applies to color as well as Z.

GEbase + 70 – Pattern Color............................................RW

31-0 Pattern Color Value

Must follow the command. The pattern data could be

repeated up to 64 times to fill out the pattern register

file.

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3D Graphics Engine Registers

VT8601 Apollo ProMedia

GEbase + 7C – Alpha........................................................RW

31-16 Reserved

........................................ always reads 0

GEbase + 80 – Alpha Function........................................ RW

31-24 Reserved

........................................always reads 0

15-8 Source Constant Alpha

23 Alpha Write

7-0 Destination Constant Alpha

0

1

Disable................................................... default

Enable. Draw each pixel with a blended alpha

value if alpha blending is enabled. Otherwise

draw with source alpha (the upper byte of the

Foreground Color register if not available).

This bit should be set in 8-bit and 16-bit color modes.

22 Constant Source Alpha

0

1

Disable .................................................. default

Enable

21 Constant Destination Alpha

0

1

Disable .................................................. default

Enable

20 Result Alpha

GEbase + 84 – Bit Mask....................................................RW

0

1

The result of blending ........................... default

Source alpha

31-0 Bit Mask

One bits indicate that the corresponding color bit will

not be written to the frame buffer.

19-16 Alpha Test Function

0000 Never accept the pixel

0001 Accept if alpha < reference alpha

0010 Accept if alpha == reference alpha

0011 Accept if alpha <= reference alpha

0100 Accept if alpha > reference alpha

0101 Accept if alpha != reference alpha

0110 Accept if alpha >= reference alpha

0111 Always accept the pixel

1xxx -reserved-

15-8 Reference Alpha Value

7-4 Destination Blending Factor

0000 (0,0,0,0)

0001 (1,1,1,1)

0010 (RS,GS,BS,AS)

0011 (1,1,1,1) - (RS,GS,BS,AS)

0100 (AS,AS,AS,AS)

0101 (1,1,1,1) – (AS,AS,AS,AS)

0110 (AD,AD,AD,AD)

0111 (1,1,1,1) – (AD,AD,AD,AD)

1xxx -reserved-

3-0 Source Blending Factor

0000 (0,0,0,0)

0001 (1,1,1,1)

001x -reserved-

0100 (AS,AS,AS,AS)

0101 (1,1,1,1) – (AS,AS,AS,AS)

0110 (AD,AD,AD,AD)

0111 (1,1,1,1) – (AD,AD,AD,AD)

1000 (RD,GD,BD,AD)

1001 (1,1,1,1) - (RD,GD,BD,AD)

1010 (F,F,F,1); F = min (AS, 1-AD)

1011 -reserved-

11xx -reserved-

Revision 1.3 September 8, 1999

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3D Graphics Engine Registers

VT8601 Apollo ProMedia

Texture Engine Registers

The texture Engine handles texture access and filtering. It is

controlled by the Span Engine. It accepts texture coordinates

from the Rasterization Engine, generates and passes addresses

to the Memory Interface, accepts raw texel data from the

Memory Interface, does filtering, and passes the results to the

Data Path.

GEbase + A0 – Texture Control.......................................RW

Textures are aligned to 64-bit boundaries on a scanline basis.

19 Tiling

0

1

Texture is not tiled

Texture is tiled.

Tile size is determined by texel depth:

Texel Depth (bpp) Tile Size

31 Texture Access Control

0

1

Disable (use cache)

Enable (bypass cache)

30 Filtering Control

1

2

4

8

16

32

16 x 16

8 x 16

8 x 8

4 x 8

4 x 4

0

1

Filter with color key. Treat alpha value for

keyed texels as 0

Downgrade filtering function based on

fractional bits of UV and key test result. Set

alpha to 0 for keyed texels.

2 x 4

29-28 Texture U Boundary Checking Function

00 Texture U wraparound

01 Texture U mirroring

10 Texture U clamping

11 -reserved-

27-26 Texture V Boundary

00 Texture V wraparound

01 Texture V mirroring

10 Texture V clamping

11 -reserved-

Inside each tile, texels are organized into 2x2

subtiles in row major

18 Texture Color Key

0

1

Disable

Enable

17 Texture Anisotropy

0

1

Disable

Enable

16-15 Palette Data Format

00 565 RGB

01 1555 ARGB

10 4444 ARGB

11 -reserved-

25 Texture in System Memory

0

1

Texture is stored in graphics memory

Texture is stored in system memory

24 Reserved (must be 0)

23 MipMap

14-12 Texel Depth

000 1-bpp palettized

001 2-bpp palettized

010 4-bpp palettized

011 8-bpp palettized

100 16-bpp 565 RGB

101 16-bpp 1555 ARGB

110 16-bpp 4444 ARGB

111 32-bpp ARGB

0

1

Disable

Enable

22 Intra-map Filter

0

1

Disable

Enable (do filtering inside a LOD level)

21 Inter-map Filter

0

1

Disable

Enable (do filtering inside a LOD level)

M must be 1.

11-8 Texture Map Levels (TML) (Range 0-8)

The number of maps in the MipMap (0 = 1 map)

7-4 Y-Axis Texture Memory Size (TRY) (Range 0-8)

This field determines the number of lsb’s (2**TRY)

of parameter V to be used in the Y axis. Any bit

higher than this will be ignored (wraparound).

3-0 X-Axis Texture Memory Size (TRX) (Range 0-8)

This field determines the number of lsb’s (2**TRX)

of parameter U to be used in the X axis. Any bit

higher than this will be ignored (wraparound).

Note: For MipMap textures, TRX/TRY is the size of the

original texture (1:1 map)

20 Magnify Filter (when LOD < 0)

0

1

Point Sample

Bi-linear

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3D Graphics Engine Registers

VT8601 Apollo ProMedia

GEbase + A4 – Texture Color ..........................................RW

Texture Filtering

31-24 Alpha

Texture data read back from the Memory Interface first goes

through palette translation if the texture is palettized. The

texture is then converted into common internal 8888 ARGB

format. If the texture doesn’t have alpha data, then a constant

alpha value is used. If the texture color key is enabled and the

texture color matches the key, set alpha to 0. Bi-linear or tri-

linear filtering is then performed on RGB and alpha. If the

color key is enabled and the result alpha is 0, the

corresponding pixel should be discarded. This is done by

attaching a validity bit with texture data passed from the

Texture Engine to the Data Path. It should be noted that

filtering depends on the LOD value. When LOD < 0, a

different filter may be applied. In bi-linear filtering, if the

texel nearest to the texture coordinate is masked by the color

key, then the texel is considered as masked. Otherwise, the

texel is considered not masked.

Constant alpha value when there is no alpha in the

texture format

23-0 Texture Color Key

Texture transparency color (888 RGB)

GEbase + A8 – Texture Palette Data.............................. WO

31-16 Texel n+1

15-0 Texel n

An internal counter is used in loading the texture palette.

Writing to the Texture register (GEbase+A0) resets the

counter to 0. Writing to the Texture Palette Data register

writes the data to the place pointed to by the counter then

increments the counter by 1. Each write writes two entries into

the palette.

GEbase + AC – Texture Boundary..................................RW

31-22 Maximum V

21-12 Minimum V

11-8 Reserved

........................................ always reads 0

7

6

5

Reverse Texture Format

0

1

Disable

Enable

Texture Cache

0

1

Disable

Enable

Texture Map Shift

0

1

Disable

Enable

4-3 Compressed Texture Format

00 No compression

01 DXT1 format

10 DXT2 format

11 -reserved-

2-0 Dither Shift

000 Disable LOD dithering

001 100% LOD dithering

010 80% LOD dithering

011 60% LOD dithering

100 40% LOD dithering

101 20% LOD dithering

11x -reserved-

Revision 1.3 September 8, 1999

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3D Graphics Engine Registers

VT8601 Apollo ProMedia

Memory Interface Registers

The registers in this group include stride and buffer base

address registers for frame buffer control. There are three

base addresses: source base address (added to blt source),

destination base address (added to color destination), and Z

base address (added to Z addresses).

There are 9 texture base registers for up to 9 levels of

MipMaps: level 0 (1:1 map) up to level 8 (smallest). The

texture may be in the frame buffer or in system memory.

GEbase+DC – Texture Base MipMap Level 0 (1:1 Map)RW

GEbase + E0 – Texture Base MipMap Level 1 .............. RW

GEbase + E4 – Texture Base MipMap Level 2 .............. RW

GEbase + E8 – Texture Base MipMap Level 3 .............. RW

GEbase + EC – Texture Base MipMap Level 4 ............. RW

GEbase + F0 – Texture Base MipMap Level 5 .............. RW

GEbase + F4 – Texture Base MipMap Level 6 .............. RW

GEbase + F8 – Texture Base MipMap Level 7 .............. RW

GEbase + B8 – Destination Stride / Buffer Base 0..........RW

GEbase + BC – Destination Stride / Buffer Base 1.........RW

GEbase + C0 – Destination Stride / Buffer Base 2 .........RW

GEbase + C4 – Destination Stride / Buffer Base 3 .........RW

GEbase + C8 – Source Stride / Buffer Base 0 .................RW

GEbase + CC – Source Stride / Buffer Base 1 ................RW

GEbase + D0 – Source Stride / Buffer Base 2 .................RW

GEbase+FC – Texture Base MipMap Level 8 (Smallest)RW

GEbase + D4 – Source Stride / Buffer Base 3 .................RW

All nine of the above registers have the same bit definitions:

All eight of the above registers have the same bit definitions:

31-0 Texture Base Address (in bytes)

Base addresses always start on QWORD boundaries

so bits 2-0 are always 0.

31-29 Bits Per Pixel

000 8 bits per pixel

001 16 bits per pixel (565 format)

010 32 bits per pixel

011 -reserved-

100 -reserved-

101 16 bits per pixel (555 format)

11x -reserved-

28-20 Stride (pixels divided by 8)

19-0 Buffer Base Address (in quadwords)

Data Port Area

GEbase + 10000-1FFFFh – Data Port Area ................... RW

GEbase + D8 – Z Depth / Z Buffer Base..........................RW

31-30 Z Depth

00 16 bits

01 24 bits (32 bits are allocated in the frame

buffer with the MSB not used)

1x -reserved-

29 Reserved

28-20 Z Stride

........................................ always reads 0

19-0 Z Buffer Base Address (in quadwords)

Revision 1.3 September 8, 1999

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3D Graphics Engine Registers

VT8601 Apollo ProMedia

FUNCTIONAL DESCRIPTIONS

System Configuration

The Apollo ProMedia has several modes that are required to

be determined at reset time. This includes DFP monitor modes

for selecting the correct display device and test modes to assist

in board debug and trouble-shooting for manufacturing.

DFP Interface Configuration

The Apollo ProMedia uses the MA[6} pin in conjunction with

the RESET# pine to select if the DFP interface is ON or OFF.

This is primarily used for test purposes.

LCD On/Off Mode

LCD OFF

MA[6]

0

1

LCD ON

The LCD type is selected by MA[5-3]:

LCD Type

TFT

LCD Resolution

1024 x 768 x 18-bit

1280 x 1024 x 18-bit

800 x 600 x 18-bit

1024 x 600 x 18-bit

1024 x 768 x 16-bit

1024 x 600 x 24-bit

800 x 600 x 16-bit

1024 x 768 x 24-bit

MA[5-3]

000

TFT

DSTN

001

010

011

100

101

110

111

Revision 1.3 September 8, 1999

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Functional Descriptions

VT8601 Apollo ProMedia

Power Management Registers

Graphics Controller Power Management

Power management control for the ProMedia Graphics

Controller is provided by extended registers SR24 (Power

Management Control), GR20 (Standby Timer Control), GR21

(Power Management Control 1), GR22 (Power Management

Control 2), GR23 (Power Status), GR24 (Soft Power Control),

GR25 (Power Control Select), GR26 (DPMS Control), GR27-

28 (GPIO Control), GR2A (Suspend Pin Timer), GR2C

(Miscellaneous Pin Control), GR2F (Miscellaneous Internal

Control), and Graphics Controller PCI Configuration Indices

90-97 (PCI Power Management Registers 1 and 2).

The ProMedia Graphics Controller power mangement feature

set complies with AGP and PCI power management

requirements.

Power Management States

Power management states (D0-D3) for both ACPI and PCI

Bus Power Management (PCI PM) refer to the same states

described in the Device Class PM Reference Specification for

Display Devices, which are equivalent to the VESA™ DPMS

power states. System software should access the ProMedia’s

configuration registers to perform PCI PM state transitions.

Table 12. PCI Power Management States

PCI PM

State

Desktop

Graphics

Notebook

Graphics

State 0

(D0)

DPMS State 0

Fully On

Proprietary State 0

Fully On

State 1

(D1)

DPMS State 1

Proprietary State 1

Standby

(Hsync Off)

DPMS State 2

Suspend

(VCLK Off)

Proprietary State 2

Suspend

State 2

(D2)

(Vsync Off)

DPMS State 3

Off

(MCLK/VCLK Both Off)

State 3

(D3)

Same as State 2

(H/Vsync Both Off)

Power Management Clock Control

If the system “South Bridge” sends a request to the ProMedia

to power down the memory controller, the ProMedia first uses

CLKRUN# (the same signal appearing external to the

ProMedia) to check to see if the internal graphics controller

needs to access main memory. The graphics controller logic

will detect CLKRUN# high for 2 or 3 PCICLK’s and check if

there are any:

Internal buffers not emptied

PCI Master or AGP Master actions pending

If either condition exists, the graphics controller logic will

assert CLKRUN# low for 2 PCICLK’s to signal the clock

generator to keep PCICLK running.

PME# is not implemented since there are no wake-up

conditions.

Revision 1.3 September 8, 1999

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Functional Descriptions

VT8601 Apollo ProMedia

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

Table 13. Absolute Maximum Ratings

Symbol Parameter

Min

0

Max

70

Unit Notes

o

T_A

T_S

Ambient operating temperature

C

1

o

Storage temperature

Input voltage

-55

-0.5

125

C

1

V_IN

V_OUT

V_RAIL+ 10%

Volts

1, 2

Output voltage

Note 1: Stress above the conditions listed may cause permanent damage to the device. Functional operation of

this device should be restricted to the conditions described under operating conditions.

Note 2. V_RAILis defined as the V_CClevel of the respective rail. The CPU interface can be 3.3V or 2.5V.

Memory can be 3.3V only. PCI can be 3.3V or 5.0V. Video can be 3.3V or 5.0V. Flat Panel can be 3.3V only.

DC Characteristics

o

T_A= 0-70 C, V_RAIL= V_CC+/- 5%, V_CORE= 2.5V +/- 5%, GND=0V

Table 14. DC Characteristics

Symbol Parameter

Min

Max

Unit Condition

V_IL

V_IH

V_OL

V_OH

I_IL

Input Low Voltage

-0.50

0.8

V

Input High Voltage

2.0

V_CC+0.5

0.55

V

Output Low Voltage

Output High Voltage

Input Leakage Current

Tristate Leakage Current

Power Supply Current

-

2.4

-

V

I_OL=4.0mA

-

I_OH=-1.0mA

0<V_IN<V_CC

+/-10

+/-20

uA

mA

I_OZ

-

0.55<V_OUT<V_CC

I_CC

-

AC Timing Specifications

AC timing specifications provided are based on external zero-pf capacitance load. Min/max cases are based on the following table:

Table 15. AC Timing Min / Max Conditions

Parameter

Min

Max

Unit

5.0V Power

4.75

5.25

Volts

3.3V Power

2.5V Power

Temperature

3.135

2.375

0

3.465

2.625

70

Volts

o

C

Drive strength for selected output pins is programmable. See Rx6D for details.

Revision 1.3 September 8, 1999

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Electrical Specifications

VT8601 Apollo ProMedia

MECHANICAL SPECIFICATIONS

97ꢀꢁꢂꢃ

Y = Date Code Year

W = Date Code Week

R = Chip Revision

L = Lot Code

510-Pin BGA

35x35x2.33 mm

JEDEC Spec MO-151

Figure 9. Mechanical Specifications - 510-Pin Ball Grid Array Package

Revision 1.3 September 8, 1999

-138-

Mechanical Specifications


型号：	VT8601
厂家：	ETC
描述：	Single-Chip Slot-1 / Socket-370 PCI North Bridge With Integrated AGP 2D / 3D Graphics Accelerator and Advanced Memory Controller 单芯片的Slot- 1 /插座-370 PCI北桥，集成AGP 2D / 3D图形加速器和先进的内存控制器插座内存控制器 PC 时钟
文件：	总144页 (文件大小：1188K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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