VT86C100A [ETC]

PCI FAST ETHERNET CONTROLLER; PCI快速以太网控制器


型号：	VT86C100A
厂家：	ETC
描述：	PCI FAST ETHERNET CONTROLLER PCI快速以太网控制器控制器 PC 以太网以太网：16GBASE-T
文件：	总32页 (文件大小：351K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VIA Technologies, Inc.

Preliminary VT86C100A

VT86C100A

PCI FAST ETHERNET CONTROLLER

DATA SHEET

(Preliminary)

DATE : Aug 31, 1997

VIA TECHNOLOGIES, INC.

VIA Technologies, Inc.

Preliminary VT86C100A

PRELIMINARY RELEASE

Please contact Via Technologies for the latest documentation.

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Incorporated.

The VT86C100A may only be used to identify products of Via Technologies.

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VIA Technologies, Inc.

Preliminary VT86C100A

VT86C100A PCI FAST ETHERNET CONTROLLER FEATURES

* Single chip Fast Ethernet controller for PCI bus interface

-- compliant to PCI v2.1 with optional delay transaction and sub-vendor, sub-system- ID

-- Provides a direct connection to PCI bus

-- Supports two network ports : 10/100 M MII interface

* High performance PCI mastering structure

-- VIA self-define 128 bytes memory I/O or register I/O based command and status register

-- Software oriented chain structure description to minimize hardware complexity

-- Include on chip bus master DMA with programmable burst length for low CPU utilization

-- Dynamic transmit packet auto queuing for back auto queuing for bac for back to back transmissin

-- Programmable activity polling intervals for description DMA

-- Programmable DMA arbitration priority to minimize overflow under flow condition

-- Support early receive and early transmit interrupt for software parallel processing

-- Interrupt controllable by receive/transmit descriptor list for saving interrupt service time

* Provides standard 100-M bits MII interface

-- Support 100Base-TX with CAT5 UTP, STP and fiber cables

-- Support 100Base-T4 with CAT3, CAT4, CAT 5 UTP, STP

* 10/100Mhz full duplex, half duplex operation

* Contains two deeper 2K bytes FIFO for receive and transmit controller both supports bursts of

up to full Ethernet length

-- Programmable receive and transmit FIFO threshold control for optimize PCI throughput

* Flexible dynamically load EEPROM algorithm.

-- Load after power-up

-- Dynamic auto reload

-- Embedded programming for configure modification

-- Dynamic direct programming for manufacturing

* Support physical, Broadcast, Multicast address filtering using hashing function

* Support Magic packet and wake on address filtering

* Support external Bootrom up to 64K bytes no external address latch

* Software controllable power down feature

* Single +5V supply, 0.5um standard CMOS technology

* 128 pin PQFP package

VIA Technologies, Inc.

Preliminary VT86C100A

Config.

EEPROM

PCI v2.1

Boot

ROM

Configuration

Registers &

EEPROM Control

_MSRD,

_MSWR,

EECS

AD[31:0]

PCICLK

PCIRST#

INTA#

Tally Counters

CBE#[3:0]

IDSEL

FRAME#

IRDY#

TRDY#

DEVSEL#

STOP#

PAR

TXD[3:0],

RXD[3:0],

TX_EN

TX_ER, RX_ER

TX_CLK, RX_CLK

RX_DV, CRS, COL

MDIO

Master

Registers

State

Machine

Buffer

Mgmt.

RxFIFO

2K bytes

PCI

Bus

Interface

Unit

10/100M

MAC Tx/Rx

Protocol

State

MII

TxFIFO

2K bytes

PCI CFG

Figure 1: Application Diagram

VIA Technologies, Inc.

Preliminary VT86C100A

PIN DIAGRAM

MRXD0

MRXD1

MRXD2

MRXD3

VSS

103

105

MA1

MA0

MD7

MD6

MD5

VSS

VDD

MD4

MD3

MD2

MD1

MD0

BPRD#

ECS

VSS

VDD

AD0

AD1

AD2

AD3

AD4

VSS

AD5

AD6

VDD

MDC

MDIO

HDRST

M10TEN

INTA#

PCIRST#

PCICLK

VSS

110

115

120

VT86C100A

VDD

GNT#

REQ#

PME#

AD31

AD30

AD29

AD28

VDD

VSS

AD27

125

128

AD26

VIA Technologies, Inc.

Preliminary VT86C100A

PIN DESCRIPTIONS

No.

Name

Type

Description

PCI Bus Interface

121-

AD31-0

I/O

Address/Data are multiplexed on the same PCI pins. A bus transaction

consists of an address phase followed by one or more data phases. The

address phase is the clock cycle in which FRAME# is asserted. Write

data is stable and valid when IRDYB is asserted and read data is stable

and valid when TRDYB is asserted.

124,127-

128,1-

2,5,7-

9,11-

14,27-

32,35-

36,38,39-

40,42-46

115

PCICLK

PCICLK provides timing for all transactions on PCI and is an input pin

to every PCI device.

113

114

INTA#

PCIRST#

INTA# is an asynchronous signal which is used to request an interrupt

When PCIRST# is asserted low, the VT86C100A chip performs an

internal system hardware reset. PCIRST# may be asynchronous to CLK

when asserted or deasserted. It is recommended that the deassertion be

synchronous to guarantee clean and bounce free edge.

Bus Command/Byte Enables are multiplexed on the same PCI pins.

During the address phase of a transaction, CBE3-0B define the Bus

Command. Burring the data phase, CBE3-0B are used as Byte Enables.

The Byte Enables define which physical byte lanes carry meaningful

data. CBE0B applies to byte 0 and CBE3B applies to byte 3.

Used as a chip select during PCI configuration cycle.

Cycle Frame is driven by the current master to indicate the beginning

and duration of an access. FRAME# is asserted to indicate a bus

transaction is beginning. While FRAME# is asserted, data transfers

continue. When FRAME# is deasserted, the transaction is in the final

data phase.

Initiator Ready indicates the initiating agent's ability to complete the

current data phase of the transaction. IRDY# is used in conjunction with

TRDY#. A data phase is completed on any clock when both IRDY# and

TRDY# are asserted. During a write, IRDY# indicates that valid data is

present on AD31-0. During a read, it indicates the master is prepared to

accept data. Wait cycles are inserted until both IRDY# and TRDY# are

asserted simultaneously.

3,16,26,37

CBE#[3:0]

IDSEL

FRAME#

I/O

IRDY#

TRDY#

I/O

Target Ready indicates the target's agent's ability to complete the current

data phase of the transaction. TRDY# is used in conjunction with

IRDY#. A data phase is completed on any clock when both IRDY# and

TRDY# are asserted. During a read, TRDY# indicates that valid data is

present on AD31-0. During a write, it indicates the target is prepared to

accept data. Wait cycles are inserted until both IRDY# and TRDY# are

asserted simultaneously.

DEVSEL#

STOP#

I/O

Device Select, when actively driven, indicates the driving device has

decoded its address as the target of the current access. As an input,

DEVSEL# indicates whether any device on the bus has been selected.

VT86C100A drives STOP# to disconnect further traction.

VIA Technologies, Inc.

Preliminary VT86C100A

PAR

T/S

Parity is even parity across AD31-0 and CBE3-0B. PAR is stable and

valid one clock after the address phase. For data phases PAR is stable

and valid one clock after either IRDY# is asserted on a write transaction

or TRDY# is asserted on a read transaction.

118

119

GNT#

REQ#

Bus grant asserts to indicate to the VT86C100A that access to the bus is

granted.

Bus request is asserted by the bus master indicate to the bus arbiter that

it wants to use the bus.

Parity error asserts when a data parity error is detected

Power management event interrupt

When PCIRST# is asserted low, the VT86C100A chip performs an

internal system hardware reset. Then HDRST is asserted high for

external device reset signal like PHY device.

PERR#

PME#

HDRST

I/O

120

111

Network Interface

92-95

MCOL

MCRS

MTXD[3-0]

Collision detect when the external PHY device

Carrier sense is asserted by the external PHY when the media is active

MII 4 parallel transmit data lines. This data be synchronized to assertion

by the MTXC signal

MTXEN

MTXC

Transmit enable signals that the transmit is active in the MII port to an

external PHY device

MII transmit clock supports the 25mhz or 2.5mhz transmit clock

supplied by the external PMD device. This clock should always be

active.

100

101

MERR

MRXC

MII receive error asserts when a data decoding error is detected by

external PHY device.

MII receive clock supports the 25mhz or 2.5mhz clock. This clock is

recovered by the PHY.

102

103-106

MRXDV

MRXD[0-3]

MII data valid

Four parallel receive data lines. This data be driven from external PHY

be synchronized with MRXC signal.

109

MDC

MII management data clock be soured by VT86C100A MDC bit

(MIIR:0) to the external PHY devices as timing reference for the

MDIO signal.

110

112

MDIO

GPIO

I/O

MII management data input/output, read from MDI bit (MIIR:1) or

written from MDO bit (MIIR:2)

GPIO

External Memory Support & General purpose I/O support

EECS

EEPROM Chip Select: Chip select signal for the external EEPROM

when a EEPROM is used to provide the configuration data and

Ethernet Address. A 100K pull-up resistor is connected.

Boot PROM Read: Read the Boot ROM on the memory support data

bus.

BPRD#

MD0/

EEDO

MD1/

I/O

Bootrom data 0

Serial ROM Data output

O/O Bootrom data 1

Serial ROM Data input

O/O Bootrom data 2

Serial ROM Clock signal

Bootrom Data [3-7] :

EEDI

MD2/ EECLK

54-55,58-

MD3-7

I/O

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Preliminary VT86C100A

63-64,67-

73,78-

MA0-MA15

Bootrom address line [0-15]

GPIO1/AUXP

GPIO2/LKC

General purpose input and output 1 : usually as Magic key interrupt line

112

General purpose input and output 2, this pin usually as link change status

from external PHY device.

Power Supply & Ground

10,22,34,47,

VDD, VDDA

Positive 5V Supply: Supply power to Internal digital logic, Digital I/O

pads, and TD, TX pads. Double bonding may be required.

56,65,76,

87,97,108

,117,125

6,15,24,33,

VSS, VSSA

Negative Supply: digital ground. Multiple bonding pads are

required to separate core and I/O pads ground.

41,48,57

,66,75,7

7,88,98,

107,116,

126

VIA Technologies, Inc.

Preliminary VT86C100A

FUNCTIONAL DESCRIPTIONS

1. GENERAL DESCRIPTION

The VT86C100A Rhine ACPI PCI bus master 100 M FAST Ethernet controller is CMOS VLSI designed for

easy implementation of CSMA/CD IEEE 802.3u 100M local area networks. Significant features include:

twisted-pair interface, PCI Plug&Play compatibility, 32 bit bus mastering, powerful buffer management and

Early Interrupt Receive/Transmit.

The VT86C100A integrates the entire bus interface of PCI systems. Setting hardware jumpers or software

configures the VT86C100A bus interface. The VT86C100A also complies with PCI specification v2.1.. The

VT86C100A supports the Media Independent Interface (MII) network interface.

1.1 FIFO AND CONTROL LOGIC

The VT86C100A incorporates two independent 2K bytes deeper FIFO for transmit or receive data from

system interface or to the network interface, providing temporary storage of data, free host system from the

real-time demands on network.

The VT86C100A enhanced the FIFO management logic to handle received data packets up to four packets

before transfer to system data buffer. This ability reduce the packets losing due to PCI bus mastering abrition

latency.

2. NETWORK INTERFACE

The VT86C100A Rhine ACPI support one MII interface

2.1 MII Interface

The MII interface is an IEEE 802.3 compliant interface that provides a simple and easy interconnection

between the MAC layer and PHY device. This interface has support the following characteristics :

Support both 10M and 100M data rate.

Contains data and synchronous clock

4-bit independent receive and transmit data.

Uses TTL signal levels and compatibles with common CMOS processes.

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Preliminary VT86C100A

EEPROM Interface and Programming

VT86C100A uses an 93C46 to store configuration data and Ethernet address.

3.1. EEPROM Contents

D15

3FH

Reserved for 93C46

10H

0FH

0EH

0DH

0CH

0BH

0AH

09H

08H

07H

06H

05H

04H

03H

02H

01H

00H

73H

CFG_D

CFG_B

BCR1

MAX_LAT

Reserved

KEY5

KEY3

KEY1

Reserved

73H

CFG_C

CFG_A

BCR0

MIN_GNT

Reserved

KEY5

KEY2

KEY0

Reserved

SUBVID1

SUBSID1

Reserved

SUBVID0

SUBSID0

Reserved

Ethernet Address 5

Ethernet Address 3

Ethernet Address 1

Ethernet Address 4

Ethernet Address 2

Ethernet Address 0

Note 1. The word on location 03H is optional to user's application requirement.

Note 2. Programming 73H into the upper address is required to protect the Ethernet address from being destroyed accidentally

Note 3. The word on location 04H, 05H is sub-System ID, sub-Vendor ID in PCI specification 2.1.

3.2. DIRECT PROGRAMMING OF EEPROM

The VT86C100A features a easy way to program external EEPROM in-situ. When the RESET is active and if

the upper byte of 0FH on EEPROM is not 73H, the EEPR bit will not be set to indicate that the current

EEPROM has not been programmed yet. This will allow the VT86C100A to enter Direct Programming mode

if EELOAD is also set. In this mode the user can directly control the EEPROM interface signals by writing to

the ECSR Port and the value on the EECS, ESK and EDI bits will be driven onto the EECS, SK(MD2), and

DI(MD1) outputs respectively. These outputs will be latched so the user can generate a clock on SK by

repetitively writing 1 then 0 to the appropriate bit. This can be used to generate the EEPROM signals as per

the 93C46 data sheet.

To read the EEPROM data, users have to generate EEPROM interface signals into EECS, DI and SK as

described above and in the mean time read the data from DO(MD0) input via pin SD0. Reading Data

Transfer Port during programming will not affect the latched data on EECS, SK, and DI outputs. When the

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Preliminary VT86C100A

EEPROM has been programmed and verified (remember to program the upper byte of 0EH & 0FH with

73H), the user must give VT86C100A a power-on reset to return to normal operation and to read in the new

data.

The Direct Programming mode is mainly used for production to program every bit of the EEPROM. Once the

upper byte of 0EH has been programmed with 073H and a power-on reset has been performed, there is no

way to change the contents of EEPROM except Configuration Registers A, B, and C, which will be discussed

in the following paragraph. For more information, refer to EECSR.

3.3. EMBEDDED PROGRAMMING OF EEPROM

If the upper byte of 0FH of EEPROM has been programmed to 073H when VT86C100A is loading the

EEPROM data during power-on reset, the EEPR bit of Signature Register will be set to prohibit the Direct

Programming mode. However, the user can still program the configuration registers A, B, and C using the

Embedded Programming mode by following the routine specified in the pseudo code below. This operation

will work regardless of the value of EECONFIG. The setting of the EELOAD bit of Configuration Register B

starts the EEPROM write process. Care should be taken not to accidentally modify the POL and GDLNK bits

because these two bits return the value indifferent from the setting. This programming process is ended when

the EELOAD bit goes to zero.

EEPROM_EMB_PROG ( )

// defined constant: CONFIG_B, EELOAD

// declared register: value, config_for_A, config_for_B, config_for_C

// declared function: DISABLE_INTERRUPTS, ENABLE_INTERRUPTS, READ, WRITE, WAIT

DISABLE_INTERRUPTS ( );

value = READ (CONFIG_B);

value = value | EELOAD;

WRITE (CONFIG_B, value);

READ (CONFIG_B);

WRITE (CONFIG_B, config_for_A);

WRITE (CONFIG_B, config_for_B);

WRITE (CONFIG_B, config_for_C);

while (value || EELOAD)

{

value = READ (CONFIG_B);

WAIT ( );

}

ENABLE_INTERRUPTS ( );

VIA Technologies, Inc.

Preliminary VT86C100A

4. PCI Configuration Space

Device ID

Vendor ID

00 h

04 h

08 h

0c h

10 h

( 1106 )

COMMAND

( 6100 )

STATUS

(DEVS1, DEVS0 ) = ( 1 , 0 )

CLASS CODE

( MMSPACE, IOSPACE)

Revision ID

( 02_00_00 )

( 04 )

Cache Line

BIST

( 00 )

Header type

Latency Timer

( R/W )

( 00 )

( R/W )

CSR Memory Map Base Addr

000

0 0 1

0 0 0

CSR IO MAP SPACE

14 h

2c h

Sub-System ID

Sub-Vendor ID

EXP ROM BASE [ 31: 15 ]

30 h

ROM14 0000_0000_00000

Reserved

Max_LAT

( 00 )

Min_GNT

( 00 )

INT PIN

( 01 )

INTLINE

INTL [7:0]

Reserved

MODE0

3c h

50H

Reserved

MODE2

MODE3

FIFOTST

5. MAGIC KEY FILTERING AND WAKE ON MAGIC KEY

The VT86C100A provides an one level power down mode. The BIOS or Network OS device driver can

configure Register A to diagnostic mode then set the Power-on bit of the diagnostic port to "on." When the

VT86C100A is in Power down mode, all power to the PCI interface is cut off and the chip clock is stopped.

Other registers are read only. Only the diagnostic port is read/writeable.

The VT86C100A can store one “Magic Key” (6 bytes Ethernet address) as external trigger event. When

VT86C100A received one Magic Key address packet, the PME# or GPIO1 will be generated to system.

These signal can be asserted to ATX power PS-ON (refere to ATX specification v2.01) or mother board wake

up interrupt line like ring-in.

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Preliminary VT86C100A

6. BUFFER MANAGEMENT & HOST COMMUNICATION

The VT86C100A provides an simply and effective buffer management and host communication

method through the PCI Bus mastering : There are two descriptor lists, one for receive and one for transmit.

The base of these two list are pointed into the CRDA (18h) and CTDA (1ch) registers.

The descriptor list reside in the host physical memory address space with double word boundary.

And each descriptor lists just point to one single buffer, but a data buffer consists of either an entire frame or

part of a frame. Data chain can be enabled or disabled by DES1 C bit. Data buffer also reside in host physical

memory double word boundary space.

The device driver can make the last descriptors next link be point to first descriptor address, become

a ring buffer structure.

Buffer 1

Descriptor 0

Buffer 1

Descriptor 1

Next Descriptor

Figure 6-1 VT86C100A Buffer Management : Chain buffer Structure

6.1 DESCRIPTOR RING AND CHAIN STRUCTURE

6.1.1 RECEIVE DESCRIPTORS

Figure 6-2 shows the receive descriptor format :

Providing single buffer, one byte-count buffers, and next descriptor address. And Chain bit control

span multiple data buffers data chain to be compatible various types of memory management schemes..

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Preliminary VT86C100A

0 0 0 0

FLNG[10:0]

RSR1

RSR0

RDES0

RDES1

RDES2

RDES3

RLNG[10:0]

Reserve

0000

Rx Data Buffer Start Address

Next Descriptor Address

FIGURE 6-2 THE RECEIVE DESCRIPTOR FORMAT :

6.1.2. RECEIVE DESCRIPTOR 0 (RDES0)

RDES0 contain the received frame status, the frame length and the descriptor ownership information.

Owner : This bit control by driver, 1 to identify this descriptor own by

VT86C100A controller, 0 means this descriptor be a free descriptor; Driver must

set this bit be zero when initialed.

Extend Frame Length : Extend byte count for no-normal size Ethernet frame

Frame Length : Received frame length,

Received OK : The VT86C100A received a good packet from network.

Multicast Address Received : VT86C100A MAC received multicast address

packet

Boardcast Address Received : VT86C100A MAC received boardcast address

packet

Physical Address Received : Physical address received

CHAIN : means of chain buffer,

Start of Packet : In descriptor ring structure, STP=EDP=1 single buffer

descriptor, or chained buffer structure be follows :

STP EDP

Description

Single buffer descriptor

First buffer descriptor, further buffer chained

Chained buffer packet end

End of Packet : End of Packet buffer

Receive Status Register 0 :

Buffer Error : Receive Buffer Error

System bus error :

Runt Packet Received :

Long Packet Received :

FIFO Overflow :

Frame Align Error :

CRC Error : received frame CRC checksum error

Receive Error : this bit be set by CRC error or frame alignmnet error or FIFO

overflow or System bus error.

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Preliminary VT86C100A

6.1.3. RECEIVE DESCRIPTOR 1 (RDES1)

RDES1 contain the interrupt control enable, the chained frame identical and the receive buffer

fragment size information.

Interrupt Control : This bit support for interrupt PACEing , set 1 mean the

VT86C100A received this descriptor will generate the interrupt.

Chain : Chain buffer , this bit be set to 1 means there are chained buffer in next

descriptor

Extend Fragment of Frame Length : must be zero now.

Rx buffer Size : Receive buffer size for this descriptor, the total byte count of

whole frame will be stored in last descriptors

6.2.1. TRANSMIT DESCRIPTORS

Reserve

TSR1

TSR0

RDES0

RDES1

RDES2

RDES3

TLNG[10:0]

Reserve

TCR

0000

Tx Data Buffer Start Address

Next Descriptor Address

FIGURE 6-3 THE TRANSMIT DESCRIPTOR FORMAT

6.2.2. TRANSMIT DESCRIPTOR 0 (TDES0)

DES0 contain the received frame status, the frame length and the descriptor ownership information.

Owner : This bit control by driver, 1 to identify this descriptor own by

VT86C100A controller, 0 means this descriptor be a descriptor waiting for

transmit; Driver must set this bit be zero when initialed.

Transmit Status Register 1

Transmit OK : This bit be 1 for transmission error, the transmit include

following

- internal FIFO under-flow

- excessive collision (ABT)

- late collision (OWC)

- carrier sense lost (CRS)

14 JAB

Jabber : This bit will set high if Jabber condition happens. Writing to this bit has

no effect

System Error : VT86C100A MAC experience error master abort, target abort,

parity error.

12 Reserve

11 Reserve

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Preliminary VT86C100A

Carrier Sense lost bit is set when the carrier is lost during the transmission of a packet.

10 CRS

OWC

ABT

TSR0

Late Collisions : This bit is set when late collision occurred.

Transmit Abort : transmit module abort after excessive collision.

Transmit Status Register 0

7-0

CD heartbeat : this bit only effective in 10Base-T mode. When set, this bit

indicates a heartbeat collision check failure.

Collision retry count : this 4-bits counter indicates the number of collisions that

occurred

FIFO under-flow : this bit set indicates that the transmitter aborted by transmit

FIFO encountered an empty while transmitting a frame.

Deferred: When set, indicates that the VT86C100A had to defer while ready to

transmit a frame because carrier was asserted.

6.2.3. TRANSMIT DESCRIPTOR 1 (TDES1)

DES1 contain the transmit status, the frame length and the descriptor ownership information.

Transmit Configure Register

Interrupt Control : This bit support for interrupt PACEing , set 1 mean the

VT86C100A received this descriptor will generate the interrupt.

End of Packet : End of Packet buffer

Start of Packet : In descriptor ring structure, STP=EDP=1 single buffer

descriptor, or chained buffer structure be follows :

STP EDP

Description

Single buffer descriptor

First buffer descriptor, further buffer chained

Chained buffer packet end

CRC disable : The VT86C100A transmitter will disable generated the CRC

when this set 1.

Chain : Chain buffer

Extend Fragment of Frame Length : must be zero now.

Transmit buffer size : the fragment of frame buffer size

6.3 Buffer Structure and Interrupt Control

data consists of an entire frame or part of a frame, but it cannot exceed a single Ethernet frame size. Buffers

contain only data; All buffer status is maintained in the descriptor . Data chaining can be enable or disable by

Chain bit in DES1[15]. The interrupt control also can be enable or disable by DES1[23]

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Preliminary VT86C100A

6.3.1 Multiple Chained buffer structure

The VT86C100A can support multiple chain buffer for direct map to OS`s data buffer. The VT86C100A bus

mastering module will direct move the data from network to the OS`s data buffer or direct transmit the data in

OS`s buffer onto network not necessary move to a temperate data buffer. But the data buffer must be double

word aligned. In this multiple chained buffer structure, the first data buffer descriptor Chain

Simple Ring Buffer Structure Multiple Buffer Frame

C=DES1[15]

Figure 6 : Ring buffer and multiple buffer structure

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Preliminary VT86C100A

6.3.2 Interrupt Control

The VT86C100A can controllable the receive descriptors and transmit descriptor for what the interrupt

occurred.

The IC bit (DES1[23]) be set 1, the receive or transmit interrupt will be generate the interrupt no matter the

frame been complete received or transmitted. This feature will enable the OS pre-fetch the frame header or

saving the interrupt service overload.

ERInterrupt

Here

Interrupt

Here

Save this

interrupt

Interrupt

Here

Interrupt

Here

Figure 7. The Interrupt Control of VT86C100A

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Preliminary VT86C100A

VT86C100A REGISTERS

Group 1 : Internal Command Status Register (CSR) Layout

byte3

byte2

byte1

byte0

type

PAR3/KEY3 PAR2/KEY2 PAR1/KEY1 PAR0/KEY0

TCR

RCR

PAR5/KEY5 PAR4/KEY4

CR1

ISR1

MAR1

MAR5

CR0

ISR0

MAR0

MAR4

IMR2

MAR3

MAR7

IMR0

MAR2

MAR6

Curr Rx Desc Addr

Curr Tx Desc Addr

Current Rx Desc 0

Current Rx Desc 1

Current Rx Desc 2

Current Rx Desc 3

Next Rx Desc 0

Next Rx Desc 1

Next Rx Desc 2

Next Rx Desc 3

Current Tx Desc 0

Current Tx Desc 1

Current Tx Desc 2

Current Tx Desc 3

Next Tx Desc 0

Next Tx Desc 1

Next Tx Desc 2

Next Tx Desc 3

Current Rx DMA Pointer

Current Tx DMA Pointer

Tally counter test port

BCR1

CFGD

BCR0

MIISR

MIIADR

TEST

CFGB

Tally counter_MPA

PHY ADR

MIICR

EECSR

CFGA

MII DATA REG

GPIO

CFGC

Tally counter_CRC

VIA Technologies, Inc.

Preliminary VT86C100A

Configuration and Diagnostic Registers

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Read/

Write

EELOAD

QPKTDIS

JUMPE

TPACE

MMIOE MIIOPT AUTO

MT10E

MRWA

MT10EOE

LATMEM

78H

OPT

MRDM

TXARB RXARB MWW

79H

Conf. B

AIT

BPS2

CAP

RES

BROPT

DLYEN DTSEL

BTSEL

BPS1

BPS0

7AH

7BH

Conf. C

Conf. D

GPIOEN

DIAG

MRDL

MAGIC

CRAD

MBA

BAKOPT

Note :

The shaded area denoted that those bits are also selective via external jumpers.

All reserved bit must be zero.

No.

Name

PAR0

PAR1

PAR2

PAR3

PAR4

PAR5

RCR

Type

R/W

Bit 7

DA7

DA15

DA9

DA17

DA25

DA33

RRFT2

RTSF

Bit 6

DA6

Bit 5

DA5

Bit 4

DA4

Bit 3

DA3

Bit 2

DA2

Bit 1

DA1

DA9

Bit 0

DA0

DA8

DA16

DA24

DA32

DA40

SEP

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

DA14

DA10

DA18

DA26

DA34

RFT1

RTFT1

RDMD

DA13

DA11

DA19

DA27

DA35

RFT0

RTFT0

TDMD

DA12

DA20

DA28

DA36

PROM

DA11

DA13

DA21

DA29

DA37

OFST

RXON

DPOLL

DA10

DA14

DA22

DA30

DA38

LB1

STOP

FDX

DA15

DA23

DA31

DA39

LB0

STRT

ETEN

TCR

CR0

CR1

TXON

INIT

EREN

SRST

RDMD1 TDMD1 KEYPA

0AH

0BH

0CH

0DH

0EH

0FH

ISR0

ISR1

IMR0

IMR1

R/W

CNT

KEYI

CNTM

KEYIM

TXE

PRAI

TXEM

PRAIM

RXE

PTX

ETI

PTXM

ETM

PRX

ERI

PRXM

ERM

SRCI

BEM

SRCM

ABTI

RUM

ABTM

NBFI

TUM

NBFM

OVFI

RXEM

OVFM

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

MAR0

MAR1

MAR2

MAR3

MAR4

MAR5

MAR6

MAR7

RDA0

RDA1

RDA2

RDA3

TDA0

TDA1

TDA2

TDA3

R/W

FB7

FB6

FB5

FB4

FB3

FB2

FB1

FB9

FB0

FB8

FB15

FB23

FB31

FB39

FB47

FB55

FB63

AB7

AB15

AB23

AB31

AB7

FB14

FB22

FB30

FB38

FB46

FB54

FB62

AB6

AB14

AB22

AB30

AB6

FB13

FB21

FB29

FB37

FB45

FB53

FB61

AB5

AB13

AB21

AB29

AB5

FB12

FB20

FB28

FB36

FB44

FB52

FB60

AB4

AB12

AB20

AB28

AB4

FB11

FB19

FB27

FB35

FB43

FB51

FB59

AB3

AB11

AB19

AB27

AB3

FB10

FB18

FB26

FB34

FB42

FB50

FB58

AB2

AB10

AB18

AB26

AB2

FB17

FB25

FB33

FB41

FB49

FB57

AB1

FB16

FB24

FB32

FB40

FB48

FB56

AB0

AB9

AB8

AB17

AB25

AB1

AB9

AB17

AB25

AB16

AB24

AB0

AB8

AB16

AB24

AB15

AB23

AB31

AB14

AB22

AB30

AB13

AB21

AB29

AB12

AB20

AB28

AB11

AB19

AB27

AB10

AB18

AB26

6CH

6DH

6EH

MPHY

MIISR

BCR0

R/W

MPO1

MPO0

PHYAD PHYAD

PHYAD0

GPIO1P

LEDPO

MFDC

CRFT2

PHYOP

MIIERR MRERR LNKFL

SPEED

REQOP

CRFT1

CRFT0 DMAL2 DMAL1

DMAL0

VIA Technologies, Inc.

Preliminary VT86C100A

6FH

70H

BCR1

R/W

CTSF

CTF1

CTF0

POT2

MDO

POT1

MDI

POT0

MDC

MIICR

MAUT

RCMD

WCMD

MDPM

MOUT

71H

MIIAD

R/W

MSRCE

MDON

MAD4

MAD3

MAD2

MAD1

MAD0

72H

73H

74H

75H

EECSR

TEST

R/W

EEPR

HBDIS

EMBP

FCOL

LOAD

BKOFF

DPM

TSTOV

ECS

TSTUD

ECK

TEST2

EDI

TEST1

EDO

TEST0

76H

77H

78H

CFGA

CFGB

R/W

EELOA

QPKTD

JUMPE

TPACE

MMIOE

MRDM

MIIOPT AUTOO MT10E

MT10E

MT10EO

RXARB

79H

TXARB

MWWA MRWAI LATMEN

7AH

7BH

CFGC

CFGD

R/W

BROPT

DIAG

DLYEN

MRDLE MAGIC

DTSEL

BTSEL

CRADO CAP

BPS2

BPS1

MBA

BPS0

BAKOPT

GPIOE

7CH

7DH

7EH

7FH

MPAC0

MPAC1

CRCC0

CRCC1

R/W

CD7

CD15

CD7

CD15

CD6

CD14

CD6

CD5

CD13

CD5

CD4

CD12

CD4

CD3

CD11

CD3

CD2

CD10

CD2

CD1

CD9

CD1

CD9

CD0

CD8

CD0

CD8

CD14

CD13

CD12

CD11

CD10

VIA Technologies, Inc.

Preliminary VT86C100A

1.1 Configure Register Layout

Configuration Register A (0x78)

GPIO2OE

MD3

GPIO2OE : Output enable of GPIO2 pin

GPIO2O : Output to GPIO2 pin

GPIO2I : GPIO2 input status

AUTOOPT : enable receive event auto transmit descriptor polling

MMIEN : Memory mapped IO enable, accept memory command

JUMPER : Jumper mode to select PHY and operation mode

EELOAD : Enable EEPROM embedded and direct programming

GPIO2

Configuration Register B (0x79)

LATMEN

n/a

LATMEN: Latency timer effect enable

MRWAIT : Master read insert one wait state 2-2-2-2

MWWAIT: Master write insert one wait state 2-2-2-2

RXARBIT : the receiving FIFO DMA will be interleave to transmitting

FIFO DMA after 32 double words transaction.

TXARBIT

QPKTDIS

n/a

TXARBIT : the transmitting FIFO DMA will be interleave to receiving

FIFO DMA after 32 double words transaction.

MRDM : Memory read multiple capable

TPACEN : Tx descriptor pacing algorithm enable

QPKTDIS : disable transmit frame queuing.

Configuration Register C (0x7A)

Bit

Symbol

Jumper

Function

0-2

BPS0-

BPS3

n/a

Boot PROM Select: Select size at which boot PROM begins and the

size

Bit2

Bit1

Bit0

Size

No Boot PROM

16K

32K

64K

BTSEL : Bootrom timing select

DLYEN : Delay transaction while memory read Bootrom

BROPT : set Bootrom address line above Bootrom size selected to logic

for small size Bootrom

Configuration Register D (0x7B)

BAKOPT n/a

BAKOPT : Back-off algorithm optional

VIA Technologies, Inc.

Preliminary VT86C100A

MBA : Modify back off algorithm

CAP : Capture effect back off

CRADOM : Random back off algorithm

MAGIC : Turn on Magic key

MAGIC

n/a

DIAG :

GPIOEN

GPIOEN : Turn on GPIO2 input status change monitor

VIA Technologies, Inc.

Preliminary VT86C100A

VT86C100A Command Status Registers

MAC command and status register Group

CR0: Command Register 0 (08H; Type=R/W)

This register is used to select register pages, enable or disable remote DMA operation and issue

commands.

Reserved

This bit indicates that the VT86C100A receive poll demand enable

This bit indicates that the VT86C100A transmit poll demand enable

This bit indicates that the VT86C100A start transmit state while STRT bit on

This bit indicates that the VT86C100A start receive state while STRT bit on

RDMD

TDMD

TXON

RXON

STOP

This bit indicates that the VT86C100A into STOP state , this bit set by SFRST bit or

hardware reset

This bit indicates that VT86C100A enter the start command.

Initialize Start : When set on the VT86C100A start to set its bus master register the start

STRT

INIT

CR1: Command Register 1 (09H; Type=R/W)

This register is used to select register pages, enable or disable remote DMA operation and issue

commands.

This bit is set when VT86C100A enters reset state and is cleared when a start command is

issued to the CR1. It is also set when receive buffer overflows or system error.

Reserved

Disable transmit auto polling

This bit set MAC to full duplex in 10BaseT or 100BaseT mode

6-4

RES

DPOLL

FDX

Early transmit mode enable while CFGD[1] be enable, this bit be clear while hardware

reset only

ETEN

Early receive mode enable while CFGD[0] be enable, this bit be clear while hardware reset

only

EREN

RCR: Receive Configuration Register (06H; Type=R/W)

This register reflects the NIC receive configuration and reset by hardware reset and software reset

Bit

6-5

Symbol

RRSF

RFT[1-0]

Description

Receive store and forward

Receive FIFO Threshold.

RRFT2

RRFT1 RRFT0

Threshold

64 bytes

128

256

512

768

1024

Receive store and forward

If PRO=1, all packets with physical destination address are accepted. If PRO=0, physical

address must match the node address programmed in PAR0-5

If AB=1, packets with broadcast destination address are accepted. If AM=0, packets with

broadcast destination are rejected.

If AM=1, packets with multicast destination address are accepted. If AM=0, packets with

multicast destination are rejected.

PRO

VIA Technologies, Inc.

Preliminary VT86C100A

If AR=1, packets smaller than 64 bytes are accepted. If AR=0, packets smaller than 64 are

rejected.

If SEP=1, packets with receive errors are accepted. If SEP=0, packets with receive errors

are rejected.

SEP

TCR: Transmit Configuration Registers (07H, Type=R/W)

Bit

6-5

Symbol

RTSF

RFT[1-0]

Description

Transmit and store and forward : till whole packet enter into FIFO then start transmit

Transmit FIFO Threshold :

RTSF

RTF1 RTF0

Threshold

64 bytes

128

256

512

768

1024

Transmit store and forward

Reserve

Back-off priority selection : change the back off algorithm as National specification

OFSET

Loopback mode select for transmit :

2-1

LB[1-0]

Normal

Internal loopback

ENDEC loopback for 10Base-T or MII loopback

223 loopback or others

Reserved.

VIA Technologies, Inc.

Preliminary VT86C100A

ISR:

Interrupt Status Register (0CH; Type=R/W)

This register reflects the NIC status. The host reads it to determine the cause of the interrupt

Individual bits are cleared by writing a "1" to the corresponding bit. It must be cleared after

power up.

Magic packet key received interrupt status

Port status change interrupt status

transmit abort interrupt status, this bit will be set while excessive collision

No more receive buffer to use

FIFO overflow condition, next packet race into FIFO with current packet

receiving FIFO overflow interrupt status

Transmit descriptor underflow while in early transmit mode or general I/O pin M10TENI

status change interrupt while GPIOEN=1, this interrupt can be used as PHY report the

link status change.

Indicates the received packet has filled the first data buffer.

CRC error or packet race tally counter overflow interrupt, software can maintain drivers

CRC error counter above 32 bit

PCI Bus error interrupt

Receive buffer unavailable

Transmit buffer underflow

Transmit error bit is set when a packet transmission is aborted due to excessive collisions.

This bit is set when a packet is received with one or more of the following errors:

1) CRC error, 2) Frame alignment error and 3) Missed packet.

This bit indicates that packet is transmitted with no errors.

This bit indicates that packet is received with no errors.

IMR

Interrupt Mask Register (0EH; Type=R/W )

All bits correspond to the bits in the ISR register. Power up=all 0s. Setting individual bits will

enable the corresponding interrupts.

EEPROM Configuration and status Register Group

EECSR EEPROM Command Status Register (74H, Type=R/W)

EEPROM programming status

EEPROM embedded program enable, the VT86C100A will set this bit to zero after

programming complete.

EMBP

Dynamic reload EEPROM content, the PAR[5-0] will be update

Direct program EEPROM

EEPROM interface chip select status

EEPROM interface clock status

EEPROM interface data in status

EEPROM interface data out status

LOAD

DPM

ECS

ECK

EDI

EDO

VIA Technologies, Inc.

Preliminary VT86C100A

MII port control and status Register Group

MIICR MII interface control register (070H, Type=R/W)

MII management port auto polling enable, MIICR has no effect while this set on

read enable to read PHY status, reset while complete and PHY status will be store in

RCMD

write enable to program PHY, reset while PHY programmed completely

WCMD

MDPM

MOUT

MDO

MDI

MDC

direct program mode enable, while MDPM be set , the WCMD and RCMD have no effect

MDIO output enable indicator while direct program mode

MII interface management port data output status

MII interface management port data input status

MII interface management port clock status

MIIAD MII CSR offset address register (071H, Type=R/W)

MSRCE

MDONE

MAD4

MAD3

MAD2

MAD1

MAD0

MII management port address bit 4

MII management port address bit 3

MII management port address bit 2

MII management port address bit 1

MII management port address bit 0

The MII management port address default value be (00001)b,

MIISR MII status register (06dH, Type=R/W)

GPIO1POL : General purpose I/O 1 pin output polarity, when this bit set as '1', the

GPIO1 pin output active high; set as '0', the GPIO1 pin output active low.

Reserve

res

MFDC

MFDC : Accelerate the MDC speed when VT86C100A enter MII auto polling; MFDC set

as '0', MDC be normal speed; or MFDC set as '1' , MDC be 4 times speed.

PHYOPT : set 1 use default external PHY device address as 0001

MIIERR : PHY device coding error by insert RX_ERR, write to clear it.

MRERR : MII Management read error, write to clear it

LNKFL : Link fail in 10 or 100MHz

PHYOPT

MIIERR

MRERR

LNKFL

SPEED

SPEED : Network speed, 0 as 100MHZ, 1 as 10MHz

PHYADR

MII configuration register (06cH, Type=R/W)

VIA Technologies, Inc.

Preliminary VT86C100A

MII management port polling timer interval, timer unit be MDC clock cycle

MPO1 MPO0

clock

1024

512

128

4-0

res

PHYAD[

4-0]

PHY[4-0] : external PHY device address , these register bytes stored from EEPROM

loading when power up or EEPROM auto-reloading or can be programmed by software,

default as (00001)b

VIA Technologies, Inc.

Preliminary VT86C100A

[This page left to blank]

VIA Technologies, Inc.

Preliminary VT86C100A

PCIVCC

MA[15:0]

CB8

22UF

CB7

22UF

CB5

22UF

CB4

22UF

CB3

22UF

CB2

22UF

CB1

22UF

JP1

AD25

-CBE3

AD23

AD22

AD20

AD19

AD17

AD24

IDSEL

MD[7:0]

AD21

AD18

AD16

-CBE2

-IRDY

-DEVSEL

-FRAME

-TRDY

-STOP

-PERR

PAR

AD15

AD13

VT3043E

121

122

123

124

127

128

100

101

102

103

104

105

106

109

110

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD17

AD16

AD15

AD14

AD13

AD12

AD11

AD10

AD9

MCRS

MCOL

-CBE1

AD14

AD12

AD10

MCRS

MCOL

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD17

AD16

AD15

AD14

AD13

AD12

AD11

AD10

AD9

MCRS

MCOL

MTXD3

MTXD2

MTXD1

MTXD0

MTXE

MTXD3

MTXD2

MTXD1

MTXD0

MTXEN

MTXCK

MRXER

MRDCK

MRXDV

MRXD0

MRXD1

MRXD2

MRXD3

MDC

MTXD3

MTXD2

MTXD1

MTXD0

MTXEN

MTXCK

MRXER

MRXCK

MRXDV

MRXD0

MRXD1

MRXD2

MRXD3

MDC

PCIVCC

-INTA

AD11

AD9

-CBE0

AD8

AD7

-PRSNT1

MTXC

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

MERR

MRXC

MRXDV

MRXD0

MRXD1

MRXD2

MRXD3

MDC

-PRSNT2

AD6

AD5

AD4

AD2

AD0

-PCIRST

PCIVCC

-GNT

AD3

AD1

-PCIRST

-PME

PCICLK

-REQ

PCIVCC

AD31

MDIO

EECS

MD0

MD2

MD4

-BPRD

MD1

MD3

MDIO

112

AD30

M10TEN

PRTENL

PRTENH

M10TEN

PRTENL

PRTENH

M10TEN

PRTENL

PRTENH

AD29

AD28

AD26

MD5

MD7

PRTENH

MA1

AD27

AD25

MD6

PRTENL

MA0

MA15

MA14

MA13

MA12

MA11

MA10

MA9

MA8

MA7

MA6

MA5

MA15

MA14

MA13

MA12

MA11

MA10

MA9

MA8

MA7

MA6

MA5

AD24

IDSEL

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

-CBE3

AD23

AD22

AD20

AD21

AD19

101

100

102

101

103

105

107

109

111

113

100

102

104

106

108

110

112

114

AD18

AD16

MA2

MA4

MA6

MA8

SVSS

MA3

MA5

MA7

SVDD

AD17

-CBE2

AD0

-FRAME

-TRDY

-STOP

-IRDY

-CBE3

-CBE2

-CBE1

-CBE0

MA4

MA3

MA2

MA1

CBE3

CBE2

CBE1

CBE0

MA4

MA3

MA2

MA1

MA9

-DEVSEL

MA10

MA12

MA14

MA11

MA13

MA15

NC2

MA0

115

113

114

118

119

-PERR

IDSEL

-FRAME

-IRDY

-TRDY

-DEVSEL

-STOP

PAR

PCICLK

-INTA

-PCIRST

-GNT

-REQ

IDSEL

FRAME

IRDY

TRDY

DEVSEL

STOP

PAR

PCICLK

INTA

PCIRST

GNT

MD7

MD6

MD5

MD4

MD3

MD2

MD1

MD0

MD7

MD6

MD5

MD4

MD3

TST

MCRS

MTXD3

MTXD1

MTXEN

PAR

AD15

MCOL

MTXD2

MTXD0

-CBE1

AD14

AD13

AD11

MD2/EECK

MD1/EEDI

MD0/EEDO

AD12

AD10

MTXCK

MRXCK

MRXER

MRXDV

AD9

EECS

-BPRD

EECS

-BPRD

EECS

BPRD

REQ

PERR

PME

AD8

AD7

-CBE0

-PERR

-PME

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

103

105

107

109

111

113

115

117

119

121

123

125

127

104

106

108

110

112

114

116

118

120

122

124

126

128

120

TST

NC2

MRXD0

MRXD2

MRXD1

MRXD3

TST

NC2

-PME

TST

NC2

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

AD6

AD4

AD5

AD3

VDD

C12

C13

C11

C14

.1u

MDC

HDRST

-INTA

MDIO

M10TEN

-PCIRST

111

AD2

AD0

PCIVCC

HDRST

SVDD

SVSS

AD1

PCIVCC

3.6

PCICLK

0805

SVDD

-GNT

-PME

AD30

AD28

-REQ

AD31

AD29

C10

.O1u

.1u

10uF

108

117

125

PCI_CONB

PCI_CONA

SVSS

AD27

AD26

C15

.1u

HEADER 72X2

VIA TECHNOLOGIES, INC.

Title

|LINK

|2.SCH

|3.SCH

VT3043E Bench Board

Size

Document Number

VT5134A

Rev

Date:

Thursday, September 04, 1997

Sheet

VIA Technologies, Inc.

Preliminary VT86C100A

R78

510

RN2

510

PWR

R48

P/F

MTXCK

TX_CLK

LED_TX

LED_RX

LED_LK

LED_P/F

LED_COL

MTXD3

MTXD2

MTXD1

MTXD0

TXD3

TXD2

TXD1

TXD0

COL

R52

510

SPEED10

100

SPEED_10

MTXEN

TX_EN

TX_ER

CRS_P2

R53

510

TX_ER

R12

R13

TXO+/TXU+

TXU+

TXU-

MII_CRS

TXU-

MCRS

R54

R55

R15

R16

MCOL

COL

TXS+

TXS-

R35

TXO-

MRXD3

MRXD2

MRXD1

MRXD0

RXD3

RXD2

RXD1

RXD0

C37

.1u

RXI+

RXI-

RXI+

RXI-

R11

C38

.1u

R40

R41

PUD01

R49

REQ

RTX

VCC

EXTVCC

VCC

TXVCC

*49.9

MRXCK

MRXDV

MRXER

RX_CLK

RX_DV

RX_ER_P4

C34

.1u

R81

MII_RXER

R10

RXVCC

PTD+

PTD-

RX_EN

TD+

TD-

PMRD+

PMRD-

4.7K

MDC

R82

TXO+/TXU+

TXO-

MDC

MDIO

MDC

MDIO

TXO+

TXO-

MDIO

PRD+

PRD-

RD+

RD-

PMID+

PMID-

C43

*10p

R79

R80

0/75

R19

R17

10/0

RESET

RXI+

RXI-

RESET

RXI+

RXI-

PSD+

PSD-

SD+

SD-

SD+

SD-

REFIN

CLK25

OSCIN

R18

10/0

REFIN

CLK25M

OSCIN

R38

47.5

R39

47.5

0/75

RN1

510

R20

39/49.9

ENCSEL_P1

LBEN_P0

ENCSEL

LBEN

TXGND

39/49.9

R21

4.7K

RXGND

C39

.1u

R32

VCC_A

PCSVCC_A

EQSEL

/CDET

P3/100

AN0

AN1

SPEED10

2N3904

AN0

AN1

REPEATER

GND

TXREF

R33

NS 840

MTD972

GND_A

PCSGND_A

R36

510

R63

4.7K

R14

*2K

R42

R22

R23

R24

DP83223

Transceiver

2N3904

OSC2

50M

25M

VCC_B

REFVCC_B

100

10BTSER

BPALIGN

BP4B5B

BPSCR

RJ-45

R25

510

RD+

GND_B

RCLKGND_B

GND_B

REFGND_B

RX+

RXI+

OSC1

J_TD0

J_TDI

J_TRST

J_TCLK

J_TMS

PUD02

VCC

R22

RXI-

R37

TD+

RX-

TX+

OSCIN

GND

OUT

RXVCC_C

TDVCC_C

PLLVCC_C

OVCC_C

10K

TXO+/TXU+

TXU-

50MHz/*25MHz

C17

10P

R24

*75

P3/100

PHYAD3

TXO-

RXGND_C

TDGND_C

PLLGND_C

OGND_C

TD-

TX-

R29

PUD03

R42

R28

REFIN

CLK25

PT4171

R27

R30

C48

39p

C47

39p

R26

4.7K

R23

C35

.1u

C41

*.1u

ANAVCC

*10K

FGND

CRMVCC_D

ECLVCC_D

ANAVCC_D

CGMVCC_D

U4A

TX_ER

CX1

.1u

RES_0

R31

R56

-PCIRST

R50

OSCGND_D

CRMGND_D

ANAGND_D

CGMGND_D

74LS14

R57

R44

R43

*4.7K

RESET

PUD01

PUD03

HDRST

RP2

130

RP1

R58

10K

*4.7K

R51

DP83840A

Physical Layer

AN0

AN1

AN0

PHY0

PHY1

PRD+

PRD-

PSD-

PSD+

PTD-

PTD+

R59

10K

R47

R45

R46

*4.7K

PUD01

PUD02

PUD03

AN1

C18

.1u

C19

.1u

C21

.1u

C24

.1u

C20

.1u

C22

.1u

C23

.1u

C42

.1u

C25

47uH

.1u

R60

10K

ANAVCC

C16

MII_CRS

P3/100

C40

22u

PHY2

PHY3

.001u

*Use RP1,RP2 or Only RP2 -> 510

R61

10K

'*' for Myson PHY and Transceiver

VIA TECHNOLOGIES, INC.

C26

.1u

C27

.1u

C32

.1u

C33

.1u

C28

.1u

C29

.1u

C30

.1u

C31

.1u

R62

10K

MII_RXER

PHY4

Title

NS or Myson's PHY & Transceiver

Document Number

Size

Rev

VT5134A

Date:

Thursday, September 04, 1997

Sheet

VIA Technologies, Inc.

Preliminary VT86C100A

RP4

RP6

RP5

RP3

EECS

-BPRD

MD7

MD6

MD5

MD4

MD3

MD2

MD1

MD0

EECS

-BPRD

M10TEN

PRTENH

PRTENL

TST

NC2

10K

4.7K

10K

TP1

TP2

1N4148

U8A

U8B

PCI_PWR

PCI_GOOD

1N4148

MD[7:0]

74HC14

MD[7:0]

R76

4.7K

MA[15:0]

R75

100K

U8D

U8C

TP3

NPN

C44

100p

ISOLATE

74HC14

R74

10K

R72

7.8K

MD1

MD2

EECS

MD0

VCC

GND

REF

RESIN

VCC

SENSE

RESET

C46

.1u

R73

10K

R77

GND

C45

.1u

TL7705A

R71

10K

93C46

TP4

ALTRST

TP5

AUX_PWR

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

MA8

MA9

MA10

MA11

MA12

MA13

MD0

MD1

MD2

MD3

MD4

MD5

MD6

MD7

AUX5V

GND

WAKUP

GND

AUX5V

R68

-PME

R66

4.7K

R67

4.7K

AUX5V_CON

A10

A11

A12

A13

A14

A15

R70

R69

R64

MA14

MA15

R65

-BPRD

27512

VIA TECHNOLOGIES, INC.

Title

VT3043E Strapping

Size

Document Number

VT5134A

Rev

Date:

Thursday, September 04, 1997

Sheet

VT86C100A [ETC]

相关型号：

VT86C926

VT87A302

VT87A442/2

VT8N1

VT8N2

VT900

VT905GA

VT905GB

VT905GC

VT90A114

VT90A432

VT90A443