US1881E [ETC]

CMOS MULTI-PURPOSE LATCH; CMOS多用途LATCH
US1881E
型号: US1881E
厂家: ETC    ETC
描述:

CMOS MULTI-PURPOSE LATCH
CMOS多用途LATCH

文件: 总11页 (文件大小:425K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
US1881  
CMOS Multi-Purpose Latc  
h
Features and Benefits  
ß Chopper stabilized amplifier stage  
ß Optimized for brushless DC motor applications  
ß Miniature high reliability package  
ß Operation down to 3.5V  
ß CMOS for optimum stability, quality and cost  
ß Low power consumption  
Ordering Information  
Part No.  
US1881  
US1881  
US1881  
Temperature Suffix  
E (-40°C to 85°C)  
K (-40°C to 125°C)  
L (-40°C to 150°C)  
Package Code  
SO (SOT-23) or UA(TO-92)  
SO (SOT-23) or UA(TO-92)  
SO (SOT-23) or UA(TO-92)  
1 Functional Diagram  
Applications  
ß Solid state switch  
ß Brushless DC motor commutation  
ß Speed Sensing  
ß Linear position sensing  
ß Angular position sensing  
ß Current sensing  
Pinout:  
Note: Static electricity sensitive device; please observe  
ESD precautions. Reverse voltage protection is not in-  
cluded. For reverse polarity protection, a 100Ohm resistor  
in series with VDD is recommended.  
UA Package:  
SO Package:  
Pin1: VDD - supply  
Pin2: GND - Ground  
Pin3: OUT - Output  
Pin1: VDD - supply  
Pin2: OUT – Output  
Pin3: GND - Ground  
2 Description  
The US1881 is the industry’s first Hall integrated circuit in SOT-23 package. The US1881 is a bipolar Hall effect  
sensor IC based on mixed signal CMOS technology. It incorporates advanced chopper stabilization techniques to  
provide accurate and stable magnetic switch points. There are many applications for this HED in addition to those  
listed above. The design, specifications and performance have been optimized for commutation applications in 5V  
and 12V brushless DC motors.  
In UA packaged device the output transistor will be latched on (Bop) in presence of a sufficiently strong South  
pole magnetic field facing the marked side of the package. Similarly, the output will be latched off (Brp) in the  
presence of a North field. The SOT-23 device behaviour is reverse to the UA device. The SOT-23 output transistor will  
be latched on (BOP) in the presence of a sufficiently strong North pole magnetic field on the marked side  
.
3901001881  
Rev. 014  
Page 1 of 12  
Jun/05  
US1881  
CMOS Multi-Purpose Latch  
Table of Contents  
1
2
3
4
5
6
7
8
Functional Diagram....................................................................................................1  
Description .................................................................................................................1  
Glossary of Terms......................................................................................................3  
Absolute Maximum Ratings ......................................................................................3  
US1881 Electrical Characteristics ............................................................................3  
Magnetic Characteristics...........................................................................................4  
Unique Features.........................................................................................................4  
Performance Graphs – unless otherwise specified Ta=25oC, VDD=12V...............5  
8.1  
Typical Magnetic Switch Points vs VDD ........................................................................... 5  
Magnetic Switch Points vs Temperature......................................................................... 5  
Output Voltage vs Magnetic Flux Density (Hysteresis).................................................... 5  
Typical Saturation Voltage vs Temperature(VDD=12V;Iout=20mA)................................. 5  
Typical Supply Current vs VDD ........................................................................................ 6  
Maximal Power Dissipation (MPD) Versus Temperature ................................................ 6  
8.2  
8.3  
8.4  
8.5  
8.6  
9
Application Information.............................................................................................7  
9.1  
Typical Three-Wire Application Circuit ............................................................................ 7  
Two-Wire Circuit ............................................................................................................. 7  
Automotive and Harsh, Noisy Environments Three-Wire Circuit ..................................... 7  
9.2  
9.3  
10 Application Comments..............................................................................................7  
11 Pin Definitions and Descriptions..............................................................................7  
12 Reliability Information ...............................................................................................8  
13 ESD Precautions ........................................................................................................8  
14 Physical Characteristics............................................................................................9  
14.1 UA Package Information................................................................................................. 9  
14.2 SOT23 Package Information......................................................................................... 10  
15 Disclaimer.................................................................................................................11  
3901001881  
Rev. 014  
Page 2 of 11  
Jun/05  
US1881  
CMOS Multi-Purpose Latch  
3 Glossary of Terms  
MilliTesla (mT), Gauss: Units of magnetic flux density; 1 milliTesla = 10 Gauss.  
CMOS – Complementary Metal-Oxide Silicon - A technology for building logic circuits that employs both “N”  
and “P” channel MOS transistors. It allows one to make ICs with lots of transistors that consume small  
amounts of power.  
4 Absolute Maximum Ratings  
Parameter  
Symbol Value  
Units  
V
Supply Voltage (Operating)  
VDD  
IDD  
24  
50  
Supply Current (Fault)  
mA  
V
Output Voltage  
VOUT  
IOUT  
PD  
24  
Output Current (Fault)  
50  
mA  
mW  
°C  
Power Dissipation, UA/SO packages  
Maximum Junction Temperature  
Storage Temperature  
700/389  
165  
TJ  
TS  
-50 to 150  
°C  
Exceeding the absolute maximum ratings may cause permanent damage. Exposure to absolute-maximum-  
rated conditions for extended periods may affect device reliability.  
Operating Temperature Range  
Temperature Suffix “E”  
Value  
Units  
°C  
-40 to 85  
Temperature Suffix “K”  
Temperature Suffix “L”  
-40 to 125  
-40 to 150  
°C  
°C  
5 US1881 Electrical Characteristics  
DC operating parameters: TA = 25oC, VDD = 12V (unless otherwise specified)  
Parameter  
Symbol  
VDD  
Test Conditions  
Operating  
Min  
3.5  
Typ  
Max Units  
Supply Voltage  
24  
5.0  
0.5  
10  
V
mA  
V
Supply current  
IDD  
VDS(on)  
IOFF  
tr  
B < BOP  
1.1  
2.0  
0.4  
Saturation Voltage  
Output Leakage  
Output Rise Time  
Output Fall Time  
Maximum Switching  
Frequency  
IOUT = 20mA, B > Bop, VDD=4.5÷18V  
B < BRP, VOUT=24V  
0.01  
0.04  
0.18  
10  
uA  
us  
VDD = 12V, RL = 1k, CL = 20pF  
VDD = 12V, RL = 1k, CL = 20pF  
Operating  
tf  
us  
fsw  
KHz  
3901001881  
Rev. 014  
Page 3 of 11  
Jun/05  
US1881  
CMOS Multi-Purpose Latch  
6 Magnetic Characteristics  
Parameter  
Symbol  
BOP  
Test Conditions  
Min  
Typ  
5.0  
Max  
9.0  
Units  
mT  
E/LUA, E/LSO,Ta=25oC,Vdd=3.5 … 24V DC  
Operating Point  
1.0  
E/LUA, E/LSO,Ta=25oC,Vdd=3.5 … 24V DC  
E/LUA, E/LSO,Ta=25oC,Vdd=3.5 … 24V DC  
EUA, ESO, Ta=85oC,Vdd=3.5 … 24V DC  
EUA, ESO, Ta=85oC,Vdd=3.5 … 24V DC  
EUA, ESO, Ta=85oC,Vdd=3.5 … 24V DC  
KUA, KSO, Ta=125oC,Vdd=3.5 … 24V DC  
KUA, KSO, Ta=125oC,Vdd=3.5 … 24V DC  
KUA, KSO, Ta=125oC,Vdd=3.5 … 24V DC  
LUA, LSO, Ta=150oC,Vdd=3.5 … 24V DC  
LUA, LSO, Ta=150oC,Vdd=3.5 … 24V DC  
LUA, LSO, Ta=150oC,Vdd=3.5 … 24V DC  
Release Point  
Hysteresis  
BRP  
BHYS  
BOP  
BRP  
-9.0  
7.0  
0.5  
-9.5  
7.0  
0.5  
-9.5  
7.0  
0.5  
-9.5  
6.0  
-5.0  
10.0  
5.0  
-1.0  
12.0  
9.5  
mT  
mT  
mT  
mT  
mT  
mT  
mT  
mT  
mT  
mT  
mT  
Operating Point  
Release Point  
Hysteresis  
-5.0  
10.0  
5.0  
-0.5  
12.0  
9.5  
BHYS  
BOP  
BRP  
Operating Point  
Release Point  
Hysteresis  
-5.0  
10.0  
5.0  
-0.5  
12.0  
9.5  
BHYS  
BOP  
BRP  
Operating Point  
Release Point  
Hysteresis  
-5.0  
10.0  
-0.5  
12.5  
BHYS  
Note: 1 mT = 10 Gauss  
7 Unique Features  
CMOS Hall IC Technology  
The chopper stabilized amplifier uses switched capacitor techniques to eliminate the amplifier offset voltage,  
which, in bipolar devices, is a major source of temperature sensitive drift. CMOS makes this advanced  
technique possible. The CMOS chip is also much smaller than a bipolar chip, allowing very sophisticated  
circuitry to be placed in less space. The small chip size also contributes to lower physical stress and less  
power consumption.  
3901001881  
Rev. 014  
Page 4 of 11  
Jun/05  
US1881  
CMOS Multi-Purpose Latch  
8 Performance Graphs – unless otherwise specified Ta=25oC, VDD=12V  
Typical Magnetic Switch Points vs VDD Magnetic Switch Points vs Temperature  
8.1  
8.2  
8.3  
Output Voltage vs Magnetic Flux Density 8.4 Typical Saturation Voltage vs Tempera-  
(Hysteresis) ture(VDD=12V;Iout=20mA)  
3901001881  
Rev. 014  
Page 5 of 11  
Jun/05  
US1881  
CMOS Multi-Purpose Latch  
8.5  
Typical Supply Current vs VDD  
8.6  
Maximal Power Dissipation (MPD) Versus Temperature  
The thermal resistance JA and rated power dissipation are defined in accordance with EIA/JESD51-3 Standard  
.
Some differences may be observed between values in the specification tables and the performance graphs.  
The performance graphs are based on initial characterization of several ICs from one lot. Hence a particular IC  
may vary from the performance graphs but all ICs should meet the values stated in the specification tables.  
3901001881  
Rev. 014  
Page 6 of 11  
Jun/05  
US1881  
CMOS Multi-Purpose Latch  
9 Application Information  
9.1  
Typical Three-Wire Application Circuit  
9.2  
Two-Wire Circuit  
Note:  
With this circuit, precise ON and OFF  
currents can be detected using only two  
connecting wires.  
9.3  
Automotive and Harsh, Noisy Environments  
Three-Wire Circuit  
The resistors RL and Rb can be used to  
bias the input current. Refer to the part  
specifications for limiting values.  
BRP  
BOP  
:
:
IOFF = IR + IDD = VDD/Rb + IDD  
ION = IOFF + IOUT = IOFF + VDD/RL  
10 Application Comments  
If a weak power supply is used or the chip is intended to be used in noisy environment, it is recommended  
that figure 9.3 from the Application Information section is used. R1 and C1 form a RC filter, which bypasses  
the disturbances over the supply pin.  
If a continuous reverse polarity protection is required for supply voltages above 5 Volts, it is recommended to  
use a diode instead of resistor, because the power dissipation demands become higher.  
11 Pin Definitions and Descriptions  
UA  
SO Pin  
Type  
Description  
Pins Pins Name  
1
3
2
1
2
3
VDD  
OUT  
VSS  
Supply  
Output  
Ground  
Power Supply pin  
Hall output pin  
(clamped)  
Ground pin  
3901001881  
Rev. 014  
Page 7 of 11  
Jun/05  
US1881  
CMOS Multi-Purpose Latch  
12 Reliability Information  
This Melexis device is classified and qualified regarding soldering technology, solderability and moisture  
sensitivity level, as defined in this specification, according to following test methods:  
°
°
°
IPC/JEDEC J-STD-020  
Moisture/Reflow Sensitivity Classification For Nonhermetic Solid State Surface Mount Devices  
(classification reflow profiles according to table 5-2)  
EIA/JEDEC JESD22-A113  
Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing  
(reflow profiles according to table 2)  
CECC00802  
Standard Method For The Specification of Surface Mounting Components (SMDs) of Assessed  
Quality  
°
°
°
EIA/JEDEC JESD22-B106  
Resistance to soldering temperature for through-hole mounted devices  
EN60749-15  
Resistance to soldering temperature for through-hole mounted devices  
MIL 883 Method 2003 / EIA/JEDEC JESD22-B102  
Solderability  
For all soldering technologies deviating from above mentioned standard conditions (regarding peak  
temperature, temperature gradient, temperature profile etc) additional classification and qualification tests  
have to be agreed upon with Melexis.  
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of  
adhesive strength between device and board.  
Based on Melexis commitment to environmental responsibility, European legislation (Directive on the  
Restriction of the Use of Certain Hazardous substances, RoHS) and customer requests, Melexis has  
installed a Roadmap to qualify their package families for lead free processes also.  
Various lead free generic qualifications are running, current results on request.  
For more information on Melexis lead free statement see quality page at our website:  
http://www.melexis.com/html/pdf/MLXleadfree-statement.pdf  
13 ESD Precautions  
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).  
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.  
3901001881  
Rev. 014  
Page 8 of 11  
Jun/05  
US1881  
CMOS Multi-Purpose Latch  
14 Physical Characteristics  
14.1 UA Package Information  
3901001881  
Rev. 014  
Page 9 of 11  
Jun/05  
US1881  
CMOS Multi-Purpose Latch  
14.2 SOT23 Package Information  
3901001881  
Rev. 014  
Page 10 of 11  
Jun/05  
US1881  
CMOS Multi-Purpose Latch  
15 Disclaimer  
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its  
Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the  
information set forth herein or regarding the freedom of the described devices from patent infringement.  
Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior  
to designing this product into a system, it is necessary to check with Melexis for current information. This  
product is intended for use in normal commercial applications. Applications requiring extended temperature  
range, unusual environmental requirements, or high reliability applications, such as military, medical life-  
support or life-sustaining equipment are specifically not recommended without additional processing by  
Melexis for each application.  
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be  
liable to recipient or any third party for any damages, including but not limited to personal injury, property  
damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential  
damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical  
data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering  
of technical or other services.  
© 2002 Melexis NV. All rights reserved.  
For the latest version of this document. Go to our website at  
www.melexis.com  
Or for additional information contact Melexis Direct:  
Europe and Japan:  
Phone: +32 1367 0495  
All other locations:  
Phone: +1 603 223 2362  
E-mail: sales_europe@melexis.com  
E-mail: sales_usa@melexis.com  
ISO/TS 16949 and ISO14001 Certified  
3901001881  
Rev. 014  
Page 11 of 11  
Jun/05  

相关型号:

US1881ESE

Hall Latch - High Sensitivity
MELEXIS

US1881ESE-AAA-000-RE

Hall Latch – High Sensitivity
MELEXIS

US1881EUA

Hall Latch - High Sensitivity
MELEXIS

US1881EUA-AAA-000-BU

Hall Latch – High Sensitivity
MELEXIS

US1881K

CMOS MULTI-PURPOSE LATCH
ETC

US1881KSE

Hall Latch - High Sensitivity
MELEXIS

US1881KSE-AAA-000-RE

Hall Latch – High Sensitivity
MELEXIS

US1881KUA

Hall Latch - High Sensitivity
MELEXIS

US1881KUA-AAA-000-BU

Hall Latch – High Sensitivity
MELEXIS

US1881L

CMOS MULTI-PURPOSE LATCH
ETC

US1881LSE

Hall Latch - High Sensitivity
MELEXIS

US1881LSE-AAA-000-RE

Hall Latch – High Sensitivity
MELEXIS