US1881ESE-AAA-000-RE [MELEXIS]
Hall Latch â High Sensitivity;
| 型号： | US1881ESE-AAA-000-RE |
| 厂家： | 
Melexis Microelectronic Systems |
| 描述： | Hall Latch â High Sensitivity |
| 文件： | 总12页 (文件大小：1199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
US1881
Hall Latch – Higgh Sensitivity
Features and Benefits
Application Exammples
ꢀ
Wide operating voltage range from 3.5V to
24V
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Automotive, Consuumer and Industrial
Solid-state switch
Brushless DC mottor commutation
Speed detection
Linear position detection
Angular position ddetection
Proximity detectionn
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
High magnetic sensitivity – Mul
CMOS technology
t
t
i-purpose
Chopper-stabilized amplifier stage
Low current consumption
Open drain output
Thin SOT23 3L and flat TO-92
both RoHS Compliant
packages
33L
Ordering Code
Product Code Temperature Co
US1881
US1881
US1881
US1881
US1881
US1881
dde
Package Code
Option Code
AAA-000
AAA-000
AAA-000
AAA-000
AAA-000
AAA-000
Packking Form Code
E
K
L
E
K
L
UA
UA
UA
SE
SE
SE
BU
BU
BU
RE
RE
RE
Legend:
Temperature Code:
L for
E for
K for
TTemperature Range -40°C to 150°C
T
T
emperature Range -40°C to 85°C
TTemperature Range -40°C to 125°C
Package Code:
Option Code:
Packing Form:
UA for TO-92(Flat), SE for TSOT
xxx-0 0: Standard version
RE for Reel, BU for Bulk
00
Ordering example:
US1881KUA-AAA-000-BU
1 Functional Diagram
2 General Descriptioon
The Melexis US1881 is aa Hall-effect latch
designed in mixed signal CMOOS technology.
The device integrates a volltage regulator, Hall
sensor with dynamic offset ccancellation system,
Schmitt trigger and an open-drain output driver, all
in a single package.
Thanks to its wide operatingg voltage range and
extended choice of temperatuure range, it is quite
suitable for use in automootive, industrial and
consumer applications.
The device is delivered in aa Thin Small Outline
Transistor (TSOT) for surface mount process and
in a Plastic Single In Line (TOO-92 flat) for through-
hole mount.
Both 3-lead packages are RoHHS compliant.
Data Sheet
Mar/12
3901001881
Rev 016
Page 1 of 12
US1881
Hall Latch – High Sensitivity
Table of Contents
1 Functional Diagram ........................................................................................................ 1
2 General Descrip ion........................................................................................................ 1
3 Glossary of Terms .......................................................................................................... 3
4 Absolute Maximum Rating ........................................................................................... 3
5 Pin Definitions and Descrip ion ................................................................................... 3
t
s
t
s
6 General Electrical Specifications .................................................................................. 4
7 Magnetic Specifications ................................................................................................. 4
8 Output Behaviour versus Magnetic Pole ...................................................................... 4
9 Detailed General Description......................................................................................... 5
10 Unique Features............................................................................................................ 5
11 Performance Graphs .................................................................................................... 6
11.1 Magnetic parameters vs. TA.....................................................................................................................6
11.2 Magnetic parameters vs. VDD...................................................................................................................6
11.3 VDSon vs. TA ..............................................................................................................................................6
11.4 VDSon vs. VDD ............................................................................................................................................6
11.5 IDD vs. TA ..................................................................................................................................................6
11.6 IDD vs. VDD ................................................................................................................................................6
11.7 IOFF vs. TA .................................................................................................................................................7
11.8 IOFF vs. VDD...............................................................................................................................................7
12 Test Conditions............................................................................................................. 7
12.1 Supply Current.........................................................................................................................................7
12.2 Output Saturation Voltage .......................................................................................................................7
12.3 Output Leakage Current..........................................................................................................................7
12.4 Magnetic Thresholds ...............................................................................................................................7
13 Application Information................................................................................................ 8
13.1 Typical Three-Wire Application Circuit ....................................................................................................8
13.2 Two-Wire Circuit ......................................................................................................................................8
13.3 Automotive and Harsh, Noisy Environments Three-Wire Circuit ............................................................8
14 Application Comments................................................................................................. 8
15 Standard information regarding manufacturability of Melexis products with
different soldering processes........................................................................................... 9
16 ESD Precautions........................................................................................................... 9
17 Package Information................................................................................................... 10
17.1 SE Package (TSOT-3L).........................................................................................................................10
17.2 UA Package (TO-92 flat) .......................................................................................................................11
18 Disclaimer.................................................................................................................... 12
Data Sheet
Mar/12
3901001881
Rev 016
Page 2 of 12
US1881
Hall Latch – High Sensitivity
3 Glossary of Terms
MilliTesla (mT), Gauss
Units of magnetic flux density:
1mT = 10 Gauss
Restriction of Hazardous Substances
Thin Small Outline Transistor (TSOT package) – also referred with the Melexis
package code “SE”
Electro-Static Discharge
RoHS
TSOT
ESD
BLDC
Operating Point (BOP
Brush-Less Direct-Current
Magnetic flux density applied on the branded side of the package which turns
)
the output driver ON (VOUT = VDSon
)
Release Point (BRP
)
Magnetic flux density applied on the branded side of the package which turns
the output driver OFF (VOUT = high)
4 Absolute Maximum Ratings
Parameter
Symbol
VDD
Value
Units
S
S
upp
upp
l
l
y
y
V
o
l
t
a
g
e
28
50
V
Curr
e
n
t
IDD
m
A
A
Output
Output Curr
Storage Temperature Range
un on Temperature
Table 1: Absolute maximum ratings
V
o
l
t
a
g
e
VO
UT
28
V
e
n
t
I
O
50
m
UT
T
S
-50 to 150
165
°
°
C
C
Ma
x
i
m
u
m
J
c
t
i
T
J
Exceeding the absolute maximum ratings may cause permanent damage. Exposure to absolute-maximum-
rated conditions for extended periods may affect device reliability.
Operating Temperature Range
Symbol
Value
Units
Temperature
Temperature
Temperature
S
S
S
u
u
u
ffi
ffi
ffi
x
x
x
“
“
“
E
K
”
”
TA
TA
TA
-40 to 85
-40 to 125
-40 to 150
°
°
°
C
C
C
L
”
5 Pin Definitions and Descriptions
SE Pin
№
UA Pin
№
Name
Type
Function
1
2
3
1
3
2
V
DD
UT
GND
S
upp
pu
ound
l
y
Supply Voltage pin
O
O
G
u
t
t
Open Drain Output pin
r
Ground pin
Table 2: Pin definitions and descriptions
SE package
UA package
Data Sheet
Mar/12
3901001881
Rev 016
Page 3 of 12
US1881
Hall Latch – High Sensitivity
6 General Electrical Specifications
DC Operating Parameters TA = 25oC, VDD = 3.5V to 24V (unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
S
S
upp
upp
l
y
y
V
o
l
t
a
g
e
VDD
O
p
e
r
a
t
i
ng
3.5
24
V
l
Curr
e
n
t
IDD
VD
B < BRP
5
m
A
Output
Output
Output
Output
S
a
t
u
r
a
ti
on
V
o
l
t
a
g
e
IOUT = 20mA, B > BO
P
0.5
10
V
S
on
Lea
k
a
g
e
Curr
e
n
t
I
B < BRP, VOUT
RL = 1kꢀ, CL
RL = 1kꢀ, CL
=
=
=
24
V
0.3
0.25
0.25
10
OFF
µ
µ
µ
A
s
R
i
s
e
T
i
m
e
tr
tf
20pF
20pF
Fall Time
s
M
a
x
i
m
u
m
S
w
i
t
c
h
i
ng F
r
e
qu
e
n
c
y
FSW
RTH
KHz
Package
T
h
e
r
m
a
l
R
e
s
i
s
t
a
n
c
e
S
i
ng
l
e
l
a
y
e
r
(1S) Jedec bo
a
r
d
301
°C/W
Table 3: Electrical specifications
7 Magnetic Specifications
DC Operating Parameters VDD = 3.5V to 24V (unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
O
p
e
r
a
t
i
ng
P
o
i
n
t
t
t
BO
P
0.5
9.5
m
m
m
m
m
m
m
m
m
T
T
T
T
T
T
T
T
T
E
spec., TA = 85°C
R
e
l
ea
s
e
P
o
i
n
t
BRP
BH
-9.5
-
0.5
12
Hysteresis
7
Y
S
T
T
T
O
R
p
e
r
a
t
i
ng
P
o
i
n
BO
0.5
9.5
P
BRP
BH
K spec., TA
L spec., TA
=
=
125°C
150°C
e
l
ea
s
e
P
o
i
n
t
-9.5
-
0.5
12
Hysteresis
7
Y
S
O
R
p
e
r
a
t
i
ng
P
o
i
n
BO
0.5
9.5
P
BRP
BH
e
l
ea
s
e
P
o
i
n
t
-9.5
-
0.5
Hy
s
t
e
r
e
si
s
6
12.5
Y
S
Table 4: Magnetic specifications
Note 1: For typical values, please refer to the performance graphs in section 11
8 Output Behaviour versus Magnetic Pole
DC Operating Parameters TA = -40oC to 150oC, VDD = 3.5V to 24V (unless otherwise specified)
Parameter Test Conditions (SE) OUT (SE) Test Conditions (UA) OUT (UA)
South po
North po
l
e
B < BRP
H
i
gh
B > BO
L
o
w
P
l
e
B > BO
L
o
w
B < BRP
H
i
gh
P
Table 5: Output behaviour versus magnetic pole
South pole
North pole
North po
le
South pole
OUT = high
OUT = low (VDSon)
OUT = high
OUT = low (VDSon)
SE package
UA package
Data Sheet
Mar/12
3901001881
Rev 016
Page 4 of 12
US1881
Hall Latch – High Sensitivity
9 Detailed General Description
Based on mixed signal CMOS technology, Melexis US1881 is a Hall-effect device with high magnetic
sensitivity. This multi-purpose latch suits most of the application requirements.
The chopper-stabilized amplifier uses switched capacitor technique to suppress the offset generally observed
with Hall sensors and amplifiers. The CMOS technology makes this advanced technique possible and
contributes to smaller chip size and lower current consumption than bipolar technology. The small chip size is
also an important factor to minimize the effect of physical stress.
This combination results in more stable magnetic characteristics and enables faster and more precise design.
The wide operating voltage from 3.5V to 24V, low current consumption and large choice of operating
temperature range according to “L”, “K” and “E” specification make this device suitable for automotive,
industrial and consumer applications.
The output signal is open-drain type. Such output allows simple connectivity with TTL or CMOS logic by using
a pull-up resistor tied between a pull-up voltage and the device output.
10 Unique Features
The US1881 exhibits latch magnetic switching characteristics. Therefore, it requires both south and north
poles to operate properly.
SE package - Latch characteristic
UA package - Latch charaacteristic
The device behaves as a latch with symmetric operating and release switching points (BOP=|BRP|). This
means magnetic fields with equivalent strength and opposite direction drive the output high and low.
Removing the magnetic field (B
device as a magnetic memory.
→0) keeps the output in its previous state. This latching property defines the
A magnetic hysteresis BHYST keeps BOOP and BRP separated by a minimal value. This hysteresis prevents
output oscillation near the switching point.
Data Sheet
Mar/12
3901001881
Rev 016
Page 5 of 12
US1881
Hall Latch – High Sensitivity
11 Performance Graphs
11.1 Magnetic parameters vs. TA
11.2 Magnetic parameters vs. VDD
12
12
9
9
6
6
3
3
Bop, VDD=3.5V
Brp, VDD=3.5V
Bhyst, VDD=3.5V
Bop, VDD=24V
Bop, Ta=25
Brp, Ta==25
Bhyst, Taa=25
°
C
Bop, Ta=150
Brp, Ta=150
Bhyst, Ta=150°C
°C
0
-3
-6
-9
0
Brp, VDD=24V
°C
°C
Bhyst, VDD=24V
°
C
-3
-6
-9
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Ta C)
3
4
5
6
7
8
9
10 11 12 13 14 15 166
17 18 19 20 21 22 23 24
(°
VDD (Volts)
11.3 VDSon vs. TA
11.4 VDSon vs. VDD
0.5
Ta = -40°C
Ta = 25
Ta = 85
°C
0.4
0.4
0.3
0.2
0.1
0
VDD = 3.5V
°C
VDD = 12V
VDD = 24V
Ta = 150°C
0.2
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Ta C)
3
4
5
6
7
8
9
10 11 12 13 14 15
116 17 18 19 20 21 22 23 24
(
°
VDD (Volts)
11.5 IDD vs. TA
11.6 IDD vs. VDD
5
4.5
4
5
4.5
4
VDD
VDD
=
=
3.5V
12V
VDD = 24V
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
Ta = -40°C
Ta = 25°C
Ta = 85
°
C
0.5
0
0.5
0
Ta = 150
°C
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Ta C)
3
4
5
6
7
8
9
10 11 12 13 14 15
116 17 18 19 20 21 22 23 24
(
°
VDD (Volts)
Data Sheet
Mar/12
3901001881
Rev 016
Page 6 of 12
US1881
Hall Latch – High Sensitivity
11.7 IOFF vs. TA
11.8 IOFF vs. VDD
60
50
40
30
20
10
0
60
50
40
30
20
10
VDD = 3.5V
Ta
Ta
=
=
25
°C
VDD = 12V
VDD = 24V
85°
C
Ta = 150°C
0
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
-40
-30
-20
-10
0
10
20
30
40
50
Ta
60
C)
70
80
90
100
110
120
130
140 150
(
°
VDD (Volts)
12 Test Conditions
Note : DUT = Device Under Test
12.1 Supply Current
12.2 Output Saturation Voltage
12.3 Output Leakage Current
12.4 Magnetic Thresholds
Data Sheet
Mar/12
3901001881
Rev 016
Page 7 of 12
US1881
Hall Latch – High Sensitivity
13 Application Information
13.1 Typical Three-Wire Application Circuit
13.2 Two-Wire Circuit
13.3 Automotive and Harsh, Noisy Environments
Three-Wire Circuit
Note:
With this circuit, precise ON and OFF
currents can be detected using only two
connecting wires.
The resistors RL and Rb can be used to
bias the input current. Refer to the part
specifications for limiting values.
BRP
BOP
:
:
IOFF = IR + IDD = VDD/Rb + IDD
ION = IOFF + IOUT = IOFF + VDD/RL
14 Application Comments
For proper operation, a 100nF bypass capacitor should be placed as close as possible to the device between
the VDD and ground pin.
For reverse voltage protection, it is recommended to connect a resistor or a diode in series with the VDD pin.
When using a resistor, three points are important:
- the resistor has to limit the reverse current to 50mA maximum (VCC / R1
≤ 50mA)
- the resulting device supply voltage VDD has to be higher than VDD min (VDD = VCC – R1.IDD
- the resistor has to withstand the power dissipated in reverse voltage condition (PD = VCC
)
2 / R1)
0.7V).
/0.25W resistor for 5V application and a diode for higher supply voltage are recommended.
When using a diode, a reverse current cannot flow and the voltage drop is almost constant (
Therefore, a 100
≈
ꢀ
Both solutions provide the required reverse voltage protection.
When a weak power supply is used or when the device is intended to be used in noisy environment, it is
recommended that figure 13.3 from the Application Information section is used.
The low-pass filter formed by R1 and C1 and the zener diode Z1 bypass the disturbances or voltage spikes
occurring on the device supply voltage VDD. The diode D1 provides additional reverse voltage protection.
Data Sheet
Mar/12
3901001881
Rev 016
Page 8 of 12
US1881
Hall Latch – High Sensitivity
15 Standard information regarding manufacturability of Melexis
products with different soldering processes
Our products are classified and qualified regarding soldering technology, solderability and moisture sensitivity
level according to following test methods:
Reflow Soldering SMD’s (Surface Mount Devices)
•
IPC/JEDEC J-STD-020
Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices
(classification reflow profiles according to table 5-2)
EIA/JEDEC JESD22-A113
•
Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing
(reflow profiles according to table 2)
Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
•
•
EN60749-20
Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat
EIA/JEDEC JESD22-B106 and EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Iron Soldering THD’s (Through Hole Devices)
•
EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
•
EIA/JEDEC JESD22-B102 and EN60749-21
Solderability
For all soldering technologies deviating from above mentioned standard conditions (regarding peak
temperature, temperature gradient, temperature profile etc) additional classification and qualification tests
have to be agreed upon with Melexis.
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.
Melexis is contributing to global environmental conservation by promoting lead free solutions. For more
information on qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of the
use of certain Hazardous Substances) please visit the quality page on our website:
http://www.melexis.com/quality.aspx
16 ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
Data Sheet
Mar/12
3901001881
Rev 016
Page 9 of 12
US1881
Hall Latch – High Sensitivity
17 Package Information
17.1 SE Package (TSOT-3L)
Data Sheet
Mar/12
3901001881
Rev 016
Page 10 of 12
US1881
Hall Latch – High Sensitivity
17.2 UA Package (TO-92 flat)
Data Sheet
Mar/12
3901001881
Rev 016
Page 11 of 12
US1881
Hall Latch – High Sensitivity
18 Disclaimer
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its
Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the
information set forth herein or regarding the freedom of the described devices from patent infringement.
Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with Melexis for current information. This
product is intended for use in normal commercial applications. Applications requiring extended temperature
range, unusual environmental requirements, or high reliability applications, such as military, medical life-
support or life-sustaining equipment are specifically not recommended without additional processing by
Melexis for each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be
liable to recipient or any third party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential
damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical
data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering
of technical or other services.
© 2012 Melexis NV. All rights reserved.
For the latest version of this document, go to our website at
www.melexis.com
Or for additional information contact Melexis Direct:
Europe, Africa, Asia:
America:
Phone: +1 248 306 5400
Phone: +32 1367 0495
E-mail: sales_europe@melexis.com E-mail: sales_usa@melexis.com
ISO/TS 16949 and ISO14001 Certified
Data Sheet
Mar/12
3901001881
Rev 016
Page 12 of 12
相关型号：
©2020 ICPDF网 联系我们和版权申明