TS30022 [ETC]
High Efficiency 1A/2A/3A Current-Mode Synchronous Buck DC/DC Converter, 2MHz and 470mA LDO; 高效率1A / 2A / 3A电流模式同步降压DC / DC转换器，为2MHz和470毫安LDO
| 型号： | TS30022 |
| 厂家： | 
ETC |
| 描述： | High Efficiency 1A/2A/3A Current-Mode Synchronous Buck DC/DC Converter, 2MHz and 470mA LDO |
| 文件： | 总19页 (文件大小：1716K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS30021/22/23
Version 1.5
High Efficiency 1A/2A/3A Current-Mode Synchronous Buck
DC/DC Converter, 2MHz and 470mA LDO
DESCRIPTION
FEATURES
.
.
.
Fixed output voltage choices: 1.5V, 1.8V, 2.5V,
3.3V, and 5V with +/- 2% output tolerance
The TS30021 (1A), TS30022 (2A) and TS30023
(3A) are DC/DC synchronous switching regulator
with fully integrated power switches, internal
compensation, and full fault protection, with a low-
dropout regulator. The switching frequency of
2MHz enables the use of small filter components
resulting in minimal board space and reduced BOM
costs. In addition, a 470mA LDO with external
voltage adjustment is provided. The LDO is capable
of working at the VCC supply.
Adjustable version output voltage range: 0.8V to
5V with +/- 1.5% reference
Wide input voltage range
TS30021/22/23: 4.5V to 16V (18V Abs Max)
.
.
2MHz +/- 10% fixed switching frequency
Continuous output current: 1A (TS30021), 2A
(TS30022) and 3A (TS30023)
.
.
High efficiency – up to 95%
The TS30021/22/23 utilizes current mode feedback
in normal regulation PWM mode. When the
regulator is disabled (EN is low), the device draws
less than 10uA quiescent current.
Current mode PWM control with PFM mode for
improved light load efficiency
.
.
.
.
Voltage supervisor for VOUT reported at the PG pin
Input supply under voltage lockout
The TS30021/22/23 integrates a wide range of
protection circuitry including input supply under-
voltage lockout, output voltage soft start, current
limit, and thermal shutdown.
Soft start for controlled startup with no overshoot
Full protection for over-current, over-temperature,
and VOUT over-voltage
.
Less than 10uA in shutdown mode
.
.
Low external component count
LDO has adjustable output voltage 0.8V to 5V and
470mA output current capability
The TS30021/22/23 includes supervisory reporting
through the PG (Power Good) open drain output to
interface other components in the system.
SUMMARY SPECIFICATION
APPLICATIONS
.
.
Junction operating temperature -40 °C to 125 °C
Packaged in a 16pin QFN (3x3)
.
.
.
On-card switching regulators
Set-top box, DVD, LCD, LED supply
Industrial power supplies
TYPICAL APPLICATIONS
Adjustable Switcher Output
Fixed Switcher Output
BST
BST
CBST
CBST
VCC
VSW
VCC
VLDO
VOUT
VCC
VLDO
VCC
VLDO
VOUT
VSW
Lout
RTOPSW
RBOTSW
Lout
Cbypass
Cbypass
Cout
Cout
FBSW
FBSW
VLDO
Cbypass-LDO
Cbypass-LDO
VOLDO
FBLDO
VOUT_LDO
PG
VOLDO
FBLDO
VOUT_LDO
PG
RTOP
RBOT
RTOP
RBOT
VOUT
VOUT
Cout_LDO
Cout_LDO
10kW
(Optional)
10kW
(Optional)
EN
EN
EN
EN
PG
PG
Specifications subject to change
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- 1 -
TS30021/22/23
Version 1.5
PINOUT
VSW
VCC
VCC
GND
VSW
VLDO
BST
PIN 1
TS30021/22/23
/EN
Figure 1: 16 Lead 3x3 QFN, Top View
PIN DESCRIPTION FOR 16 LEAD 3X3 QFN
Pin Symbol
Pin #
Function
Description
VSW
1
Switching Voltage Node
Connected to 1.5uH (typical) inductor
Input voltage
VCC
VCC
2
3
Input Voltage
Input Voltage
Input voltage
Primary ground for the majority of the device except
the low-side power FET
GND
4
5
6
GND
Switching Regulator FB Voltage. Connects to VOUT for
fixed mode and the output resistor divider for
adjustable mode
FB
Feedback Input for Switcher
Feedback Input for LDO
LDO Regulator FB Voltage. Connects to output resistor
divider to adjust LDO voltage
FBLDO
VOLDO
PG
7
8
9
LDO Output
PG Output
LDO regulator output
Open-drain output
EN
Enable Input
Active high enable pin. Includes internal pull-up.
Bootstrap capacitor for the high-side FET gate driver.
22nF ceramic capacitor from BST pin to VSW pin
BST
10
Bootstrap Capacitor
VLDO
VSW
VSW
PGND
PGND
VSW
11
12
13
14
15
16
LDO Input Voltage
Switching Voltage Node
Switching Voltage Node
Power GND
Input Voltage for LDO regulator
Connected to 1.5uH (typical) inductor
Connected to 1.5uH (typical) inductor
GND supply for internal low-side FET/integrated diode
GND supply for internal low-side FET/integrated diode
Connected to 1.5uH (typical) inductor
Power GND
Switching Voltage Node
Specifications subject to change
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TS30021/22/23
Version 1.5
FUNCTIONAL BLOCK DIAGRAM
PG
EN
VCC
4.2V
VCC
BST
VCC
VIN
Under Voltage
Protection
MONITOR
&
CBYPASS
VCC
CONTROL
Over & Under
Voltage
Protection
FB
Bootstrap
Voltage
Oscillator
Thermal
Protection
Ramp
Generator
Over Current
Protection
VCC
Vref
&
CBST
Gate
Drive
Softstart
VSW
Gate Drive
Control
LOUT
VOUT
COUT
Comparator
Vref
Gate
Drive
Error Amp
PGND
Compensation
Network
RTOPSW
PFM Mode
Comparator
FB
RBOTSW
VLDO
VLDO
VLDO
Vref
GND
FBLDO
VOLDO
CLDO
RBOT
RTOP
Figure 2: TS30021/22/23 Block Diagram
PG
Filter
Filter
Filter
Filter
Filter
VOUT-UV
EN
ENABLE
REGULATOR
Internal
POR
VCC-UV
TSD
Filter
VOUT-OV
TRISTATE
VSW OUTPUT
OCD_Filter
IOCD
Figure 3: Monitor & Control Logic Functionality
Specifications subject to change
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TS30021/22/23
Version 1.5
ABSOLUTE MAXIMUM RATINGS
Over operating free–air temperature range unless otherwise noted(1, 2)
Parameter
Value
-0.3 to 18
-0.3 to (VCC+6)
-1 to 18
Unit
V
VCC, VLDO
BST
V
VSW
V
EN, PG,FB, FBLDO, VOLDO
-0.3 to 6
+/-2k
V
Electrostatic Discharge – Human Body Model
Electrostatic Discharge – Charge Device Model
Lead Temperature (soldering, 10 seconds)
V
+/-500
V
260
C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
38
Unit
°C/W
°C
JA
Thermal Resistance Junction to Air (Note 1)
Storage Temperature Range
TSTG
TJ MAX
TJ
-65 to 150
150
Maximum Junction Temperature
Operating Junction Temperature Range
°C
-40 to 125
°C
Note 1: Assumes 16LD 3x3 QFN with hi-K JEDEC board and 13.5 inch2 of 1 oz Cu
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
4.5
Typ
Max
16
Unit
V
Input Operating Voltage
12
VLDO
LDO Input Operating Voltage
2.2
16
V
CBST
Bootstrap Capacitor
17.6
1.2
22
1.5
22
1
26.4
1.8
nF
uH
uF
uF
mW
uF
uF
LOUT
Output Filter Inductor Typical Value (Note 1)
Output Filter Capacitor Typical Value (Note 2)
LDO Output Filter Capacitor Typical Value (Note 2)
Output Filter Capacitor ESR
COUT
17.6
COUT_LDO
COUT-ESR
CBYPASS
CBYPASS-LDO
2
8
8
100
Input Supply Bypass Capacitor Typical Value (Note 3)
LDO Input Supply Bypass Capacitor Typical Value (Note 3)
10
10
Note 1: For best performance, an inductor with a saturation current rating higher than the maximum VOUT load requirement plus the inductor current ripple.
Note 2: For best performance, a low ESR ceramic capacitor should be used.
Note 3: For best performance, a low ESR ceramic capacitor should be used. If CBYPASS is not a low ESR ceramic capacitor, a 0.1uF ceramic capacitor should be
added in parallel to CBYPASS
.
Specifications subject to change
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TS30021/22/23
Version 1.5
ELECTRICAL CHARACTERISTICS
Electrical Characteristics, TJ = -40C to 125C, VCC = 12V (unless otherwise noted)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VCC Supply Voltage
VCC
Input Supply Voltage
Quiescent current
Normal Mode
4.5
16
V
ICC-NORM
VCC = 12V, ILOAD = 0A
VCC=12V, ILOAD=0A, Non-switching
VCC = 12V, EN = 0V
5.2
2.3
5
mA
Quiescent current Normal
Mode – Non-switching
Quiescent current
ICC-NOSWITCH
ICC-STBY
mA
uA
10
Standby Mode
VCC Under Voltage Lockout
Input Supply Under Voltage
VCC-UV
VCC Increasing
4.0
1.8
4.5
V
Threshold
Input Supply Under Voltage
Threshold Hysteresis
VCC-UV_HYST
650
2
mV
OSC
FOSC
Oscillator Frequency
2.2
MHz
PG Open Drain Output
TPG
IOH-PG
VOL-PG
PG Release Timer
High-Level Output Leakage
Low-Level Output Voltage
PG de-assert from low to high
VPG = 5V
150
0.5
ms
uA
V
IPG = -0.3mA
0.01
0.8
EN Input Voltage Thresholds
VIH-EN
VIL-EN
VHYST-EN
High Level Input Voltage
Low Level Input Voltage
Input Hysteresis
2.2
V
V
mV
uA
uA
480
3.5
8.0
VEN=5V
VEN=0V
IIN-EN
Input Leakage
Thermal Shutdown
Thermal Shutdown Junction
TSD
Note: not tested in production
Note: not tested in production
150
170
10
°C
°C
Temperature
TSD Hysteresis
TSDHYST
Specifications subject to change
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TS30021/22/23
Version 1.5
REGULATOR CHARACTERISTICS
Electrical Characteristics, TJ = -40C to 125C, VCC = 12V (unless otherwise noted)
Symbol
Parameter
Condition
ILOAD =1A
ILOAD = 0A
Min
Typ
Max
Unit
Switch Mode Regulator: L=1.5uH and C=22uF
VOUT-PWM
VOUT-PFM
Output Voltage Tolerance in PWM
Mode
Output Voltage Tolerance in PFM
Mode
VOUT
2%
–
VOUT
2%
+
VOUT
V
V
VOUT
1%
–
VOUT
1%
+
VOUT +
3.5%
High Side Switch On Resistance
Low Side Switch On Resistance
IVSW = -1A (Note 1)
IVSW = 1A (Note 1)
180
120
mΩ
mΩ
RDSON
TS30023 (Note 4)
TS30012 (Note 4)
TS30011
HS switch current
TS30023
HS switch current
TS30012
HS switch current
TS30011
3
A
IOUT,SW
Output Current, Switcher
2
1
A
A
3.4
2.4
1.4
3.8
2.8
1.8
0.8
4.4
3.4
2.4
A
A
A
V
IOCD,SW
Over Current Detect, Switcher
FBTH, SW
Feedback Reference, Switcher
(Adjustable Mode)
Feedback Reference Tolerance
Soft start Ramp Time
(Note 3)
(Note 3)
FBTH-TOL
TSS
-1.5
1.5
%
ms
4
VOUT
1%
+
FBTH-PFM
VOUT-UV
VOUT-UV_HYST
VOUT-OV
PFM Mode FB Comparator Threshold
VOUT Under Voltage Threshold
VOUT Under Voltage Hysteresis
VOUT Over Voltage Threshold
V
91%
VOUT
93%
VOUT
1.5%
VOUT
103%
VOUT
1%
95%
VOUT
VOUT-OV_HYST
VOUT Over Voltage Hysteresis
Max Duty Cycle
VOUT
DUTYMAX
(Note 2)
95%
0.8
97%
99%
LDO Regulator
VOLDO = 1.2V, IOUT,LDO
450mA
=
VODROPOUT
Dropout Voltage, LDO
0.8
V
VLDO
-
VOLDO
Output Voltage, LDO
Output Current, LDO
VODROP
OUT
V
IOUT,LDO
470
mA
IOCD,LDO
FBTHLDO
Over Current Detect, Switcher
Feedback Reference, LDO
490
0.8
mA
V
Note 1: RDSON is characterized at 1A and tested at lower current in production.
Note 2: Regulator VSW pin is forced off for 240ns every 8 cycles to ensure the BST cap is replenished.
Note 3: For the adjustable version, the ratio of VCC/Vout cannot exceed 16.
Note 4: Based on Over Current Detect testing
Specifications subject to change
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TS30021/22/23
Version 1.5
FUNCTIONAL DESCRIPTION
The TS30021/22/23 current-mode synchronous step-down power supply product is ideal for use in the commercial, industrial,
and automotive market segments. It includes flexibility to be used for a wide range of output voltage and is optimized for high
efficiency power conversion with low RDSON integrated synchronous switches. A 2MHz internal switching frequency facilitates
low cost LC filter combinations. Additionally, the fixed output versions enable a minimum external component count to provide
a complete regulation solution with only 4 external components: an input bypass capacitor, an inductor, an output capacitor,
and the bootstrap capacitor. The regulator automatically transitions between PFM and PWM mode to maximize efficiency for
the load demand.
In addition, the TS30021/22/23 provides a linear low drop-out regulator capable of operating over a wide range of output
voltage, input voltage and output current. LDO operation only requires 4 external components: an input bypass capacitor, an
output capacitor and two resistors to set output voltage. It features a separate input supply pin that is regulated down to the
output voltage. This supply input can be connected to the main SMPS supply (VCC) or the SMPS output (VOUT) or to a separate
supply thus making the device very flexible.
The TS30021/22/23 was designed to provide these system benefits:
Reduced board real estate
Lower system cost
o
o
Lower cost inductor
Low external parts count
Ease of design
o
o
o
o
Bill of Materials and suggested board layout provided
Power Good output
Integrated compensation network
Wide input voltage range
Robust solution
Over current, over voltage and over temperature protection
o
DETAILED PIN DESCRIPTION
Unregulated input, VCC
This terminal is the unregulated input voltage source for the IC. It is recommended that a 10uF bypass capacitor be placed
close to the device for best performance. Since this is the main supply for the IC, good layout practices need to be followed for
this connection.
Bootstrap control, BST
This terminal will provide the bootstrap voltage required for the upper internal NMOS switch of the buck regulator. An external
ceramic capacitor placed between the BST input terminal and the VSW pin will provide the necessary voltage for the upper
switch. In normal operation the capacitor is re-charged on every low side synchronous switching action. In the case of where
the switch mode approaches 100% duty cycle for the high side FET, the device will automatically reduce the duty cycle switch
to a minimum off time on every 8th cycle to allow this capacitor to re-charge.
Sense feedback, FB
This is the input terminal for the output voltage feedback.
For the fixed mode versions, this should be hooked directly to VOUT. The connection on the PCB should be kept as short as
possible, and should be made as close as possible to the capacitor. The trace should not be shared with any other connection.
For adjustable mode versions, this should be connected to the external resistor divider. To choose the resistors, use the
following equation:
VOUT = 0.8 (1 + RTOPSW/RBOTSW
)
Specifications subject to change
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TS30021/22/23
Version 1.5
The input to the FB pin is high impedance, and input current should be less than 100nA. As a result, good layout practices are
required for the feedback resistors and feedback traces. When using the adjustable version, the feedback trace should be kept
as short as possible and minimum width to reduce stray capacitance and to reduce the injection of noise.
For the adjustable version, the ratio of VCC/Vout cannot exceed 16.
Switching output, VSW
This is the switching node of the regulator. It should be connected directly to the 1.5uH inductor with a wide, short trace and to
one end of the Bootstrap capacitor. It is switching between VCC and PGND at the switching frequency.
Ground, GND
This ground is used for the majority of the device including the analog reference, control loop, and other circuits.
Power Ground, PGND
This is a separate ground connection used for the low side synchronous switch to isolate switching noise from the rest of the
device.
Enable, high-voltage, EN
This is the input terminal to activate both the switching regulator and LDO. The input threshold is TTL/CMOS compatible. It
also has an internal pull-up to ensure a stable state if the pin is disconnected.
Option available for sequential power-up of switching regulator first, followed by activating the LDO after switching regulator
voltage is above VOUT-UV threshold.
PG Output, PG
This is an open drain, active low output. The switched mode output voltage is monitored and the PG line will remain low until
the output voltage reaches the VOUT-UV threshold. Once the internal comparator detects the output voltage is above the desired
threshold, an internal delay timer is activated and the PG line is de-asserted to high once this delay timer expires. In the event
the output voltage decreases below VOUT-UV, the PG line will be asserted low and remain low until the output rises above VOUT-UV
and the delay timer times out. See Figure 2 for the circuit schematic for the PG signal.
Options are available for PG only based on switcher output voltage, or the combination of both switcher and LDO outputs being
higher than the VOUT-UV thresholds.
Unregulated LDO input, VLDO
This terminal is the unregulated input voltage source for regulation stage of the LDO. It is recommended that a 10uF bypass
capacitor be placed close to the device for best performance.
LDO Sense feedback, FBLDO
This is the input terminal for the adjustable voltage feedback for the LDO. The following formula determines the output
voltage.
VOLDO = 0.8 (1 + RTOP/RBOT
)
The same guidelines as given for the switching regulator FB pin apply to the LDO FB pin as well.
Regulated LDO Output, VOLDO
This terminal is the output of the LDO and should be connected to a 1uF output capacitor.
INTERNAL PROTECTION DETAILS
SMPS Internal Current Limit
The current through the high side FET is sensed on a cycle by cycle basis and if current limit is reached, it will abbreviate the
cycle. In addition, the device senses the FB pin to identify hard short conditions and will direct the VSW output to skip 4 cycles
if current limit occurs when FB is low. This allows current built up in the inductor during the minimum on time to decay
sufficiently. Current limit is always active when the regulator is enabled. Soft start ensures current limit does not prevent
regulator startup.
Specifications subject to change
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TS30021/22/23
Version 1.5
Under extended over current conditions (such as a short), the device will automatically disable. Once the over current
condition is removed, the device returns to normal operation automatically. (Alternately the factory can configure the device’s
NVM to shutdown the regulator if an extended over current event is detected and require a toggle of the Enable pin to return
the device to normal operation.)
Thermal Shutdown
If the temperature of the die exceeds 170°C (typical), the VSW outputs will tri-state to protect the device from damage. The PG
and all other protection circuitry will stay active to inform the system of the failure mode. Once the device cools to 160°C
(typical), the device will start up again, following the normal soft start sequence. If the device reaches 170°C, the
shutdown/restart sequence will repeat.
SMPS Reference Soft Start
The reference in this device is ramped at a rate of 4ms to prevent the output from overshoot during startup. This ramp restarts
whenever there is a rising edge sensed on the Enable pin. This occurs in both the fixed and adjustable versions. During the soft
start ramp, current limit is still active, and will still protect the device in case of a short on the output.
SMPS Output Overvoltage
If the output of the regulator exceeds 103% of the regulation voltage, the VSW outputs will tri-state to protect the device from
damage. This check occurs at the start of each switching cycle. If it occurs during the middle of a cycle, the switching for that
cycle will complete, and the VSW outputs will tri-state at the beginning of the next cycle.
VCC Under-Voltage Lockout
The device is held in the off state until VCC reaches 5.75V (typical). There is a 500mV hysteresis on this input, which requires
the input to fall below 5.25V (typical) before the device will disable.
LDO Internal Current Limit
The LDO output current is sensed and if current limit is reached, it will restrict further current draw from the LDO. Current
limit is always active when the regulator is enabled.
Specifications subject to change
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TS30021/22/23
Version 1.5
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = -40C to 125C, VCC = 12V (unless otherwise noted)
Figure 5. 100mA to 1A Load Step (Vcc=12V, VOUT=1.8V)
Figure 4. Startup Response
Figure 6. 100mA to 2A Load (VCC=12V, VOUT=1.8V)
Figure 7. 100mA to 1A Load Step (VCC=12V, VOUT=3.3V)
Figure 9. Line Transient Response (VCC=10V to 15V, VOUT=3.3V)
Figure 8. 100mA to 2A Load Step (VCC=12V, VOUT=3.3V)
Specifications subject to change
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TS30021/22/23
Version 1.5
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = -40C to 125C, VCC = 12V (unless otherwise noted)
Figure 10. Load Regulation
Figure 11. Line Regulation (IOUT=1A)
Figure 12. Efficiency vs. Output Current ( VOUT = 1.8V)
Figure 13. Efficiency vs. Output Current ( VOUT = 3.3V)
Figure 15. Efficiency vs. Input Voltage (VOUT = 3.3V)
Figure 14. Efficiency vs. Output Current ( VOUT = 5V)
Specifications subject to change
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TS30021/22/23
Version 1.5
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = -40C to 125C, VCC = 12V (unless otherwise noted)
Figure 16. Standby Current vs. Input Voltage
Figure 17. Standby Current vs. Temperature
Figure 18. Output Voltage vs. Temperature
Figure 19. Oscillator Frequency vs. Temperature (Iout=300mA)
Figure 20. Quiescent Current vs. Temperature (No load)
Figure 21. Input Current vs. Temperature (No load, No switching)
Specifications subject to change
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TS30021/22/23
Version 1.5
TYPICAL APPLICATION SCHEMATIC
Adjustable Switcher Output
BST
CBST
VCC
VLDO
VCC
VLDO
VOUT
VSW
Lout
RTOPSW
RBOTSW
Cbypass
Cout
FBSW
Cbypass-LDO
VOLDO
FBLDO
VOUT_LDO
PG
RTOP
RBOT
VOUT
Cout_LDO
10kW
(Optional)
EN
EN
PG
Figure 22: TS30021/22/23 Application Schematic
A minimal schematic suitable for most applications is shown on page 1. Figure 22 includes optional
components that may be considered to address specific issues as listed in the External Component
Selection section.
PCB LAYOUT
For proper operation and minimum EMI, care must be taken during PCB layout. An improper layout can lead to issues such as
poor stability and regulation, noise sensitivity and increased EMI radiation. The main guidelines are the following:
.
.
.
provide low inductive and resistive paths for loops with high di/dt,
provide low capacitive paths with respect to all the other nodes for traces with high di/dt,
sensitive nodes not assigned to power transmission should be referenced to the analog signal ground (GND) and be
always separated from the power ground (PGND).
The negative ends of CBYPASS, COUT and the Schottky diode DCATCH (optional) should be placed close to each other and connected
using a wide trace. Vias must be used to connect the PGND node to the ground plane. The PGND node must be placed as close as
possible to the TS30021/22/23 PGND pins to avoid additional voltage drop in traces.
The bypass capacitor CBYPASS (optionally paralleled to a 0.1µF capacitor) must be placed close to the VCC pins of
TS30021/22/23.
The inductor must be placed close to the VSW pins and connected directly to COUT in order to minimize the area between the
VSW pin, the inductor, the COUT capacitor and the PGND pins. The trace area and length of the switching nodes VSW and BST
should be minimized.
For the adjustable output voltage version of the TS30021/22/23, feedback resistors RBOTSW and RTOPSW are required for Vout
settings greater than 0.8V and should be placed close to the TS30021/22/23 in order to keep the traces of the sensitive node FB
as short as possible and away from switching signals. RBOTSW should be connected to the analog ground pin (GND) directly and
should never be connected to the ground plane. The analog ground trace (GND) should be connected in only one point to the
power ground (PGND). A good connection point is under the TS30021/22/23 package to the exposed thermal pad and vias
which are connected to PGND. RTOPSW will be connected to the VOUT node using a trace that ends close to the actual load.
Specifications subject to change
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TS30021/22/23
Version 1.5
For fixed output voltage versions of the TS30021/22/23, RBOTSW and RTOPSW are not required and the FB pin should be
connected directly to the Vout.
PCB layout for the LDO should follow the same approach and guidelines as given above.
The exposed thermal pad must be soldered to the PCB for mechanical reliability and to achieve good power dissipation. Vias
must be placed under the pad to transfer the heat to the ground plane.
EXTERNAL COMPONENT BILL OF MATERIALS
Suggested
Manufacturer
Designator Function
Description
Manufacturer Code
Qty
Input Supply Bypass
Capacitor
10uF 10%
35V
CBYPASS
TDK
CGA5L3X5R1V106K160AB
1
Input Supply Bypass
Capacitor
10uF 10%
35V
CBYPASS-LDO
TDK
TDK
CGA5L3X5R1V106K160AB
C2012X5R1A226K125AB
1
22uF 10%
10V
COUT
COUT_LDO
LOUT
Output Filter Capacitor
1
1
1
LDO Output Filter Capacitor
Output Filter Inductor (1A)
1uF
TDK
Wurth
1.5uH 2A
TDK
Wurth
LOUT
Output Filter Inductor (2A)
1.5uH 3A
1
TDK
Wurth
LOUT
CBST
Output Filter Inductor (3A)
Boost Capacitor
1.5uH 4.37A
22nF 10V
1
1
1
TDK
C1005X7R1C223K
17.8K
(Note 1)
RTOPSW
RTOP
&
&
Voltage Feedback Resistor
(RTOPSW optional)
10K
(Note 1)
RBOTSW
RBOT
Voltage Feedback Resistor
(RBOTSW optional)
1
1
1
1
1
PG Pin Pull-up Resistor
(optional)
RPLP
10K
30V 2A
SOD-123FL
On
DCATCH
DCATCH
DCATCH
Catch Diode (optional, 1A)
Catch Diode (optional, 2A)
Catch Diode (optional, 3A)
MBR230LSFT1G
PMEG4030ER,115
PMEG4050EP,1
Semiconductor
40V 3A
SOD-123
NXP
Semiconductors
40V 5A
SOD-123FL
NXP
Semiconductors
Note 1: The voltage divider resistor values are calculated for an output voltage of 2.5V. For fixed output versions, the FB pin is connected directly to VOUT
.
EXTERNAL COMPONENT SELECTION
The 2MHz internal switching frequency of the TS30021/22/23 facilitates low cost LC filter combinations. Additionally, the fixed
output versions enable a minimum external component count to provide a complete regulation solution with only 4 external
components: an input bypass capacitor, an inductor, an output capacitor, and the bootstrap capacitor. The internal
compensation is optimized for a 22uF output capacitor and a 1.5uH inductor.
Specifications subject to change
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TS30021/22/23
Version 1.5
For best performance, a low ESR ceramic capacitor should be used for CBYPASS. If CBYPASS is not a low ESR ceramic capacitor, a
0.1uF ceramic capacitor should be added in parallel to CBYPASS
.
The minimum allowable value for the output capacitor is 22uF. To keep the output ripple low, a low ESR (less than 35mOhm)
ceramic is recommended. Multiple capacitors can be paralleled to reduce the ESR.
The inductor range is 1.5uH +/-20%. For optimal over-current protection, the inductor should be able to handle up to the
regulator current limit without saturation. Otherwise, an inductor with a saturation current rating higher than the maximum
IOUT load requirement plus the inductor current ripple should be used.
For high current modes, the optional Schottky diode will improve the overall efficiency and reduce the heat. It is up to the user
to determine the cost/benefit of adding this additional component in the user’s application. The diode is typically not needed.
For the adjustable output version of the TS30021/22/23, the SMPS output voltage can be adjusted by sizing RTOPSW and RBOTSW
feedback resistors. The equation for the output voltage is VOUT = 0.8 (1 + RTOPSW/RBOTSW).
For the adjustable version, the ratio of VCC/Vout cannot exceed 16.
RPUP is only required when the Power Good signal (PG) is utilized.
THERMAL INFORMATION
TS30021/22/23 is designed for a maximum operating junction temperature Tj of 125°C. The maximum output power is limited
by the power losses that can be dissipated over the thermal resistance given by the package and the PCB structures. The PCB
must provide heat sinking to keep the TS30021/22/23 cool. The exposed metal on the bottom of the QFN package must be
soldered to a ground plane. This ground should be tied to other copper layers below with thermal vias. Adding more copper to
the top and the bottom layers and tying this copper to the internal planes with vias can reduce thermal resistance further. For a
hi-K JEDEC board and 13.5 square inch of 1 oz Cu, the thermal resistance from junction to ambient can be reduced to JA
=
38°C/W. The power dissipation of other power components (catch diode, inductor) cause additional copper heating and can
further increase what the TS30021/22/23 sees as ambient temperature.
Specifications subject to change
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TS30021/22/23
Version 1.5
PACKAGE MECHANICAL DRAWINGS (all dimensions in mm)
TOP VIEW
EXPOSED
PAD
BOTTOM VIEW
Units
Dimensions Limits
MILLIMETERS
NOM MAX
MIN
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Length
Exposed Pad Width
Overall Width
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
N
e
A
A1
A3
D
E2
E
16
0.50 BSC
0.90
0.80
0.00
1.00
0.05
0.02
0.20 REF
3.00 BSC
1.70
3.00 BSC
1.70
0.25
0.30
-
1.55
1.80
D2
b
L
1.55
0.20
0.20
0.20
1.80
0.30
0.40
-
K
Specifications subject to change
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TS30021/22/23
Version 1.5
RECOMMEDED PCB LAND PATTERN
Silk Screen
RECOMMENDED
LAND PATTERN
DIMENSIONS IN MILLIMETERS
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Contact Pitch
E
W2
T2
C1
C2
X1
Y1
G
0.50 BSC
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
-
-
-
-
-
-
-
-
1.70
1.70
-
3.00
3.00
-
-
-
Contact Pad Spacing
-
Contact Pad Width (X16)
Contact Pad Length (X16)
Distance Between Pads
0.35
0.65
-
0.15
Notes:
Dimensions and tolerances per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact values shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information only.
PACAKGING INFORMATION
Pb-Free (RoHS): The TS30021/22/23 devices are fully compliant for all materials covered by European Union Directive 2002/95/EC, and meet all IPC-
1752 Level 3 materials declaration requirements.
MSL, Peak Temp: The TS30021/22/23 family has a Moisture Sensitivity Level (MSL) 1 rating per JEDEC J-STD-020D. These devices also have a Peak
Profile Solder Temperature (Tp) of 260°C.
Specifications subject to change
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TS30021/22/23
Version 1.5
ORDERING INFORMATION
TS3002x-MvvvQFNR
x
Output Current
vvv
015
018
025
033
050
000
Output Voltage
1.5 V
1
2
3
1 Amp
2 Amp
3 Amp
1.8 V
2.5 V
3.3 V
5.0 V
Adjustable
Specifications subject to change
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TS30021/22/23
Version 1.5
Legal Notices
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by
updates. It is your responsibility to ensure that your application meets with your specifications. “Typical” parameters which may be provided in Triune
Systems data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for your application by your technical experts. TRIUNE SYSTEMS MAKES NO REPRESENTATIONS
OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE
INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR
PURPOSE. Triune Systems disclaims all liability arising from this information and its use. Triune System products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for
any other application in which the failure of the Triune Systems product could create a situation where personal injury or death may occur. Should the
Buyer purchase or use Triune Systems products for any such unintended or unauthorized application, the Buyer shall indemnify and hold Triune Systems,
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Triune Systems was negligent regarding the design or manufacture of the part. No licenses are conveyed, implicitly or otherwise, under any
Triune Systems intellectual property rights.
Trademarks
The Triune Systems® name and logo, MPPT-lite™, and nanoSmart® are trademarks of Triune Systems, LLC. in the U.S.A..
All other trademarks mentioned herein are property of their respective companies.
© 2013 Triune Systems, LLC. All Rights Reserved.
Specifications subject to change
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- 19 -
相关型号：
TS30023
High Efficiency 1A/2A/3A Current-Mode Synchronous Buck DC/DC Converter, 2MHz and 470mA LDO
ETC
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