TPS56302PWPR [ETC]
SMPS Controller ; SMPS控制器\n
| 型号： | TPS56302PWPR |
| 厂家： | 
ETC |
| 描述： | SMPS Controller
|
| 文件： | 总34页 (文件大小：810K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
PWP PowerPAD PACKAGE
(TOP VIEW)
2.8 V – 5.5 V Input Voltage Range
Programmable Dual Output Controller
Supports Popular DSP, FPGA and
Microcontroller Core and I/O Voltages
– Switching Regulator Controls I/O Voltage
– Low Dropout Controller Regulates Core
Voltage
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VID0
VID1
SLOWST
VHYST
DROOP
OCP
IOUT
PWRGD
VSEN–LDO
NGATE–LDO
INHIBIT
2
3
4
5
VREFB
6
VSEN–RR
ANAGND
BIAS
VLDODRV
CPC1
Thermal
Pad
Adjustable Slow-Start for Simultaneous
Powerup of Both Outputs
7
8
IOUTLO
Power Good Output Monitors Both Outputs
9
HISENSE
LOSENSE/LOHIB
HIGHDR
BOOT
BOOTLO
LOWDR
Fast Ripple Regulator Reduces Bulk
Capacitance for Lower System Costs
10
11
12
13
14
V
CC
CPC2
VDRV
DRVGND
±1.5% Reference Voltage Tolerance
Efficiencies Greater Than 90%
Overvoltage, Undervoltage, and Adjustable
Overcurrent Protection
AVAILABLE VID CODE RANGES
TPS56302
Drives Logic Level N-Channel MOSFETs
Through Entire Input Voltage Range
OUTPUTS
TPS56300
V
–LDO
1.3 V TO 2.5 V
1.3 V TO 3.3 V
1.3 V TO 3.3 V
1.3 V TO 2.5 V
Evaluation Module TPS56302EVM–163
Available
OUT
V
–Switcher
OUT
NOTE: See Table 1 for actual VID codes.
description
The high-performance TPS56302 synchronous-buck regulator provides two supply voltages to power the core
and I/O of digital signal processors. The TPS56302 is identical to the TPS56300 except that the reference
voltages of the LDO and switching regulator have been reversed. The switching regulator, using hysteretic
control with droop compensation, supports high current and efficiency for the I/O and other peripheral
components. The LDO controller, suitable for powering the core voltage, drives an external N-channel power
MOSFET and functions as an LDO regulator and as a power distribution switch.
typical design
V
I
(2.8 V – 5.5 V)
U1
TPS56302PWP
V
CC
CPC1
PWRGD
CPC2
NGATE–LDO
VREFB
VHYST
DROOP
OCP
VSEN–LDO
V
INHIBIT
IOUTLO
CORE
IOUT
SLOWST
VID0
VID1
BIAS
HISENSE
HIGHDR
VSEN–RR
DSP
V
I/O
See Table 1
See Table 1
Data
Data Bus
LOSENSE/LOHIB
BOOT
+
VLDODRV
VDRV
ANAGND
BOOTLO
LOWDR
PERIPHERAL
DRVGND
PwrPad
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
description (continued)
To promote better system reliability during power up, voltage sequencing and protection are controlled such that
the core and I/O power up together with the same slow-start voltage. At power down, the LDO and ripple
regulator are discharged towards ground for added protection. The TPS56302 also includes inhibit, slow-start,
and under-voltage lockout features to aide in controlling power sequencing. A tri-level voltage identification
definition (VID) sets both regulated voltages to any of 9 preset voltage pairs from 1.3 V to 3.3 V. Other voltages
are possible by implementing an external voltage divider. Strong MOSFET drivers, with a typical peak current
rating of 2-A sink and source are included on chip, which allows paralleling MOSFETs to be driven and allowing
highercurrenttobecontrolled. Thehigh-sidedriverfeaturesafloatingbootstrapdriverwithaninternalbootstrap
synchronous rectifier. Many protection features are incorporated within the device to ensure better system
integrity. An open-drain output power good status circuit monitors both output voltages, and is pulled low if either
output falls below the threshold. An over current shutdown circuit protects the high-side power MOSFET against
short-to-ground faults, while over voltage protection turns off the output drivers and LDO controller if either
output exceeds its threshold. Under voltage protection turns off the high-side and low-side MOSFET drivers and
the LDO controller if either output is 25% below V
. Lossless current-sensing is implemented by detecting
REF
the drain-source voltage drop across the high-side power MOSFET while it is conducting. The TPS56302 is fully
compliant with TI DSP power requirements.
AVAILABLE OPTIONS
PACKAGES
†
T
J
EVALUATION MODULE
TSSOP
(PWP)
–40°C to 125°C
TPS56302PWP
TPS56302EVM–163 (SLVP163)
†
The PWP package is also available taped and reel. To order, add an R to the end of
the part number (e.g., TPS56302PWPR).
¶#
Table 1. Voltage Identification Code
‡
VID TERMINALS
56302
56300
#
#
#
#
V
V
V
V
REF–LDO
REF–LDO
(VDC)
REF–RR
(VDC)
REF–RR
(VDC)
VID1
VID0
(VDC)
0
0
0
1
1
1
2
2
2
0
1
2
0
1
2
0
1
2
1.30
1.50
1.30
1.80
1.30
2.50
1.30
1.50
1.80
1.50
1.80
1.80
3.30
1.30
3.30
2.50
3.30
2.50
1.30
1.50
1.30
1.80
1.30
2.50
1.30
1.50
1.80
1.50
1.80
1.80
3.30
1.30
3.30
2.50
3.30
2.50
‡
§
¶
0 = ground (GND), 1 = floating(V
RR = Ripple Regulator, LDO = Low Drop-Out Regulator
/2), 2 = (V
)
BIAS
BIAS
V
/2 is internal, leave the VID pin floating. Adding an external 0.1-µF capacitor to ANAGND may be used
BIAS
to avoid erroneous level.
#
External resistors may be used as a voltage divider (from V
voltages to other values.
to VSEN–xx to ground) to program output
OUT
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
functional block diagram
LOSENSE/
LOHIB
IOUTLO
HISENSE
IOUT
PWRGD
25
19
21
20
26
+
8
9
Bias
>0.93xVSEN–RR
>0.93xVSEN–LDO
–
Reg.
VDRV
VLDODRV
22
SHUTDOWN
INHIBIT
VDRV UVLO
Delay
V
UVLO
CC
INHIBIT
11
10
V
HIGHDR
CC
RR_OVP
LDO_OVP
RR_UVP *
Fault
Latch
CPC1
CPC2
Q
R
S
LDO_UVP *
BOOT
12
SHUTDOWN
27
24
23
OCP
VDRV
+
–
125 mV
5 V
13
VDRV
VSEN–LDO
NGATE–LDO
SHUTDOWN
VLDODRV
E/A
–
1
2
VID0
VID1
SLOWST
VREF_LDO
VID
+
(see Table 1)
SHUTDOWN
Vbias
Hysteresis
SLOWST
17
18
16
15
BOOT
Comparator
Ivrefb/5
VREF_RR
SLOWST
Adaptive
Deadtime
3
+
HIGHDR
BOOTLO
–
SHUTDOWN
Hysteresis
Setting
VDRV
SHUTDOWN
LOWDR
7
5
4
28
6
14
ANAGND
VREFB
VHYST DROOP
VSEN–RR
DRVGND
* UVP is disabled during slowstart
FET
Synchronous
RR–Ripple Regulator
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
VID0
1
Voltage identification input 0. The VID pins are tri-level programming pins that set the output voltages for both
converters. The code pattern for setting the output voltage is located in table 1. The VID pins are internally pulled to
V /2, allowing floating voltage set to logic 1 (see Table 1).
BIAS
VID1
2
3
Voltage identification input 1 (see VID0 pin description and Table 1).
SLOWST
Slow-start(softstart).Acapacitorfrompin3toGNDsetstheslow-starttimeforV
will ramp-up together while tracking the slow-start voltage.
andV .Bothsupplies
OUT-LDO
OUT-RR
VHYST
4
5
6
Hysteresis set pin. The hysteresis equals 2 × (VREFB – VHYST).
VREFB
Buffered ripple regulator reference voltage from VID network.
VSEN-RR
Ripple regulator voltage sense input. This pin is connected to the ripple regulator output. It is used to sense the ripple
regulator voltage for regulation, OVP, UVP, and power good functions. It is recommended that an RC low pass filter be
connected at this pin to filter high frequency noise.
ANAGND
BIAS
7
8
9
Analog ground
Analog BIAS pin. Recommended that a 1-µF capacitor be connected to ANAGND.
VLDODRV
Output of charge pump generated through bootstrap diode. Approximately equal to VDRV + V – 300 mV. Used as
supply for LDO driver and bias regulator. Recommended that a 1-µF capacitor be connected to DRVGND.
IN
CPC1
10
11
Connect one end of charge pump capacitor. Recommended that a 1-µF capacitor be connected from CPC1 to CPC2.
V
CC
3.3 V or 5 V supply (2.8 V – 5.5 V). It is recommended that a low ESR capacitor be connected directly from V
to
CC
DRVGND (bulk capacitors supplied at power stage input).
CPC2
VDRV
12
13
Other end of charge pump capacitor from CPC1.
Regulated output of internal charge pump. Supplies DRIVE charge for the low-side MOSFET driver (5 V).
Recommended that a 10-µF capacitor be connected to DRVGND.
DRVGND
LOWDR
BOOTLO
BOOT
14
15
16
17
18
19
Drive ground. Ground for FET drivers. Connect to source of low-side FET.
Low drive. Output drive to synchronous rectifier low-side FET.
Bootstrap low. This pin connects to the junction of the high-side and low-side FETs.
Bootstrap pin. Connect a 1-µF low ESR capacitor to BOOTLO to generate floating drive for the high-side FET driver.
High drive. Output drive to high-side power switching FETs
HIGHDR
LOSENSE/
LOHIB
Low sense/low-side inhibit. This pin is connected to the junction of the high and low-side FETs and is used in current
sensing and the anti-cross-conduction to eliminate shoot-through current.
HISENSE
IOUTLO
INHIBIT
20
21
22
High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs.
Current sense low output. Voltage on this pin is the voltage on the LOSENSE pin when the high-side FETs are on.
This pin inhibits the drive signals to the MOSFET drivers. The IC is in a low-current state if INHIBIT is grounded. It is
recommended that an external pullup resistor be connected to 5 V.
NGATE-LDO
23
24
Drives external N-channel power MOSFET to regulate LDO voltage to VREF-LDO.
VSEN–LDO
LDO voltage sense. This pin is connected to the LDO output. It is used to sense the LDO voltage for regulation, OVP,
UVP, and power good functions.
PWRGD
IOUT
25
26
Power good. Power good signal goes high when output voltage is above 93% of V
LDO. This is an open-drain output.
for both ripple regulator and
REF
Current signal output. Output voltage on this pin is proportional to the load current as measured across the high-side
FETs on-resistance. The voltage on this pin equals 2 × R
high-side FETs
× IOUT, where R is the equivalent on-resistance of the
ON
ON
OCP
27
28
Overcurrentprotection. CurrentlimittrippointforrippleregulatorissetwitharesistordividerbetweentheIOUTpinand
ANAGND. The trip point is typically 125 mV.
DROOP
Droopvoltage.Voltageinputusedtosettheamountofoutputvoltagedroopasafunctionofloadcurrent.Theamountof
droop compensation is set with a resistor divider between the IOUT pin and ANAGND.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
†
absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)
Supply voltage range, V
(see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
CC
Input voltage range: VDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
BOOT to DRVGND (High-side Driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
BOOT to HIGHDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
BOOTLO to DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 15 V
DRV to DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
BIAS to ANAGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
DROOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
CC
OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
VID0, VID1 (tri-level terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V
BIAS
PWRGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
LOSENSE, LOHIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 14 V
IOUTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V
HISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
VSEN–LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
VSEN–RR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Voltage difference between ANAGND and DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±300 mV
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.
DISSIPATION RATING TABLE
‡
PWP
T
A
< 25°C
DERATING FACTOR
0.0358 W/°C
T
A
= 70°C
T = 85°C
A
PowerPAD mounted
PowerPAD unmounted
3.58 W
1.78 W
1.96 W
0.98 W
1.43 W
0.71 W
0.0178 W/°C
‡
Test Board Conditions:
1.. Thickness: 0.062”
2. 3”× 3”
3. 2 oz. Copper traces located on the top of the board (0.071 mm thick )
4. Copper areas located on the top and bottom of the PCB for soldering
5. Power and ground planes, 1 oz. Copper (0.036 mm thick)
6. Thermal vias, 0.33 mm diameter, 1.5 mm pitch
7. Thermal isolation of power plane
For more information, refer to TI technical brief SLMA002.
JUNCTION-CASE THERMAL RESISTANCE TABLE
Junction-case thermal resistance
0.72 °C/W
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
electrical characteristics T = 0° to 125°C, V
= 2.8 V to 5.5 V (unless otherwise noted)
CC
J
input
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
V
Supply voltage range
Quiescent current
2.8
5.5
V
CC
I
INHIBIT = 0 V,
V
= 5 V
CC
15
mA
CC
NOTE 2: Ensured by design, not production tested.
reference/voltage identification
PARAMETER
TEST CONDITIONS
MIN
– 0.3 V
TYP
MAX
UNITS
VID0–VID1 High-level input voltage (2)
V
V
BIAS
V
V
BIAS
2
BIAS
2
VID0–VID1 Mid-level floating voltage (1)
V
1
1
VID0–VID1 Low-level input voltage (0)
0.3
95
V
Input pull-to-mid resistance
36.5
73
kΩ
cumulative reference
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
V
= 1.3 V,
Hysteresis window = 30 mV,
REF
T = 25°C
–1.3% 0.25% 1.3%
–0.2%
J
V
= 1.3 V,
Hysteresis window = 30 mV,
See Note 2
REF
T = –40°C,
Cumulative accuracy ripple regulator
J
V
= full range,
Hysteresis window = 30 mV,
See Note 2
REF
Droop = 0,
–1.5%
–2%
1.5%
2%
V
= 1.3 V,
I
O
= 0.1 A,
REF
Closed Loop,
T = 25°C,
Pass device = IRFZ24N,
See Note 2
J
Cumulative accuracy LDO
V
= full range,
I
= 0.1 A,
Closed Loop,
See Note 2
REF
Pass device = IRFZ24N,
O
–2.5%
2.5%
NOTE 2. Ensured by design, not production tested.
buffered reference
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
REF
V
REF
+1.5%
I
I
=50 µA,
=50 µA,
Accuracy from V
nominal
nominal
V
REF
REFB
REF
REF
–1.5%
VREFB output voltage
VREFB load regulation
Accuracy from V
See Note 2
REFB
J
V
–0.6%
REF
T = –40°C,
10 µA < I
< 500 µA
2
mV
REFB
NOTE 2. Ensured by design, not production tested.
hysteretic comparator(ripreg)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Input bias current
See Note 2
– V
500
nA
V
= 15 mV,
VHYST
VREFB
Hysteresis window = 30 mV
Hysteresis accuracy
–3.5
3.5
mV
V
– V = 30 mV,
VREFB
See Note 2
VHYST
Maximum hysteresis setting
60
mV
Propagation delay time from VSENSE to HIGHDR or 10 mV overdrive, 1.3 V <= V
<= 3.3 V,
REF
150
5
250
ns
LOWDR (excluding deadtime)
See Note 2
Prefilter pole frequency
See Note 2
MHz
NOTE 2. Ensured by design, not production tested.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
electrical characteristics T = 0° to 125°C, V
= 2.8 V to 5.5 V (unless otherwise noted) (continued)
CC
J
overvoltage protection
PARAMETER
TEST CONDITIONS
Upper threshold
MIN
TYP
MAX UNITS
120 %V
OVP ripple regulator trip point (RR)
112
115
REF
mV
Upper threshold – lower threshold,
(see Note 2)
Hysteresis (RR)
10
1
Comparator propagation delay time (RR)
V
= 30 mV,
= 30 mV,
See Note 2
See Note 2
µs
µs
overdrive
Deglitch time (includes comparator propagation delay time) (RR)
OVP LDO trip point (LDO)
V
2.25
112
11
overdrive
Upper threshold
115
10
1
120 %V
REF
mV
Upper threshold – lower threshold,
(see Note 2)
Hysteresis (LDO)
Comparator propagation delay time (LDO)
V
= 50 mV,
= 50 mV,
See Note 2
See Note 2
µs
µs
overdrive
Deglitch time (includes comparator propagation delay time)
(LDO)
V
2.25
11
overdrive
NOTE 2. Ensured by design, not production tested.
undervoltage protection
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
80 %V
UVP ripple regulator trip point (RR)
Lower threshold
70
75
REF
mV
Upper threshold – lower threshold,
(see Note 2)
Hysteresis (RR)
10
1
Comparator propagation delay time (RR)
V
= 50 mV,
= 50 mV,
See Note 2
See Note 2
µs
overdrive
Deglitch time (includes comparator
propagation delay time) (RR)
V
0.1
70
1
ms
overdrive
UVP LDO trip point (LDO)
Hysteresis (LDO)
Lower threshold
75
10
1
80 %V
REF
Upper threshold – lower threshold,
(see Note 2)
mV
Comparator propagation delay time (LDO)
V
= 50 mV,See Note 2
= 50 mV,See Note 2
µs
overdrive
Deglitch time (includes comparator
propagation delay time) (LDO)
V
0.1
1
ms
overdrive
NOTE 2. Ensured by design, not production tested.
inhibit comparator
PARAMETER
CONDITIONS
MIN
TYP
2.1
MAX UNITS
2.35
V
Start threshold
T = –40°C,
J
See Note 2
2.1
Stop threshold
1.79
V
NOTE 2. Ensured by design, not production tested.
VDRV UVLO
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Start threshold
Hysteresis
See Note 2
4.9
V
V
V
See Note 2
See Note 2
0.3
4.4
0.35
Stop threshold
NOTE 2. Ensured by design, not production tested.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
electrical characteristics T = 0° to 125°C, V
= 2.8 V to 5.5 V (unless otherwise noted) (continued)
CC
J
slow-start
PARAMETER
CONDITIONS
MIN
10.4
3
TYP
MAX UNITS
V
= 0.5 V,
(S/S)
Resistance from VREFB pin to ANAGND = 20 kΩ
VREFB = 1.3 V, Ichg = (I /5)
Charge current
13
15.6
µA
VREFB
= 1.3 V
Discharge current
V
(S/S)
mA
mV
nA
Comparator input offset voltage
Comparator input bias current
Hysteresis accuracy
10
100
See Note 2
10
–7.5
7.5
mV
ns
Comparator propagation delay
Overdrive = 10 mV,
See Note 2
560
1000
NOTE 2. Ensured by design, not production tested.
V
UVLO
CC
PARAMETER
CONDITIONS
MIN
TYP
2.72
2.71
MAX UNITS
(see Note 2)
2.80
V
Start threshold
T = –40°C,
J
See Note 2
Stop threshold
(see Note 2)
2.48
V
NOTE 2. Ensured by design, not production tested.
power good
PARAMETER
CONDITIONS
and VDRV above UVLO thresholds
MIN
TYP
93
MAX UNITS
V
90
95
Undervoltage trip point ripple regulator
(VSENSE–RR)
IN
T = –40°C,
%V
REF
REF
See Note 2
and VDRV above UVLO thresholds
93
J
V
90
93
95
Undervoltage trip point LDO
(VSENSE–LDO)
IN
T = –40°C,
%V
See Note 2
93
J
Output saturation voltage
Leakage current
I
=5 mA
0.5
1
0.75
V
O
V
V
V
= 4.5 V
µA
mV
mV
PGD
REF
REF
= 1.3 V, 1.5 V, or 1.8 V
= 2.5 V, or 3.3 V
50
75
Hysteresis
100
125
Comparator high-low transition time
(propagation delay only)
See Note 2
1
1
µs
Comparator low-high transition time
(propagation delay + deglitch)
See Note 2
0.2
2
ms
NOTE 2. Ensured by design, not production tested.
droop compensation
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
54 mV
Initial accuracy
V
= 50 mV
46
DROOP
overcurrent protection (RR)
PARAMETER
OCP trip point
CONDITIONS
MIN
TYP
MAX UNITS
118
130
142
300
mV
nA
µs
Input bias current
Comparator propagation delay time
V
= 30 mV,
= 30 mV,
See Note 2
See Note 2
1
overdrive
Deglitch time (includes comparator
propagation delay time)
V
2.25
11
µs
overdrive
NOTE 2. Ensured by design, not production tested.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
electrical characteristics T = 0° to 125°C, V
= 2.8 V to 5.5 V (unless otherwise noted) (continued)
CC
J
high-side VDS sensing
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Gain
2
V/V
V
= 3.3 V,
V
= 3.2 V,
HISENSE
Differential input to Vds sensing amp = 100 mV
IOUTLO
Initial accuracy
194
69
208
250
mV
V
V
=2.8 V to 5.5 V,
– V
HISENSE
HISENSE IOUTLO
Common-mode rejection ratio
Sink current (IOUTLO)
75
dB
nA
µA
=100 mV
2.8 V < V
IOUTLO
< 5.5 V
V
V
= 0.5 V,
=2.8 V
V
V
=3.3 V,
IOUT
IOUTLO
HISENSE
Source current (IOUT)
500
50
V
V
= 0.05 V,
=3.3 V
=3.35 V,
IOUT
IOUTLO
HISENSE
Sink current (IOUT)
Output voltage swing
µA
V
V
V
V
V
V
V
V
V
V
V
V
V
=5.5 V,
=4.5 V,
=3 V,
R
R
R
= 10 kΩ
0
0
1.75
1.5
HISENSE
HISENSE
HISENSE
HISENSE
HISENSE
HISENSE
HISENSE
HISENSE
HISENSE
HISENSE =
HISENSE =
HISENSE =
HISENSE =
IOUT
IOUT
IOUT
= 10 kΩ
= 10 kΩ
V
0
0.75
LOSENSE high-level input voltage
LOSENSE low-level input voltage
LOSENSE high-level input voltage
LOSENSE low-level input voltage
LOSENSE high-level input voltage
LOSENSE low-level input voltage
=2.8 V,
=2.8 V,
=4.5 V,
=4.5 V,
=5.5 V,
=5.5 V,
See Note 2
See Note 2
See Note 2
See Note 2
See Note 2
See Note 2
See Note 2
See Note 2
See Note 2
See Note 2
1.77
V
V
V
V
V
V
1.49
2.4
2.85
3.80
3.2
90
6 V,
70
80
4.5 V,
3.6 V,
2.8 V,
100
120
180
Sample/hold resistance
Ω
90
120
V
V
= 2.55 V,
HISENSE
pulsed from 2.55 V to 2.45 V,
4
3.5
3
IOUTLO
100 ns rise and fall times,
See Note 2
V
V
= 2.8 V,
HISENSE
pulsed from 2.8 V to 2.7 V,
IOUTLO
100 ns rise and fall times,
See Note 2
Response time (measured from 90% of
µs
V
to 90% of V
)
IOUTLO
IOUT
V
V
= 4.5 V,
HISENSE
pulsed from 4.5 V to 4.4 V,
IOUTLO
100 ns rise and fall times,
See Note 2
V
V
= 5.5 V,
HISENSE
pulsed from 5.5 V to 5.9 V,
3
IOUTLO
100 ns rise and fall times,
See Note 2
Short circuit protection rising edge delay
Sample/hold switch turnon/turnoff delay
LOSENSE grounded,
See Note 2
300
30
500
100
ns
ns
2.8 V < V
HISENSE
< 5.5 V,
V
= V
,
See Note 2
LOSENSE
HISENSE
NOTE 2. Ensured by design, not production tested.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
electrical characteristics T = 0° to 125°C, V
= 2.8 V to 5.5 V (unless otherwise noted) (continued)
CC
J
thermal shutdown
PARAMETER
CONDITIONS
MIN
TYP
145
10
MAX UNITS
Over temperature trip point
Hysteresis
See Note 2
See Note 2
°C
°C
NOTE 2. Ensured by design, not production tested.
synch charge pump regulator
PARAMETER
CONDITIONS
MIN
200
TYP
300
5.2
MAX UNITS
2.8 V < V < 5.5 V,
VDRV=5 V ,
I
= 50 mA,
IN
DRV
Internal oscillator frequency
400
kHz
See Note 2
See Note 2
See Note 2
Internal oscillator turnon threshold
Internal oscillator turnon hysteresis
V
V
above UVLO threshold,
5.05
V
CC
above UVLO threshold,
20
mV
CC
NOTE 2. Ensured by design, not production tested.
hysteretic comparator (charge pump)
PARAMETER
CONDITIONS
above UVLO threshold,
MIN
TYP
MAX UNITS
Threshold
Hysteresis
V
See Note 2
See Note 2
5.05
5.2
V
IN
IN
V
above UVLO threshold,
20
mV
NOTE 2. Ensured by design, not production tested.
deadtime circuit
PARAMETER
CONDITIONS
MIN
TYP MAX UNITS
LOSENSE/LOHIB high level input voltage
LOSENSE/LOHIB low level input voltage
LOWDR high-level input voltage
V
V
V
V
=2.55 V – 5.5 V, See Note 2
=2.55 V – 5.5 V, See Note 2
2.4
V
HISENSE
HISENSE
HISENSE
HISENSE
1.33
V
V
V
=2.55 V–5.5 V,
=2.55 V–5.5 V,
See Note 2
See Note 2
3
LOWDR low-level input voltage
1.7
C
= 9 nF, 10% threshold on LOWDR,
LOWDR
VDRV=5 V
Driver nonoverlap time
40
170
ns
NOTE 2. Ensured by design, not production tested.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
electrical characteristics T = 0° to 125°C, V
= 2.8 V to 5.5 V (unless otherwise noted) (continued)
J
CC
output drivers (see Note 5)
PARAMETER
CONDITIONS
< 100 us,
MIN
TYP
MAX UNITS
Duty cycle < 2%,
t
pw
V
V
– V
= 4.5 V,
0.7
2
BOOT
BOOTLO
= 4 V (sink),
See Note 2 and Figure 15
< 100 us,
HIGHDR
Duty cycle < 2%,
t
pw
V
V
– V
= 4.5 V,
1.2
1.3
1.4
2
2
2
BOOT
BOOTLO
= 0.5 V (source), See Note 2 and Figure 15
HIGHDR
Peak output current
A
Duty cycle < 2%,
= 4.5 V,
t
V
< 100 µs,
pw
V
DRV
= 4 V (sink),
LOWDR
See Note 2 and Figure 15
Duty cycle < 2%,
t
V
< 100 us,
pw
V
= 4.5 V,
= 0.5 V (source),
DRV
See Note 2 and Figure 15
LOWDR
HIGHDR
HIGHDR
V
– V
= 4.5 V, V
= 0.5 V,
= 4 V,
BOOT
BOOTLO
– V
BOOTLO
5
See Note 2
V
= 4.5 V, V
BOOT
See Note 2
45
Output resistance
Ω
V
V
= 4.5 V,
V
V
V
= 0.5 V, See Note 2
9
DRV
LOWDR
= 4.5 V,
= 4 V,
See Note 2
45
DRV
LOWDR
C
= 3.3 nF,
= 4.5 V,
L
BOOT
HIGHDR rise/fall time
LOWDR rise/fall time
60
40
10
ns
ns
µA
V
=grounded,
See Note 2
See Note 2
BOOTLO
C
= 3.3 nF,
V
DRV
= 4.5 V,
L
INHIBIT grounded,
BOOTLO grounded
V
IN
< UVLO, V
=6 V,
BOOT
INHIBIT connected to +5 V,
= 200 kHz,
BOOTLO = 0,
See Note 2
V
V
C
> UVLO
= 5.5 V,
= 50 pF,
HIGHDR
IN
BOOT
High-side driver quiescent current
f
(swx)
2
mA
NOTES: 2. Ensured by design, not production tested.
5. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the R
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
of the MOSFET transistor when
ds(on)
LDO N-channel output driver
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
V
V
= 7.5 V,
= 0.9 × V
V
= 3 V (source),
LDODRV
IOSENSE
N–DRV
See Note 2
100
1.5
µA
,
LDOREF
Peak output current
V
V
= 7.5 V,
= 1.1 × V
V
=0 V (sink),
LDODRV
IOSENSE
N–DRV
mA
,
See Note 2
LDOREF
Open loop voltage gain
7.5 V ≥ V
See Note 2
≥ 0.5 V,
V
IN
= 5.5 V,
3000
(70)
V/V
(dB)
NGATE–LDO
(V
/ V
)
NGATE–LDO SENSE–LDO
f = 1 kHz,
C
=10 µF,
O
5.5 V ≥ V ≥ 2.55 V,
T =125 °C,
J
Power supply ripple rejection
60
dB
IN
See Note 2
NOTE 2. Ensured by design, not production tested.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
electrical characteristics T = 0° to 125°C, V
= 2.8 V to 5.5 V (unless otherwise noted) (continued)
CC
J
V
and V
discharge
SENSE–RR
SENSE–LDO
PARAMETER
CONDITIONS
= 1.5 V, See Note 2
= 5.5 V
MIN
TYP
5
MAX UNITS
V
discharge FET current saturation
V
mA
SENSE–RR
SENSE–RR
SENSE–RR
SENSE–LDO
SENSE–LDO
SENSE–LDO
SENSE–RR
V
discharge series resistance (limits current)
discharge FET propagation delay time
INHIBIT = 0 V,
See Note 2
V
IN
1
kΩ
V
V
V
V
100
100
ns
mA
kΩ
ns
discharge FET current saturation
V
= 3.3 V,
See Note 2
= 5.5 V,
5
1
SENSE–LDO
discharge series resistance (limits current)
discharge FET propagation delay time
INHIBIT = 0 V,
See Note 2
V
IN
NOTE 2. Ensured by design, not production tested.
detailed description
reference/voltage identification
The reference/voltage identification definition (VID) section consists of a temperature compensated bandgap
reference and a 2-pin voltage selection network. Both ripple regulator and LDO reference voltages are
programmedwitheachVIDsetting. The2VIDpinsareinputstotheVIDselectionnetworkandaretri-levelinputs
that may be set to GND, floating (V
/2), or V
. The VID codes allow the controller to power both current
BIAS
BIAS
and future DSP products. The output voltages may also be programmed by external resistor voltage dividers
for any values not included in the VID code settings. Refer to Table 1 for the VID code settings. The output
voltages of the VID network, V
, is within 1.5% and V
is within 2.5% of the nominal setting over
REF–RR
REF–LDO
the VID range of 1.3 V to 3.3 V. The reference tolerance conditions include a junction temperature range of
–40 C to +125 C and a V supply voltage range of 2.8 V to 5.5 V. The V output of the reference/VID
CC
REF–RR
network is indirectly brought out through a buffer to the VREFB pin. The voltage on this pin will be within 1.5%
ofV . ItisnotrecommendedtodriveloadswithVREFB, otherthansettingthehysteresisofthehysteretic
REF–RR
comparator, becausethecurrentdrawnfromVREFBsetsthechargingcurrentfortheslow-startcapacitor. Refer
to the slow-start section of this document for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered around V
. The two external resistors form a resistor divider from
REF
VREFB to ANAGND, and the divided down voltage connects to the VHYST pin. The hysteresis of the
comparator will be equal to twice the voltage difference that is across the VREFB and VHYST pins. The
propagation delay from the comparator inputs to the driver outputs is 250 ns maximum. The maximum
hysteresis setting is 60 mV.
low-side driver
The low-side driver is designed to drive low r
logic-level N-channel MOSFETs. The current rating of the
DS(on)
driver is 2-A typical, source and sink. The bias to the low-side driver is internally connected to the regulated
synchronous charge pump output.
high-side driver
The high-side driver is designed to drive low r
logic-level N-channel MOSFETs. The current rating of the
DS(on)
driver is 2 amps typical, source and sink. The high-side driver can be configured either as a floating bootstrap
driver or as a ground-reference driver. When configured as a floating driver, the bias voltage to the driver is
developed from the charge pump VDRV voltage. The internal synchronous bootstrap rectifier, connected
between the VDRV and BOOT pins, is a synchronously-rectified MOSFET for improved drive efficiency. The
maximum voltage that can be applied between the BOOT pin and ground is 14 V.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
detailed description (continued)
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon time of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate drive voltage to the low-side FET is below 1 V, and the low-side driver is not allowed
to turn on until the voltage at the junction of the 2 FETs (Vphase) is below 2 V.
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FET while the
high-side FET is on. The sampling network consists of an internal 60-Ω switch and an external hold capacitor.
Internal logic controls the turnon and turnoff of the sample/hold switch such that the switch does not turn on until
the Vphase voltage transitions high, and the switch turns off when the input to the high-side driver goes low.
Thus sampling will occur only when the high-side FET is conducting current. The voltage on the IOUT pin equals
2 times the sensed high-side voltage.
droop compensation
The droop compensation network reduces the load transient overshoot / undershoot on V
, relative to V
REF
OUT
(see the application information section of this document for more details). V
is programmed to a voltage
OUT
greater than V
by an external resistor divider from V
to the VSENSE pin to reduce the undershoot on
REF
OUT
V
during a low to high load transient. The overshoot during a high to low load transient is reduced by
OUT
subtracting the voltage that is on the DROOP pin from V
. The voltage on the IOUT pin is divided down with
REF
an external resistor divider, and connected to the DROOP pin.
inhibit
INHIBIT is a TTL-compatible comparator pin that is used to enable the controller. When INHIBIT is lower than
the threshold, the output drivers are low and the slow-start capacitor is discharged. When INHIBIT goes high
(above 2.1 V), the short across the slow-start capacitor is released and normal converter operation begins.
When another system logic supply is connected to the INHIBIT pin, this pin controls power sequencing by
locking out controller operation until the system logic supply exceeds the input threshold voltage of the inhibit
circuit; thus the +3.3-V supply and another system logic supply (either +5 V or +12 V) must be above UVLO
thresholds before the controller is allowed to start up. Toggling the INHIBIT pin from low to high or recycling V
clears the fault latch.
CC
slow-start
The slow-start circuit controls the rate at which both V
and V
power up (at the same time). A
OUT–RR
OUT–LDO
capacitor is connected between the SLOWST and ANAGND pins and is charged by an internal current source.
The value of the current source is proportional to the reference voltage, so that the charging rate of C
SLOWST
is proportional to the ripple regulator reference voltage. The slow-start charging current is determined by the
following equation:
I
VREFB
I
SLOWSTART
5
Where I
is the current flowing out of the VREFB pin. It is recommended that no additional loads be
VREFB
connectedtoVREFB, otherthantheresistordividerforsettingthehysteresisvoltage. Thustheseresistorvalues
will determine the slow-start charging current. The maximum current that can be sourced by the VREFB circuit
is 500 µA. The equation for the slow-start time is:
T
5
C
R
SLOWSTART
SLOWSTART
VREFB
Where R
is the total external resistance from VREFB to ANAGND.
VREFB
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
detailed description (continued)
V
and VDRV undervoltage lockout
CC
The V
undervoltage lockout circuit disables the controller while the V
supply is below the 2.8-V start
CC
CC
threshold. The VDRV undervoltage lockout circuit disables the controller while the VDRV supply is below the
4.9 V start threshold during powerup. While the controller is disabled, the output drivers will be low, the LDO
drive is off, and the slow-start capacitor will be shorted. When V
short across the slow-start capacitor is released and normal converter operation begins. Recycling V
toggling the INHIBIT pin from low to high clears the fault latch.
and VDRV exceed the start threshold, the
CC
or
CC
power good
The power good circuit monitors for an undervoltage condition on V
and V
. The power good
OUT–RR
OUT–LDO
(PWRGD) pin is pulled low if either V
is 7% below V
, or V
is 7% below V
.
OUT–RR
REF–RR
OUT–LDO
REF–LDO
PWRGD is an open drain output. The PWRGD pin is also pulled down, if either V
UVLO thresholds.
or VDRV are below their
CC
overvoltage protection
The overvoltage protection circuit monitors V
and V
for an overvoltage condition. If V
OUT–RR
OUT–LDO OUT–RR
or V
are 15% above their reference voltage, then a fault latch is set and both output drivers and LDO
OUT–LDO
are turned off. The latch remains set until the V or inhibit voltages go below their undervoltage lockout turnoff
CC
values. A 1-µs to 5 µs deglitch timer is included for noise immunity.
overcurrent protection
The overcurrent protection circuit monitors the current through the high-side FET. The overcurrent threshold
is adjustable with an external resistor divider between IOUT and ANAGND pins, with the divider voltage
connected to the OCP pin. If the voltage on the OCP pin exceeds 125 mV, a fault latch is then set and the output
drivers are turned off. The latch remains set until the V or inhibit voltages go below their undervoltage lockout
CC
values. A 1-µs to 5-µs deglitch timer is included for noise immunity. The OCP circuit is also designed to protect
the high-side power FET against a short-to-ground fault on the terminal common to both power FETs.
undervoltage protection
TheundervoltageprotectioncircuitmonitorsV
andV
foranundervoltagecondition.IfV
OUT–RR
OUT–LDO OUT–RR
or V
is 15% below their reference voltage, then a fault latch is set and both output drivers and LDO are
OUT–LDO
turned off. The latch remains set until the V
or inhibit voltages go below their undervoltage lockout values.
CC
A 100-µs to 1-ms deglitch timer is included for noise immunity.
synchronous charge pump
The regulated synchronous charge pump provides drive voltage to the low-side driver at VDRV (5 V), and to
the high-side driver configured as a floating driver. The minimum drive voltage is 4.5 V, (typical is 5 V). The
minimum short-circuit current is 80 mA. The bootstrap capacitor is used to provide voltage for the high-side FET,
the power for VLDODRV, and the bias regulator. Instead of diodes, synchronous rectified MOSFETs are used
to reduce voltage drop losses and allow a lower input voltage threshold. The charge pump oscillator operates
at 300 kHz until the UVLO VDRV is set; after which it is synchronized to the converter switching frequency and
is turned on and off to regulate VDRV at 5 V.
The charge pump is designed to operate at a switching frequency of 200 kHz to 400 kHz. Operation at low
frequency may require larger capacitors on the CPCx and VDRV pins. Higher frequencies (> 400 kHz) may not
be possible.
power sequence
The V
voltage is powered up with respect to the same slow-start reference voltage as the V
OUT–RR
OUT–LDO
Also, at power down, the V
series with 1-kΩ resistors.
and V
are discharged to ground through P-channel MOSFETs in
OUT–RR
OUT–LDO
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
vs
V
UVLO HYSTERESIS
vs
CC
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
13
12
11
10
180
175
170
165
160
155
150
V
= 3.3 V
CC
INHIBIT = 0 V
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 1
Figure 2
V
UVLO START THRESHOLD VOLTAGE
SLOW-START CHARGE CURRENT
vs
CC
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.750
2.725
2.700
2.675
2.65
15
14
13
12
11
10
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 3
Figure 4
15
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
TYPICAL CHARACTERISTICS
†
SLOW-START TIME
vs
SUPPLY CURRENT (VREFB)
SLOW-START TIME
vs
SLOW-START CAPACITANCE
1000
100
100
10
V
V
= 3.3 V
= 1.3 V
= 0.1 µF
CC
(VREFB)
V
V
= 3.3 V
CC
= 1.3 V
(VREFB)
(VREFB)
J
C
S
J
I
T
= 65 µA
T
= 27°C
= 25°C
10
1
1
0.1
0.0001
1
10
100
1000
0.0010
0.0100
0.1000
1
I
– Supply Current (VREFB) – µA
CC
Slow-start Capacitance – µF
Figure 5
Figure 6
DRIVER
RISE TIME
DRIVER
FALL TIME
vs
vs
GATE CAPACITANCE
GATE CAPACITANCE
1000
100
1000
T
J
= 27°C
T = 27°C
J
100
High Side
High Side
Low Side
Low Side
10
10
1
0.1
1
0.1
1
10
100
1
10
100
Gate Capacitance – nF
Gate Capacitance – nF
Figure 7
Figure 8
16
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
TYPICAL CHARACTERISTICS
DRIVER
DRIVER
HIGH-SIDE OUTPUT RESISTANCE
vs
LOW-SIDE OUTPUT RESISTANCE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
8
7
6
5
4
3
2
1
0
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 9
Figure 10
DRIVER
CURRENT
vs
VDRV UVLO START THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
OUTPUT VOLTAGE
5
4.5
4
4.70
4.69
4.68
4.67
4.66
4.65
3.5
3
2.5
2
2 A Typical
1.5
1
4.5 V
0.5
0
0
1
2
3
4
5
6
7
8
9
0
25
50
75
100
125
V
O
– Output Voltage – V
T
J
– Junction Temperature – °C
Figure 11
Figure 12
17
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
TYPICAL CHARACTERISTICS
RIPPLE REGULATOR
POWER GOOD THRESHOLD
vs
VDRV UVLO HYSTERESIS
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
300
280
260
240
220
200
180
160
140
120
100
96
95
94
93
92
91
90
89
88
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 13
Figure 14
INHIBIT START THRESHOLD VOLTAGE
INHIBIT HYSTERESIS VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.100
2.075
2.050
2.025
2.000
140
130
120
110
100
90
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 15
Figure 16
18
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
TYPICAL CHARACTERISTICS
RIPPLE REGULATOR OVP THRESHOLD
RIPPLE REGULATOR UVP THRESHOLD
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
118
117
116
115
77
76
75
74
114
113
112
73
72
71
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 17
Figure 18
OCP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
135
133
131
129
0
25
50
75
100
125
T
J
– Junction Temperature – °C
Figure 19
19
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
TYPICAL CHARACTERISTICS
LDO OVP THRESHOLD
vs
JUNCTION TEMPERATURE
118
117
116
115
114
113
112
0
25
50
75
100
125
T
J
– Junction Temperature – °C
Figure 20
LDO UVP THRESHOLD
vs
JUNCTION TEMPERATURE
77
76
75
74
73
72
71
0
25
50
75
100
125
T
J
– Junction Temperature – °C
Figure 21
20
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
APPLICATION INFORMATION
evaluation module
In many DSP applications, the voltage bus powering DSP I/O also has to power peripheral circuitry. The total
current is much higher than the requirement for the I/O only. This is the reason to use the high-efficiency ripple
regulator to power I/O. In turn, the core power is delivered by LDO output. Since the I/O voltage is lower than
the input voltage in cases such as 5-V input, but higher than the core voltage, the ripple regulator output should
be used as the input voltage for LDO to achieve higher efficiency. In EVM testing, J1–4 (RR–OUT) is connected
to J2–1(VI–LDO). The test results displayed in this section are all based on this configuration.
TP6
FB2
+
J2
TP5
+
JP3
L1
R17
3.3 uH
+
TP8
TP7
Q1:A
J1
Q4
TP1
TP11
E1
TP3
U1
TPS563xxPWP
TP4
TP2 Q1:B
+
+
+
Q5
+
TP10
FB1
JP1
JP2
†
When an output current greater than 4 A is desired on the ripple regulator, please add a 10 Ω resistor (R17) between pin 18 and Q1:A.
Because the EVM is configured for 4 A and below, R17 is 0 Ω and is not included on the module.
Figure 22. EVM Schematic
Table 2. EVM Input and Outputs
V
IN
5 V
I
V
RR
3.3 V
I
V
LDO
1.8 V
I
IN
4 A
RR
4 A
LDO
0.5 A
21
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
APPLICATION INFORMATION
Table 3. Ripple Regulator Power Stage Components
Ripple Regulator Section
†
†
†
Ref Des
Function
Input bulk
4A (EVM Design)
C3: open
8A
12A
20A
C3, C6
C3: 150 µF
C3: 150 µF
C3: 150 µF
capacitor
C6: 150 µF
(Sanyo,
C6: 150 µF
(Sanyo,
C6: 150 µF
(Sanyo,
C6: 2x150 µF
(Sanyo,
6TPB150M)
6TPB150M)
6TPB150M)
6TPB150M)
C11, C2
Input high-freq
capacitor
C2: 0.1 µF
C11: 0.1 µF
(muRata
C2: 0.1 µF
C11: 0.1 µF
(muRata
C2: 0.1 µF
C11: 0.1 µF
(muRata
C2: 0.33 µF
C11: 0.33 µF
(muRata
GRM39X7R104K016A,
0.1 µF, 16–V, X7R)
GRM39X7R104K016A,
0.1 µF, 16–V, X7R)
GRM39X7R104K016A, 0.1 GRM39X7R334K016A,
µF, 16–V, X7R)
0.33 µF, 16–V, X7R)
C13, C14 Output bulk
capacitor
C13: 150 µF
(Sanyo, 6TPB150M)
C14: open
C13: 150 µF
(Sanyo, 6TPB150M)
C14: open
C13: 150 µF
C14: 150 µF
(Sanyo, 6TPB150M)
C13: 150 µF
C14: 150 µF
(Sanyo, 6TPB150M)
C15,C30, Output mid-freq C15: open
C15: open
C30: 10 µF
C31: 10 µF
(muRata
C15: 10 µF
C30: 10 µF
C31: 10 µF
(muRata
C15: 10 µF
C30: 10 µF
C31: 10 µF
(muRata
C31
capacitor
C30: 10 µF
C31: 10 µF
(muRata
GRM39X7R106K016A,
10 µF, 16–V, X7R)
GRM39X7R106K016A,
10 µF, 16–V, X7R)
GRM39X7R106K016A, 10 GRM39X7R106K016A,
µF, 16–V, X7R)
10 µF, 16–V, X7R)
C16
Output high-freq open
capacitor
0.1 µF
(muRata
0.1 µF
(muRata
0.1 µF
(muRata
GRM39X7R104K016A,
0.1 µF, 16–V, X7R)
GRM39X7R104K016A, 0.1 GRM39X7R104K016A,
µF, 16–V, X7R)
0.1 µF, 16–V, X7R)
L1
L2
Input filter
3.3 µH
Coilcraft
DO3316P–332, 5.4 A
3.3 µH
Coilcraft
DO3316P–332,5.4 A
1.5 µH
Coilcraft
DO3316P–152,6.4 A
1 µH
Coiltronics
UP3B–1R0, 12.5–A
Output filter
3.3 µH
3.3 µH
1.5 µH
3.3 µH
Coilcraft
DO3316P–332, 5.4 A
Coilcraft
Coilcraft
Micrometals,
T68–8/90 Core w/7T,
#16, 25 A
DO5022P–332HC, 10 A DO5022P–152HC,
15 A
R8
Low side gate
resistor
10 Ω
10 Ω
5.1 Ω
5.1 Ω
Q1A,Q4
Q1B,Q5
Power switch
Q1A: Dual FET
IRF7311
Q4: IRF7811
Q5: IRF7811
Q4: 2xIRF7811
Q5: 2xIRF7811
Q4: 2xIRF7811
Synchronous
switch
Q1B: Dual FET
IRF7311
Q5:
2xIRF7811
†
Position available on the EVM board
The values listed in Table 3 are recommendations based on actual test circuits. Many variations of the above
are possible based upon the desires and/or requirements of the user. Performance of the circuit is equally, if
not more, dependent upon the layout than on the specific components, as long as the device parameters are
not exceeded. Fast-response, low-noise circuits require circuits require critical attention to the layout details.
22
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
APPLICATION INFORMATION
Table 4. LDO Power Stage Components
LDO Section
Ref. Des
Q2:A
Part
V
IN
V
Description
OUT
†
IRF7811(EVM)
or
Si4410, IRF7413
FDS6680
V
IN
V
– V
Used as a power distribution switch for
LDO output control
IN DROPOUT
‡
‡
IRF9410, Si9410
Low cost solution for low LDO output cur-
Q2:A
Q2:A
Q2: B
rent (V –V
)*I
< 1 W
IN OUT OUT
‡
IRF7811
Higher current and still surface mount
1 W < (V –V )*I ) < 2 W
IN OUT OUT
‡
IRLZ24N
High output current requiring heat sink.
Low cost but through–hole package.
(V –V > 2 W
)*I
IN OUT OUT
†
‡
V
= I
× RDSON. It should be as small as possible.
DROPOUT OUT
Position available on the EVM board
frequency calculation
With hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the
hysteresis window, the delay of the hysteresis comparator and the driver, the output inductance, the resistance
in the output inductor, the output capacitance, the ESR and ESL in the output capacitor, the output current, and
the turnon resistance of high-side and low-side MOSFET. It is a very complex equation if everything is included.
To make it more useful to designers, a simplified equation is developed that considers only the most influential
factors. The tolerance of the result for this equation is about 30%:
–9
250 10
C
T
d
V
V
V
ESR
OUT
IN
OUT
out
f
s
–9
V
V
ESR
250 10
T
d
V
L
ESL
V
IN
IN
hys
OUT
IN
Where f is the switching frequency (Hz); V
theoutputcapacitance;ESRistheequivalentseriesresistanceintheoutputcapacitor(Ω);ESListheequivalent
is the output voltage (V); V is the input voltage (V); C is
OUT
IN
s
OUT
series inductance in the output capacitor (H); L
is the output inductance (H); T is output feedback RC filter
OUT
d
time constant (S); V
is the hysteresis window (V).
hys
output voltage setpoint calculation
In some applications, the required output voltage is different from the VID reference voltage. In this case,
external voltage divider can be used for the setpoint adjustment. The voltage divider is composed of two
resistors. The equation for the setpoint is:
R
V
top
R
R
bottom
V
V
O
R
Where V is the reference voltage; V is the required output voltage setpoint. V should be lower than V . In
R
O
R
O
EVM design, the top resistor is R14 for the LDO output, or R10 for ripple regular output; the bottom resistor is
R15 for LDO output, or R12 for ripple regulator output.
23
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
APPLICATION INFORMATION
hysteresis window
The changeable hysteresis window in TPS56302 is used for switching frequency and output voltage ripple
adjustment. The hysteresis window setup is decided by a two-resistor voltage divider on VREFB and VHYST
pin. Two times the voltage drop on the top resistor is the hysteresis window. The formula is shown in the
following:
R13
= 2 × VREFB× (1 –
)
V
hyswindow
R11 + R13
Where V
is the hysteresis window (V); VREFB is the regulated voltage from VREVB (pin 5); R11 is the
hyswindow
top resistor in the voltage divider; R13 is the bottom resistor in the voltage divider. The maximum hysteresis
window is 60 mV.
slow-start
Slow-start reduces the start-up stresses on the power-stage components and reduces the input current surge.
The minimum slow-start time is limited to 1 ms due to the power good function deglitch time. Slow-start timing
is dependent on the timing capacitor value on the slow-start pin and the total resistance on VREFB. The
following formula can be used for setting the slow-start timing:
T
5
C
R
SLOW-START
SLOW-START
VREFB
isthecapacitorvalueonSLOWST(pin3).R isthetotal
VREFB
T
istheslow-starttime;C
SLOW-START
resistance on VREFB (pin 5).
SLOW-START
current limit
Current limit is implemented using the on-resistance of the upper FETs as the sensing elements. The IOUT
signal is used for the current limit and the droop function. The voltage at IOUT at the output current trip point
will be:
V
R
I
2
IOUT
ON
O
R
is the high-side on-time resistance; I is the output current. The current limit is calculated by using the
ON
O
equation:
R4
I
2
R
0.125
ON
O MAX
R5
0.125
Where R4 is the bottom resistor in the voltage divider on OCP pin, and R5 is the top resistor; I
is the
O(MAX)
maximum current allowed; R
is the high-side FET on-time resistance.
ON
Since the FET on-time resistance varies according to temperature, the current limit is basically for catastrophic
failure.
24
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
APPLICATION INFORMATION
droop compensation
DroopcompensationwiththeoffsetresistordividerfromV
totheVSENSEisusedtokeeptheoutputvoltage
OUT
in range during load transients by increasing the output voltage setpoint toward the upper tolerance limit during
light loads and decreasing the voltage setpoint toward the lower tolerance limit during heavy loads. This allows
the output voltage to swing a greater amount and still remain within the tolerance window. The maximum droop
voltage is set with R6 and R7:
R6
R6 R7
V
V
DROOP max
IOUT max
Where V
is the maximum droop voltage; V
is the maximum V that reflects the
IOUT
DROOP(max)
IOUT(max)
maximum output current (full load); R6 is the bottom resistor of the divider connected to the DROOP pin, R7
is the top resistor.
The offset voltage is set to be half of the maximum droop voltage higher than the nominal output voltage, so
the whole droop voltage range is symmetrical to the nominal output voltage. The formula for setting the offset
voltage is:
1
2
R12
R10 R12
V
V
V
OFFSET
DROOP max
O
Where V
is the desired offset voltage; V
is the droop voltage at full load; V is the nominal
O
OFFSET
DROOP(max)
output voltage; R10 is the top resistor of the offset resistor divider, and R12 is the bottom one.
Therefore, with the setup above, at light load, the output voltage is:
1
V
V
V
V
V
O nom
OFFSET
O nom
DROOP
V
O NO LOAD
2
And, at full load, the output voltage is:
1
2
V
V
V
V
O nom
OFFSET
O nom
DROOP
O FULL LOAD
output inductor ripple current
The output inductor current ripple can affect not only the efficiency, but also the output voltage ripple. The
equation for calculating the inductor current ripple is exhibited in the following:
V
V
I
r
R
IN
OUT
OUT
L
DS(on)
L
I
D
Ts
ripple
OUT
Where I
output voltage (V); I
is the peak-to-peak ripple current (A) through the inductor; V is the input voltage (V); V
is the
ripple
IN
OUT
is the output current; r
is the on-time resistance of MOSFET (Ω); R is the output
OUT
DS(on) L
inductor equivalent series resistance; D is the duty cycle; and Ts is the switch cycle (S). From the equation, it
can be seen that the current ripple can be adjusted by changing the output inductor value.
Example:
V
IN
= 5 V; V
= 1.8 V; I
= 5 A; r
= 10 mΩ; R = 5 mΩ; D = 0.36; Ts = 5 µs; L
= 6 µH
OUT
OUT
DS(on)
L
OUT
Then, the ripple I
= 1 A.
ripple
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
APPLICATION INFORMATION
output capacitor RMS current
Assuming the inductor ripple current totally goes through the output capacitor to ground, the RMS current in the
output capacitor can be calculated as:
∆I
I
=
O(rms)
12
Where I
current (A).
is the maximum RMS current in the output capacitor (A); ∆I is the peak-to-peak inductor ripple
O(rms)
Example:
∆I = 1 A, so IO(rms) = 0.29 A
input capacitor RMS current
The input capacitor RMS current is important for input capacitor design. Assuming the input ripple current totally
goes into the input capacitor to the power ground, the RMS current in the input capacitor can be calculated as:
2
2
1
12
(
)
D
I
I
D
1
D
I
I(rms)
O
ripple
Where I
is the input RMS current in the input capacitor (A); I is the output current (A); I
is the
I(rms)
O
ripple
peak-to-peak output inductor ripple current; D is the duty cycle. From the equation, it can be seen that the
highest input RMS current usually occurs at the lowest input voltage, so it is the worst case design for input
capacitor ripple current.
Example:
I
= 5 A; D = 0.36; I
= 1 A,
ripple
O
Then, I
= 2.46 A
I(rms)
layout and component value consideration
Good power supply results will only occur when care is given to proper design and layout. Layout and
component value will affect noise pickup and generation and can cause a good design to perform with less than
expected results. With a range of current from milliamps to tens or even hundreds of amps, good power supply
layout and component selection, especially for a fast ripple controller, is much more difficult than most general
PCB design. The general design should proceed from the switching node to the output, then back to the driver
section, and, finally, to placing the low-level components. In the following list are several specific points to
consider before layout and component selection for TPS56302:
1. All sensitive analog components should be referenced to ANAGND. These include components connected
to SLOWST, DROOP, IOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and LOSENSE/LOHIB.
2. The input voltage range for TPS56302 is low from 2.8-V to 5.5-V, so it has a voltage tripler (charge pump)
inside to deliver proper voltage for internal circuitry. To avoid any possible noise coupling, a low ESR
capacitor on V
is recommended.
CC
3. For the same reason in Item 2, the ANAGND and DRVGND should be connected as close as possible to
the IC.
4. The bypass capacitor should be placed close to the TPS56302.
26
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
APPLICATION INFORMATION
layout and component value consideration (continued)
5. When configuring the high-side driver as a boot-strap driver, the connection from BOOTLO to the power
FETs should be as short and as wide as possible. LOSENSE/LOHIB should have a separate connection
to the FETs since BOOTLO will have large peak current flowing through it.
6. The bulk storage capacitors across V should be placed close to the power FETs. High-frequency bypass
IN
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
7. HISENSE and LOSENSE/LOHIB should be connected very close to the drain and source, respectively, of
the high-side FET. HISENSE and LOSENSE/LOHIB should be routed very close to each other to minimize
differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to
where HISENSE connects to V , to reduce high-frequency noise coupling on HISENSE.
IN
The EVM board (SLVP-139) is used in the test. The test results are shown in the following.
EFFICIENCY OF
RIPPLE REGULATOR
RIPPLE REGULATOR (3.3 V)
LOAD REGULATION (3.3 V)
100
2
V
IN
= 5 V
V
IN
= 5 V
90
80
70
1
0
60
50
40
–1
–2
0
1
2
3
4
5
0
1
2
3
4
5
I
O
– Output Current – A
I
O
– Output Current – A
Figure 23
Figure 24
27
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
APPLICATION INFORMATION
RIPPLE REGULATOR
LINE REGULATION (3.3 V)
LDO LOAD REGULATION (1.8 V)
2
2
I
O
= 2 A
V
IN
= 5 V
1
0
1
0
–1
–2
–1
–2
3
3.5
4
4.5
5
5.5
6
0
0.2
0.4
I – Output Current – A
O
0.6
0.8
1
1.2
V
IN
– Input Voltage – V
Figure 25
Figure 26
SLOW-START
DROOP COMPENSATION EFFECT
6
10
5
4
5
0
3.3 V
3
2
No Droop
280 mV
–5
1
0
Output Voltage
200
1.8 V
100
0
220 mV
–1
–2
With Droop
–100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
4
8
12 16 20 24 28 32 36 40
t – Time – ms
t – Time – ms
Figure 27
Figure 28
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
APPLICATION INFORMATION
layouts
2.7 in
Figure 29. Top Layer
Figure 30. Bottom Layer (Top View)
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
APPLICATION INFORMATION
bill of materials
REF
PN
Description
MFG
Size
C1
10TPA33M
Std
Capacitor, POSCAP, 33 µF, 10 V
Capacitor, Ceramic, 10 µF, 16 V
Capacitor, POSCAP, 150 µF, 6 V
Capacitor, Ceramic, 0.1 µF, 16 V
Capacitor, Ceramic, 1 µF, 16 V
Open
Sanyo
Sanyo
Sanyo
Sanyo
Sanyo
C
C2, C20, C21, C30, C31
1210
D
C3. C6, C8, C13, C25
6TPB150M
Std
C4, C5, C11, C12, C23, C26, C27,
603
C7, C22
C9
Std
805
Std
1210
603
C10, C16
C14, C15
C17, C24
C18, C19
D1
Std
Open
Std
Open
D
Std
Capacitor, Ceramic, 1000 pF, 16 V
Capacitor, Ceramic, 1 µF, 16 V
Diode, LED, Green, 2.1 V SM
Inductor, 3.3 µH, 5.4 A
Sanyo
Sanyo
Lumwx
Coilcraft
OST
603
Std
805
SML-LX2832G
DO3316P-332
ED2227
ED1515
S1132-3-ND
1210
0.5 × 0.37 in
5.08 mm
n, 6 A,
#S1132-3-ND
L1, L2
J1
Terminal Block, 4-pin, 15 A, 5.08 mm
Terminal Block, 3-pin, 6 A, 3.5 mm
J2
OST
JP1, JP2
Header, Right straight, 3-pin, 0.1 ctrs,
Sullins
0.3” pins
JP1shunt
J3
929950-00-ND
S1132-2-ND
Shunt jumper, 0.1” (for JP1)
3M
0.1”
Header, Right straight, 2-pin, 0.1 ctrs,
0.3” pins
Sullins
#S1132-2-ND
Q1
Open
SO-8
SO-8
TO–220
TO-236
603
Q2:A, Q4, Q5
Q2:B
Q3
IRF7811
MOSFET, N-ch, 30 V, 10 mΩ
Open
2N7002DICT-N
MOSFET, N-ch, 115 mA, 1.2 Ω
Resistor, 10 kohms, 5 %
Resistor, 1 kohms, 1%
Resistor, 0 ohms, 1%
Resistor, 1 kohms, 1%
Resistor, 3.32 kohms, 1%
Resistor, 10 ohms, 5 %
Resistor, 2.7 ohms, 5 %
Resistor, 150 ohms, 5 %
Resistor, 100 ohms, 1 %
Resistor, 10 kohms, 5 %
Resistor, 20.0 kohms, 1 %
Resistor, 0 ohms, 5%
Resistor, open
Diodes, Inc.
R3
std
R4
std
603
R5
std
603
R6
std
603
R7
std
603
R8
std
603
R9
std
1206
603
R10
R11
std
std
603
R12
R13
R14
R15
R16
TP1–TP10
TP11
std
603
std
603
std
603
std
603
std
Resistor, 15 kohms, 5 %
Test Point, Red
805
240–345
131–4244–00
Farnell
Adaptor, 3.5-mm probe clip
Tektronix
(or 131–5031–00)
U1
TPS56302PWP
Dual controller
TSSOP–28pin
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
APPLICATION INFORMATION
Power Supply
+
Load
0 – 4 A
5–V, 5–A Supply
–
–
+
6.8 Ohms
2 W
Jumper Pins 2–3
NOTE A: All wire pairs should be twisted.
Figure 31. Test Setup
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
APPLICATION INFORMATION
DSP power application
In DSP power applications, TPS56302 is used in the applications that require more current for peripheral and
DSP I/O. The power good (PG) output can be used for monitoring or controlling as an optional function. In the
EVM schematic, Q3, D1, R1, and R2 are the circuit to show this function.
RR
LDO
Output
Output
Ripple
Regulator
V
IN
LDO
Core
DSP
I/O
Peripheral
PG output (optional)
Figure 32. TPS56302 For High Peripheral Current DSP Application
TPS56300is used in the applications that require high current for core, but low current for I/O. Another important
feature is that, if the input voltage is the same as the LDO output, the LDO switch acts as a distribution switch
to control the on/off of the LDO output.
RR Output
Ripple
Regulator
V
IN
Core
DSP
LDO Output
I/O
LDO
PG output (optional)
Figure 33. TPS56300 For On/Off Control DSP Application
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A – MARCH 2000 – REVISED OCTOBER 2000
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
20-PIN SHOWN
0,30
0,19
11
0,65
20
M
0,10
Thermal Pad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°–8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/E 03/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. Thepackagethermalperformancemaybeenhancedbybondingthethermalpadtoanexternalthermalplane.Thispadiselectrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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