RD-19230FX-303 [ETC]
Resolver-to-Digital Converter ; 分解器数字转换器\n
| 型号： | RD-19230FX-303 |
| 厂家： | 
ETC |
| 描述： | Resolver-to-Digital Converter
|
| 文件： | 总20页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RD-19230
16-BIT MONOLITHIC TRACKING
RESOLVER-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
The RD-19230 is a versatile, low cost, range of 4 V relative to analog ground.
state-of-the-art 16-bit monolithic Resolver- The velocity scale factor/tracking rate is
to-Digital Converter. This single chip con- programmed with a single resistor. This
verter offers programmable features such converter provides the option of using a
as resolution, bandwidth, velocity output second set of filter components which can
Accuracy up to 2.3 arc minutes
Internal Synthesized Reference
+5 Volt Only Option
•
•
•
•
scaling and encoder emulation.
be used in dual bandwidth or switch on the
fly applications.
Programmable Resolution,
Bandwidth and Tracking Rate
Resolution programming allows selec-
tion of 10, 12, 14, or 16-bit, with accura- The RD-19230 is available with operating
cies to 2.3 min. The parallel digital data temperature ranges of 0° to +70°C and
and the internal encoder emulation sig- -40° to +85°C.
Internal Encoder Emulation
with Independent Resolution
Control
•
nals (A QUAD B) have independent res-
Differential Resolver Input
Mode
•
•
•
•
olution control. Internal encoder emula-
tion will permit inhibiting (freezing) the
APPLICATIONS
parallel digital data without interrupting With its low cost, small size, high accura-
Velocity Output Eliminates
Tachometer
the A and B outputs.
cy, and versatile performance, the RD-
19230 converter is ideal for use in modern
The internal Synthesized Reference sec- high performance industrial control sys-
tion eliminates errors due to quadrature tems. It is ideal for users who wish to use
voltage and ensures operation with a a resolver input in their encoder based
rotor-to-stator phase shift of up to 45 system. Typical applications include motor
degrees. The velocity output (VEL) can control, machine tool control, robotics, and
be used in place of a tachometer. It has a process control.
Built-In-Test (BIT) Output,
No 180° Hangup
-40° to +85°C Operating
Temperature
C
bw
R
b
C
bw/
10
V
E
L
V
E
L
R
b
C
bw
C
S
J
1
S
J
2
RH
RL BIT
bw/
10
VEL2 VEL1
SYNTHESIZED
REFERENCE
SHIFT
SIN
-S
-
+
+S
COS
-C
CONTROL
TRANSFORMER
GAIN
-
DEMODULATOR
VEL
-
+
D1 D0
+
+C
R
V
D1
D0
HYSTERESIS
16 BIT
UP/DOWN
COUNTER
VDDP
PCAP
NCAP
VSSP
-5 V
INVERTER
VCO
&
-VCO
TIMING
R CLK
A GND
VDD
INTERNAL
ENCODER
EMULATION
DATA
LATCH
R SET
GND
VSS
EM
EL
INH
D1 D0
A QUAD B A U/B
UP/DN
CB/ZIP
ZIP_EN
BIT 1 - BIT 16
FIGURE 1. RD-19230 SERIES BLOCK DIAGRAM
1999 Data Device Corporation
©
TABLE 1. RD-19230 SPECIFICATIONS (CONTINUED)
TABLE 1. RD-19230 SPECIFICATIONS
These specs apply over the rated power supply, temperature, and refer-
ence frequency ranges; 10ꢀ signal amplitude variation, and 10ꢀ har-
monic distortion.
PARAMETER
UNIT
VALUE
DIGITAL OUTPUTS
Parallel Data (1-16)
10, 12, 14, or 16 parallel lines;
natural binary angle positive
logic (see note 2)
0.25 to 0.75 µs positive pulse
leading edge initiates counter
update. (CB functions with
ZIP_EN pin tied to +5 V or NC)
Logic 1 at all 0’s
PARAMETER
RESOLUTION
UNIT
VALUE
Bits 10, 12, 14, or 16 (note 1 & 2)
Converter Busy (CB)
(4)
FREQUENCY RANGE
ACCURACY -XX2
-XX3 (note 3)
REPEATABILITY
Hz
47-1k
1k - 4k 4k - 10k
Min
Min
LSB
4 +1 LSB 4 +1 LSB 5 +1 LSB
2 +1 LSB 2 +1 LSB 3 +1 LSB
Zero Index Pulse (ZIP)
Built-In-Test (BIT)
1
1
1
1
2
2
(ZIP_EN pin tied to GND)
Logic 0 for BIT condition.
DIFFERENTIAL LINEARITY LSB
REFERENCE
Type
(+REF, -REF)
Differential
~
100 LSB’s of error with a fil-
ter of 500 µs, Loss of Signal
(LOS) less than 500 mV, or
Loss of Reference (LOR) less
than 500 mV
Incremental Encoder Output
50 pF+
Voltage: differential
single ended
overload
Vp-p 10 max.
Vp
5 max.
Vrms 25 continuous; 100 transient
Hz DC to 10k
Frequency
A, B
Ω
Input Impedance
10M min. || 20 pf
Drive Capability
SYNTHESIZED REFERENCE
(note 5)
Logic 0: 1 TTL load, 1.6 mA at
0.4 V max.
Sig/Ref Phase Shift Correction deg 45 max. from 400 Hz to 10kHz
Logic 1; 10 TTL loads, -0.4 mA
at 2.8 V min.
Logic 0; 100 mV max. driving
CMOS
Logic 1; +5 V supply minus
100 mV min. driving CMOS
High Z; 10 µA || 5 pF max.
SIGNAL INPUT
Type
(+S, -S, SIN, +C, -C, COS)
Resolver, differential,
groundbased
Voltage: operating
overload
Input impedance
Vrms
Vrms
Ω
2
15ꢀ
25 continuous
10M min || 10 pF.
DIGITAL INPUTS
TTL / CMOS Compatible
Inputs
DYNAMIC
CHARACTERISTICS
Resolution
(at maximum bandwidth)
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading = 10 µA max P.U. cur-
rent source to +5 V || 5 pF max.
CMOS transient protected
bits
10
12
14
16
Tracking Rate (min)(note 6)
Bandwidth (Closed Loop)
Ka
A1
A2
A
B
rps
Hz
1152 288
72
18
1200 1200 600
300
2
1/sec
1/sec
1/sec
1/sec
1/sec
5.7M 5.7M 1.4M 360k
19.5 19.5 4.9 1.2
295k 295k 295k 295k
Inhibit (INH)
Logic 0 inhibits; Data stable with-
in 150 ns
2400 2400 1200
1200 1200 600
600
300
2k
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
Logic 0 enables; Data stable
within 150 ns
Logic 1 = High Impedance; Data
High Z within 100 ns
2
Acceleration (1 LSB lag)
Settling Time (179° step)
2M
2
500k 30k
20
deg/s
msec
8
50
VELOCITY
CHARACTERISTICS
Polarity
Resolution and Mode
Control (D1 & D0)
(See notes 1 & 2)
Mode D1 D0 Resolution
Positive for increasing angle
4 (at nominal power supply)
resolver
0
0
1
1
0
1
0
1
10 bits
12 bits
14 bits
16 bits
8 bits
Voltage Range (Full Scale)
Scale Factor Error
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
V
ꢀ
10 typ
100 typ
0.75 typ
0.25 typ
5 typ
20 max
200 max
1.3 max
0.50 max
10 max
30 max
8 max
PPM/°C
ꢀ
ꢀ
mV
µV/°C
kΩ
LVDT -5V
0
0
1
-5V
-5V
10 bits
12 bits
14 bits
15 typ
-5V -5V
Logic 0 enables ZIP
Logic 1 enables CB
ZIP_EN
(note 6)
V
ꢀ
V
+5 (VDD)
-5 (VSS)
5
+7
5
-7
CMOS Compatable Inputs
Logic 0 = 1.5 V max.
Logic 1 = 3.5 V min.
negative voltage = -3.5 V min.
Logic 1 select VEL1 components
Logic 0 select VEL2 components
mA
25 max. (each)
TEMPERATURE RANGE
Operating
-30X
-20X
SHIFT
UP/DN
°C
°C
°C
0 to +70
-40 to +85
-40 to +85
Logic 1 will increase gain by 4
Logic 0 will decrease gain by 4
-5 V gain remains constant
Storage
PHYSICAL
CHARACTERISTICS
Size: 64-pin Quad Flat Pack in(mm)
WEIGHT
A QUAD B
Logic 0 enables encoder emulation
Falling edge latches encoder
resolution
0.52 x 0.52 (13.2 x 13.2)
0.018 ( 0.5 )
oz(g)
2
TABLE 1 notes:
1ꢀ Unused data bits are set to logic “0ꢀ”
clamps to the 5 VDC supplies. By performing the following
trigonometric identity, SINθ(COSφ) - COSθ(SINφ) = SIN(θ-φ),
the Control Transformer (CT) compares the analog input signals
( θ ) with the digital output ( φ ), resulting in an error signal pro-
portional to the sin of the angular difference. The CT uses a
combination of amplifiers, switches, logic and capacitors in pre-
cision ratios to perform the calculation.
.ꢀ In LVDT mode, Bit 3 is the MSB and resolution is
programmable to 8,10, 1., and 14 bitsꢀ
3ꢀ Accuracy in LVDT mode is 0ꢀ15% + 1 LSB of full scaleꢀ
4ꢀ In the frequency range of 47Hz to 1kHz, there will be
1 LSB of jitter at quadrant boundariesꢀ
5ꢀ The maximum phase shift tolerance will degrade linearly
from 45 degrees at 400 Hz to 30 degrees at 60 Hzꢀ
6ꢀ When using the -5V inverter, the VDD supply current will
double and VSSP can be up to .0% low, or -4Vꢀ
7ꢀ || = in parallel withꢀ
Note:The error output of the CT is normally sinusoidal, but
in LVDT mode, it is triangular (linear) and can be used to
convert any linear transducer output.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. Instead of a traditional precision
resistor network, this converter uses capacitors with precisely
controlled ratios. Sampling techniques are used to eliminate
errors due to voltage drift and op-amp offsets.
THEORY OF OPERATION
The RD-19230 is a mixed signal CMOS IC containing analog
input and digital output sections. Precision analog circuitry is
merged with digital logic to form a complete high-performance
tracking resolver-to-digital converter. For user flexibility and con-
venience, the converter bandwidth, dynamics, and velocity scal-
ing are externally set with passive components.
The error processing is performed using the industry standard
technique for Type II tracking converters. The DC error is inte-
grated yielding a velocity voltage which in turn drives a voltage
controlled oscillator (VCO). This VCO is an incremental integra-
tor (constant voltage input to position rate output) which, togeth-
er with the velocity integrator, forms a Type II servo feedback
loop. A lead in the frequency response is introduced to stabilize
the loop and another lag at higher frequency is introduced to
reduce the gain and ripple at the carrier frequency and above.
The settings of the various error processor gains and break fre-
quencies are done with external resistors and capacitors so that
the converter loop dynamics can be easily controlled by the user.
FIGURE 1 is the Functional Block Diagram of RD-19230. The
analog conversion electronics require 5 VDC power supplies,
and the converter contains a charge pump to provide the user
with the option of a single-ended +5 VDC supply. The converter
front-end consists of differential sine and cosine input amplifiers
which are protected up to 25 V with 2 kΩ resistors and diode
C
R
BW
B
VEL
C
/10
R
V
BW
VEL SJ1
VEL
-VCO
50 pf
C
VCO
CT
R
1
16 BIT
UP/DOWN
COUNTER
RESOLVER
INPUT
(θ)
+
VCO
GAIN
DEMOD
1
1ꢀ.5 V
THRESHOLD
-
C
F
S
S
11 mV/LSB
DIGITAL
OUTPUT
(φ)
H = 1
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
3
TRANSFER FUNCTION AND BODE PLOT
GENERAL SETUP CONDITIONS
The dynamic performance of the converter can be determined
from its Transfer Function Block Diagrams and Bode Plots (open
and closed loop)ꢀ These are shown in FIGURES ., 3, and 4ꢀ
DDC has external component selection software which consid-
ers all the criteria belowꢀ In a simple fashion, it asks the key sys-
tem parameters (carrier frequency, resolution, bandwidth, and
tracking rate) needed to derive the external component valuesꢀ
The open loop transfer function is as follows:
The following recommendations should be considered when
installing the RD-19.30 R/D converter:
S
A.
S.
+1
(B )
Open Loop Transfer Function =
S
1) In setting the bandwidth (BW) and Tracking Rate (TR) (select-
ing five external components), the system requirements need to
be consideredꢀ For the greatest noise immunity, select the mini-
mum BW and TR the system will allowꢀ Selecting a fBW that is
too low relative to the maximum application tracking rate can cre-
ate a spin-around condition in which the converter never settlesꢀ
The relationship to insure against this condition is detailed in
TABLE .ꢀ
+1
(10B )
where A is the gain coefficient and A.=A1A.
and B is the frequency of lead compensationꢀ
The components of gain coefficient are error gradient, integrator
gain, and VCO gainꢀ These can be broken down as follows:
.) Power supplies are 5 VDCꢀ For lowest noise performance it
is recommended that a 0ꢀ1 µF or larger cap be connected from
each supply to ground near the converter packageꢀ
- Error Gradient = 0ꢀ011 volts per LSB (CT + Error Amp + Demod
with . Vrms input)
Cs Fs
1ꢀ1 CBW
- Integrator Gain =
- VCO Gain =
volts per second per volt
LSBs per second per volt
3) Resolver inputs and velocity output are referenced to AGNDꢀ
This pin should be connected to GND near the converter pack-
ageꢀ Digital currents flowing through ground will not disturb the
analog signalsꢀ
1
1ꢀ.5 RV CVCO
where: Cs = 10 pF
Fs = 67 kHz when R CLK = 30 kΩ
4) This device has several high impedance amplifier inputs
(+C, -C, +S, -S, -VCO, VEL SJ1, and VEL SJ.) that are sensitive
to noise couplingꢀ External components should be connected as
close to the converter as possibleꢀ
CVCO = 50 pF
RV, RB, and CBW are selected by the user to set velocity scaling
and bandwidthꢀ
(CRITICALLY DAMPED)
GAIN = 4
.A
VELOCITY
OUT
ω (rad/sec)
10B
OPEN LOOP
B
A
-6 db/oct
ERROR PROCESSOR
VCO
(B = A/.)
CT
S
B
A
S
+ 1
1
A
S
DIGITAL
POSITION
OUT (φ)
+
.
RESOLVER
INPUT
(θ)
e
GAIN = 0ꢀ4
S
10B
+ 1
-
. A
fBW = BW (Hz) =
π
H = 1
.A
.
. A
ω (rad/sec)
CLOSED LOOP
FIGURE 3. TRANSFER FUNCTION
BLOCK DIAGRAM #2
FIGURE 4. BODE PLOTS
4
5) Setup of bandwidth and velocity scaling for the optimized crit-
ically damped case should proceed as follows:
Note: Use of the -5 V inverter is not recommended for appli-
cations that require the highest BW and Tracking Rates.
- Select the desired f BW (closed loop) based on overall
system dynamicsꢀ
HIGHER TRACKING RATES AND CARRIER
FREQUENCIES.
- Select f
≥ 3ꢀ5f BW
carrier
Maximum tracking rate is limited by the velocity voltage satura-
tion (nominally 4 V) and the maximum internal clock rate (nomi-
nally 1,333,333 Hz for R CLK = 30k)ꢀ To achieve higher tracking
- Select the applications tracking rate (in accordance with TABLE 3),
and use appropriate values for R SET and R CLK
Full Scale Velocity Voltage
- Compute Rv =
resolution
Tracking Rate (rps) x .
x 50 pF x 1ꢀ.5 V
TABLE 3. MAX TRACKING RATE (MIN) IN RPS
3ꢀ. x Fs (Hz) x 108
- Compute CBW (pF) =
RESOLUTION
R SET
(Ω)
R CLK
(Ω)
Rv x (f BW).
10
12 14 16
115. .88 7. 18
17.8 43. 108 .7
30k** or open
30k
.0k
15k
- Where Fs = 67 kHz for R CLK = 30 KΩ
100 kHz for R CLK = .0 KΩ
.3k
.3k
1.5 kHz for R CLK = 15 KΩ
.304 576
*
*
0ꢀ9
CBW x f BW
- Compute RB =
TABLE 4. CARRIER FREQUENCY (MAX)
IN KHZ
CBW
- Compute
10
RESOLUTION
R SET
R CLK
(Ω)
(Ω)
10
10
10
10
10
12
10
10
10
10
14
7
16
30k** or open
30k
30k
.0k
15k
5
7
As an example:
.3k
.3k
.3k
10
10
*
10
*
Calculate component values for a 16 bit converter with 100Hz
bandwidth, a tracking rate of 10 RPS and a full scale velocity
of 4 Voltsꢀ
* Not recommendedꢀ
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving openꢀ
4 V
- Rv =
= 97655 Ω
10 rps x .16 x 50 pF x 1ꢀ.5 V
3ꢀ. x 67 kHz x 108
- Compute CBW (pF) =
= .1955 pF
97655 x 100 Hz.
+5V
0ꢀ9
- Compute RB =
= 410 kΩ
.1955 x 10 -1. x 100 Hz
33
58
.7
VDD
VDD
VDDP
6) Using the -5V Inverter will eliminate the need for a -5 V sup-
plyꢀ Refer to FIGURE 5ꢀ for the necessary connectionsꢀ
.6
PCAP
+
RD-19.30
10 F/10V
When using the built-in -5 V inverter, the maximum tracking rate
should be scaled for a full-scale velocity output of 3ꢀ5 V maxꢀ
.4
NCAP
.3
16
VSSP
VSS
17
VSS
TABLE 2. TRACKING/BW RELATIONSHIP
47 F/10V
+
RPS (MAX)/BW
RESOLUTION
.5
..
GND
AGND
1
10
1.
14
16
0ꢀ50
0ꢀ.5
0ꢀ1.5
FIGURE 5. -5V INVERTER CONNECTIONS
5
rates, a higher internal counting rate must be programmed by
setting RCLK to a value less than 30kꢀ See TABLE 4ꢀ for the
appropriate valuesꢀ
internal clock rateꢀ Choose the tracking rate in accordance with
TABLE 3 to insure this relationshipꢀ The rates shown in TABLE
3 are based on ~90% of the nominal internal clock rateꢀ
The Rv resistor and an internal 50pF cap are configured as an
integrating circuit that resets to zero after a count occurs in either
directionꢀ This circuit acts as a VCO with velocity as its input and
CB as its outputꢀThe Rv resistor and an internal 50pF cap deter-
mine the maximum rate of the VCOꢀ Rv must be chosen such
that the maximum rate of the VCO is less than the maximum
The relationship between the velocity voltage and the VCO rate
is given by:
1
Velocity Voltage
VCO Frequency
=
(Rv x 50 pF x 1ꢀ.5)
TABLE 5. TRANSFORMERS
INPUT SIGNAL INPUT VOLTAGE INPUT FREQUENCY
PART
FIGURE
TYPE
(Vrms)
(HZ)
NUMBER
NUMBER
Synchro
11ꢀ8
400
5.034
5.035
5.036
5.037
5.038
B-4.6*
5.039**
.4133**
6
6
7
7
7
8
9
9
Synchro
Resolver
Resolver
Resolver
Reference
Synchro
90
11ꢀ8
400
400
400
400
400
60
.6
90
Reference
Synchro
Reference
Reference
60
* Beta Transformer
** 60 Hz synchro transformers are active (require 15V DC power supplies) and are available in two
temperature ranges; -1: -55° to +1.5° and -3: 0° to + 70°ꢀ
6
0ꢀ61 MAX
(15ꢀ49)
0ꢀ61 MAX
(15ꢀ49)
0ꢀ15 MAX
(3ꢀ81)
0ꢀ09 MAX
(.ꢀ.9)
0ꢀ30 MAX
(7ꢀ6.)
0ꢀ09 MAX
(.ꢀ.9)
0ꢀ15 MAX
(3ꢀ81)
1
3
T1A
8
4
7
5
6
11 1.
14 15
0ꢀ81 MAX
(.0ꢀ57)
T1B
0ꢀ600
(15ꢀ.4)
10
9
.0 19 18 17 16
0ꢀ115 MAX
(.ꢀ9.)
SIDE VIEW
0ꢀ100 (.ꢀ54) TYP
TOL NON CUM
BOTTOM VIEW
BOTTOM VIEW
TERMINALS
0ꢀ0.5 –0ꢀ001 (6ꢀ35 –0ꢀ03) DIAM
0ꢀ1.5 (3ꢀ18) MIN LENGTH
SOLDER PLATED BRASS
PIN NUMBERS FOR REF. ONLY
Dimensions are shown in inches (mm)ꢀ
T1A
1
6
-SIN
S1
S3
5
3
10
+SIN
SYNCHRO
INPUT
RESOLVER
OUTPUT
T1B
11
16
.0
-COS
15
+COS
S.
FIGURE 6. TRANSFORMER LAYOUT AND SCHEMATIC (SYNCHRO INPUT - 52034/52035)
0ꢀ61 MAX
(15ꢀ49)
0ꢀ61 MAX
(15ꢀ49)
0ꢀ15 MAX
(3ꢀ81)
0ꢀ09 MAX
(.ꢀ.9)
0ꢀ30 MAX
(7ꢀ6.)
0ꢀ09 MAX
(.ꢀ.9)
0ꢀ15 MAX
(3ꢀ81)
1
3
T1A
8
4
5
6
11 1.
14 15
0ꢀ81 MAX
(.0ꢀ57)
T1B
0ꢀ600
(15ꢀ.4)
10
9
7
.0 19 18 17 16
0ꢀ115 MAX
(.ꢀ9.)
SIDE VIEW
0ꢀ100 (.ꢀ54) TYP
TOL NON CUM
BOTTOM VIEW
BOTTOM VIEW
TERMINALS
0ꢀ0.5 –0ꢀ001 (6ꢀ35 –0ꢀ03) DIAM
0ꢀ1.5 (3ꢀ18) MIN LENGTH
SOLDER PLATED BRASS
PIN NUMBERS FOR REF. ONLY
Dimensions are shown in inches (mm)ꢀ
T1A
1
6
-SIN
S1
S3
3
10
+SIN
RESOLVER
INPUT
RESOLVER
OUTPUT
T1B
11
16
.0
-COS
S4
S.
15
+COS
FIGURE 7. TRANSFORMER LAYOUT AND SCHEMATIC (RESOLVER INPUT - 52036/52037/52038)
7
CASE IS BLACK AND
NON-CONDUCTIVE
0ꢀ.5
(6ꢀ35)
MINꢀ
0ꢀ61 MAX
(15ꢀ49)
0ꢀ3. MAX
(8ꢀ13)
1ꢀ14 MAX
(.8ꢀ96)
0ꢀ1.5 MIN
(3ꢀ17)
0ꢀ09 MAX
(.ꢀ.9)
0ꢀ15 MAX
(3ꢀ81)
+
•
•
•
•
S3
S1
+15 V
+S
*
*
(+15 V) (-R)
*
*
1
.
9
3
T1A
8
5
6
0ꢀ600
(15ꢀ.4)
0ꢀ81 MAX
(.0ꢀ57)
1ꢀ14 MAX
(.8ꢀ96)
0ꢀ85 0ꢀ010
(.1ꢀ59 0ꢀ.5)
5.039
or
.4133
10
7
0ꢀ105 (.ꢀ66)
SIDE VIEW
0ꢀ100 (.ꢀ54) TYP
TOL NON CUM
BOTTOM VIEW
(RH)
S.
•
(RL)
(V)
V
•
(+R)
+C
•
(-Vs)
-Vs
•
TERMINALS
*
0ꢀ0.5 0ꢀ001 (6ꢀ35 0ꢀ03) DIAM
0ꢀ1.5 (3ꢀ18) MIN LENGTH
SOLDER-PLATED BRASS
+
(BOTTOM VIEW)
0ꢀ4.
(10ꢀ67)
MAXꢀ
0ꢀ13 0ꢀ03
(3ꢀ30 0ꢀ76)
Dimensions are shown in inches (mm)ꢀ
0ꢀ.1 0ꢀ3
(5ꢀ33 0ꢀ76)
0ꢀ175 0ꢀ010 (4ꢀ45 0ꢀ.5)
NONCUMULATIVE
TOLERANCE
0ꢀ040 0ꢀ00. DIAꢀ PINꢀ
SOLDER PLATED BRASS
1
6
INPUT
OUTPUT
5
10
The mechanical outline is the same for the synchro input trans-
former (5.039) and the reference input transformer (.4133),
except for the pinsꢀ Pins for the reference transformer are shown
in parenthesis ( ) belowꢀ An asterisk * indicates that the pin is
omittedꢀ
FIGURE 9. 60 HZ SYNCHRO AND REFERENCE
TRANSFORMER DIAGRAMS
(SYNCHRO INPUT - 52039 / REFERENCE INPUT - 24133)
FIGURE 8. TRANSFORMER LAYOUT AND SCHEMATIC
(REFERENCE INPUT - B-426)
TYPICAL INPUTS
FIGURES 10 through 14 illustrate typical input configurationsꢀ
EXTERNAL
REFERENCE
LO HI
6
1
B-4.6
10
5
RH
RL
RESOLVER INPUT OPTION
S1
-S SIN
+S
-R +R
1
10
TIA
S3
S4
6
3
+C
-C
RD-19.30
11
15
.0
TIB
S.
COS
16
AGND
5.036(11ꢀ8V)
OR
5.037(.6V)
OR
GND
5.038(90V)
OR
SYNCHRO INPUT OPTION
RH
RL
S1
+S
1
3
10
S3
TIA
TIB
6
5
+C
.0
11
S.
15
16
5.034(11ꢀ8V)
OR
5.037(90V)
FIGURE 10. TYPICAL TRANSFORMER CONNECTIONS
8
EXTERNAL
REF
LO HI
R
R
R
1
.
4
R
3
RL RH
See Note 3ꢀ
+S
-S
S3
S1
SIN
COS
-C
+C
See Note 3ꢀ
S.
S4
A GND
GND
RESOLVER
Notes:
1) Resistors selected to limit Vref peak to between 1ꢀ5 V and 4 Vꢀ
.) External reference LO is grounded, then R3 and R4 are not
needed, and -R is connected to GNDꢀ
3) 10k ohms, 1% series current limit resistors are recommendedꢀ
FIGURE 11. TYPICAL CONNECTIONS, 2 V RESOLVER, DIRECT INPUT
R
1
-S
SIN
S3
S1
+S
R
R
.
R
1
S.
S4
+C
.
A GND
GND
-C
COS
.
R
.
=
X Volt
R + R
1
.
R + R should not load the Resolver; it is recommended to use a R = 10 kΩ
1
.
.
R + R Ratio erros will result in Angular errors,
1
.
. cycle, 0ꢀ1% Ratio error = 0ꢀ0.9 Peak Errorꢀ
FIGURE 12. TYPICAL CONNECTIONS, X- VOLT RESOLVER, DIRECT INPUT
9
SIN
3
R
R
f
R
R
i
i
-S
1
6
-
S1
S3
.
5
+S
+
f
f
4
RESOLVER
INPUT
A GND
COS
13
R
R
R
i
i
-C
15
16
7
-
S4
S.
+C
+
8
10
R
f
1.
CONVERTER
S1 and S3, S. and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GND at the converterꢀ
For DDC-49530: R = 70ꢀ8 KΩ, 11ꢀ8 V input, synchro or resolverꢀ
i
For DDC-49590: R = .70 KΩ, 90 Volt input, synchro or resolverꢀ
i
Maximum additional error is 1 minuteꢀ
When using discrete resistors: Resolver L-L voltage =
R
R
i
f
x . Vrms, where R ≥ 6 kΩ
f
FIGURE 13. DIFFERENTIAL RESOLVER INPUT, USING DDC-49530 (11.8 V) OR DDC-49590 (90 V)
SIN
3
R
f
R
i
-S
1
6
-
S1
S3
.
5
R
i
+S
+
R
f
4
A GND
SYNCHRO
INPUT
COS
14
R
R
i
i
16
7
R /
f
3
8
15
-C
15
-
R /.
i
+C
10
9
+
S.
R /
f
3
11
CONVERTER
S1, S., S3 should be triple twisted shielded; RH and RL should be twisted shielded;
In both cases the shield should be tied to GND at the converterꢀ
11ꢀ8 Volt input = DDC-49530: R = 70ꢀ8 KΩ, 11ꢀ8 V input, synchro or resolverꢀ
i
90 Volt input = DDC-49590: R = .70 KΩ, 90 Volt input, synchro or resolverꢀ
i
Maximum additional error is 1 minuteꢀ
When using discrete resistors: Resolver L-L voltage =
R
R
i
f
x . Vrms, where R ≥ 6 kΩ
f
FIGURE 14. SYNCHRO INPUT, USING DDC-49530 (11.8 V) OR DDC-49590 (90 V)
10
DC INPUTS
TABLE 6. PRECHARGE AMPLIFIER
GAIN PROGRAMMING
As noted in TABLE 1 the RD-19.30 will accept DC inputsꢀ It is
necessary to set the REF input to DC by tying RH to +5 V and
RL to GND or -5 \/ꢀ
UP/DN
GAIN
4
Logic 0
Logic 1
-5 V
1/4
1
VELOCITY TRIMMING
RD-19.30 specifications for velocity scaling, reversal error, and
offset are contained in TABLE 1ꢀ Velocity scaling and offset are
externally trimmable for applications requiring tighter specifica-
tions than those available from the standard unitꢀ FIGURE 15
shows the setup for trimming these parameters with external
potsꢀ It should also be noted that when the resolution is changed,
VEL Scaling is also changedꢀ
UP/DN
The UP/DN input selects the gain of the amplifier driving the de-
selected set of bandwidth componentsꢀ UP/DN has three input
statesꢀ See TABLE 6 to relate input to gainꢀ
BENEFIT OF SWITCHING RESOLUTION ONTHE FLY
OPTIONAL BANDWIDTH COMPONENTS
Switching resolution on the fly can be used in applications that
require high resolution for accurate position control, and tracking
rates or settling times that are faster than the high resolution
mode will allowꢀ
The RD-19.30 provides the option of using a second set of
bandwidth componentsꢀ The second set of components can be
used for switch-on-the-fly or dual-bandwidth applicationsꢀ The
SHIFT and UP/DN inputs are used when when switching band-
width components, and their operation is described belowꢀ Refer
to the block diagram on page 1ꢀ
The RD-19.30 can track four times faster for each step down in
resolution (iꢀeꢀ, a step from 16 bits to 14 bits)ꢀ The velocity out-
put will be scaled down by a factor of four with each step down
in resolutionꢀ For example, if the velocity output is scaled such
that 4 Volts = 10 RPS in 16 bit resolution, then the same con-
verter will output 1 Volt for 10 RPS in 14 bit resolutionꢀ To avoid
glitches in the velocity output, the second set of bandwidth com-
ponents can be pre-charged to the expected voltage, and
switched in using the SHIFT input at the same time the resolu-
tion is changedꢀ This will allow for a smooth velocity transition,
resulting in reduced errors and minimal settling time after the
changeꢀ
SHIFT
The SHIFT pin is an input that chooses between the VEL1 and
VEL. bandwidth componentsꢀ This pin has an internal pull-up to
+5Vꢀ When the SHIFT pin is left open, or a logic 1 is applied, the
VEL1 components are selectedꢀ When a Logic 0 is applied, the
VEL. components are selectedꢀ The deselected set of band-
width components are driven by an amplifier, with programmable
gain, that follows the velocity amplifierꢀ This amplifier can be
used to pre-charge the deselected set of components to the volt-
age level that is expected after a change in resolutionꢀ (See
description on BENEFIT OF SWITCHING RESOLUTION ON
THE FLYꢀ)
FIGURE 17 shows the way the converter behaves during a
change in resolution while tracking at a constant velocityꢀ The
first illustration shows the benefits of switching in pre-charged
components while changing resolutionꢀ The second illustration
shows the result without the benefits of switching on the flyꢀ
The signals that have been recorded are:
1) VEL: velocity output pin on the RD-19.30
+5 V
100 R
V
.
100 kΩ
-VCO
(OFFSET)
-5 V
0ꢀ8 R
V
.) ERROR: this is the analog representation of the error between
the input and the output of the RD-19.30
RD-19.30
0ꢀ4 R (SCALING)
V
3) D0: an input resolution control line to the RD-19.30
4) BIT: built-in-test output pin of the RD-19.30
1
VEL
When this system uses the switch resolution on the fly imple-
mentation, the velocity signal immediately assumes the pre-
FIGURE 15. VELOCITY TRIMMING
11
charged level of the second set of components, resulting in small
errors and reduced settling timesꢀ Notice that the BIT output
does not indicate a fault conditionꢀ (refer to FIGURE 17)
components to settle to the pre-charged levelꢀ This time will
depend on the time constant of the bandwidth components being
chargedꢀ If switching is limited to two adjacent resolutions (iꢀeꢀ,
14 and 16) then the pre-charge amplifier can be set up to con-
tinuously maintain the appropriate velocity voltage on the dese-
lected components, resulting in the fastest possible switching
timesꢀ See FIGURE 16 for an example of the input wiring con-
nections necessary for switching on the fly between 14 and 16
bit resolutionꢀ
When this system type does not use the switch resolution on the
fly implementation, large errors and increased settling times
resultꢀ The errors exceed 100 LSBs causing the BIT to flag for a
fault conditionꢀ
SWITCH ONTHE FLY IMPLEMENTATION
DUAL BANDWIDTHS
The following steps detail switching resolution on the flyꢀ
With the second set of BW component pins, the user can set two
bandwidths for the RD-19.30 and choose between themꢀ To use
two bandwidths, proceed as follows:
1) The SHIFT pin should be controlled synchronously with the
change in resolutionꢀ When shift is logic high, the VEL1 compo-
nents will be selectedꢀ When shift is logic 0, the VEL. compo-
nents will be selectedꢀ
1) Tie UP/DN to pin -5Vꢀ
.) The second set of BW components (CBW., RB., CBW./10
should typically be of the same value as the first set (CBW1, RB1
BW1/10,) and should be installed on VEL. and VEL SJ.ꢀ
)
,
C
With Switch Resolution on the Fly Implemented
Note: Each set of bandwidth components must be chosen to
insure that the tracking rate to BW ratio (listed in TABLE 2)
is not exceeded for the resolution in which it will be used.
VEL 0V
-5V
3) UP/DN will program the direction of the gainꢀ If the resolution
is increasing (UP/DN logic 0), the gain of the pre-charge amplifi-
er should be set to fourꢀ If the resolution is decreasing
(UP/DN logic 1), the gain should be set to 1/4ꢀ The gain of the
pre-charge amplifier should be programmed prior to switching
the resolution of the converter, allowing enough time for the the
0°
ERROR
5V
D0
0V
5V
BIT
0V
ERROR = 13ꢀ6 LSBs per box
Without Switch Resolution on the Fly Implemented
VEL 0V
+5V
-5V
D1
0°
ERROR
RD-19.30
5V
D0
0V
D0
58
5V
SHIFT
.7
UP/DN
BIT
0V
ERROR = 1500 LSBs per box
FIGURE 17. BENEFIT OF SWITCHING
RESOLUTION ON THE FLY
FIGURE 16. INPUT WIRING - SWITCHING ON THE FLY
BETWEEN 14 AND 16 BIT RESOLUTION
12
.) Choose the two bandwidths following the guidelines in the
General Setup Considerations; the RV resistor must be the same
value for both bandwidthsꢀ
The Converter Busy (CB) signal indicates that the tracking con-
verter output angle is changing 1 LSBꢀ As shown in FIGURE .0,
output data is valid 50 nS maximum after the middle of the CB
pulseꢀ CB pulse width is 1/40 FS, which is nominally 375 nsꢀ
3) Use the SHIFT pin to choose between bandwidthsꢀ A logic 1
selects the VEL1 components and a logic 0 selects the VEL.
componentsꢀ
INTERNAL ENCODER EMULATION
The RD-19.30 can be programmed to encoder emulation mode
by connecting the A_QUAD_B input to GNDꢀ The U/B output pin
becomes B (LSB XOR LSB + 1) The A (LSB + 1) and B output
signals can be used in control systems that are designed to inter-
face with incremental optical encodersꢀ To enable the Zero Index
pulse, ZIP_EN should be tied to GNDꢀ
INHIBIT, ENABLE, AND CB TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferredꢀ Application of an Inhibit signal does not interfere with the
continuous tracking of the converterꢀ As shown in FIGURE 18,
angular output data is valid 150 ns maximum after the applica-
tion of the negative inhibit pulseꢀ
The resolution of the incremental outputs is latched from the D0
and D1 inputs on the low going edge of A_QUAD_BꢀThe resolu-
tion of the parallel data outputs may be changed any time after
the encoder resolution is latched (see FIGURE .3)ꢀ
Output angle data is enabled onto the tri-state data bus in two
bytesꢀ Enable MSBs (EM) is used for the most significant 8 bits
and Enable LSBs (EL) is used for the least significant 8 bitsꢀ As
shown in FIGURE 19, output data is valid 150 ns maximum after
the application of a negative enable pulseꢀ The tri-state data bus
returns to the high impedance state 100 ns maximum after the
rising edge of the enable signalꢀ
Note: The encoder resolution must be less than or equal to
the resolution of the parallel data outputs. Refer to FIGURE
21.
The timing of the A, B and ZIP (or North Reference Pole [NRP])
output is dependent on the rate of change of the
synchro/resolver position (rps or degrees per second) and the
encoder resolution latched into the RD-19.30 (refer to
FIGURE ..)ꢀ The calculations for the timing is:
n = encoder resolution latched into RD-19.30
t = 1 / ( .n* Velocity(RPS))
INHIBIT
T = 1 / ( Velocity(RPS))
150 nsec max
DATA
DATA
VALID
FIGURE 18. INHIBIT TIMING
.50 to 750 nsec
CB
ENABLE
50 nsec
100 nsec MAX
HIGH Z
150 nsec MAX
DATA
VALID
DATA
VALID
DATA
VALID
DATA
HIGH Z
DATA
FIGURE 19. ENABLE TIMING
FIGURE 20. CONVERTER BUSY TIMING
13
SYNTHESIZED REFERENCE
BUILT-IN-TEST (BIT)
The synthesized reference section of the RD-19.30 eliminates
errors due to phase shift between the reference and signal
inputsꢀ Quadrature voltages in a resolver or synchro are by def-
inition the resulting 90° fundamental signal in the nulled out error
voltage (e) in the converterꢀ Due to the inductive nature of syn-
chros and resolvers, their output signals lead the reference input
signal (RH and RL)ꢀ When an uncompensated reference signal
is used to demodulate the control transformer’s output, quadra-
ture voltages are not completely eliminatedꢀ As shown in FIG-
URE 1, the converter synthesizes its own internal reference sig-
nal based on the SIN and COS signal inputsꢀ Therefore, the
phase of the synthesized (internal) reference is determined by
the signal input, resulting in reduced quadrature errorsꢀ
The BIT output is active low, and will be asserted during the fol-
lowing three error conditions:
Loss of Signal (LOS) - Sin and Cos inputs both less than 500mVꢀ
Loss of Reference (LOR) - Reference Input less than 500 mVꢀ
Excessive Error - This error is detected by monitoring the
demodulator output, which is proportional to the difference
between the analog input and digital outputꢀ When it exceeds
approximately 100 LSBs (in the selected resolution), BIT will be
assertedꢀ This condition can occur any time the analog input
changes at a rate in excess of the maximum tracking rateꢀ
During power up, the converter may see a large difference
between the sin/cos inputs and the digital output angle held in its
counterꢀ BIT will be asserted until the converter settles within
~ 100 LSB’s of the final resultꢀ
RD-19.30
1 MSB
.
3
4
5
6
7
8
9
10
11
1.
13
14
15
BIT 16 LSB
1
0
1
.
1
4
1
6
A
B
FIGURE 21. INCREMENTAL ENCODER EMULATION RESOLUTION CONTROL
B(X- or LSB & LSB+1)
A (LSB+1)
.t
Data Valid
D0/D1
50 nsec
ZIP (NRP)
A QUAD B
t
T
359ꢀ95
0
FIGURE 23. TIMING FOR INCREMENTAL ENCODER
EMULATION RESOLUTION CONTROL
FIGURE 22. INCREMENTAL ENCODER EMULATION
14
LVDT MODE
As shown in TABLE 1 the RD-19.30 unit can be made to oper-
ate as an LVDT-to-digital converterꢀ In this mode the RD-19.30
functions as a ratiometric tracking linear converterꢀ When linear
AC inputs are applied from a LVDT the converter operates over
one quarter of its rangeꢀThis results in two less bits of resolution
for LVDT mode than are provided in resolver modeꢀ
Data output of the RD-19.30 is Binary Coded in LVDT modeꢀThe
most negative stroke of the LVDT is represented by ALL ZEROS
and the most positive stroke of the LVDT is represented by ALL
ONESꢀThe most significant . bits (. MSBs) may be used as over-
range indicatorsꢀ Positive overrange is indicated by code “01” and
negative overrange is indicated by code “11“ (see TABLE 7)ꢀ
LDVT output signals need to be scaled to be compatible with the
converter inputꢀ FIGURE .5 is a schematic of an input scaling
circuit applicable to 3-wire LVDTsꢀ The value of the scaling con-
stant “a” is selected to provide an input of . Vrms at full stroke of
the LVDTꢀThe value of scaling constant “b” is selected to provide
an input of 1 Vrms at null of the LVDTꢀ Suggested components
for implementing the input scaling circuit are a quad op-amp,
such as a OP11 type, and precision thin-film resistors of 0ꢀ1%
toleranceꢀ FIGURE .4 illustrates a .-wire LVDT configurationꢀ
TABLE 7. 12-BIT LVDT OUTPUT CODE FOR FIGURE 25
LVDT OUTPUT
MSB
LSB
+ over full travel
+ full travel -1 LSB
+0ꢀ5 travel
+1 LSB
null
- 1 LSB
-0ꢀ5 travel
- full travel
- over full travel
01
00
00
00
00
00
00
00
11
xxxx
1111
1100
1000
1000
0111
0100
0000
xxxx
xxxx
1111
0000
0000
0000
1111
0000
0000
xxxx
xxxx
1111
0000
0001
0000
1111
0000
0000
xxxx
C1
SIN
aR
-S
. WIRE LVDT
R
-
R
+S
REF IN
R
+
FS = . V
aR
C.
COS
bR
R
R
.R
-C
R
R
-
.R
+C
+
. V
R
bR
+RH
-RL
C
= C , set for phase lag = phase lead through the LVDTꢀ
.
1
FIGURE 24. 2-WIRE LVDT DIRECT INPUT
15
aR
SIN
-S
R
R
V
B
-
R'
R'
+S
+
R'
aR
bR
R
.R'
COS
-C
R
-
V
A
R'
R/.
.R'
+
+C
+RH
-RL
bR
Notes:
1ꢀ R' ≥ 10 kΩ
.ꢀ Consideration for the value of R is LVDT loadingꢀ
1
null
1
b =
a =
=
RDC-19.30
INPUT
VA
VB
null
LVDT
OUTPUT
.V
.
SIN
(VA - VB) max
V
A
1V
a
SIN = 1+ (VA - VB)
.
V
B
COS
+FS
+FS
NULL
-FS
-FS
NULL
a
COS = 1- (VA - VB)
.
FIGURE 25. 3-WIRE LVDT SCALING CIRCUIT
16
TABLE 8. RD-19230 PINOUTS
#
1
NAME
#
NAME
VSS (-5V)
#
NAME
VDD (+5V)
N/C
#
NAME
VEL
-VCO
SJ1
17
18
19
.0
.1
..
.3
.4
.5
.6
.7
.8
.9
30
31
3.
33
34
35
36
37
38
39
40
41
4.
43
44
45
46
47
48
49
50
51
5.
53
54
55
56
57
58
59
60
61
6.
63
64
Bit 8
.
TP3 (test point)
R CLK
R SET
ENM
Bit 16
3
Bit 9
A (LSB + 1)
TP4 (test point)
N/C
4
SJ.
Bit .
5
SHIFT
Bit 10
Bit 3
6
VEL.
AGND
VSSP
TP5 (test point)
ZIP_EN
TP6 (test point)
ENL
7
TP1 (test point)
Bit 11
Bit 4
8
VEL1
NCAP
GND
9
TP. (test point)
N/C
10
11
1.
13
14
15
16
+C
PCAP
VDDP
BIT
Bit 1.
Bit 5
VDD (+5V)
UP/DN
D0
COS
-C
Bit 13
Bit 6
+S
U/B
D1
SIN
A_QUAD_B
CB (ZI)
Bit 1
Bit 14
Bit 7
INH
-S
RH
VSS (-5V)
Bit 15
RL
Notes:
1ꢀ See FIGURE 5 for +5 V only operationꢀ
0ꢀ078+0ꢀ004
-0ꢀ00.
.ꢀ00+0ꢀ10
(
)
-0ꢀ05
17
3.
0ꢀ096MAX
(.ꢀ45MAX)
16
33
0ꢀ0098MIN,0ꢀ0197MAX
(0ꢀ.5MIN,0ꢀ50MAX)
0ꢀ0197
(0ꢀ50)
0ꢀ5.0 0ꢀ010
(13ꢀ. 0ꢀ.5)
RD-19230FX
-XXX
Date Code
0ꢀ394 0ꢀ004
(10ꢀ00 0ꢀ10)
pin1
48
0ꢀ0098MIN,0ꢀ0197MAX
(0ꢀ.5MIN,0ꢀ50MAX)
0ꢀ096MAX
(.ꢀ45MAX)
49
64
0ꢀ394 0ꢀ004
(10ꢀ00 0ꢀ10)
0ꢀ007MAX
(0ꢀ17MAX)
0ꢀ008
(0ꢀ..)
0ꢀ5.0 0ꢀ010
(13ꢀ. 0ꢀ.5)
0ꢀ035+0ꢀ006
-0ꢀ004
0ꢀ88+0ꢀ15
(
)
-0ꢀ10
Dimensions shown are in inches (millimeters)
FIGURE 26. RD-19230 MECHANICAL OUTLINE
17
TABLE 9. FRONT-END THIN-FILM RESISTOR NETWORKS
(SEE FIGURE 27)
DDC-49530, DDC-57470 RESISTOR VALUES (11.8 V INPUTS)
SYMBOL
ABS
VALUE
TOL
(%)
REL TO
REL
VALUE
TOL TCR(PPM)
(%)
R1
R.
R3
R4
R5
R6
R7
R8
R9
R10
R11
70ꢀ8 k
0ꢀ1
.5
R1
R4
1. k
1. k
0ꢀ0.
0ꢀ0.
0ꢀ0.
0ꢀ0.
0ꢀ0.
.
.
.
.
.
.
.
.
.
.
R1
70ꢀ8 k
70ꢀ8 k
35ꢀ4 k
R1
R1
16
R11
15
R10
14
R9
13
1.
R8
11
R7
10
R6
9
R6
6ꢀ9.8. k 0ꢀ0.
5ꢀ0718 k 0ꢀ0.
R6
R11
R11
R1
5ꢀ0718
6ꢀ9.8. k 0ꢀ0.
70ꢀ8 k 0ꢀ0.
0ꢀ0.
R1
R.
R3
R4
R5
DDC-49590 RESISTOR VALUES (90 V INPUTS)
.70 k 0ꢀ1
R1
R.
R3
R4
R5
R6
R7
R8
R9
R10
R11
.5
.
.
.
.
.
.
.
.
.
.
1
.
3
4
5
6
7
8
R1
R4
6 k
0ꢀ0.
0ꢀ0.
0ꢀ0.
0ꢀ0.
0ꢀ0.
6 k
R1
.70 k
.70 k
135 k
R1
R1
R6
3ꢀ4641 k 0ꢀ0.
.ꢀ5359 k 0ꢀ0.
.ꢀ5359 k 0ꢀ0.
3ꢀ4641 k 0ꢀ0.
R6
R11
R11
R1
FIGURE 27. (DDC-49530, DDC-49590, DDC-57470)
LAYOUT AND RESISTOR VALUES (SEE TABLE 9)
.70 k
0ꢀ0.
0ꢀ870 MAX
(..ꢀ10)
ꢀ405
7˚
45˚
0ꢀ.50 0ꢀ005
(6ꢀ35 0ꢀ13)
0ꢀ.99
(7ꢀ6)
0ꢀ101
(.ꢀ6)
0ꢀ406
(10ꢀ3)
0ꢀ3.0 - 0ꢀ300
(8ꢀ13 - 7ꢀ6.)
0ꢀ014
(ꢀ36)
0ꢀ13 0ꢀ005
(3ꢀ30 0ꢀ13)
0ꢀ34.
(8ꢀ7)
0ꢀ009
(0ꢀ.3)
0ꢀ09.
(.ꢀ3)
0ꢀ015 0ꢀ009
(0ꢀ38 0ꢀ.3)
0ꢀ0.0 MIN
(0ꢀ51)
0ꢀ1.5 MIN
(3ꢀ18)
0ꢀ075 0ꢀ015
(1ꢀ91 0ꢀ38)
0ꢀ018 0ꢀ003
(0ꢀ46 0ꢀ08)
0ꢀ016
(0ꢀ40)
+0ꢀ0.5
0ꢀ3.5
0ꢀ050
(1ꢀ.7)
-0ꢀ015
0ꢀ100 TYP
(.ꢀ54)
+0ꢀ64
(8ꢀ.6
)
-0ꢀ38
DIMENSIONS SHOWN ARE IN INCHES (MM)ꢀ
DIMENSIONS SHOWN ARE IN INCHES (MM)ꢀ
FIGURE 28. 16-PIN THIN-FILM RESISTOR NETWORK
DIP MECHANICAL OUTLINE
FIGURE 29. 16-PIN THIN-FILM RESISTOR NETWORK
FLAT-PACK MECHANICAL OUTLINE
(DDC-57470)
(DDC-49530, DDC-49590)
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ORDERING INFORMATION
RD-19.30FX-X X X X
Supplemental Process Requirements:
T = Tape and Reel (50 pcꢀ minꢀ order)
Accuracy:
. = 4 min + 1 LSB
3 = . min + 1 LSB
Reliability:
0 = Standard DDC Procedures
Operating Temperature Range:
. = -40° to +85°C
3 = 0° to +70°C
THIN-FILM RESISTOR NETWORKS:
DDC-49530 = 11ꢀ8 V inputs DIP package
DDC-57470 = 11ꢀ8 V inputs Flat-pack package
DDC-49590 = 90 V inputs DIP package
COMPONENT SELECTION SOFTWARE:
Component selection software can be downloaded from our website ( wwwꢀddc-webꢀcom )
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The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewithꢀ
Specifications are subject to change without noticeꢀ
105 Wilbur Place, Bohemia, New York 11716-.48.
For Technical Support - 1-800-DDC-5757 ext. 7402 or 7413
Headquarters - Tel: (631) 567-5600 extꢀ 740. or 7413, Fax: (631) 567-7358
West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988
Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610
United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-3..64
Ireland - Tel: +353-.1-341065, Fax: +353-.1-341568
France - Tel: +33-(0)1-41-16-34.4, Fax: +33-(0)1-41-16-34.5
Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089
Sweden - Tel: +46-(0)8-54490044, Fax +46-(0)8-7550570
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://wwwꢀddc-webꢀcom
PRINTED IN THE UꢀSꢀAꢀ
D-05/00-500
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