RD-19230NEW [ETC]
Resolver and Synchro To Digital Converters ; 解析器和同步数字转换器\n
| 型号： | RD-19230NEW |
| 厂家： | 
ETC |
| 描述： | Resolver and Synchro To Digital Converters
|
| 文件： | 总24页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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RD-19230
16-BIT MONOLITHIC TRACKING
RESOLVER-TO-DIGITAL CONVERTER
FEATURES
• Accuracy up to 2.3 Arc Minutes
• Internal Synthesized Reference
• +5 Volt Only Option
• Programmable Resolution, Dual
Bandwidth and Tracking Rate
• Internal Encoder Emulation with
Independent Resolution Control
• Differential Resolver Input Mode
• Velocity Output Eliminates
Tachometer
• Built-In-Test (BIT) Output, No 180°
Hangup
• -40° to +85°C Operating Temperature
DESCRIPTION
The RD-19230 is a small and versatile, low cost, state-of-the-art 16-
bit monolithic Resolver-to-Digital Converter. This single chip convert-
er offers programmable features such as resolution, bandwidth,
velocity output scaling and encoder emulation.
Resolution programming allows selection of 10, 12, 14, or 16 bit, with
accuracies to 2.3 min. The parallel digital data and the internal
encoder emulation signals (A QUAD B) have independent resolution
control. Internal encoder emulation will permit inhibiting (freezing) the
parallel digital data without interrupting the A and B outputs.
The internal Synthesized Reference section eliminates errors due to
quadrature voltage and ensures operation with a rotor-to-stator phase
shift of up to 45 degrees. The velocity output (VEL) can be used in
place of a tachometer. It has a range of ±4 V relative to analog
ground. The velocity scale factor/tracking rate is programmed with a
single resistor. This converter provides the option of using a second
set of filter components which can be used in dual bandwidth or
switch on the fly applications.
APPLICATIONS
With its low cost, small size, high accuracy, and versatile perfor-
mance, the RD-19230 converter is ideal for use in modern high per-
formance industrial control systems. It is ideal for users who wish to
use a resolver input in their encoder based system. Typical applica-
tions include motor control, machine tool control, robotics, and
process control.
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7382
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
©
1998, 1999 Data Device Corporation
C
bw
R
b
C
bw/
V
E
L
V
E
L
10
R
b
C
bw
S
J
1
S
J
2
RH
RL BIT
C
bw/
10
VEL2 VEL1
SYNTHESIZED
REFERENCE
SHIFT
SIN
-S
-
+
+S
COS
-C
CONTROL
TRANSFORMER
GAIN
-
DEMODULATOR
VEL
-
+
D1 D0
+
+C
R
V
D1
D0
HYSTERESIS
16 BIT
UP/DOWN
COUNTER
VDDP
PCAP
NCAP
VSSP
-5 V
INVERTER
VCO
&
-VCO
TIMING
R CLK
AGND
VDD
GND
VSS
INTERNAL
ENCODER
EMULATION
DATA
LATCH
R SET
EM
EL
INH
D1 D0
A QUAD B A U/B
UP/DN
CB/ZIP
ZIP_EN
BIT 1 - BIT 16
FIGURE 1. RD-19230 SERIES BLOCK DIAGRAM
TABLE 1. RD-19230 SPECIFICATIONS
TABLE 1. RD-19230 SPECIFICATIONS (CONTINUED)
These specs apply over the rated power supply, temperature, and ref-
erence frequency ranges; 10% signal amplitude variation, and 10%
harmonic distortion.
These specs apply over the rated power supply, temperature, and ref-
erence frequency ranges; 10% signal amplitude variation, and 10%
harmonic distortion.
PARAMETER
UNIT
VALUE
PARAMETER
RESOLUTION
UNIT
VALUE
DIGITAL OUTPUTS
Drive Capability
Bits 10, 12, 14, or 16 (note 1 & 2)
50 pF+
CARRIER FREQUENCY
RANGE
Logic 0: 1 TTL load, 1.6 mA
at 0.4 V max.
Logic 1; 10 TTL loads, -0.4
mA at 2.8 V min.
Logic 0; 100 mV max. driving
CMOS
(NOTE 4)
Hz
47-1k
1k - 4k 4k - 10k
ACCURACY -XX2
-XX3 (NOTE 3) Min
REPEATABILITY
Min
4 +1 LSB 4 +1 LSB 5 +1 LSB
2 +1 LSB 2 +1 LSB 3 +1 LSB
LSB
±1
±1
±1
±1
± 2
± 2
DIFFERENTIAL LINEARITY LSB
REFERENCE
Type
Voltage: differential
single ended
(+REF, -REF)
Differential
Vp-p ±10 max. (1 min.)
Vp ±5 max. (0.5 min)
Logic 1; +5 V supply minus
100 mV min. driving
CMOS High Z; 10 µA
|| 5 pF max. (Note 8)
overload
Frequency
Vp ±25 continuous; ±100 transient
Hz DC to 10k
Parallel Data (1-16)
Converter Busy (CB)
10, 12, 14, or 16 parallel
lines; natural binary angle
positive logic (see note 2)
Ω
Vp
Input Impedance
Common Mode Range
10M min. || 20 pf
3
SYNTHESIZED REFERENCE
(note 5)
0.25 to 0.75 µs positive pulse
leading edge initiates counter
update. (CB functions with
ZIP_EN pin tied to +5 V or NC)
Logic 1 at all 0’s
±Sig/Ref Phase Shift Correction deg 45 max. from 400 Hz to 10kHz
SIGNAL INPUT
Type
(+S, -S, SIN, +C, -C, COS)
Resolver, differential,
groundbased
Voltage: operating
overload
Input impedance
Vrms 2 ±15%
Vp
Ω
±25 continuous
10M min || 10 pF.
Zero Index Pulse (ZIP)
Built-In-Test (BIT)
(ZIP_EN pin tied to GND)
Logic 0 for BIT condition.
DIGITAL INPUTS
TTL / CMOS COMPATIBLE
INPUTS
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading = 10 µA max P.U. cur-
rent source to +5 V || 5 pF max.
CMOS transient protected
The BIT error is triggered if
any of the following conditions
exist: ~ ±100 LSB’s of error,
Loss of Signal (LOS), or Loss
of Reference (LOR) is less
than 500 mVp, or a false null
occurs when the phase detect
circuitry causes a BIT and
corrects the error
Inhibit (INH)
Logic 0 inhibits; Data stable
within 150 ns
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
Logic 0 enables; Data stable
within 150 ns
Logic 1 = High Impedance; Data
High Z within 100 ns (Note 8)
A, B
Incremental Encoder Output
(at maximum bandwidth)
DYNAMIC
CHARACTERISTICS
Resolution
Resolution and Mode
Control (D1 & D0)
(See notes 1 & 2)
Mode D1 D0 Resolution
bits
10
12
14
16
Resolver 0
0
1
10 bits
12 bits
14 bits
16 bits
8 bits
10 bits
12 bits
14 bits
Tracking Rate (min)
Bandwidth (Closed Loop)
Ka
A1
A2
A
B
Acceleration (1 LSB lag)
Settling Time (179° step)
VELOCITY
rps
Hz
1152 288
72
18
0
1200 1200 600
300
1
0
2
1/sec
1/sec
1/sec
1/sec
1/sec
5.7M 5.7M 1.4M 360k
19.5 19.5 4.9 1.2
295k 295k 295k 295k
1
1
LVDT -5V
0
0
1
-5V
-5V
2400 2400 1200
1200 1200 600
600
300
2k
-5V -5V
Logic 0 enables ZIP
Logic 1 enables CB
2
2M
2
500k 30k
20
deg/s
msec
ZIP_EN
8
50
CHARACTERISTICS
Polarity
CMOS Compatible Inputs
Logic 0 = 1.5 V max.
Logic 1 = 3.5 V min.
negative voltage = -3.5 V min.
Logic 1 select VEL1 components
Logic 0 select VEL2 components
Positive for increasing angle
±4 (at nominal power supply)
Voltage Range (Full Scale)
Scale Factor Error
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
V
%
10 typ
100 typ
0.75 typ
0.25 typ
5 typ
20 max
200 max
1.3 max
0.50 max
10 max
30 max
8 max
SHIFT
UP/DN
PPM/°C
%
%
mV
µV/°C
kΩ
Logic 1 will increase gain by 4
Logic 0 will decrease gain by 4
-5 V gain remains constant
15 typ
A QUAD B
Logic 0 enables encoder emulation
Falling edge latches encoder
resolution
Data Device Corporation
RD-19230
www.ddc-web.com
3
K-11/02-300
TABLE 1. RD-19230 SPECIFICATIONS (CONTINUED)
THEORY OF OPERATION
These specs apply over the rated power supply, temperature, and ref-
erence frequency ranges; 10% signal amplitude variation, and 10%
harmonic distortion.
The RD-19230 is a mixed signal CMOS IC containing analog
input and digital output sections. Precision analog circuitry is
merged with digital logic to form a complete high-performance
tracking resolver-to-digital converter. For user flexibility and con-
venience, the converter bandwidth, dynamics, and velocity scal-
ing are externally set with passive components.
PARAMETER
UNIT
VALUE
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
(note 6)
+5 (VDD)
±5
V
%
V
-5 (VSS)
±5
-7
+7
mA
25 max. (each), 17 typ.*
(* Typical current is when
a 30K resistor is used for
the current set.)
FIGURE 1 is the RD-19230 Functional Block Diagram. The ana-
log conversion electronics require ±5 VDC power supplies, and
the converter contains a charge pump to provide the user with
the option of a single-ended +5 VDC supply. The converter front-
end consists of differential sine and cosine input amplifiers which
are protected up to ±25 V with 2 kΩ resistors and diode clamps
to the ±5 VDC supplies. By performing the following trigonomet-
ric identity, SINθ(COSφ) - COSθ(SINφ) = SIN(θ-φ), the Control
Transformer (CT) compares the analog input signals ( θ ) with
the digital output ( φ ), resulting in an error signal proportional to
the sin of the angular difference. The CT uses a combination of
amplifiers, switches, logic and capacitors in precision ratios to
perform the calculation.
TEMPERATURE RANGE
Operating
-30X
-20X
Storage
Junction-to-Case
Junction-to-Ambient
Junction Temp Max
°C
°C
°C
°C/W
°C/W
°C
0 to +70
-40 to +85
-65 to +150
20
50
150
PHYSICAL
CHARACTERISTICS
Size: 64-pin Quad Flat Pack in(mm)
WEIGHT
0.52 x 0.52 (13.2 x 13.2)
0.018 ( 0.5 )
oz(g)
TABLE 1 notes:
1. As parallel resolution is reduced, pairs of bits are disabled.
(Unused bits are set to a logic “0.”)
Note:The error output of the CT is normally sinusoidal, but
in LVDT mode, it is triangular (linear) and can be used
to convert any linear transducer output.
• 14 bit resolution: 15/16 disabled
• 12 bit resolution: 13/14, 15/16 disabled
• 10 bit resolution: 11/12, 13/14, 15/16 disabled
2. In LVDT mode, Bit 3 is the MSB and resolution is programmable to
8, 10, 12, and 14 bits.
3. Accuracy in LVDT mode is 0.15% + 1 LSB of full scale.
4. In the frequency range of 47Hz to 1kHz, there will be 1 LSB of jitter
at quadrant boundaries.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. Instead of a traditional precision
resistor network, this converter uses capacitors with precisely
controlled ratios. Sampling techniques are used to eliminate
errors due to voltage drift and op-amp offsets.
5. The maximum phase shift tolerance will degrade linearly from 45
degrees at 400 Hz to 30 degrees at 60 Hz.
6. When using the -5V inverter, the V
supply current will double
DD
and V
can be up to 20% low, or -4V.
SSP
7. || = in parallel with.
8. High Z refers to parallel data only.
9. Normal ESD (Electro Static Device) handling precautions should
be observed.
10. Any unused pins may be left floating (unconnected).
The error processing is performed using the industry standard
technique for Type II tracking converters. The DC error is inte-
grated yielding a velocity voltage which in turn drives a voltage
controlled oscillator (VCO). This VCO is an incremental integra-
tor (constant voltage input to position rate output) which, togeth-
er with the velocity integrator, forms a Type II servo feedback
loop. A lead in the frequency response is introduced to stabilize
the loop and another lag at higher frequency is introduced to
reduce the gain and ripple at the carrier frequency and above.
The settings of the various error processor gains and break fre-
quencies are done with external resistors and capacitors so that
the converter loop dynamics can be easily controlled by the user.
Data Device Corporation
www.ddc-web.com
RD-19230
K-11/02-300
4
TRANSFER FUNCTION AND BODE PLOT
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
The dynamic performance of the converter can be determined
from its Transfer Function Block Diagrams and Bode Plots (open
and closed loop). These are shown in FIGURES 2, 3, and 4.
- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod
with 2 Vrms input)
Cs Fs
1.1 CBW
The open loop transfer function is as follows:
- Integrator Gain =
- VCO Gain =
volts per second per volt
LSBs per second per volt
S
A2
S2
+1
1
(B )
Open Loop Transfer Function =
1.25 RV CVCO
S
+1
(10B )
where: Cs = 10 pF
Fs = 67 kHz when R CLK = 30 kΩ
CVCO = 50 pF
where A is the gain coefficient and A2=A1A2
and B is the frequency of lead compensation.
RV, RB, and CBW are selected by the user to set velocity scaling
and bandwidth.
C
R
BW
B
VEL
C
/10
R
V
BW
VEL SJ1
VEL
-VCO
50 pf
C
VCO
CT
R
1
16 BIT
UP/DOWN
COUNTER
RESOLVER
INPUT
(θ)
+
VCO
GAIN
DEMOD
1
±1.25 V
THRESHOLD
-
C
F
S
S
11 mV/LSB
DIGITAL
OUTPUT
(φ)
H = 1
FIGURE 2.TRANSFER FUNCTION BLOCK DIAGRAM #1
(CRITICALLY DAMPED)
2A
GAIN = 4
OPEN LOOP
ω (rad/sec)
10B
B
A
VELOCITY
OUT
(B = A/2)
GAIN = 0.4
ERROR PROCESSOR
S
VCO
CT
A
S
+ 1
1
A
DIGITAL
POSITION
OUT (φ)
+
2
RESOLVER
INPUT
(θ)
B
e
2 A
S
fBW = BW (Hz) =
2 A
π
S
10B
+ 1
-
2A
2
ω (rad/sec)
CLOSED LOOP
H = 1
FIGURE 4. BODE PLOTS
FIGURE 3.TRANSFER FUNCTION BLOCK DIAGRAM #2
Data Device Corporation
RD-19230
www.ddc-web.com
5
K-11/02-300
GENERAL SETUP CONDITIONS
5) Setup of bandwidth and velocity scaling for the optimized crit-
ically damped case should proceed as follows:
DDC has external component selection software which consid-
ers all the criteria below. In a simple fashion, it asks the key sys-
tem parameters (carrier frequency, resolution, bandwidth, and
tracking rate) needed to derive the external component values.
- Select the desired f BW (closed loop) based on overall
system dynamics.
- Select f
≥ 3.5f BW
carrier
The following recommendations should be considered when
installing the RD-19230 R/D converter:
- Select the applications tracking rate (in accordance with TABLE 3),
and use appropriate values for R SET and R CLK
Full Scale Velocity Voltage
- Compute Rv =
1) In setting the bandwidth (BW) and Tracking Rate (TR) (select-
ing five external components), the system requirements need
to be considered. For the greatest noise immunity, select the
minimum BW and TR the system will allow. Selecting a fBW
that is too low relative to the maximum application tracking
rate can create a spin-around condition in which the convert-
er never settles. The relationship to insure against this condi-
tion is detailed in TABLE 2.
resolution
Tracking Rate (rps) x 2
x 50 pF x 1.25 V
3.2 x Fs (Hz) x 108
- Compute CBW (pF) =
Rv x (f BW)2
- Where Fs = 67 kHz for R CLK = 30 KΩ
100 kHz for R CLK = 20 KΩ
125 kHz for R CLK = 15 KΩ
0.9
CBW x f BW
- Compute RB =
TABLE 2. TRACKING / BW RELATIONSHIP
RPS (MAX)/BW
RESOLUTION
CBW
10
- Compute
1
10
12
14
16
0.50
0.25
0.125
As an example:
2) Power supplies are ±5 VDC. For lowest noise performance it
is recommended that a 0.1 µF or larger cap be connected
from each supply to ground near the converter package.
Calculate component values for a 16-bit converter with 100Hz
bandwidth, a tracking rate of 10 RPS and a full scale velocity
of 4 Volts.
4 V
3) Resolver inputs and velocity output are referenced to AGND.
This pin should be connected to GND near the converter
package. Digital currents flowing through ground will not dis-
turb the analog signals.
- Rv =
= 97655 Ω
10 rps x 216 x 50 pF x 1.25 V
3.2 x 67 kHz x 108
- Compute CBW (pF) =
= 21955 pF
97655 x 100 Hz2
0.9
4) This device has several high impedance amplifier inputs
(+C, -C, +S, -S, -VCO, VEL SJ1, and VEL SJ2) that are sensi-
tive to noise coupling. External components should be con-
nected as close to the converter as possible.
- Compute RB =
= 410 kΩ
21955 x 10 -12 x 100 Hz
6) Using the -5V Inverter will eliminate the need for a -5 V sup-
ply. Refer to FIGURE 5 for the necessary connections.
+5V
33
58
27
VDD
When using the built-in -5 V inverter, the maximum tracking rate
should be scaled for a full-scale velocity output of 3.5 V max.
VDD
VDDP
26
PCAP
+
Notes:
RD-19230
10 µF/10V
24
NCAP
23
16
VSSP
VSS *
1)
Use of the -5 V inverter is not recommended for appli-
cations that require the highest BW and Tracking
Rates.
17
VSS
47 µF/10V
+
25
22
GND
AGND
2)
When using the RD-19230FX with the -5V inverter, the
negative velocity output voltage should be limited to
-3.5 Volts. When performing tracking rate calculations
this must be taken into consideration.
FIGURE 5. -5V INVERTER CONNECTIONS
* Pin 16 has been renamed Vss since it will typically be connected to -5 VDC.
Applications requiring a differential front-end configuration must connect this pin
to Vss. Voltage follower mode can be implemented with pin 16 tied to Vss by mak-
ing external connections between the output of the sin/cos amplifiers and their
respective inputs. When left unconnected, the RD-19230 will internally configure
the front-end amplifiers in voltage follower mode.
Data Device Corporation
RD-19230
www.ddc-web.com
6
K-11/02-300
HIGHER TRACKING RATES AND CARRIER
FREQUENCIES
TABLE 4. CARRIER FREQUENCY (MAX) IN KHZ
RESOLUTION
R SET
R CLK
(Ω)
(Ω)
10
10
10
10
10
12
10
10
10
10
14
7
16
5
Maximum tracking rate is limited by the velocity voltage satura-
tion (nominally 4 V) and the maximum internal clock rate (nomi-
nally 1,333,333 Hz for R CLK = 30k). To achieve higher tracking
rates, a higher internal counting rate must be programmed by
setting RCLK to a value less than 30k. See TABLE 4 for the
appropriate values.
30k** or open
30k
30k
20k
15k
23k
23k
23k
10
10
*
7
10
*
* Not recommended.
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open.
The Rv resistor and an internal 50pF capacitor are configured as
an integrating circuit that resets to zero after a count occurs in
either direction. This circuit acts as a VCO with velocity as its
input and CB as its output. The Rv resistor and an internal 50pF
capacitor determine the maximum rate of the VCO. Rv must be
chosen such that the maximum rate of the VCO is less than the
maximum internal clock rate. Choose the tracking rate in accor-
dance with TABLE 3 to insure this relationship. The rates shown
in TABLE 3 are based on ~90% of the nominal internal clock rate.
The relationship between the velocity voltage and the VCO rate
is given by:
1
Velocity Voltage
VCO Frequency
=
(Rv x 50 pF x 1.25)
INPUT CONFIGURATION
TABLE 3. MAX TRACKING RATE (MIN) IN RPS
The converter input can be configured using either transformers
or thin film networks per the following tables and figures.
RESOLUTION
R SET
(Ω)
R CLK
(Ω)
10
12
14
16
30k** or open
30k
20k
15k
1152 288
72
18
Signal input configuration using 0.02% tol thin film networks add
1 LSB of additional error to accuracy.
23k
23k
1728 432 108 27
2304 576
*
*
Signal input configuration using transformers adds 1 min of addi-
tional error to accuracy.
* Not recommended.
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open.
INPUT TRANSFORMERS
Refer to TABLE 5 to select the proper transformer for Reference,
Synchro and Resolver inputs.
TABLE 5. TRANSFORMERS
ANGLE
ACCURACY***
FIGURE
NUMBER
P/N
TYPE
FREQUENCY (HZ)* IN (VRMS)* OUT (VRMS)**
LENGTH (IN) WIDTH (IN) HEIGHT (IN)
52034
52035
52036
52037
52038
B-426
52039
24133
S - R
S - R
400
400
400
400
400
400
60
11.8
90
2
1
1
0.81
0.81
0.81
0.81
0.81
0.81
1.1
0.61
0.61
0.61
0.61
0.61
0.61
1.14
1.125
0.3
0.3
0.3
0.3
0.3
0.32
.42
.42
6
6
7
7
7
8
9
9
2
R - R
11.8
26
2
1
R - R
2
1
R - R
90
2
3.4
1
Reference
Synchro
Reference
115
90
N/A
1
2
60
115
3/6 ****
N/A
1.125
*
±10% Frequency (Hz) and Line-to-Line input voltage (Vrms) tolerances
** 2 Vrms Output Magnitudes are -2 Vrms ±0.5% full scale
*** Angle Accuracy (Max Minutes)
**** 3 Vrms to ground or 6 Vrms differential (±3% full scale)
Dimensions are for each individual main and teaser
60 Hz Synchro transformers are active (requires ±15 Vdc power supplies)
400 Hz transformer temperature range: -55°C to +125°C
60 Hz transformer temperature ranges: -55°C to +125°C, 0 to +70°C
Data Device Corporation
RD-19230
www.ddc-web.com
7
K-11/02-300
0.61 MAX
(15.49)
0.61 MAX
(15.49)
0.15 MAX
(3.81)
0.09 MAX
(2.29)
0.30 MAX
(7.62)
0.09 MAX
(2.29)
0.15 MAX
(3.81)
1
3
T1A
8
4
7
5
6
11 12
14 15
0.81 MAX
(20.57)
T1B
0.600
(15.24)
10
9
20 19 18 17 16
0.115 MAX
(2.92)
SIDE VIEW
0.100 (2.54) TYP
TOL NON CUM
BOTTOM VIEW
BOTTOM VIEW
TERMINALS
0.025 –0.001 (6.35 –0.03) DIAM
0.125 (3.18) MIN LENGTH
SOLDER PLATED BRASS
PIN NUMBERS FOR REF. ONLY
Dimensions are shown in inches (mm).
T1A
1
6
-SIN
S1
S3
5
3
10
+SIN
SYNCHRO
INPUT
RESOLVER
OUTPUT
T1B
11
16
20
-COS
15
+COS
S2
FIGURE 6. TRANSFORMER LAYOUT AND SCHEMATIC (SYNCHRO INPUT - 52034/52035)
0.61 MAX
(15.49)
0.61 MAX
(15.49)
0.15 MAX
(3.81)
0.09 MAX
(2.29)
0.30 MAX
(7.62)
0.09 MAX
(2.29)
0.15 MAX
(3.81)
1
3
T1A
8
4
5
6
11 12
14 15
0.81 MAX
(20.57)
T1B
0.600
(15.24)
10
9
7
20 19 18 17 16
0.115 MAX
(2.92)
SIDE VIEW
0.100 (2.54) TYP
TOL NON CUM
BOTTOM VIEW
BOTTOM VIEW
TERMINALS
0.025 –0.001 (6.35 –0.03) DIAM
0.125 (3.18) MIN LENGTH
SOLDER PLATED BRASS
PIN NUMBERS FOR REF. ONLY
Dimensions are shown in inches (mm).
T1A
1
6
-SIN
S1
S3
3
10
+SIN
RESOLVER
INPUT
RESOLVER
OUTPUT
T1B
11
16
20
-COS
S4
S2
15
+COS
FIGURE 7. TRANSFORMER LAYOUT AND SCHEMATIC (RESOLVER INPUT - 52036/52037/52038)
Data Device Corporation
www.ddc-web.com
RD-19230
K-11/02-300
8
CASE IS BLACK AND
NON-CONDUCTIVE
0.25
(6.35)
MIN.
1.14 MAX
(28.96)
+
•
•
•
•
+S
0.61 MAX
(15.49)
S3
S1
+15 V
0.32 MAX
(8.13)
*
*
(+15 V) (-R)
*
*
0.125 MIN
(3.17)
0.09 MAX
(2.29)
0.15 MAX
(3.81)
1.14 MAX
(28.96)
0.85 ±0.010
(21.59 ±0.25)
52039
or
24133
1
2
9
3
T1A
8
5
6
(RH)
S2
•
(RL)
(V)
V
•
(+R)
+C
•
(-Vs)
-Vs
•
0.600
(15.24)
0.81 MAX
(20.57)
*
+
(BOTTOM VIEW)
0.42
(10.67)
MAX.
10
7
0.13 ±0.03
(3.30 ±0.76)
0.105 (2.66)
0.21 ±0.3
(5.33 ±0.76)
0.175 ±0.010 (4.45 ±0.25)
NONCUMULATIVE
TOLERANCE
SIDE VIEW
0.100 (2.54) TYP
TOL NON CUM
0.040 ±0.002 DIA. PIN.
SOLDER PLATED BRASS
TERMINALS
BOTTOM VIEW
0.025 ±0.001 (6.35 ±0.03) DIAM
0.125 (3.18) MIN LENGTH
SOLDER-PLATED BRASS
+15 V
+15 V
Dimensions are shown in inches (mm).
Input
RH
Input
S1
Output
+R (RH)
Output
+S
24133
52039
S2
-R (RL)
+C
RL
S3
1
6
V
-Vs
(-15 V)
V
-Vs
(-15 V)
(Analog
Gnd)
(Analog
Gnd)
INPUT
OUTPUT
5
10
The mechanical outline is the same for the synchro input trans-
former (52039) and the reference input transformer (24133),
except for the pins. Pins for the reference transformer are shown
in parenthesis ( ) below. An asterisk * indicates that the pin is
omitted.
FIGURE 9. 60 HZ SYNCHRO AND REFERENCE
TRANSFORMER DIAGRAMS
(SYNCHRO INPUT - 52039 / REFERENCE INPUT - 24133)
FIGURE 8. TRANSFORMER LAYOUT AND SCHEMATIC
(REFERENCE INPUT - B-426)
TYPICAL INPUTS
FIGURES 10 through 14 illustrate typical input configurations.
EXTERNAL
REFERENCE
LO HI
6
1
B-426
10
5
RH
RL
RESOLVER INPUT OPTION
S1
-S SIN
+S
-R +R
1
10
TIA
S3
S4
6
3
+C
-C
RD-19230
11
15
20
TIB
S2
COS
AGND
16
52036(11.8V)
OR
52037(26V)
OR
GND
52038(90V)
OR
SYNCHRO INPUT OPTION
Note: The external BW components
as shown in Figures 1 and 2
are necessary for the R/D to
function.
RH
RL
S1
+S
1
3
10
S3
TIA
TIB
6
5
+C
20
11
S2
15
16
52034(11.8V)
OR
52035(90V)
FIGURE 10. TYPICAL TRANSFORMER CONNECTIONS
Data Device Corporation
RD-19230
www.ddc-web.com
9
K-11/02-300
EXTERNAL
REF
LO HI
R
R
R
1
2
4
R
3
RL RH
See Note 3.
+S
-S
S3
S1
SIN
Note: The external BW components
as shown in Figures 1 and 2
are necessary for the R/D to
function.
COS
-C
+C
See Note 3.
S2
S4
A GND
GND
RESOLVER
Notes:
1) Resistors selected to limit Vref peak to between 1.5 V and 4 V.
2) External reference LO is grounded, then R3 and R4 are not
needed, and -R is connected to GND.
3) 10k ohms, 1% series current limit resistors are recommended.
FIGURE 11. TYPICAL CONNECTIONS, 2 V RESOLVER, DIRECT INPUT
R
1
-S
SIN
S3
S1
+S
R
R
2
Note: The external BW components
as shown in Figures 1 and 2
are necessary for the R/D to
function.
R
1
S2
S4
+C
2
A GND
GND
-C
COS
2
R
2
=
X Volt
R + R
1
2
R + R should not load the Resolver; it is recommended to use an R = 10 kΩ
1
2
2
R + R Ratio errors will result in Angular errors,
1
2
2 cycle, 0.1% Ratio error = 0.029˚ Peak Error.
FIGURE 12. TYPICAL CONNECTIONS, X- VOLT RESOLVER, DIRECT INPUT
Data Device Corporation
www.ddc-web.com
RD-19230
K-11/02-300
10
SIN
3
R
R
f
R
R
i
i
-S
1
6
-
S1
S3
2
5
+S
+
Note: The external BW components
as shown in Figures 1 and 2
are necessary for the R/D to
function.
f
f
4
RESOLVER
INPUT
A GND
COS
13
R
R
R
i
i
-C
15
16
7
-
S4
S2
+C
+
8
10
R
f
12
CONVERTER
S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GND at the converter.
For DDC-49530: R = 70.8 KΩ, 11.8 V input, synchro or resolver.
i
For DDC-49590: R = 270 KΩ, 90 Volt input, synchro or resolver.
i
Maximum additional error is 1 minute.
When using discrete resistors: Resolver L-L voltage =
R
R
i
f
x 2 Vrms, where R ≥ 6 kΩ
f
FIGURE 13. DIFFERENTIAL RESOLVER INPUT, USING DDC-49530 (11.8 V) OR DDC-49590 (90 V),
OR (2 V) DIRECT USING DISCRETE RESISTORS
SIN
3
R
f
R
i
-S
1
6
-
S1
S3
2
5
R
i
+S
+
Note: The external BW components
as shown in Figures 1 and 2
are necessary for the R/D to
function.
R
f
4
A GND
SYNCHRO
INPUT
COS
14
R
R
i
i
16
7
R /
f
3
8
15
-C
15
-
R /2
i
+C
10
9
+
S2
R /
f
3
11
CONVERTER
S1, S2, S3 should be triple twisted shielded; RH and RL should be twisted shielded;
In both cases the shield should be tied to GND at the converter.
11.8 Volt input = DDC-49530: R = 70.8 KΩ, 11.8 V input, synchro or resolver.
i
90 Volt input = DDC-49590: R = 270 KΩ, 90 Volt input, synchro or resolver.
i
Maximum additional error is 1 minute.
When using discrete resistors: Resolver L-L voltage =
R
R
i
f
x 2 Vrms, where R ≥ 6 kΩ
f
FIGURE 14. SYNCHRO INPUT, USING DDC-49530 (11.8 V) OR DDC-49590 (90 V)
Data Device Corporation
www.ddc-web.com
RD-19230
K-11/02-300
11
DC INPUTS
UP/DN
The UP/DN input selects the gain of the amplifier driving the de-
selected set of bandwidth components. UP/DN has three input
states. See TABLE 6 to relate input to gain.
As noted in TABLE 1, the RD-19230 will accept DC inputs. It is
necessary to set the REF input to DC by tying RH to +5 V and
RL to GND or -5 \/.
TABLE 6. PRECHARGE AMPLIFIER
GAIN PROGRAMMING
VELOCITY TRIMMING
UP/DN
Logic 1
Logic 0
-5 V
GAIN
4
FUNCTION
RD-19230 specifications for velocity scaling, reversal error, and
offset are listed in TABLE 1. Velocity scaling and offset are exter-
nally trimmable for applications requiring tighter specifications
than those available from the standard unit. FIGURE 15 shows
the setup for trimming these parameters with external pots. It
should also be noted that when the resolution is changed, VEL
Scaling is also changed.
Resolution Increase
Resolution Decrease
Dual Bandwidth
1/4
1
BENEFIT OF SWITCHING RESOLUTION
ON THE FLY
Switching resolution on the fly can be used in applications that
require high resolution for accurate position control, and tracking
rates or settling times that are faster than the high resolution
mode will allow.
OPTIONAL BANDWIDTH COMPONENTS
The RD-19230 provides the option of using a second set of
bandwidth components. The second set of components can be
used for switch-on-the-fly or dual-bandwidth applications. The
SHIFT and UP/DN inputs are used when switching bandwidth
components, and their operation is described below. Refer to the
block diagram, FIGURE 1.
The RD-19230 can track four times faster for each step down in
resolution (i.e., a step from 16 bits to 14 bits). The velocity out-
put will be scaled down by a factor of four with each step down
in resolution. For example, if the velocity output is scaled such
that 4 Volts = 10 RPS in 16 bit resolution, then the same con-
verter will output 1 Volt for 10 RPS in 14 bit resolution. To avoid
glitches in the velocity output, the second set of bandwidth com-
ponents can be pre-charged to the expected voltage, and
switched in using the SHIFT input at the same time the resolu-
tion is changed. This will allow for a smooth velocity transition,
resulting in reduced errors and minimal settling time after the
change.
SHIFT
The SHIFT pin is an input that chooses between the VEL1 and
VEL2 bandwidth components. This pin has an internal pull-up to
+5V. When the SHIFT pin is left open, or a logic 1 is applied, the
VEL1 components are selected. When a Logic 0 is applied, the
VEL2 components are selected. The deselected set of band-
width components are driven by an amplifier, with programmable
gain, that follows the velocity amplifier. This amplifier can be
used to pre-charge the deselected set of components to the volt-
age level that is expected after a change in resolution. (See
description on BENEFIT OF SWITCHING RESOLUTION ON
THE FLY.)
FIGURE 17 shows the way the converter behaves during a
change in resolution while tracking at a constant velocity. The
first illustration shows the benefits of switching in pre-charged
components while changing resolution. The second illustration
shows the result without the benefits of switching on the fly.
The signals that have been recorded are:
1) VEL: velocity output pin on the RD-19230
+5 V
100 R
V
2
100 kΩ
(OFFSET)
-VCO
2) ERROR: this is the analog representation of the error between
the input and the output of the RD-19230
-5 V
0.8 R
V
RD-19230
3) D0: an input resolution control line to the RD-19230
4) BIT: built-in-test output pin of the RD-19230
0.4 R (SCALING)
V
1
VEL
When this system uses the switch resolution on the fly imple-
mentation, the velocity signal immediately assumes the pre-
charged level of the second set of components, resulting in small
FIGURE 15. VELOCITY TRIMMING
Data Device Corporation
www.ddc-web.com
RD-19230
K-11/02-300
12
errors and reduced settling times. Notice that the BIT output,
in FIGURE 17, does not indicate a fault condition.
ble switching times. See FIGURE 16 for an example of the
input wiring connections necessary for switching on the fly
between 14 and 16 bit resolution.
When this system type does not use the switch resolution on the
fly implementation, large errors and increased settling times
result. The errors exceed 100 LSBs causing the BIT to flag for a
fault condition.
DUAL BANDWIDTHS
With the second set of BW component pins, the user can set two
bandwidths for the RD-19230 and choose between them. To use
two bandwidths, proceed as follows:
SWITCH ON THE FLY IMPLEMENTATION
The following steps detail switching resolution on the fly.
1) Tie UP/DN to pin -5V.
1) The SHIFT pin should be controlled synchronously with the
change in resolution. When shift is logic high, the VEL1 com-
ponents will be selected. When shift is logic 0, the VEL2 com-
ponents will be selected.
2) Choose the two bandwidths following the guidelines in the
General Setup Considerations; the RV resistor must be the
same value for both bandwidths.
3) Use the SHIFT pin to choose between bandwidths. A logic 1
selects the VEL1 components and a logic 0 selects the VEL2
components.
2) The second set of BW components (CBW2, RB2, CBW2/10
should typically be of the same value as the first set (CBW1
B1, CBW1/10,) and should be installed on VEL2 and VEL SJ2.
)
,
R
Note: Each set of bandwidth components must be chosen to
insure that the tracking rate to BW ratio (listed in
TABLE 2) is not exceeded for the resolution in which
it will be used.
With Switch Resolution on the Fly Implemented
0V
VEL
3) UP/DN will program the direction of the gain. If the resolution
is increasing (UP/DN logic 0), the gain of the pre-charge
amplifier should be set to four. If the resolution is decreasing
(UP/DN logic 1), the gain should be set to 1/4. The gain of the
pre-charge amplifier should be programmed prior to switching
the resolution of the converter, allowing enough time for the
components to settle to the pre-charged level. This time will
depend on the time constant of the bandwidth components
being charged. If switching is limited to two adjacent resolu-
tions (i.e., 14 and 16) then the pre-charge amplifier can be set
up to continuously maintain the appropriate velocity voltage
on the deselected components, resulting in the fastest possi-
-5V
0˚
ERROR
5V
D0
0V
5V
BIT
0V
ERROR = 13.6 LSBs per box
Without Switch Resolution on the Fly Implemented
0V
VEL
-5V
+5V
0˚
ERROR
D1
RD-19230
5V
D0
0V
D0
58
SHIFT
5V
27
UP/DN
BIT
0V
ERROR = 1500 LSBs per box
FIGURE 17. BENEFIT OF SWITCHING
RESOLUTION ON THE FLY
FIGURE 16. INPUT WIRING - SWITCHING ON THE FLY
BETWEEN 14 AND 16 BIT RESOLUTION
Data Device Corporation
RD-19230
www.ddc-web.com
13
K-11/02-300
INHIBIT, ENABLE, AND CB TIMING
An example circuit to create a low going edge of A_QUAD_B is
depicted in Figure 23B. A time constant greater than 50ns
should be considered.
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 18,
angular output data is valid 150 ns maximum after the applica-
tion of the negative inhibit pulse.
The resolution of the incremental outputs is latched from the D0
and D1 inputs on the low going edge of A_QUAD_B. The resolu-
tion of the parallel data outputs may be changed any time after
the encoder resolution is latched (see FIGURE 23).
Output angle data is enabled onto the tri-state data bus in two
bytes. Enable MSBs (EM) is used for the most significant 8 bits
and Enable LSBs (EL) is used for the least significant 8 bits. As
shown in FIGURE 19, output data is valid 150 ns maximum after
the application of a negative enable pulse. The tri-state data bus
returns to the high impedance state 100 ns maximum after the
rising edge of the enable signal.
When in A_QUAD_B mode, the resolution of the parallel data
can be changed to a resolution equal to or greater than the
A_QUAD_B resolution setting only. For example if the
A_QUAD_B mode is active and the resolution is set to 12-bits,
the resolution of the parallel programmed data can be changed
using D0 & D1 to 14 or 16-bits only. If 10-bit mode is required for
the parallel data, the A_QUAD_B resolution must also be pro-
grammed to 10-bits.
The Converter Busy (CB) signal indicates that the tracking con-
verter output angle is changing 1 LSB. As shown in FIGURE 20,
output data is valid 50 nS maximum after the middle of the CB
pulse. CB pulse width is 1/40 FS, which is nominally 375 ns.
Note: The encoder resolution must be less than or equal to
the resolution of the parallel data outputs. Refer to
FIGURE 21.
INHIBIT
The timing of the A, B and ZIP (or North Reference Pole [NRP])
output is dependent on the rate of change of the
synchro/resolver position (rps or degrees per second) and the
encoder resolution latched into the RD-19230 (refer to
FIGURE 22). The calculations for the timing are:
150 nsec max
DATA
DATA
VALID
FIGURE 18. INHIBIT TIMING
n = resolution of parallel data
t = 1 / ( 2n* Velocity(RPS))
T = 1 / ( Velocity(RPS))
ENABLE
100 nsec MAX
HIGH Z
150 nsec MAX
DATA
VALID
DATA
HIGH Z
Note: The Z1 pulse is high when all the bits of the counter
are zero. If the resolution of the counter, (parallel data) is
programmed differently than that of the A_QUAD_B then the
resolution of the counter will determine the resolution of the
ZIP.
FIGURE 19. ENABLE TIMING
250 to 750 nsec
CB
50 nsec
DATA
VALID
DATA
VALID
DATA
CLARIFICATION OF A_QUAD_B, U/B AND
ZIP_EN FUNCTIONS
FIGURE 20. CONVERTER BUSY TIMING
INTERNAL ENCODER EMULATION
The RD-19230 is a tracking converter which is designed with a
Type II closed servo loop. The Type II closed servo loop has an
internal incremental integrator. This integrator acts as an up-
down position counter. An AC error (e) within the RD-19230 rep-
resents the difference between θ (current angle to be digitized)
and φ (the angle stored in digital form in the up-down counter).
Because the RD-19230 constitutes in itself a Type II closed loop
servomechanism, it continuously attempts to null the error to
zero. This is accomplished by counting up or down 1 LSB until φ
is equal to θ thus having an error of zero.
The RD-19230 can be programmed to encoder emulation mode
by toggling the A_QUAD_B input to a logic 0. The U/B output pin
becomes B (LSB XOR LSB + 1). The A (LSB + 1) and B output
signals can be used in control systems that are designed to inter-
face with incremental optical encoders. To enable the Zero Index
pulse, ZIP_EN should be tied to a logic 0.
Data Device Corporation
RD-19230
www.ddc-web.com
14
K-11/02-300
B(X- or LSB & LSB+1)
A (LSB+1)
When A_QUAD_B is logic 0, encoder emulation mode is select-
ed (i.e. The U/B output [Pin 29] is programmed to B). The
encoder emulator resolution is set on the falling edge of
A_QUAD_B (see TABLE 7).
2t
ZIP (NRP)
t
TABLE 7. A_QUAD_B (PIN 30) FUNCTION
A_QUAD_B (PIN 30)
U/B (PIN 29)
T
359.95
0
0
1
B
U
FIGURE 22. INCREMENTAL ENCODER EMULATION
TABLE 8. ZIP_EN (PIN 55) FUNCTION
ZIP_EN (PIN 55)
CB/ZI (PIN 31)
DATA
D0/D1
VALID
0
1
ZI
CB
50 nsec
When A_QUAD_B is logic 1, encoder emulation mode is not
selected (i.e. The U/B output is set to U, which indicates the
direction of the internal position counter).
A QUAD B
FIGURE 23A. TIMING FOR INCREMENTAL ENCODER
EMULATION RESOLUTION CONTROL
Note: U indicates the direction of the counter. It stands for
“UP”. If the RD-19230 is at a static angle awaiting a
new angle θ, U indicates the direction the counter was
going to get to the current angle φ. As the error is
approaching zero, the internal analog circuitry voltage
may over shoot before settling - which would then
indicate an incorrect direction. Because of this over
shoot, the U output should not be relied on after set-
tling to a static state. Only during active resolver
movement will the U output state be reliable. U is a
logic 1 when going in the positive direction (increas-
ing angle). It is a logic 0 when going in the negative
direction (decreasing angle). This is the same as it is
in the RDC-19220.
+5V
C
A quad B
R
~
= RC
(ie. 50ms = 50Kohms x 1µf)
FIGURE 23B. EXAMPLE CIRCUIT FOR A QUAD B
RESET
ZIP_EN chooses between the CB and Zero Index pulse outputs
and is independent of encoder emulation mode. A logic 1
enables the CB pulse, a logic 0 enables the Zero Index pulse
(see TABLE 8).
Note: When the RD-19230FX is set for 16-bit mode, the LSB
is bit 16. When the RD-19230FX is set for 14-bit mode,
the LSB is bit 14 and bits 15 and 16 are set to logic“0”.
(See TABLE 1, NOTE 1).
RD-19230
1
MSB
2
3
4
5
6
7
8
SYNTHESIZED REFERENCE
9
10
11
The synthesized reference section of the RD-19230 eliminates
errors due to phase shift between the reference and signal
inputs. Quadrature voltages in a resolver or synchro are by def-
inition the resulting 90° fundamental signal in the nulled out error
voltage (e) in the converter. Due to the inductive nature of syn-
chros and resolvers, their output signals lead the reference input
signal (RH and RL). When an uncompensated reference signal
is used to demodulate the control transformer’s output, quadra-
ture voltages are not completely eliminated. As shown in
12
13
14
15
BIT 16 LSB
1
0
1
2
1
4
1
6
A
B
FIGURE 21. INCREMENTAL ENCODER EMULATION
RESOLUTION CONTROL
Data Device Corporation
RD-19230
www.ddc-web.com
15
K-11/02-300
the block diagram, FIGURE 1, the converter synthesizes its own
internal reference signal based on the SIN and COS signal
inputs. Therefore, the phase of the synthesized (internal) refer-
ence is determined by the signal input, resulting in reduced
quadrature errors.
the LVDT. The value of scaling constant “b” is selected to provide
an input of 1 Vrms at null of the LVDT. Suggested components
for implementing the input scaling circuit are a quad op-amp,
such as a OP11 type, and precision thin-film resistors of 0.1%
tolerance. FIGURE 24 illustrates a 2-wire LVDT configuration.
Data output of the RD-19230 is Binary Coded in LVDT mode.The
most negative stroke of the LVDT is represented by ALL ZEROS
and the most positive stroke of the LVDT is represented by ALL
ONES.The most significant 2 bits (2 MSBs) may be used as over-
range indicators. Positive overrange is indicated by code “01” and
negative overrange is indicated by code “11“ (see TABLE 9).
BUILT-IN-TEST (BIT)
The BIT output is active low, and is triggered if any of the follow-
ing conditions exist:
1) Loss of Signal (LOS) - Sin and Cos inputs both less than
500mV.
2) Loss of Reference (LOR) - Reference Input less than 500 mV.
TABLE 9. 12-BIT LVDT OUTPUT CODE
FOR FIGURE 25
3) Excessive Error - This error is detected by monitoring the
demodulator output, which is proportional to the difference
between the analog input and digital output. When it exceeds
approximately 100 LSBs (in the selected resolution), BIT will
be asserted. This condition can occur any time the analog
input changes at a rate in excess of the maximum tracking
rate. During power up, the converter may see a large differ-
ence between the sin/cos inputs and the digital output angle
held in its counter. BIT will be asserted until the converter set-
tles within ~ 100 LSB’s of the final result.
LVDT OUTPUT
MSB
LSB
+ over full travel
+ full travel -1 LSB
+0.5 travel
+1 LSB
null
- 1 LSB
-0.5 travel
- full travel
- over full travel
01
00
00
00
00
00
00
00
11
xxxx
1111
1100
1000
1000
0111
0100
0000
xxxx
xxxx
1111
0000
0000
0000
1111
0000
0000
xxxx
xxxx
1111
0000
0001
0000
1111
0000
0000
xxxx
4) 180° phase error input signal to reference input (false null)
causes a BIT plus kickstarts the converter counter to correct
the error.
The LOS has a filter on it to filter out the reference. Since the
lowest specified reference frequency is 47 Hz (~27 mS), the
filter must have a time constant long enough to filter this out.
Time constants of 50 mS or more are possible.
C1
SIN
aR
A 500 µs dynamic delay occurs before the error BIT becomes
active. This dynamic delay is responsive to the active filter
loop.
-S
2 WIRE LVDT
R
-
R
+S
REF IN
R
+
FS = 2 V
aR
C2
COS
bR
R
LVDT MODE
R
2R
-C
R
R
As shown in TABLE 1, the RD-19230 unit can be made to oper-
ate as an LVDT-to-digital converter. In this mode the RD-19230
functions as a ratiometric tracking linear converter. When linear
AC inputs are applied from a LVDT the converter operates over
one quarter of its range. This results in two less bits of resolution
for LVDT mode than are provided in resolver mode.
-
2R
+C
+
2 V
R
bR
+RH
-RL
C
= C , set for phase lag = phase lead through the LVDT.
2
1
LDVT output signals need to be scaled to be compatible with the
converter input. FIGURE 25 is a schematic of an input scaling
circuit applicable to 3-wire LVDTs. The value of the scaling con-
stant “a” is selected to provide an input of 2 Vrms at full stroke of
FIGURE 24. 2-WIRE LVDT DIRECT INPUT
Data Device Corporation
RD-19230
www.ddc-web.com
16
K-11/02-300
aR
SIN
-S
R
R
V
B
-
R'
R'
+S
+
R'
aR
bR
R
2R'
COS
-C
R
-
V
A
R'
R/2
2R'
+
+C
+RH
-RL
bR
Notes:
1. R' ≥ 10 kΩ
2. Consideration for the value of R is LVDT loading.
1
null
1
VB
b =
=
VA
null
RDC-19230
INPUT
LVDT
OUTPUT
2
a =
2V
SIN
(VA - VB) max
V
A
1V
a
SIN = 1+ (VA - VB)
2
V
B
COS
+FS
+FS
NULL
-FS
-FS
NULL
a
COS = 1- (VA - VB)
2
FIGURE 25. 3-WIRE LVDT SCALING CIRCUIT
Data Device Corporation
www.ddc-web.com
RD-19230
K-11/02-300
17
TABLE 10. RD-19230 PINOUTS
#
1
NAME
#
NAME
VSS (-5V)
#
NAME
VDD (+5V)
N/C
#
NAME
VEL
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Bit 8
2
-VCO
TP3 (test point)
R CLK
R SET
ENM
Bit 16
3
SJ1
Bit 9
A (LSB + 1)
TP4 (test point)
N/C
4
SJ2
Bit 2
5
SHIFT
Bit 10
Bit 3
6
VEL2
AGND
VSSP
TP5 (test point)
ZIP_EN
TP6 (test point)
ENL
7
TP1 (test point)
Bit 11
Bit 4
8
VEL1
NCAP
GND
9
TP2 (test point)
N/C
10
11
12
13
14
15
16
+C
PCAP
Bit 12
Bit 5
VDD (+5V)
UP/DN
D0
COS
-C
VDDP
BIT
Bit 13
Bit 6
+S
U/B
D1
SIN
A_QUAD_B
CB (ZI)
Bit 1
Bit 14
Bit 7
INH
-S
RH
VSS (-5V)
Bit 15
RL
NOTES:
1. See FIGURE 5 for +5 V only operation.
0.078+0.004
-0.002
2.00+0.10
-0.05
(
)
17
32
0.096MAX
(2.45MAX)
16
33
0.0098MIN,0.0197MAX
(0.25MIN,0.50MAX)
0.0197
(0.50)
0.520±0.010
(13.2±0.25)
RD-19230FX
-XXX
0.394±0.004
(10.00±0.10)
*
Date Code
pin1
48
0.0098MIN,0.0197MAX
(0.25MIN,0.50MAX)
0.096MAX
(2.45MAX)
49
64
0.394±0.004
(10.00±0.10)
0.007MAX
(0.17MAX)
*
0.008
(0.22)
0.520±0.010
(13.2±0.25)
0.035+0.006
-0.004
0.88+0.15
(
)
-0.10
Dimensions shown are in inches (millimeters).
Mechanical Design done in millimeters.
DIMENSIONS SHOWN ARE TO
DOTTED LINES
*
FIGURE 26. RD-19230 MECHANICAL OUTLINE
Data Device Corporation
RD-19230
www.ddc-web.com
18
K-11/02-300
TABLE 11. FRONT-END THIN-FILM RESISTOR
NETWORKS(SEE FIGURE 28)
16
15
14
13
12
11
10
9
DDC-49530, DDC-57470 RESISTOR VALUES (11.8 V INPUTS)
SYMBOL
ABS
VALUE
TOL
(%)
REL TO
REL
VALUE
TOL TCR(PPM)
(%)
R1
R2
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
70.8 k
0.1
25
R1
R4
12 k
12 k
0.02
0.02
0.02
0.02
0.02
2
2
2
2
2
2
2
2
2
2
1
2
3
4
5
6
7
8
R1
70.8 k
70.8 k
35.4 k
FIGURE 27. (DDC-55688)
LAYOUT AND RESISTOR VALUES
(R1 AND R2 = 10 K 1.0% TOL,
R1
R1
Ω
R6
6.9282 k 0.02
5.0718 k 0.02
ABSOLUTE TC = ±100 PPM MAX)
R6
R11
R11
R1
5.0718
6.9282 k 0.02
70.8 k 0.02
0.02
DDC-49590 RESISTOR VALUES (90 V INPUTS)
270 k 0.1
16
15
R10
14
R9
13
12
R8
11
R7
10
R6
9
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
25
2
2
2
2
2
2
2
2
2
2
R1
R4
6 k
0.02
0.02
0.02
0.02
0.02
R11
6 k
R1
270 k
270 k
135 k
R1
R2
R3
R4
R5
R1
R1
R6
3.4641 k 0.02
2.5359 k 0.02
2.5359 k 0.02
3.4641 k 0.02
1
2
3
4
5
6
7
8
R6
R11
R11
R1
FIGURE 28. (DDC-49530, DDC-49590, DDC-57470)
LAYOUT AND RESISTOR VALUES (SEE TABLE 11)
270 k
0.02
0.870 MAX
(22.10)
.405
7˚
45˚
0.250 ±0.005
(6.35 ±0.13)
0.299
(7.6)
0.101
(2.6)
0.406
(10.3)
0.320 - 0.300
(8.13 - 7.62)
0.014
(.36)
0.13 ±0.005
(3.30 ±0.13)
0.342
(8.7)
0.009
(0.23)
0.092
(2.3)
0.015 ±0.009
(0.38 ±0.23)
0.020 MIN
(0.51)
0.125 MIN
(3.18)
0.075 ±0.015
(1.91 ±0.38)
0.018 ±0.003
(0.46 ±0.08)
0.016
(0.40)
+0.025
0.325
0.050
(1.27)
-0.015
0.100 TYP
(2.54)
+0.64
(8.26
)
-0.38
DIMENSIONS SHOWN ARE IN INCHES (MM).
DIMENSIONS SHOWN ARE IN INCHES (MM).
FIGURE 29. 16-PIN THIN-FILM RESISTOR NETWORK
DIP MECHANICAL OUTLINE
FIGURE 30. 16-PIN THIN-FILM RESISTOR NETWORK
FLAT-PACK MECHANICAL OUTLINE
(DDC-57470)
(DDC-49530, DDC-49590, DDC-55688)
Data Device Corporation
RD-19230
www.ddc-web.com
19
K-11/02-300
0.810 MAX
XXX-XXX
0.305 MAX
0.200 MAX
0.300 ±0.10
DATECODE
Pin #1
0.125 MIN
0.100 TYP
0.820 MAX
XXX-XXX
0.260 ±0.010
0.200 MAX
DATECODE
Pin #1
0.325 ±0.010
0.125 MIN
0.010 TYP
0.087 MAX
0.100 TYP
DIMENSIONS SHOWN ARE IN INCHES
FIGURE 31. 16-PIN THIN-FILM RESISTOR NETWORK DIP MECHANICAL OUTLINE
(ALTERNATIVE CERAMIC PACKAGE FOR DDC-49590)
Data Device Corporation
RD-19230
www.ddc-web.com
20
K-11/02-300
NOTES:
Data Device Corporation
RD-19230
www.ddc-web.com
21
K-11/02-300
NOTES:
Data Device Corporation
RD-19230
www.ddc-web.com
22
K-11/02-300
NOTES:
Data Device Corporation
RD-19230
www.ddc-web.com
23
K-11/02-300
ORDERING INFORMATION
RD-19230FX-X X X X
Supplemental Process Requirements:
T = Tape and Reel (50 pc. min. order)
Accuracy:
2 = 4 min + 1 LSB
3 = 2 min + 1 LSB
Reliability:
0 = Standard DDC Procedures
Operating Temperature Range:
2 = -40° to +85°C
3 = 0° to +70°C
Notes:
1) DDC reserves the right to supply ceramic packages in place of plastic packages.
2) Consult factory for External Component Selection Software.
3) DDC does not recommend Tape and Reel due to potential lead damage.
THIN-FILM RESISTOR NETWORKS:
DDC-49530 = 11.8 V input, DIP package
DDC-57470 = 11.8 V input, Flat-pack package
DDC-49590 = 90 V input, DIP package
DDC-55688 = 2 V direct, DIP package
COMPONENT SELECTION SOFTWARE:
Component selection software can be downloaded from our website ( www.ddc-web.com )
Evaluation Card Available
P/N RD19230EX-300 (See the DDC website for this card’s user guide)
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2482
For Technical Support - 1-800-DDC-5757 ext. 7382
Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358
Southeast, U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610
West Coast, U.S.A. - Tel: (714) 895-9777, Fax: (714) 895-4988
United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
Ireland - Tel: +353-21-341065, Fax: +353-21-341568
France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425
Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://www.ddc-web.com
U
®
DATA DEVICE CORPORATION
REGISTERED TO ISO 9001
FILE NO. A5976
K-11/02-300
24
PRINTED IN THE U.S.A.
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