PC87312_技术文档

October 1993

PC87311A/PC87312 (SuperI/O^TMII/III)

Floppy Disk Controller with Dual UARTs,

Parallel Port, and IDE Interface

General Description

Features

100% compatible with IBM PC, XT, and AT architec-

tures (PC87311A), or ISA, EISA, and Micro Channel ar-

chitectures (PC87312)

Y

The PC87311A/12 incorporates a floppy disk controller

(FDC), two full function UARTs, a bidirectional parallel port,

and IDE interface control logic in one chip. The PC87311A

includes standard AT/XT address decoding for on-chip

functions and a Configuration Register, offering a single

Y

FDC:

Ð Software compatible with the DP8473, the 765A and

the N82077

chip solution to the most commonly used IBM PC

,

PC-XT , and PC-AT peripherals. The PC87312 includes

É

Ð 16-byte FIFO (default disabled)

Ð Burst and Non-Burst modes

É

standard AT address decoding for on-chip functions and a

Configuration Register set, offering a single chip solution to

the most commonly used ISA, EISA and Micro Channel pe-

ripherals.

Ð Perpendicular Recording drive support

Ð High performance internal analog data separator (no

external filter components required)

Ð Low power CMOS with power down mode

UARTs:

Ð Software compatible with the INS8250N-B and the

NS16450 (PC87311A), or PC16550A and PC16450

(PC87312)

The on-chip FDC is software compatible to the PC8477,

which contains a superset of the DP8473 and NEC mPD765

and the N82077 floppy disk controller functions. The on-

chip analog data separator requires no external compo-

nents and supports the 4 Mb drive format as well as the

other standard floppy drives used with 5.25 and 3.5 me-

Y

Parallel Port:

Ð Bidirectional under either software or hardware

control

×

dia.

In the PC87311A, the UARTs are equivalent to two

INS8250N-Bs or NS16450s. The bidirectional parallel port

maintains complete compatibility with the IBM PC, XT and

AT. In the PC87312 the UARTs are equivalent to two

NS16450s or PC16550s. The bidirectional parallel port

maintains complete compatibility with the ISA, EISA and Mi-

cro Channel parallel ports.

Ð Compatible with all IBM PC, XT and AT architectures

(PC87311A), or all ISA, EISA, and Micro Channel ar-

chitectures (PC87312)

Ð Back Voltage protection circuit against damage

caused when printer is powered up

IDE Control Logic:

Ð Provides a complete IDE interface except for option-

al buffers

Y

The IDE control logic provides a complete IDE interface ex-

cept for the signal buffers. The Configuration Registers con-

sist of three byte-wide registers. An Index and a Data Regis-

ter which can be relocated within the ISA I/O address space

access the Configuration Registers.

Address Decoder:

Ð Provides selection of all primary and secondary ISA

addresses including COM 1–4.

100-pin PQFP package

Ð The PC87311A and PC87312 are pin compatible

Block Diagram

TL/F/11362–1

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

SuperI/O^TMis a trademark of National Semiconductor Corporation.

IBMÉ, PCÉ, PC-ATÉ, PC-XTÉ and PS/2É are registered trademarks of International Business Machines Corporation.

C

1995 National Semiconductor Corporation

TL/F/11362

RRD-B30M75/Printed in U. S. A.

Table of Contents

1.0 PIN DESCRIPTIONÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ6

4.2.10 Read Deleted Data Command ÀÀÀÀÀÀÀÀÀÀ36

4.2.11 Read ID Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ36

4.2.12 Read A Track Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ36

4.2.13 Recalibrate Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ36

4.2.14 Relative Seek CommandÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ36

4.2.15 Scan CommandsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ37

4.2.16 Seek CommandÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ37

4.2.17 Sense Drive Status Command ÀÀÀÀÀÀÀÀÀÀ37

4.2.18 Sense Interrupt Command ÀÀÀÀÀÀÀÀÀÀÀÀÀ37

4.2.19 Set Track CommandÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38

4.2.20 Specify CommandÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38

4.2.21 Verify Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39

4.2.22 Version Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39

4.2.23 Write Data CommandÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39

4.2.24 Write Deleted Data Command ÀÀÀÀÀÀÀÀÀÀ40

2.0 CONFIGURATION REGISTERS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12

2.1 OverviewÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12

2.2 Software ConfigurationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12

2.3 Hardware Configuration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12

2.4 Index and Data RegistersÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14

2.5 Base Configuration Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14

2.5.1 Function Enable Register (FER) ÀÀÀÀÀÀÀÀÀÀÀÀ14

2.5.2 Function Address Register (FAR)ÀÀÀÀÀÀÀÀÀÀÀ16

2.5.3 Power and Test Register (PTR)ÀÀÀÀÀÀÀÀÀÀÀÀÀ16

2.6 Power Down Options ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ16

2.7 Power Up Procedure and Considerations ÀÀÀÀÀÀÀÀÀ17

2.7.1 Crystal StabilizationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17

2.7.2 UART Power-Up ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17

2.7.3 FDC Power-UpÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17

5.0 FDC FUNCTIONAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ40

3.0 FDC REGISTER DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17

5.1 Microprocessor InterfaceÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ40

5.2 Modes of Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ41

5.3 Controller Phases ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ41

5.3.1 Command PhaseÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ41

5.3.2 Execution Phase ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ41

5.3.2.1 DMA ModeÐFIFO Disabled ÀÀÀÀÀÀÀ41

3.1 Status Register A (SRA)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ18

3.1.1 SRAÐPS/2 ModeÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ19

3.1.2 SRAÐModel 30 Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ19

3.2 Status Register B (SRB)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ19

3.2.1 SRBÐPS/2 ModeÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ19

3.2.2 SRBÐModel 30 Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ19

3.3 Digital Output Register (DOR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ20

3.4 Tape Drive Register (TDR)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ20

3.5 Main Status Register (MSR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ20

3.6 Data Rate Select Register (DSR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ21

3.7 Data Register (FIFO)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ22

3.8 Digital Input Register (DIR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ22

3.8.1 DIRÐPC-AT Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ22

3.8.2 DIRÐPS/2 Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ22

3.8.3 DIRÐModel 30 Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ22

3.9 Configuration Control Register (CCR) ÀÀÀÀÀÀÀÀÀÀÀÀ23

3.9.1 CCRÐPC-AT and PS/2 Modes ÀÀÀÀÀÀÀÀÀÀÀÀ23

3.9.2 CCRÐModel 30 Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ23

3.10 Result Phase Status Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ23

3.10.1 Status Register 0 (ST0) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ23

3.10.2 Status Register 1 (ST1) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ23

3.10.3 Status Register 2 (ST2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ24

3.10.4 Status Register 3 (ST3) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ24

5.3.2.2 DMA ModeÐFIFO Enabled ÀÀÀÀÀÀÀÀ42

5.3.2.3 Interrupt ModeÐFIFO Disabled ÀÀÀÀ42

5.3.2.4 Interrupt ModeÐFIFO Enabled ÀÀÀÀÀ43

5.3.2.5 Software Polling ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ43

5.3.3 Result Phase ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ43

5.3.4 Idle PhaseÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ43

5.3.5 Drive Polling PhaseÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ43

5.4 Data Separator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ43

5.5 Crystal OscillatorÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ45

5.6 Perpendicular Recording Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ46

5.7 Data Rate Selection ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ47

5.8 Write Precompensation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ47

5.9 FDC Low Power Mode LogicÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ47

5.10 Reset Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ47

6.0 SERIAL PORTS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ48

6.1 Introduction ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ48

6.2 PC87311A Serial PortsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ48

6.2.1 Serial Port Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ48

6.2.2 Line Control Register (LCR)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ48

6.2.3 Programmable Baud Rate GeneratorÀÀÀÀÀÀÀÀ51

6.2.4 Line Status Register (LSR)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ51

6.2.5 Interrupt Identification Register (IIR) ÀÀÀÀÀÀÀÀ52

6.2.6 Interrupt Enable Register (IER) ÀÀÀÀÀÀÀÀÀÀÀÀÀ52

6.2.7 MODEM Control Register (MCR) ÀÀÀÀÀÀÀÀÀÀÀ52

6.2.8 MODEM Status Register (MSR) ÀÀÀÀÀÀÀÀÀÀÀÀ53

6.2.9 Scratchpad Register (SCR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ53

6.3 PC87312 Serial Ports ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ53

6.3.1 Serial Port Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ53

6.3.2 Line Control Register (LCR)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ53

6.3.3 Programmable Baud Rate GeneratorÀÀÀÀÀÀÀÀ56

4.0 FDC COMMAND SET DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀ24

4.1 Command Set Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ24

4.2 Command Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ28

4.2.1 Configure CommandÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ28

4.2.2 Dumpreg Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ29

4.2.3 Format Track CommandÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ29

4.2.4 Invalid CommandÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ32

4.2.5 Lock Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ32

4.2.6 Mode Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ32

4.2.7 NSC Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ33

4.2.8 Perpendicular Mode CommandÀÀÀÀÀÀÀÀÀÀÀÀÀ33

4.2.9 Read Data Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ34

2

Table of Contents

6.3.4 Line Status Register (LSR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ56

9.2 AC Electrical Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ64

9.2.1 AC Test ConditionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ64

9.2.2 Clock Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ64

9.2.3 Microprocessor Interface Timing ÀÀÀÀÀÀÀÀÀÀ65

9.2.4 Baudout Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ66

9.2.5 Transmitter Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ67

9.2.6 Receiver TimingÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ68

9.2.7 MODEM Control Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ69

9.2.8 DMA Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ70

9.2.9 Reset Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ71

9.2.10 Write Data Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ71

9.2.11 Drive Control Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ72

9.2.12 Read Data Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ72

9.2.13 IDE Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ72

9.2.14 Parallel Port TimingÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ73

6.3.5 FIFO Control Register (FCR)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ57

6.3.6 Interrupt Identification Register (IIR) ÀÀÀÀÀÀÀ57

6.3.7 Interrupt Enable Register (IER)ÀÀÀÀÀÀÀÀÀÀÀÀ57

6.3.8 MODEM Control Register (MCR) ÀÀÀÀÀÀÀÀÀÀ58

6.3.9 MODEM Status Register (MSR) ÀÀÀÀÀÀÀÀÀÀÀ59

6.3.10 Scratchpad Register (SCR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ59

7.0 PARALLEL PORT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ59

7.1 Introduction ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ59

7.2 Data Register (DTR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ60

7.3 Status Register (STR)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ60

7.4 Control Register (CTR)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ60

8.0 INTEGRATED DEVICE ELECTRONICS

INTERFACE (IDE) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ61

8.1 Introduction ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ61

8.2 IDE Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ61

10.0 REFERENCE SECTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ74

10.1 Mnemonic Definitions for FDC CommandsÀÀÀÀÀÀÀ74

9.0 DEVICE DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ62

10.2 Example Four Drive Circuit

Using the PC87311A/12 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ75

9.1 DC Electrical Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ62

List of Figures

FIGURE 2-1

FIGURE 3-1

FIGURE 4-1

FIGURE 5-1

FIGURE 5-2

FIGURE 5-3

FIGURE 5-4

FIGURE 6-1

FIGURE 6-2

FIGURE 9-1

FIGURE 9-2

FIGURE 9-3

FIGURE 9-4

FIGURE 9-5

PC87311A/87312 Configuration Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12

FDC Functional Block DiagramÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ18

IBM, Perpendicular, and ISO Formats Supported by Format Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ30

FDC Data Separator Block Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ44

PC87311A/87312 Dynamic Window Margin Performance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ45

Read Data AlgorithmÐState DiagramÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ46

Perpendicular Recording Drive R/W Head and Pre-Erase Head ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ46

PC87311A Composite Serial Data ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ48

PC87312 Composite Serial Data ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ54

Clock Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ64

Microprocessor Read Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ65

Microprocessor Write Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ66

Baudout Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ66

Transmitter Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ67

FIGURE 9-6a Receiver TimingÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ68

FIGURE 9-6b PC87312 FIFO Mode Receiver Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ68

FIGURE 9-6c PC87312 Timeout Receiver Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ69

FIGURE 9-7

FIGURE 9-8

FIGURE 9-9

MODEM Control Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ69

DMA Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ70

Reset Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ71

FIGURE 9-10 Write Data Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ71

FIGURE 9-11 Drive Control Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ72

FIGURE 9-12 Read Data Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ72

FIGURE 9-13 IDE Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ72

FIGURE 9-14 Parallel Port Interrupt Timing (Compatible Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ73

FIGURE 9-15 Parallel Port Interrupt Timing (Extended Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ73

FIGURE 9-16 Typical Parallel Port Data Exchange ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ73

FIGURE 10-1 PC87311A/87312 Four Floppy Drive Circuit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ75

FIGURE 10-2 IDE Interface Signal Equations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ75

FIGURE 10-3 PC87311A/87312 Adapter Card Schematic ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ76

3

List of Tables

TABLE 2-1

TABLE 2-2

TABLE 2-3

TABLE 2-4

TABLE 2-5

Default Configurations Controlled by Hardware ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ13

Index and Data Register Optional LocationsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14

Primary and Secondary Drive Address Selection ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15

Encoded Drive and Motor Pin Information ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15

Parallel Port AddressesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ16

TABLE 2-6a COM Port Selection for UART1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ16

TABLE 2-6b COM Port Selection for UART2 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ16

TABLE 2-7

TABLE 3-1

TABLE 3-2

TABLE 3-3

TABLE 3-4

TABLE 3-5

TABLE 3-6

TABLE 4-1

TABLE 4-2

TABLE 4-3

TABLE 4-4

Address Selection for COM3 and COM4 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ16

Register Description and AddressesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ18

Drive Enable Values ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ20

Tape Drive Assignment Values ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ20

Write Precompensation Delays ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ21

Default Precompensation Delays ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ21

Data Rate Select Encoding ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ22

Typical Format Gap Length ValuesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ31

DENSEL EncodingÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ33

DENSEL Default EncodingÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ33

Effect of Drive Mode and Data Rate on Format and Write CommandsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ34

TABLE 4-4a Effect of GAP and WG on Format and Write Commands ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ34

TABLE 4-5

TABLE 4-6

TABLE 4-7

TABLE 4-8

TABLE 4-9

Sector Size Selection ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ34

SK Effect on Read Data CommandÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ35

Result Phase Termination Values with No Error ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ35

SK Effect on Read Deleted Data Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ36

Maximum Recalibrate Step Pulses Based on R255 and ETRÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ36

TABLE 4-10 Scan Command Termination Values ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ37

TABLE 4-11 Status Register 0 Termination CodesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38

TABLE 4-12 Set Track Register Address ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38

TABLE 4-13 Step Rate (SRT) Values ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38

TABLE 4-14 Motor Off Time (MFT) ValuesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39

TABLE 4-15 Motor On Time (MNT) Values ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39

TABLE 4-16 Verify Command Result Phase Table ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ40

e

0) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ48

TABLE 6-1

TABLE 6-2

TABLE 6-3

TABLE 6-4

TABLE 6-5

TABLE 6-6

TABLE 6-7

TABLE 6-8

TABLE 6-9

PC87311A UART Register Addresses (AEN

PC87311A Register Summary for an Individual UART ChannelÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ49

PC87311A UART Reset ConfigurationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ50

PC87311A UART Divisors, Baud Rates, and Clock Frequencies ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ51

PC87311A Interrupt Control FunctionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ52

e

PC87312 UART Register Addresses (AEN

0) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ53

PC87312 Register Summary for an Individual UART Channel ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ54

PC87312 UART Reset Configuration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ55

PC87312 UART Divisors, Baud Rates, and Clock Frequencies ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ56

TABLE 6-10 PC87312 Interrupt Control Functions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ58

TABLE 7-1

TABLE 7-2

TABLE 7-3

TABLE 7-4

TABLE 8-1

TABLE 9-1

TABLE 9-2

Parallel Interface Register Addresses ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ59

Data Register Read and Write Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ59

Parallel Port Mode of Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ59

Parallel Port Reset StatesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ60

IDE Registers and Their ISA AddressesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ61

Nominal t , t

Values ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ64

Values ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ71

ICP DRP

Minimum t

WDW

TABLE 10-1 PC87311A/87312 Four Floppy Drive Encoding ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ75

4

Basic Configuration

TL/F/11362–2

*Note: PC87311A only

5

1.0 Pin Description

Connection Diagram

Plastic Quad Flatpak, EIAJ

*Note: XTSEL PC87311A only

TL/F/11362–3

Order Number PC87311AVF or PC87312VF

See NS Package Number VLJ100A

6

1.0 Pin Description (Continued)

Symbol

I/O

Function

A9–A0

21–30

I

Address. These address lines from the microprocessor determine which internal register is accessed.

A0–A9 are don’t cares during an FDC DMA transfer.

ACK

AFD

85

78

I

Acknowledge. This input is pulsed low by the printer to indicate that it has received data from the

parallel port. This pin has a nominal 25 kX pull-up resistor attached.

O

Automatic Feed XT. When this signal is low the printer should automatically line feed after each line is

printed. This pin will be in a TRI-STATE condition 10 ns after a zero is loaded into the corresponding

É

Control Register bit. The system should pull this pin high using a 4.7 kX resistor.

AEN

20

55

I

Address Enable. This input disables function selection via A9–A0 when it is high. Access to the FDC

Data Register during DMA transfer is NOT affected by this pin.

BADDR0

Base Address. This bit determines one of two base addresses from which the Index and Data

Registers will be offset (see Table 2-2). An internal pull-down resistor of 40 kX is on each pin. Use a

10 kX resistor to pull this pin to the required level during reset.

BOUT1,2 73, 65

O

BAUD Output. This multi-function pin provides the associated serial channel Baud Rate generator

output signal, if test mode is selected in the Power and Test Configuration Register and the DLAB bit

(LCR7) is set. After Master Reset this pin provides the SOUT function. (See SOUT and CFG0–4 for

further information.)

BUSY

84

I

Busy. This pin is set high by the printer when it can’t accept another character. This pin has a nominal

25 kX pull-down resistor attached to it.

CFG0–4

65, 66,

71, 73,

74

Default Configuration. These CMOS inputs select 1 of 32 default configurations in which the

PC87311A/12 will power-up (see Table 2-1). An internal pull-down resistor of 40 kX is on each pin.

Use a 10 kX resistor to pull these pins to the required level during reset.

CSOUT

CTS1,2

3

O

I

Chip Select Output. When the associated bit in the Power and Test Configuration Register is set, this

multi-function pin provides an active signal each time the internal address decoder decodes an

address enabled for the PC87311A/12. (See PWDN for further information.)

72, 64

Clear to Send. When low, this indicates that the MODEM or data set is ready to exchange data. The

CTS signal is a MODEM status input whose condition the CPU can test by reading bit 4 (CTS) of the

MODEM Status Register (MSR) for the appropriate serial channel. Bit 4 is the complement of the CTS

signal. Bit 0 (DCTS) of the MSR indicates whether the CTS input has changed state since the previous

reading of the MSR. CTS has no effect on the transmitter.

Note: Whenever the DCTS bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled.

D7–D0

DACK

10–17 I/O Data. Bi-directional data lines to the microprocessor. D0 is the LSB and D7 is the MSB. These signals

all have 24 mA (sink) buffered outputs.

5

I

DMA Acknowledge. Active low input to acknowledge the FDC DMA request and enable the RD and

WR inputs during a DMA transfer. When in PC-AT or Model 30 mode, this signal is enabled by bit D3 of

the Digital Output Register (DOR). When in PS/2 mode, DACK is always enabled, and bit D3 of the

É

DOR is reserved. DACK should be held high during PIO accesses.

DCD1,2

77, 69

I

Data Carrier Detect. When low, this indicates that the data carrier has been detected by the MODEM

or data set. The DCD signal is a MODEM status input whose condition the CPU can test by reading bit

7 (DCD) of the MODEM Status Register (MSR) for the appropriate serial channel. Bit 7 is the

complement of the DCD signal. Bit 3 (DDCD) of the MSR indicates whether the DCD input has

changed state since the previous reading of the MSR.

Note: Whenever the DDCD bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.

DENSEL

DIR

48

41

O

Density Select. Indicates when a high FDC density data rate (500 kb/s or 1 Mb/s) or a low density

data rate (250 or 300 kb/s) has been selected. DENSEL is active high for high density (5.25 drives)

×

when IDENT is high, and active low for high density (3.5 drives) when IDENT is low. DENSEL is also

×

programmable via the Mode command (see Section 4.2.6).

Direction. This output determines the direction of the floppy disk drive (FDD) head movement (active

e

step out) during a seek operation. During read or writes, DIR will be inactive.

e

step in, inactive

7

1.0 Pin Description (Continued)

Symbol

I/O

Function

DR0,1

44, 45

O

Drive Select 0,1. These are the decoded drive select outputs that are controlled by Digital Output

Register bits D0, D1. The Drive Select outputs are gated with DOR bits 4–7. These are active low

outputs. They are encoded with information to control four FDDs when bit 4 of the Function Enable

Register (FER) is set. (See MTR0,1 and Table 2-4 for more information.)

DRATE0,1 52, 51

O

Data Rate 0,1. These outputs reflect the currently selected FDC data rate, (bits 0 and 1 in the

Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written

to last). These pins are totem-pole buffered outputs (6 mA sink, 6 mA source).

DRQ

4

DMA Request. Active high output to signal the DMA controller that a FDC data transfer is needed.

When in PC-AT or Model 30 mode, this signal is enabled by bit D3 of the DOR. When in PS/2 mode,

DRQ is always enabled, and bit D3 of the DOR is reserved.

DRV2

49

32

I

Drive2. This input indicates whether a second disk drive has been installed. The state of this pin is

available from Status Register A in PS/2 mode.

DSKCHG

Disk Change. The input indicates if the drive door has been opened. The state of this pin is available

from the Digital Input register. This pin can also be configured as the RGATE data separator

diagnostic input via the Mode command (see Section 4.2.6).

DSR1,2

DTR1,2

76, 68

I

Data Set Ready. When low, this indicates that the data set or MODEM is ready to establish a

communications link. The DSR signal is a MODEM status input whose condition the CPU can test by

reading bit 5 (DSR) of the MODEM Status Register (MSR) for the appropriate channel. Bit 5 is the

complement of the DSR signal. Bit 1 (DDSR) of the MSR indicates whether the DSR input has

changed state since the previous reading of the MSR.

Note: Whenever the DDSR bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.

71, 63

O

Data Terminal Ready. When low, this output indicates to the MODEM or data set that the UART is

ready to establish a communications link. The DTR signal can be set to an active low by programming

bit 0 (DTR) of the MODEM Control Register to a high level. A Master Reset operation sets this signal

to its inactive (high) state. In the PC87312, loop mode operation holds this signal to its inactive state.

(See CFG4–0 for further information.) In the PC87311A, loop mode operation holds this signal to its

inactive state if the XTSEL pin is high during reset. If the XTSEL pin is low during reset, the associated

pin state is controlled by the MCR0 bit during loop mode operation. (See XTSEL and CFG0–4 for

further information.)

ERR

79

58

I

Error. This input is set low by the printer when it has detected an error. This pin has nominal 25 kX

pull-up resistor attached to it.

HCS0

O

Hard Drive Chip Select 0. This output is active in the AT mode when the hard drive registers from

1F0–1F7h are selected if the primary address is used or when 170–177h are selected if the

secondary address is used. In the XT mode (PC87311A) this output is active if the addresses from

320–324h are selected. This output is inactive if the IDE interface is disabled via the Configuration

Register. (See POE for further information.)

HCS1

57

O

Hard Drive Chip Select 1. This output is active in the AT mode when the hard drive registers from

3F6–7 are selected if the primary address is used or when 376–377 are selected if the secondary

address is used. In the XT mode (PC87311A) this output is inactive. This output is also inactive if the

IDE interface is disabled via the Configuration Register. (See PDIR for further information.)

HDSEL

IDED7

34

60

Head Select. This output determines which side of the FDD is accessed. Active selects side 1,

inactive selects side 0.

I/O IDE Bit 7. This pin provides the data bus bit 7 signal to the IDE hard drive during accesses in the

address range 1F0–1F7h, 170–177h and 3F6h and 376h. This pin is TRI-STATE during read or write

accesses to 3F7h and 377h.

IDEHI

56

55

O

IDE High Byte. This output enables the high byte data latch during a read or write to the hard drive if

the hard drive returns IOCS16. This output is inactive if the IDE interface is disabled via the

Configuration Register.

IDELO

O

IDE Low Byte. This output enables the low byte data latch during a read or write to the hard drive .

This output is inactive if the IDE interface is disabled via the Configuration Register. (See BADDR0 for

further information.)

8

1.0 Pin Description (Continued)

Symbol

I/O

Function

IDENT

54

I

Identity. During chip reset, the IDENT and MFM pins are sampled to determine the mode of operation

according to the following table:

IDENT

MFM

MODE

1

0

1 or NC

PC-AT Mode

Illegal

0

1 or NC

0

PS/2 Mode

Model 30 Mode

AT ModeÐThe DMA enable bit in the DOR is valid. TC is active high. Status Registers A and B are

disabled (TRI-STATE).

Model 30 ModeÐThe DMA enable bit in the DOR is valid. TC is active high. Status Registers A and B

are enabled.

PS/2 ModeÐThe DMA enable bit in the DOR is a don’t care, and the DRQ and IRQ6 signals will always

be enabled. TC is active low. Status Registers A and B are enabled.

After chip reset, the state of IDENT determines the polarity of the DENSEL output.

When IDENT is a logic ‘‘1’’, DENSEL is active high for the 500 kbs/1 Mbs data rates.

When IDENT is a logic ‘‘0’’, DENSEL is active low for the 500 kbs/1 Mbs data rates.

(See Mode command for further explanation of DENSEL.)

INDEX

INIT

47

80

I

Index. This input signals the beginning of a FDD track.

O

Initialize. When this signal is low it causes the printer to be initialized. This pin will be in a TRI-STATE

condition 10 ns after a zero is loaded into the corresponding Control Register bit. The system should pull

this pin high using a 4.7 kX resistor.

IOCS16

IRQ3,4

59

I

I/O Chip Select 16-Bit. This input will be driven by the peripheral device when it can accommodate a

16-bit access.

1, 100

O

Interrupt 3 and 4. These are active high interrupts associated with the serial ports. IRQ3 presents the

signal if the serial channel has been designated as COM2 or COM4. IRQ4 presents the signal if the serial

port is designated as COM1 or COM3. The appropriate interrupt goes active whenever it is enabled via

IER, the associated Interrupt Enable bit (Modem Control Register bit 3, MCR3), and any of the following

conditions are active: Receiver Error, Receive Data available, Transmitter Holding Register Empty, or a

Modem Status Flag is set. The interrupt is reset low (inactive) after the appropriate interrupt service

routine is executed, after being disabled via the IER, or after a Master Reset. Either interrupt can be

disabled, putting them into TRI-STATE, by setting the MCR3 bit low.

IRQ5

IRQ6

IRQ7

MR

98

97

96

2

O

I

Interrupt 5. Active high output that indicates a parallel port interrupt. When enabled this bit follows the

ACK signal input. When bit 4 in the parallel port Control Register is set and the parallel port address is

designated as shown in Table 2-5, this interrupt is enabled. When it is not enabled or when operating in

the XT mode this signal is TRI-STATE.

Interrupt 6. Active high output to signal the completion of the execution phase for certain FDC

commands. Also used to signal when a data transfer is ready during a Non-DMA operation. When in

PC-AT or Model 30 mode, this signal is enabled by bit D3 of the DOR. When in PS/2 mode, IRQ6 is

always enabled, and bit D3 of the DOR is reserved.

Interrupt 7. Active high output that indicates a parallel port interrupt. When enabled this bit follows the

ACK signal input. When bit 4 in the parallel port Control Register is set and the parallel port address is

designated as shown in Table 2-5, this interrupt is enabled. When it is not enabled this signal is

TRI-STATE.

Master Reset. Active high input that resets the controller to the idle state, and resets all disk interface

outputs to their inactive states. The DOR, DSR, CCR, Mode command, Configure command, and Lock

command parameters are cleared to their default values. The Specify command parameters are not

affected. The Configuration Registers are set to their selected default values.

9

1.0 Pin Description (Continued)

Symbol

I/O

Function

MFM

53

I/O MFM. During a chip reset when in PS/2 mode (IDENT low), this pin is sampled to select the PS/2 mode

(MFM high), or the Model 30 mode (MFM low). An internal pull-up or external pull-down 10 kX resistor

will select between the two PS/2 modes. When the PC-AT mode is desired, (IDENT high), MFM should

be left pulled high internally. MFM reflects the current data encoding format when RESET is inactive.

e

low. Defaults to low after a chip reset. This signal can also be configured as the

PUMP data separator diagnostic output via the Mode command (see Section 4.2.6).

MFM

high, FM

MTR0,1

46, 43

O

Motor Select 0,1. These are the motor enable lines for drives 0 and 1, and are controlled by bits

D7–D4 of the Digital Output register. They are active low outputs. They are encoded with information to

control four FDDs when bit 4 of the Function Enable Register (FER) is set. (See DR0,1 and Table 2-4

for more information.)

PD0–7

PDIR

94–91, I/O Parallel Port Data. These bidirectional pins transfer data to and from the peripheral data bus and the

parallel port Data Register. These pins have high current drive capability. (See DC Electrical

Characteristics.)

89–86

57

I

Parallel Port Direction. During reset the state of this pin determines the direction of the parallel port

e

input (scanner) when PDIR

e

0 and it will be

data, if the PTR7

0. The direction will be output (printer) when PDIR

0 and PTR7

e

0. An internal pull-down resistor or 40 kX is on this pin.

e

1 and PTR7

Use a 10 kX resistor to pull this pin to the required level during reset.

PDWN

PE

3

I

Power Down. This multi-function pin will stop the clocks and/or the external crystal based on the

selections made in the Power and Test Register bits 1-2. (See CSOUT for additional information.)

83

58

Paper End. This input is set high by the printer when it is out of paper. This pin has a nominal 25 kX

pull-down resistor attached to it.

POE

Parallel Port Output Enable. This pin is sensed during reset. If it is low, bit 7 of the Power and Test

Register (PTR7) is set high and the parallel port will operate in the Extended Mode. In this mode

software determines the direction of parallel port data via the parallel port Control Register (CTR5). If

e

this pin is high (PTR7

0) then the Compatible Mode is selected and the data direction is determined

by the state of PDIR pin at reset. An internal pull-down resistor of 40 kX is on this pin. Use a 10 kX

resistor to pull this pin to the required level during reset.

RD

19

35

I

Read. Active low input to signal a data read by the microprocessor.

RDATA

RI1,2

Read Data. This input is the raw serial data read from the floppy disk drive.

70, 62

Ring Indicator. When low this indicates that a telephone ringing signal has been received by the

MODEM. The RI signal is a MODEM status input whose condition the CPU can test by reading bit 6 (RI)

of the MODEM Status Register (MSR) for the appropriate serial channel. Bit 6 is the complement of the

RI signal. Bit 2 (TERI) of the MSR indicates whether the RI input has changed from low to high since the

previous reading of the MSR.

Note: Whenever the TERI bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.

RTS1,2

74, 66

O

Request to Send. When low, this output indicates to the MODEM or data set that the UART is ready to

exchange data. The RTS signal can be set to an active low by programming bit 1 (RTS) of the MODEM

Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. In

the PC87312, loop mode operation holds this signal to its inactive state. (See CFG0–4 for further

information.) In the PC87311A, loop mode operation holds this signal to its inactive state if the XTSEL

pin is high during reset. If the XTSEL pin is low during reset, the associated pin state is controlled by the

MCR1 bit during loop mode operation. (See CFG0–4 for further information.)

SIN1,2

SLCT

SLIN

75, 67

82

I

Serial Input. This input receives composite serial data from the communications link (peripheral device,

MODEM, or data set).

Select. This input is set high by the printer when it is selected. This pin has a nominal 25 kX pull-down

resistor attached to it.

81

O

Select Input. When this signal is low it selects the printer. This pin will be in a TRI-STATE condition

10 ns after a zero is loaded into the corresponding Control Register bit. The system should pull this pin

high using a 4.7 kX resistor.

10

1.0 Pin Description (Continued)

Symbol

I/O

Function

SOUT1,2 73, 65

O

Serial Output. This output sends composite serial data to the communications link (peripheral device,

MODEM, or data set). The SOUT signal is set to a marking state (logic 1) after a Master Reset

operation. (See BOUT and CFG0–4 for further information on these pins.)

STB

95

O

Data Strobe. This output indicates to the printer that valid data is available at the printer port. This pin

will be in a TRI-STATE condition 10 ns after a zero is loaded into the corresponding Control Register bit.

The system should pull this pin high using a 4.7 kX resistor.

STEP

TC

40

6

O

I

Step. This output signal issues pulses to the disk drive at a software programmable rate to move the

head during a seek operation.

Terminal Count. Control signal from the DMA controller to indicate the termination of a DMA transfer.

TC is accepted only when DACK is active. TC is active high in PC-AT and Model 30 modes, and active

low in PS/2 mode.

TRK0

37

I

Track 0. This input indicates to the controller that the head of the selected floppy disk drive is at track

zero.

VDDA

33

50, 99

31

Analog Supply. This pin is the 5V supply for the analog data separator.

Digital Supply. This is the 5V supply voltage for the digital circuitry.

Analog Ground. This is the analog ground for the data separator.

Digital Ground. This is the ground for the digital circuitry.

VDDB,C

VSSA

VSSB-E

42, 9,

90, 61

WR

18

39

I

Write. Active low input to signal a write from the microprocessor to the controller.

WDATA

O

Write Data. This output is the write precompensated serial data that is written to the selected floppy

disk drive. Precompensation is software selectable.

WGATE

38

O

Write Gate. This output signal enables the write circuitry of the selected disk drive. WGATE has been

designed to prevent glitches during power up and power down. This prevents writing to the disk when

power is cycled.

WP

36

7

I

Write Protect. This input indicates that the disk in the selected drive is write protected.

X1/OSC

Crystal1/Clock. One side of an external 24 MHz crystal is attached here. If a crystal is not used, a TTL

or CMOS compatible clock is connected to this pin.

X2

8

O

I

Crystal2. One side of an external 24 MHz crystal is attached here. This pin is left unconnected if an

external clock is used.

XTSEL*

63

XT Select. When this pin is high during reset the chip will operate in the XT mode. When this pin is low

during reset the chip will operate in the AT mode. An internal pull-down resistor of 40 kX is on this pin.

Use a 10 kX resistor to pull this pin to the required level during reset.

There are five differences between AT and XT mode. One concerns hard disk operation and the other

four concern UART operation. In AT mode the IDE hard drive chip selects (HCS0, HCS1) will be active

for addresses 1F0–7H and 3F6, 7H; respectively. In XT mode the IDE chip select HCS0 responds to

addresses 320–3H and HCS1 is inactive. The differences in UART operation are: the function of LSR

bit (see Section 6.5 bit 6), the modem control outputs during loop back mode (see Section 6.8 bit 4), the

Scratch Pad Register (see Section 6.10), and the availability of edge (XT) or level (AT) sensitive UART

interrupts.

*Note: XTSEL is an option for the PC87311A only.

11

2.0 Configuration Registers

2.1 OVERVIEW

D. Modify the configuration data.

Three registers constitute the Base Configuration Register

set which controls the set-up of the PC87311A/12. In gen-

eral, these registers control the enabling of each major

function (e.g., FDC, UARTs, parallel port, etc.), the I/O ad-

dresses of those functions, and whether those functions

power down via hardware control or not. These three con-

figuration registers are called the Function Enable Register

(FER), the Function Address (FAR) Register and the Power

and Test Register (PTR).

E. Write the changed data for the Configuration Register

in two consecutive writes to the Data Register. The

register updates on the second consecutive write.

F. Enable CPU interrupts.

A single read access to the Index and Data Registers can

be done at any time without disabling CPU interrupts. When

the Index Register is read, the last value loaded into the

Index Register will be returned. When the Data Register is

read, the Configuration Register data pointed to by the In-

dex Register will be returned.

These registers can be accessed via hardware or software.

During reset, the PC87311A/12 loads a set of default val-

ues selected by a hardware strapping option into the Config-

uration Registers. This defines the setting of all Configura-

tion Registers via hardware.

An index and data register pair are used to read and write

these registers. Each Configuration Register is pointed to by

the value loaded into the Index Register. The data to be

written into the Configuration Register is transferred via the

Data register. Reading a Configuration Register is done in a

similar way (i.e., by pointing to it via the Index Register and

then reading its contents via the Data Register).

Accessing the Configuration Registers in this way requires

only two system I/O addresses. Since that I/O space is

shared by other devices the Index and Data Registers could

still be inadvertantly accessed, even though, there are only

two registers in this I/O address space. In order to reduce

the chances of an inadvertant access, a simple procedure

(Section 2.2) has been developed.

TL/F/11362–38

2.2 SOFTWARE CONFIGURATION

If the system requires access to the Configuration Registers

after reset, then the following procedure is used to change

data in the registers.

1. Determine the default location of the PC87311A/12 In-

dex Register.

TL/F/11362–39

A. Check the two possible default locations (see Table

2-2) by reading them twice. The first byte is the ID byte

(88H). The second byte read is always 00H. Compare

the data read with the ID byte and then 00h. A match

will occur at the correct location. Note that the ID byte

is only issued from the Index Register during the first

read after a reset. Subsequent reads return the value

loaded into the Index Register. Bits 2–6 are reserved

and always read 0.

2. Load the Configuration Registers.

A. Disable CPU interrupts.

B. Write the index of the Configuration Register (00h–

02h) to the Index Register one time.

TL/F/11362–40

FIGURE 2-1. PC87311A/12 Configuration Registers

C. Write the correct data for the Configuration Register in

two consecutive write accesses to the Data Register.

2.3 HARDWARE CONFIGURATION

D. Enable CPU interrupts.

During reset, 1 of 32 possible sets of default values are

loaded into the Configuration Registers. A strapping option

on five pins (CFG0–4) selects the set of values that is load-

ed. This allows for automatic configuration without software

intervention. Table 2-1 shows the 32 possible default con-

figurations. The default configuration can be modified by

software at any time after reset by using the access proce-

dure described in the Software Configuration Section.

3. Load the Configuration Registers (read-modify-write).

A. Disable CPU interrupts.

B. Write the index of the Configuration Register (00h–

02h) to the Index Register one time.

C. Read the configuration data in that register via the

Data Register.

12

2.0 Configuration Registers (Continued)

TABLE 2-1. Default Configurations Controlled by Hardware

Configuration Pins (CFGn)

Data

Activated Functions

(Hex)

4

3

2

1

0

e

FER

PTR

FAR

FER

PTR

FAR

FER

PTR

FAR

FER

PTR

FAR

FER

PTR

FAR

FER

PTR

FAR

4F, CF

00

FDC, IDE, UART1, UART2, PORT

ll

Power Down Clocks Option

PRI, PRI, COM1, COM2, LPT2

PRI, PRI, COM1, COM2, LPT1

PRI, SEC, COM1, COM2, LPT1

PRI, PRI, COM3, COM4, LPT1

PRI, PRI, COM2, COM3, LPT2

PRI, SEC, COM3, COM4, LPT2

0

1

0

1

0

1

0

1

0

1

10

11

39

24

38

4B, CB

00

FDC, IDE, UART1, PORT

ll

Power Down Clocks Option

PRI, PRI, COM1, LPT2

PRI, PRI, COM1, LPT1

PRI, SEC, COM1, LPT1

PRI, PRI, COM3, LPT1

PRI, PRI, COM3, LPT2

PRI, SEC, COM3, LPT2

0

1

0

1

0

1

0

1

0

1

0

1

00

01

09

08

0F

FDC, UART1, UART2, PORT

ll

Power Clocks Option

00

0

1

0

1

0

1

0

1

10

PRI, COM1, COM2, LPT2

PRI, COM1, COM2, LPT1

PRI, COM3, COM4, LPT1

PRI, COM2, COM3, LPT2

11

39

24

49, C9

00

FDC, IDE, PORT

ll

Power Down Clocks Option

1

0

1

0

1

0

1

00

PRI, PRI, LPT2

01

PRI, PRI, LPT1

01

PRI, SEC, LPT1

00

PRI, SEC, LPT2

07

UART1, UART2, PORT

ll

00

Power Down Clocks Option

COM1, COM2, LPT2

COM1, COM2, LPT1

COM3, COM4, LPT1

COM2, COM3, LPT2

1

0

1

0

1

0

1

0

1

10

11

39

24

47, C7

00

IDE, UART1, UART2, PORT

ll

Power Down Clocks Option

PRI, COM1, COM2, LPT2

PRI, COM1, COM2, LPT1

1

0

1

10

11

13

2.0 Configuration Registers (Continued)

TABLE 2-1. Default Configurations Controlled by Hardware (Continued)

Configuration Pins (CFGn)

Data

Activated Functions

(Hex)

4

1

3

2

0

1

0

1

0

1

0

e

1

0

1

FAR

FER

PTR

FAR

FER

PTR

FAR

11

SEC, COM1, COM2, LPT1

PRI, COM3, COM4, LPT1

PRI, COM2, COM3, LPT2

SEC, COM3, COM4, LPT2

FDC

39

24

38

08

00

Power Down Clocks Option

PRI

10, 80

00

1

None

02, 82

10

Power Down XTAL and Clocks

NA

Table 2-1 is organized in the following way. The logic values

of the 5 external Configuration Pins are associated with the

resulting Configuration Register Data and the activated

functions. The activated functions are grouped into 7 cate-

gories based on the data in the FER. In some cases the

data in the FER is given as one of two options. This is be-

cause the primary or secondary IDE address is chosen via

the FER.

TABLE 2-2. Index and Data

Register Optional Locations

BADDR0

Index Addr.

398h

Data Addr.

0

1

399h

26Fh

26Eh

2.5 BASE CONFIGURATION REGISTERS

The PTR has one value associated with the active functions

in the FER. This value allows the power down of all clocks

when the PWDN pin goes active. In the last case where no

functions are active after reset, activating the PWDN pin will

also stop the crystal.

2.5.1 Function Enable Register (FER, Index 0)

This register enables and disables all major chip functions.

Disabled functions have their clocks automatically powered

down, but the data in their registers remains intact. It also

selects whether the FDC and the IDE controller will be lo-

cated at their primary or secondary address.

Most of the variability available is through the FAR. Ad-

dresses controlled by the FAR are coded in the following

way:

Bit 0 When this bit is one the parallel port can be accessed

at the address specified in the FAR.

PRI

is the PRImary floppy or IDE address (i.e., 3F0–7h

or 1F0–7, 3F6, 7h)

Bit 1 When this bit is one, UART1 can be accessed at the

address specified in the FAR. When this bit is zero,

access to UART1 is blocked and it will be in power

down mode. The UART1 registers retain all data in

power down mode. Caution: Any UART1 interrupt

that is enabled and active or becomes active after

UART1 is disabled will assert the associated IRQ pin

when UART1 is disabled. If disabling UART1 via soft-

ware, clear the IRQ Enable bit (MCR3) to zero before

clearing FER 1. This is not an issue after reset be-

cause MCR3 will be zero until it is written.

SEC is the SECondary IDE address (170–7, 376, 7h)

COM1 is the UART address at 3F8–Fh

COM2 is the UART address at 2F8–Fh

COM3 is the UART address at 3E8–Fh

COM4 is the UART address at 2E8–Fh

LPT1 is the parallel port ( PORT ) address at 3BC–3BEh

ll

LPT2 is the PORT address at 378–37Fh

ll

The chosen addresses are given under active functions and

are in the same order as the active functions they are asso-

ciated with. In other words, if the active functions are given

Bit 2 When this bit is one, UART2 can be accessed at the

address specified in the FAR. When this bit is zero,

access to UART2 is blocked and it will be in power

down mode. The UART2 registers retain all data in

power down mode. Caution: Any UART2 interrupt

that is enabled and active or becomes active after

UART2 is disabled will assert the associated IRQ pin

when UART2 is disabled. If disabling UART2 via soft-

ware, clear the IRQ Enable bit (MCR3) to zero before

clearing FER2. This is not an issue after reset be-

cause MCR3 will be zero until it is written.

as FDC, IDE, UART1, UART2, PORT and the addresses

ll

are given as PRI, PRI, COM1, COM2, LPT2; then the func-

e

COM1, UART2 COM2,

tions and the addresses are associated as follows: FDC

e

PRI, IDE

PORT

PRI, UART1

LPT2.

ll

2.4 INDEX AND DATA REGISTERS

One more general aspect of the Configuration Registers is

that the Index and the Data Register pair can be relocated

to any one of two locations. This is controlled through a

hardware strapping option on one pin (BADDR0) and it al-

lows the registers to avoid conflicts with other adapters in

the I/O address space. Table 2-2 shows the address op-

tions.

14

2.0 Configuration Registers (Continued)

Bit 3 When this bit is one, the FDC can be accessed at the

Bit 5 This bit selects the primary or secondary FDC address

in the PC87312. In the PC87311A, this bit selects the

primary or secondary FDC address when in the AT

mode. In the XT mode it has no significance (see Ta-

ble 2-3).

[ ]

address specified in FER 5 . When this bit is zero ac-

cess to the FDC is blocked and it will be in power

down mode. The FDC registers retain all data in power

down mode.

Bit 4 When this bit is zero the PC87311A/12 can control

two floppy disk drives directly without an external de-

coder. When this bit is one the two drive select signals

and two motor enable signals from the FDC are en-

coded so that four floppy disk drives can be controlled

(see Table 2-4). Controlling four FDDs requires an ex-

ternal decoder. The pin states shown in Table 2-4 are

a direct result of the bit patterns shown. All other bit

patterns produce pin states that should not be decod-

ed to enable any drive or motor.

Bit 6 When this bit is a one the IDE drive interface can be

accessed at the address specified by FER bit 7. When

it is zero, access to the IDE interface is blocked, the

IDE control signals (i.e., HCS0, HCS1, IDELO, IDEHI)

are held in the inactive state, and the IDED7 signal will

be in TRI-STATE.

Bit 7 This bit selects the primary or secondary IDE address

in the PC87312. In the PC87311A, this bit selects the

primary or secondary IDE address when in the AT

mode. In the XT mode it has no significance (see Ta-

ble 2-3).

TABLE 2-3. Primary and Secondary Drive Address Selection

BIT 5

BIT 7

DRIVE

Ð

AT

XT (Note)

Ð

X

0

Primary

Secondary

Ð

0

FDC

IDE

3F0–7h

Ð

1

Ð

370–7h

Ð

X

Ð

3F0–7h

Ð

X

1F0–7, 3F6, 3F7h

Ð

170–7, 376-7h

Ð

X

1

IDE

Ð

X

IDE

320–3h

Note: PC87311A only

e

TABLE 2-4. Encoded Drive and Motor Pin Information (FER 4

Digital Output Reg Drive Control Pins

1)

Decoded Functions

7

X

1

6

X

1

5

X

1

4

1

X

0

X

3

X

2

X

1

0

1

0

1

0

1

0

1

0

1

0

1

MTR1

MTR0

DR1

0

DR0

0

(Note 1)

0

1

Activate Drive 0 and Motor 0

0

1

Activate Drive 1 and Motor 1

X

0

1

0

Activate Drive 2 and Motor 2

X

0

1

Activate Drive 3 and Motor 3

X

0

Activate Drive 0 and Deactivate Motor 0

Activate Drive 1 and Deactivate Motor 1

Activate Drive 2 and Deactivate Motor 2

Activate Drive 3 and Deactivate Motor 3

0

1

X

1

0

X

1

e

address 3F2h or 372h takes place. This pulse is delayed by 25 ns–80 ns after the leading edge of IOW and its leading edge can be used to clock data into an

Note 1: When FER4

1, MTR1 will present a pulse that is the inverted image of the IOW strobe. This inverted pulse will be active whenever an I/O write to

e

1). See the AC Electrical Characteristics (Section 9.2) for detailed timing.

external latch (e.g., 74LS175). Address 3F2h will be used if the FDC is located at the primary address (FER5

e

0) and address 372h will be used if the FDC is

located at the secondary address (FER5

15

2.0 Configuration Registers (Continued)

e

2.5.2 Function Address Register (FAR, Index

1)

(PWDN) is asserted (crystal and clocks vs clocks only),

whether hardware power down is enabled, and provides a

bit for software power down of all enabled functions. It se-

lects whether IRQ7 or IRQ5 is associated with LPT2. It puts

the enabled UARTs into their test mode. Independent of this

register the floppy disk controller can enter low power mode

via the Mode Command or the Data Rate Select Register.

This register selects the ISA I/O address range to which

each peripheral function will respond.

Bits 0,1 These bits select the parallel port address as

shown in Table 2-5:

TABLE 2-5. Parallel Port Addresses

Bit 0 Setting this bit causes all enabled functions to be

powered down. If the crystal power down option is

selected (see Bit 1) the crystal will also be powered

down. All register data is retained when the crystal or

clocks are stopped.

Parallel

Bit Bit

AT

XT

Port

1

0

Interrupt

Address

0

1

0

1

0

1

LPT2 (378–37F)

LPT1 (3BC–3BE)

LPT3 (278–27F)

Reserved

IRQ5 (Note)

IRQ7

Bit 1 When the Power Down pin or Bit 0 is asserted this bit

determines whether the enabled functions will have

e

their internal clocks stopped (Bit 1

0) or the exter-

1) will be stopped. Stopping the

crystal is the lowest power consumption state of the

IRQ5

e

nal crystal (Bit 1

TRI-STATE TRI-STATE

e

0)

e

(CTR4

0) (CTR4

part. However, if the crystal is stopped,

a finite

E

amount of time ( 8 ms) will be required for crystal

stabilization once the Power Down pin (PWDN) or

Bit 0 is deasserted. If all internal clocks are stopped,

but the crystal continues to oscillate, no stabilization

period is required after the Power Down pin or Bit 0 is

deasserted.

Note: The interrupt assigned to this address can be changed to IRQ7 by

setting Bit 3 of the power and test register.

Bits 2–5 These bits determine which ISA I/O address range

is associated with each UART (see Tables 2-6a,

2-6b).

Bit 2 Setting this bit enables the chip select function of the

PWDN/CSOUT pin. Resetting this bit enables the

power down function of this pin.

TABLE 2-6a. COM Port Selection for UART1

FAR

UART1

Bit 3 Setting this bit associates the parallel port with IRQ7

when the address for the parallel port is 378–37Fh

(LPT2). This bit is a ‘‘don’t care’’ when the parallel

port address is 3BC–3BEh (LPT1) or 278–27Fh

(LPT3).

Ý

COM

Bit 3

Bit 2

0

1

0

1

0

1

1 (3F8-F)

2 (2F8-F)

3 (Table 2–7)

4 (Table 2–7)

Bit 4 Setting this bit puts UART1 into a test mode, which

causes its Baudout clock to be present on its SOUT1

pin if the Line Control Register bit 7 is set to 1.

TABLE 2-6b. COM Port Selection for UART2

FAR UART2

Bit 5 Setting this bit puts UART2 into a test mode, which

causes its Baudout clock to be present on its SOUT2

pin if the Line Control Register bit 7 is set to 1.

Ý

Bit 5

Bit 4

COM

Bit 6 Setting this bit to a one prevents all further write ac-

cesses to the Configuration Registers. Once this bit is

set by software it can only be cleared by a hardware

reset. After the initial hardware reset this bit is zero.

0

1

0

1

0

1

2

3

4

Bit 7 This bit determines the operating mode of the parallel

port. If PTR7 is low, then the parallel port is in Com-

patible Mode. If PTR7 is high, then the parallel port is

in Extended Mode. This bit will be the inverse of the

state of the POE pin immediately after reset has oc-

curred. PTR7 can be programmed at any time.

Note: COM3 and COM4 addresses are determined by Bits 6 and 7.

Bits 6,7 These bits select the addresses that will be used

for COM3 and COM4 (see Table 2-7).

2.6 POWER DOWN OPTIONS

TABLE 2-7. Address Selection for COM3 and COM4

There are various methods for entering the power down

mode. All methods result in one of three possible modes.

This section associates the methods of entering the power

down with the resulting mode.

Bit 7

Bit 6

COM3 IRQ4

3E8–Fh

338–Fh

COM4 IRQ3

2E8–Fh

238–Fh

0

1

0

1

0

1

Mode 1: The internal clock stops for a specific function (i.e.,

UART1 and/or UART2 and/or FDC).

2E8–Fh

220–7h

2E0–7h

This mode is entered by:

228–Fh

A. Clearing the FER bit for the specific function that will be

powered down. See Section 2.5.1 FER bits 1–3.

e

2.5.3 Power and Test Register (PTR, Index

2)

B. Also during reset by setting certain CFG0–4 pins. See

Table 2-1.

This register determines several power down features: the

power down method used when the power down pin

16

2.0 Configuration Registers (Continued)

C. Or by executing the FDC Mode Command with the PTR

3. and if the PWDN pin option (PTR2) is used the CSOUT/

PDWN pin must be inactive.

e

bit 1

0. (XTAL/CLK) See Section 4.2.6 LOW PWR.

D. Or by setting Data Rate Select Register bit 6 high in the

e

If the crystal has been stopped follow the guidelines in Sec-

tion 2.7.1 before sending data or signaling that the receiver

channel is ready.

FDC with the PTR bit 1

0. See Section 3.6 bit 6.

Mode 2: The internal clocks are stopped for all enabled

functions.

2.7.3 FDC Power-Up

Note: Clocks to disabled functions are always inactive.

The clock signal to the FDC is controlled through the Con-

figuration Registers, the FDC Mode Command and the Data

Rate Select Register. In order to restore the clock signal to

the FDC the following conditions must exist:

This mode is entered by:

A. Clearing all FER bits for any enabled function. See Sec-

tion 2.5.1 (FER bits 1–3).

B. Or by clearing PTR bits 1 (XTAL/CLK) and 2 (CSOUT/

PWDN select) and then asserting the PWDN signal low.

See Section 2.5.3 PTR bits 1,2 and Section 1.0 PWDN

pin.

1. The appropriate enable bit (FER3) must be set

2. and the Power Down bit (PTR0) must not be set

3. and if the PWDN pin option (PTR2) is used the CSOUT/

PDWN pin must be inactive.

C. Or by clearing PTR bit 1 and then setting PTR bit 0 (Pow-

er Down) high. See Section 2.5.3 (PTR bits 0 and 1).

In addition to these conditions, one of the following must be

done to initiate the recovery from Power Down mode:

Mode 3: The external crystal is stopped and internal clocks

are stopped for all enabled functions.

1. Read the Main Status Register until the ROM bit (MSR7)

is set

This mode is entered by:

2. or write to the Data Rate Select Register and set the

Software Reset bit (DSR7)

A. Clearing all FER bits that enable the FDC, UART1, and

UART2 functions. See Section 2.5.1 (FER bits 1–3).

3. or write to the Digital Output Register and set, and then

the clear Reset bit (DOR2)

B. Setting PTR bit

1 (XTAL/CLK), clearing PTR bit 2

(CSOUT/PWDN select), and then asserting the PWDN

signal low. See Section 2.5.3 PTR bits 1,2 and Section

1.0 PWDN pin.

4. or read the Data Register and the Main Status Register

until the ROM bit is set.

If the crystal has been stopped, read the RQM bit in the

Main Status Register until it is set. The RQM bit does not get

set until the crystal has stabilized.

C. Or by setting PTR bit 1 and then setting PTR bit 0 high.

See Section 2.5.3 PTR bits 0 and 1.

D. Or during reset by pulling CFG0–4 pins high.

E. Or by executing the FDC Mode Command with the PTR

e

3.0 FDC Register Description

bit 1

1. See Section 4.2.6 LOW PWR.

The floppy disk controller is suitable for all PC-AT, EISA,

PS/2, and general purpose applications. The operational

mode (PC-AT, PS/2, and Model 30) of the FDC is deter-

mined by hardware strapping of the IDENT and MFM pins.

DP8473 and N82077 software compatibility is provided. Key

features include the 16-byte FIFO, PS/2 diagnostic register

support, the perpendicular recording mode, CMOS disk in-

terface, and a high performance analog data separator.

F. Or by setting Data Rate Select Register bit 6 high in the

e

FDC with the PTR bit 1

1. See Section 3.6 bit 6.

2.7 POWER-UP PROCEDURE AND CONSIDERATIONS

2.7.1 Crystal Stabilization

If the crystal is stopped by putting either the FDC or the

UARTs into low power mode, then a finite amount of time

E

(

8 ms) must be allowed for crystal stabilization during

The FDC supports the standard PC data rates of 250 kb/s,

300 kb/s and 500 kb/s, and 1 Mb/s in MFM encoded data

mode, but is no longer guaranteed through functional test-

ing to support the older FM encoded data mode. Refer-

ences to the older FM mode remain in this document to

clarify the true functional operation of the device.

subsequent power-up. The stabilization period can be

sensed by reading the Main Status Register in the FDC, if

the FDC is being powered up. (The Request for Master bit

E

will not be set for 8 ms.) If either one of the UARTs are

being powered up, but the FDC is not, then the software

E

must determine the 8 ms crystal stabilization period. Sta-

The 1 Mb/s data rate is used by new high performance tape

and floppy drives emerging in the PC market today. The new

floppy drives utilize high density media which requires the

FDC supported perpendicular recording mode format. When

used with the 1 Mb/s data rate this new format allows the

use of 4 MB floppy drives which format ED media to 2.88

MB data capacity.

bilization of the crystal can also be sensed by putting the

UART into local loopback mode and sending bytes until

they are received correctly.

2.7.2 UART Power-Up

The clock signal to the UARTs is controlled through the

Configuration Registers (FER, PTR). In order to restore the

clock signal to one or both UARTs the following conditions

must exist:

The high performance internal analog data separator needs

no external components. It improves on the window margin

performance standards of the DP8473, and is compatible

with the strict data separator requirements of floppy and

floppy-tape drives.

1. The appropriate enable bit (FER1,2) for the UART(s)

must be set

2. and the Power Down bit (PTR0) must not be set

17

3.0 FDC Register Description (Continued)

TL/F/11362–4

FIGURE 3-1. FDC Functional Block Diagram

The FDC contains write precompensation circuitry that will

default to 125 ns for 250, 300, and 500 kb/s (41.67 ns at

1 Mb/s). These values can be overridden in software to

disable write precompensation or to provide levels of pre-

compensation up to 250 ns. The FDC has internal 24 mA

data bus buffers which allow direct connection to the sys-

tem bus. The internal 40 mA totem-pole disk interface buff-

ers are compatible with both CMOS drive inputs and 150X

resistor terminated disk drive inputs.

TABLE 3-1. Register Description and Addresses

A2 A1 A0 IDENT R/W

Register

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

R

Status Register A

Status Register B

SRA

SRB

DOR

TDR

MSR

DSR

FIFO

X

R/W Digital Output Register

R/W Tape Drive Register

R

Main Status Register

W

Data Rate Select Register

R/W Data Register (FIFO)

The following FDC registers are mapped into the addresses

shown below, with the base address range being provided

by the on-chip address decoder pin. For PC-AT or PS/2

applications, the diskette controller primary address range is

3F0 to 3F7 (hex), and the secondary address range is 370

to 377 (hex). The FDC supports three different register

modes: the PC-AT mode, PS/2 mode (Micro Channel sys-

tems), and the Model 30 mode (Model 30). See Section 5.1

for more details on how each register mode is enabled.

When applicable, the register definition for each mode of

operation will be given. If no special notes are made, then

the register is valid for all three register modes.

X

R

None (Bus TRI-STATE)

Digital Input Register

DIR

W

Configuration Control Register CCR

e

Note: SRA and SRB are enabled by IDENT

0 during a chip reset only.

3.1 STATUS REGISTER A (SRA) Read Only

This is a read-only diagnostic register that is part of the

PS/2 floppy controller register set, and is enabled when in

the PS/2 or Model 30 mode. This register monitors the state

of the IRQ6 pin and some of the disk interface signals. The

SRA can be read at any time when in PS/2 mode. In the

PC-AT mode, D7–D0 are TRI-STATE during a mP read.

18

3.0 FDC Register Description (Continued)

3.1.1 SRAÐPS/2 Mode

3.2 STATUS REGISTER B (SRB) Read Only

This is a read-only diagnostic register that is part of the

PS/2 floppy controller register set, and is enabled when in

the PS/2 or Model 30 mode. The SRB can be read at any

time when in PS/2 mode. In the PC-AT mode, D7–D0 are

TRI-STATE during a mP read.

D7

D6

D5

D4

D3

D2

D1

D0

DESC

IRQ6

DRV2 STEP TRK0 HDSEL INDX WP DIR

PEND

RESET

COND

0

N/A

0

N/A

0

N/A N/A

0

3.2.1 SRBÐPS/2 Mode

D7

Interrupt Pending: This active high bit reflects the

state of the IRQ6 pin.

D7

D6

D5

D4

D3

D2

D1

D0

DESC

1

DR0 WDATA RDATA WGATE MTR1 MTR0

D6

2nd Drive Installed: Active low status of the

DRV2 disk interface input, indicating if a second

drive has been installed.

RESET

COND

N/A N/A

0

D5

D4

D3

D2

D1

D0

Step: Active high status of the STEP disk interface

output.

D7

D6

D5

Reserved: Always 1.

Track 0: Active low status of the TRK0 disk inter-

face input.

Drive Select 0: Reflects the status of the Drive Se-

lect 0 bit in the DOR (address 2, bit 0). This bit is

cleared after a hardware reset, not a software reset.

Head Select: Active high status of the HDSEL disk

interface output.

D4

D3

Write Data: Every inactive edge transition of the

WDATA disk interface output causes this bit to

change states.

Index: Active low status of the INDEX disk interface

input.

Write Protect: Active low status of the WP disk in-

terface input.

Read Data: Every inactive edge transition of the

RDATA disk interface output causes this bit to

change states.

Direction: Active high status of the DIR disk inter-

face output.

D2

D1

Write Gate: Active high status of the WGATE disk

interface output.

3.1.2 SRAÐ Model 30 Mode

Motor Enable 1: Active high status of the MTR1

disk interface output. Low after a hardware reset,

unaffected by a software reset.

D7

D6

D5

D4

D3

D2

D1

D0

DESC

IRQ6

DRQ STEP TRK0 HDSEL INDX WP DIR

PEND

D0

Motor Enable 0: Active high status of the MTR0

disk interface output. Low after a hardware reset,

unaffected by a software reset.

RESET

COND

0

N/A

1

N/A N/A

1

3.2.2 SRBÐModel 30 Mode

D7

Interrupt Pending: This active high bit reflects that

state of the IRQ6 pin.

D7

D6

D5

D4

D3

D2

D1

D0

D6

D5

DMA Request: Active high status of the DRQ signal.

DESC

DRV2 DR1 DR0 WDATA RDATA WGATE DR3 DR2

Step: Active high status of the latched STEP disk

interface output. This bit is latched with the STEP

output going active, and is cleared with a read from

the DIR, or with a hardware or software reset.

RESET

COND

N/A

1

0

1

D7

2nd Drive Installed: Active low status of the

DRV2 disk interface input.

D4

D3

D2

D1

D0

Track 0: Active high status of TRK0 disk interface

input.

D6

D5

D4

Drive Select 1: Active low status of the DR1 disk

interface output.

Head Select: Active low status of the HDSEL disk

interface output.

Drive Select 0: Active low status of the DR0 disk

interface output.

Index: Active high status of the INDEX disk inter-

face input.

Write Data: Active high status of latched WDATA

signal. This bit is latched by the inactive going edge

of WDATA and is cleared by a read from the DIR.

This bit is not gated by WGATE.

Write Protect: Active high status of the WP disk

interface input.

Direction: Active low status of the DIR disk inter-

face output.

19

3.0 FDC Register Description (Continued)

D3

Read Data: Active high status of latched RDATA

signal. This bit is latched by the inactive going edge

of RDATA and is cleared by a read from the DIR.

It is common programming practice to enable both the mo-

tor enable and drive select outputs for a particular drive.

Table 3-2 below shows the DOR values to enable each of

the four drives.

D2

Write Gate: Active high status of latched WGATE

signal. This bit is latched by the active going edge of

WGATE and is cleared by a read from the DIR.

TABLE 3-2. Drive Enable Values

Drive

DOR Value

D1

D0

Drive Select 3: Active low status of the DR3 disk

interface output. (Note 1)

0

1

2

3

1C (hex)

2D

Drive Select 2: Active low status of the DR2 disk

interface output. (Note 1)

4E

8F

3.3 DIGITAL OUTPUT REGISTER (DOR) Read/Write

The DOR controls the drive select and motor enable disk

interface outputs, enables the DMA logic, and contains a

software reset bit. The content of the DOR is set to 00 (hex)

after a hardware reset, and is unaffected by a software re-

set. (Note 2)

3.4 TAPE DRIVE REGISTER (TDR) Read/Write

This register is used to assign a particular drive number with

the tape drive support mode of the data separator. All other

logical drives are assigned floppy drive support with the

data separator. Any future reference to the assigned tape

drive will invoke tape drive support. The TDR is unaffected

by a software reset.

DOR

D7

D6

D5

D4

D3

D2

D1

D0

TDR

DRIVE DRIVE

SEL 1 SEL 0

DESC MTR3 MTR2 MTR1 MTR0 DMAEN RESET

D7

D6

D5

D4

D3

D2

D1

D0

RESET

0

DESC

TAPE

SEL 1

TAPE

SEL 0

COND

X

RESET

COND

D7

Motor Enable 3: This bit controls the MTR3 disk

interface output. A 1 in this bit causes the MTR3 pin

to go active. (Note 1)

N/A

0

D7–D2 Reserved: These bits are ignored when written to

and are TRI-STATE when read.

D6

D5

D4

D3

Motor Enable 2: Same function as D7 except for

MTR2. (Note 1)

D1,D0 Tape Select 1,0: These two bits assign a logical

drive number to be a tape drive. Drive 0 is not avail-

able as a tape drive, and is reserved as the floppy

disk boot drive. See Table 3-3 for the tape drive

assignment values.

Motor Enable 1: Same function as D7 except for

MTR1.

Motor Enable 0: Same function as D7 except for

MTR0.

DMA Enable: This bit has two modes of operation.

PC-AT mode or Model 30 mode: Writing a 1 to this

bit will enable the DRQ, DACK, TC, and IRQ6 pins.

Writing a 0 to this bit will disable the DACK and TC

pins and TRI-STATE the DRQ and the IRQ6 pins.

This bit is a 0 after a reset when in these modes.

PS/2 mode: This bit is reserved, and the DRQ,

DACK, TC, and IRQ6 pins will always be enabled.

During a reset, the DRQ, DACK, TC, and IRQ6 lines

will remain enabled, and D3 will be a 0.

TABLE 3-3. Tape Drive Assignment Values

Drive

TAPESEL1

TAPESEL0

Selected

0

1

0

1

0

1

None

1

2

3

D2

Reset Controller: Writing a 0 to this bit resets the

controller. It will remain in the reset condition until a

1 is written to this bit. A software reset does not

affect the DSR, CCR, and other bits of the DOR. A

software reset will affect the Configure and Mode

command bits (see Section 4.0 Command Set De-

scription). The minimum time that this bit must be

low is 100 ns. Thus, toggling the Reset Controller bit

during consecutive writes to the DOR is an accept-

able method of issuing a software reset.

3.5 MAIN STATUS REGISTER (MSR) Read Only

The read-only Main Status Register indicates the current

status of the disk controller. The Main Status Register is

always available to be read. One of its functions is to control

the flow of data to and from the Data Register (FIFO). The

Main Status Register indicates when the disk controller is

ready to send or receive data through the Data Register. It

should be read before each byte is transferred to or from

the Data Register except during a DMA transfer. No delay is

required when reading this register after a data transfer.

D1,D0 Drive Select: These two bits are binary encoded for

the four drive selects DR0–DR3, so that only one

drive select output is active at a time. (Note 1)

e

Note 1: The MTR3, MTR2, DRV3, DRV2 pins are only available in 4-drive mode (FER4

1) and require external logic.

Note 2: The DOR can be written to at any time, but only one drive select output in conjunction with its corresponding motor is active at a time.

20

3.0 FDC Register Description (Continued)

After a hardware or software reset, or recovery from a pow-

er down state, the Main Status Register is immediately avail-

able to be read by the mP. It will contain a value of 00 hex

until the oscillator circuit has stabilized, and the internal reg-

isters have been initialized. When the FDC is ready to re-

ceive a new command, it will report an 80 hex to the mP.

The system software can poll the MSR until it is ready. The

worst case time allowed for the MSR to report an 80 hex

value (RQM set) is 2.5 ms after reset or power up.

The DSR is unaffected by a software reset. A hardware re-

set will set the DSR to 02 (hex), which corresponds to the

default precompensation setting and 250 kb/s.

DSR

D7

D6

D5

D4

D3

D2

D1

D0

DESC

S/W

LOW

PRE-

0

DRATE1 DRATE0

RESET POWER

COMP2 COMP1 COMP0

RESET

COND

0

1

0

MSR

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

Software Reset: This bit has the same function as

the DOR RESET (D2) except that this software re-

set is self-clearing.

DESC

RQM DIO NON

CMD

DRV3 DRV2 DRV1 DRV0

DMA PROG BUSY BUSY BUSY BUSY

RESET

COND

Low Power: A 1 to this bit will put the controller into

the Manual Low Power mode. The oscillator and

data separator circuits will be turned off. Manual

Low Power can also be accessed via the Mode

command. The chip will come out of low power after

a software reset, or access to the Data Register or

Main Status Register.

0

D7

Request for Master: Indicates that the controller is

ready to send or receive data from the mP through

the FIFO. This bit is cleared immediately after a byte

transfer and will become set again as soon as the

disk controller is ready for the next byte. During a

Non-DMA Execution phase, the RQM indicates the

status of the interrupt pin.

D5

Undefined. Should be set to 0.

D4–D2 Precompensation Select: These three bits select

the amount of write precompensation the floppy

controller will use on the WDATA disk interface out-

put. Table 3-4 shows the amount of precompensa-

tion used for each bit pattern. In most cases, the

default values (Table 3-5) can be used; however,

alternate values can be chosen for specific types of

drives and media. Track 0 is the default starting

track number for precompensation. The starting

track number can be changed in the Configure com-

mand.

D6

D5

Data I/O (Direction): Indicates whether the con-

troller is expecting a byte to be written to (0) or read

from (1) the Data Register.

Non-DMA Execution: Indicates that the controller

is in the Execution Phase of a byte transfer opera-

tion in the Non-DMA mode. Used for multiple byte

transfers by the mP in the Execution Phase through

interrupts or software polling.

D4

D3

Command in Progress: This bit is set after the first

byte of the Command Phase is written. This bit is

cleared after the last byte of the Result Phase is

read. If there is no Result Phase in a command, the

bit is cleared after the last byte of the Command

Phase is written.

TABLE 3-4. Write Precompensation Delays

Precomp 432

Precompensation Delay

111

001

010

011

100

101

110

000

0.0 ns

41.7 ns

Drive 3 Busy: Set after the last byte of the Com-

mand Phase of a Seek or Recalibrate command is

issued for drive 3. Cleared after reading the first

byte in the Result Phase of the Sense Interrupt

Command for this drive.

83.3 ns

125.0 ns

166.7 ns

208.3 ns

250.0 ns

DEFAULT

D2

D1

D0

Drive 2 Busy: Same as above for drive 2.

Drive 1 Busy: Same as above for drive 1.

Drive 0 Busy: Same as above for drive 0.

TABLE 3-5. Default Precompensation Delays

3.6 DATA RATE SELECT REGISTER (DSR) Write Only

Data Rate

Precompensation Delay

This write-only register is used to program the data rate,

amount of write precompensation, power down mode, and

software reset. The data rate is programmed via the CCR,

not the DSR, for PC-AT and PS/2 Model 30 and MicroChan-

nel applications. Other applications can set the data rate in

the DSR. The data rate of the floppy controller is deter-

mined by the most recent write to either the DSR or CCR.

1 Mb/s

500 kb/s

300 kb/s

250 kb/s

41.7 ns

125.0 ns

21

3.0 FDC Register Description (Continued)

D1,D0 Data Rate Select 1,0: These bits determine the

data rate for the floppy controller. See Table 3-6 for

the corresponding data rate for each value of D1,

D0. The data rate select bits are unaffected by a

software reset, and are set to 250 kb/s after a hard-

ware reset.

Configure command, which sets the FIFO threshold. If the

FIFO is disabled, THRESH is zero in the above formula. The

c

last term of the formula, (16

to the microcode overhead required by the FDC. This delay

is also data rate dependent. See Table 9-1 for the t and

t

) is an inherent delay due

ICP

DRP

t

times.

ICP

The programmable FIFO threshold (THRESH) is useful in

adjusting the floppy controller to the speed of the system. In

other words, a slow system with a sluggish DMA transfer

capability would use a high value of THRESH, giving the

system more time to respond to a data transfer service re-

quest (DRQ for DMA mode or IRQ6 for Interrupt mode).

Conversely, a fast system with quick response to a data

transfer service request would use a low value of THRESH.

TABLE 3-6. Data Rate Select Encoding

Data Rate Select

Data Rate

MFM

1

0

FM

1

0

1

0

1

0

1 Mb/s

500 kb/s

300 kb/s

250 kb/s

Illegal

250 kb/s

150 kb/s

125 kb/s

3.8 DIGITAL INPUT REGISTER (DIR) Read Only

This diagnostic register is used to detect the state of the

DSKCHG disk interface input and some diagnostic signals.

The function of this register depends on the register mode

of operation. When in the PC-AT mode, the D6–D0 are

TRI-STATE to avoid conflict with the fixed disk status regis-

ter at the same address. The DIR is unaffected by a soft-

ware reset.

Note: FM mode is not guaranteed through functional testing.

3.7 DATA REGISTER (FIFO) Read/Write

The FIFO (read/write) is used to transfer all commands,

data, and status between the mP and the FDC. During the

Command Phase, the mP writes the command bytes into the

FIFO after polling the RQM and DIO bits in the MSR. During

the Result Phase, the mP reads the result bytes from the

FIFO after polling the RQM and DIO bits in the MSR.

3.8.1 DIRÐPC-AT Mode

D7

D6

D5

D4

D3

D2

D1

D0

The enabling of the FIFO and setting of the FIFO threshold

is done via the Configure command. If the FIFO is enabled,

only the Execution Phase byte transfers use the 16 byte

FIFO. The FIFO is always disabled during the Command

and Result Phases of a controller operation. If the FIFO is

enabled, it will not be disabled after a software reset if the

LOCK bit is set in the Lock Command. After a hardware

reset, the FIFO is disabled to maintain compatibility with

PC-AT systems.

DESC

DSKCHG

X

RESET

COND

N/A

N/A N/A N/A N/A N/A N/A N/A

D7

Disk Changed: Active high status of DSKCHG disk

interface input. During power down this bit will be

invalid, if it is read by the software.

D6–D0 Undefined: TRI-STATE. Used by Hard Disk Con-

troller Status Register.

The 16-byte FIFO can be used for DMA, Interrupt, or soft-

ware polling type transfers during the execution of a read,

write, format, or scan command. In addition, the FIFO can

be put into a Burst or Non-Burst mode with the Mode com-

mand. In the Burst mode, DRQ or IRQ6 remains active until

all of the bytes have been transferred to or from the FIFO. In

the Non-Burst mode, DRQ or IRQ6 is deasserted for 350 ns

to allow higher priority transfer requests to be serviced. The

Mode command can also disable the FIFO for either reads

or writes separately. The FIFO allows the system a larger

latency without causing a disk overrun/underrun error. Typi-

cal uses of the FIFO would be at the 1 Mb/s data rate, or

with multi-tasking operating systems. The default state of

the FIFO is disabled, with a threshold of zero. The default

state is entered after a hardware reset.

3.8.2 DIRÐPS/2 Mode

1

D7

D6

D5

D4

D3

D2

D1

D0

DESC

HIGH

DEN

DSKCHG

1

DRATE1 DRATE0

RESET

COND

N/A

N/A N/A N/A N/A

N/A

1

D7

Disk Changed: Active high status of DSKCHG disk

interface input. During power down this bit will be

invalid, if it is read by the software.

D6–D3 Reserved: Always 1.

D2,D1 Data Rate Select 1,0: These bits indicate the

status of the DRATE1,0 bits programmed through

the DSR CCR.

Data Register (FIFO)

D7

D6

D5

D4

D3

D2

D1

D0

High Density: This bit is low when the 1 Mb/s or

500 kb/s data rate is chosen, and high when the

300 kb/s or 250 kb/s data rate is chosen. This bit is

independent of the IDENT value.

[

Data 7:0

]

DESC

RESET

COND

Byte Mode

During the Execution Phase of a command involving data

transfer to/from the FIFO, the system must respond to a

data transfer service request based on the following formu-

la:

3.8.3 DIRÐModel 30 Mode

D7

D6 D5 D4

D3

D2

D1

D0

DESC DSKCHG

0

DMAEN NOPRE DRATE1 DRATE0

RESET

N/A

COND

Maximum Allowable Data Transfer Service Time

0

1

0

a

c

b

c

(16 t

ICP

(THRESH

1)

8

t

)

DRP

This formula is good for all data rates with the FIFO enabled

or disabled. THRESH is a four bit value programmed in the

22

3.0 FDC Register Description (Continued)

D7

Disk Changed: Active low status of DSKCHG disk

interface input. During power down this bit will be

invalid, if it is read by the software.

D7–D6 Interrupt Code:

e

00

01

Normal Termination of Command.

Abnormal Termination of Command. Execu-

tion of command was started, but was not

successfully completed.

D6–D4 Reserved: Always 0.

D3

DMA Enable: Active high status of the DMAEN bit

in the DOR.

e

10

11

Invalid Command Issued. Command issued

was not recognized as a valid command.

D2

No Precompensation: Active high status of the

NOPRE bit in the CCR.

Internal drive ready status changed state dur-

ing the drive polling mode. Only occurs after a

hardware or software reset.

D1,D0 Data Rate Select 1,0: These bits indicate the

status of the DRATE 1,0 bits programmed through

the DSR/CCR.

D5

D4

Seek End: Seek, Relative Seek, or Recalibrate

command completed by the controller. (Used during

a Sense Interrupt command.)

3.9 CONFIGURATION CONTROL REGISTER (CCR)

Write Only

Equipment Check: After a Recalibrate command,

Track 0 signal failed to occur. (Used during Sense

Interrupt command.)

This is the write-only data rate register commonly used in

PC-AT applications. This register is not affected by a soft-

ware reset, and is set to 250 kb/s after a hardware reset.

The data rate of the floppy controller is determined by the

last write to either the CCR or DSR.

D3

D2

Not Used. Always 0.

Head Select: Indicates the active high status of the

HDSEL pin at the end of the Execution Phase.

3.9.1 CCRÐPC-AT and PS/2 Modes

D1,D0 Drive Select 1,0: These two binary encoded bits

indicate the logical drive selected at the end of the

Execution Phase.

D7

D6

D5

D4

D3

D2

D1

D0

DESC

0

DRATE1 DRATE0

e

RESET

COND

00

01

10

11

Drive 0 selected.

Drive 1 selected.

Drive 2 selected.

Drive 3 selected.

N/A N/A N/A N/A N/A N/A

1

0

D7–D2 Reserved: Should be set to 0.

D1,D0 Data Rate Select 1,0: These bits determine the

data rate of the floppy controller. See Table 3-6 for

the appropriate values.

3.10.2 Status Register 1 (ST1)

D7

D6

D5

D4

D3

D2

D1

D0

3.9.2 CCRÐModel 30 Mode

DESC

ET

0

CE

OR

0

ND

NW

MA

D7

D6

D5

D4

D3

D2

D1

D0

RESET

COND

0

DESC

0

NOPRE DRATE1 DRATE0

RESET

COND

N/A N/A N/A N/A N/A

N/A

1

0

D7

End of Track: Controller transferred the last byte of

the last sector without the TC pin becoming active.

The last sector is the End of Track sector number

programmed in the Command Phase.

D7–D3 Reserved: Should be set to 0.

D2

No Precompensation: This bit can be set by soft-

ware, but it has no functionality. It can be read by bit

D2 of the DIR when in the Model 30 register mode.

Unaffected by a software reset.

D6

D5

Not Used. Always 0.

CRC Error: If this bit is set and bit 5 of ST2 is clear,

then there was a CRC error in the Address Field of

the correct sector. If bit 5 of ST2 is also set, then

there was a CRC error in the Data Field.

D1,D0 Data Rate Select 1,0: These bits determine the

data rate of the floppy controller. See Table 3-6 for

the appropriate values.

D4

Overrun: Controller was not serviced by the mP

soon enough during a data transfer in the Execution

Phase. For read operations, indicates a data over-

run. For write operations, indicates a data underrun.

3.10 RESULT PHASE STATUS REGISTERS

The Result Phase of a command contains bytes that hold

status information. The format of these bytes is described

below. Do not confuse these status bytes with the Main

Status Register, which is a read only register that is always

valid. The Result Phase status registers are read from the

Data Register (FIFO) only during the Result Phase of certain

commands (see Section 4.1 Command Set Summary). The

status of each register bit is indicated when the bit is a 1.

D3

D2

Not Used. Always 0.

No Data: Three possible problems:

1. Controller cannot find the sector specified in the

Command Phase during the execution of a Read,

Write, Scan, or Verify command. An address

mark was found however, so it is not a blank disk.

2. Controller cannot read any Address Fields with-

out a CRC error during a Read ID command.

3.10.1 Status Register 0 (ST0)

D7

D6

D5

D4

D3

D2

D1

D0

3. Controller cannot find starting sector during exe-

cution of Read A Track command.

DESC

IC

SE

EC

0

HDS

DS1

DS0

D1

Not Writable: Write Protect pin is active when a

Write or Format command is issued.

RESET

COND

0

23

3.0 FDC Register Description

(Continued)

4.0 FDC Command Set Description

The following is a table of the FDC command set. Each

command contains a unique first command byte called the

opcode byte which will identify to the controller how many

command bytes to expect. If an invalid command byte is

issued to the controller, it will immediately go into the Result

Phase and the status will be 80 (hex), which signifies Invalid

Command.

D0

Missing Address Mark: If bit 0 of ST2 is clear then

the controller cannot detect any Address Field Ad-

dress Mark after two disk revolutions. If bit 0 of ST2

is set then the controller cannot detect the Data

Field Address Mark after finding the correct Ad-

dress Field.

3.10.3 Status Register 2 (ST2)

4.1 COMMAND SET SUMMARY

CONFIGURE

D7

D6

D5

D4

D3

D2

D1

D0

DESC

0

CM

CD

WT

SEH

SNS

BT

MD

Command Phase

RESET

COND

0

1

0

1

0

1

0

D7

Not Used. Always 0.

EIS

FIFO

POLL

PRETRK

THRESH

D6

Control Mark: Controller tried to read a sector

which contained a deleted data address mark dur-

ing execution of Read Data or Scan commands. Or,

if a Read Deleted Data command was executed, a

regular address mark was detected.

Execution Phase: Internal registers written.

No Result Phase

D5

D4

CRC Error in Data Field: Controller detected a

CRC error in the Data Field. Bit 5 of ST1 is also set.

DUMPREG

Command Phase

Wrong Track: Only set if desired sector is not

found, and the track number recorded on any sector

of the current track is different from the track ad-

dress specified in the Command Phase.

0

1

0

Execution Phase: Internal registers read.

D3

D2

Scan Equal Hit: ‘‘Equal’’ condition satisfied during

any Scan command.

Result Phase

PTR Drive 0

PTR Drive 1

PTR Drive 2

PTR Drive 3

Scan Not Satisfied: Controller cannot find a sector

on the track which meets the desired condition dur-

ing any Scan command.

D1

D0

Bad Track: Only set if the desired sector is not

found, the track number recorded on any sector on

the track is FF (hex) indicating a hard error in IBM

format, and is different from the track address spec-

ified in the Command Phase.

Step Rate Time

Motor On Time

Sector per Track/End of Track

Motor Off Time

DMA

WG

Missing Address Mark in Data Field: Controller

cannot find the Data Field AM during a Read, Scan,

or Verify command. Bit 0 of ST1 is also set.

LOCK

0

DC3

DC2

DC1

DC0

GAP

EIS

FIFO

POLL

THRESH

PRETRK

3.10.4 Status Register 3 (ST3)

Note: Sectors per Track parameter returned if last command issued was

Format. End of Track parameter returned if last command issued was Read

or Write.

D7

D6

D5

D4

D3

D2

D1

D0

DESC

0

WP

1

TK0

1

HDS

DS1

DS0

RESET

COND

0

1

0

1

0

FORMAT TRACK

Command Phase

D7

Not Used. Always 0.

0

MFM

X

0

1

0

1

D6

Write Protect: Indicates active high status of the

WP pin.

X

HD

DR1

DR0

Bytes per Sector

D5

D4

Not Used. Always 1.

Sectors per Track

Format Gap

Track 0: Indicates active high status of the TRK0

pin.

D3

D2

Not Used. Always 1.

Data Pattern

Head Select: Indicates the active high status of the

HD bit in the Command Phase.

Execution Phase: System transfers four ID bytes (track,

head, sector, bytes/sector) per sector to the floppy control-

ler via DMA or Non-DMA modes. The entire track is format-

ted. The data block in the Data Field of each sector is filled

with the data pattern byte.

D1,D0 Drive Select 1,0: These two binary encoded bits

indicate the DS1,DS0 bits in the Command Phase.

24

4.0 FDC Command Set Description (Continued)

Result Phase

READ DATA

Status Register 0

Status Register 1

Status Register 2

Undefined

Command Phase

MT

IPS

MFM

X

SK

X

0

1

0

X

HD

DR1

DR0

Track Number

Undefined

Drive Head Number

Sector Number

Undefined

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Data Length

INVALID

Command Phase

Invalid Op Codes

Execution Phase: Data read from disk drive is transferred

to system via DMA or Non-DMA modes.

Result Phase

Status Register 0 (80 hex)

Status Register 0

Status Register 1

Status Register 2

Track Number

LOCK

Command Phase

LOCK

0

1

0

1

0

Head Number

Execution Phase: Internal register is written.

Sector Number

Bytes per Sector

Result Phase

0

LOCK

0

READ DELETED DATA

Command Phase

MODE

MT

IPS

MFM

X

SK

X

0

1

0

Command Phase

X

HD

DR1

DR0

0

1

ETR

0

Track Number

TMR

FWR

IAF

FRD

IPS

BST

BFR

0

LOW PWR

1

0

Drive Head Number

Sector Number

R255

WLD

0

DENSEL

Head Settle

RG

Bytes per Sector

0

PU

End of Track Sector Number

Intersector Gap Length

Data Length

Execution Phase: Internal registers are written.

No Result Phase

Execution Phase: Data read from disk drive is transferred

to system via DMA or Non-DMA modes.

NSC

Command Phase

Result Phase

0

1

0

1

0

1

Status Register 0

Status Register 1

Status Register 2

Track Number

Result Phase

0

1

PERPENDICULAR MODE

Command Phase

Head Number

Sector Number

Bytes per Sector

0

1

0

1

0

OW

DC3

DC2

DC1

DC0

GAP

WG

Execution Phase: Internal registers are written.

No Result Phase

25

4.0 FDC Command Set Description (Continued)

READ ID

RELATIVE SEEK

Command Phase

0

MFM

X

0

1

0

1

0

1

DIR

X

0

1

X

HD

DR1

DR0

X

HD

DR1

DR0

Relative Track Number

Execution Phase: Controller reads first ID Field header

bytes it can find and reports these bytes to the system in the

result bytes.

Execution Phase: Disk drive head stepped in or out a pro-

grammable number of tracks.

Result Phase

No Result Phase

Status Register 0

Status Register 1

Status Register 2

Track Number

SCAN EQUAL

Command Phase

MT

IPS

MFM

X

SK

X

1

0

1

Head Number

X

HD

DR1

DR0

Sector Number

Bytes per Sector

Track Number

Drive Head Number

Sector Number

READ A TRACK

Command Phase

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Sector Step Size

0

MFM

X

0

1

0

IPS

X

HD

DR1

DR0

Track Number

Execution Phase: Data transferred from system to control-

ler is compared to data read from disk.

Drive Head Number

Sector Number

Result Phase

Bytes per Sector

Status Register 0

Status Register 1

Status Register 2

Track Number

End of Track Sector Number

Intersector Gap Length

Data Length

Head Number

Execution Phase: Data read from disk drive is transferred

to system via DMA or non-DMA modes.

Sector Number

Bytes per Sector

Result Phase

Status Register 0

Status Register 1

Status Register 2

Track Number

SCAN HIGH OR EQUAL

Command Phase

MT

IPS

MFM

X

SK

X

1

0

1

Head Number

X

HD

DR1

DR0

Sector Number

Bytes per Sector

Track Number

Drive Head Number

Sector Number

RECALIBRATE

Bytes per Sector

Command Phase

End of Track Sector Number

Intersector Gap Length

Sector Step Size

0

1

0

1

DR1

DR0

Execution Phase: Disk drive head is stepped out to Track

0.

Execution Phase: Data transferred from system to control-

ler is compared to data read from disk.

No Result Phase

26

4.0 FDC Command Set Description (Continued)

Result Phase

Status Register 0

Status Register 1

Status Register 2

Track Number

Status Register 3

SENSE INTERRUPT

Command Phase

Head Number

0

1

0

Sector Number

Bytes per Sector

Execution Phase: Status of interrupt is reported.

Result Phase

Status Register 0

SCAN LOW OR EQUAL

Command Phase

Present Track Number (PTR)

MSN of PTR

0

MT

IPS

MFM

X

SK

X

1

0

1

Note: Third Result Phase byte can only be read if ETR is set in the Mode

X

HD

DR1

DR0

Command.

Track Number

Drive Head Number

Sector Number

SET TRACK

Command Phase

Bytes per Sector

0

WNR

0

1

0

1

0

1

End of Track Sector Number

Intersector Gap Length

Sector Step Size

MSB

DR1

DR0

New Track Number (PTR)

Execution Phase: Internal register is read or written.

Execution Phase: Data transferred from system to control-

ler is compared to data read from disk.

Result Phase

Value

Result Phase

Status Register 0

Status Register 1

Status Register 2

Track Number

SPECIFY

Command Phase

0

1

Step Rate Time

Motor On Time

Motor Off Time

Head Number

DMA

Sector Number

Bytes per Sector

Execution Phase: Internal registers are written.

No Result Phase

SEEK

Command Phase

VERIFY

0

1

Command Phase

X

HD

DR1

DR0

MT

EC

MFM

X

SK

X

1

0

1

0

New Track Number

MSN of Track Number

X

HD

DR1

DR0

0

Track Number

Note: Last Command Phase byte is required only if ETR is set in Mode

Drive Head Number

Sector Number

Command.

Execution Phase: Disk drive head is stepped in or out to a

programmable track.

Bytes per Sector

No Result Phase

End of Track Sector Number

Intersector Gap Length

SENSE DRIVE STATUS

Command Phase

Data Length/Sector Count

Execution Phase: Data is read from disk but not transferred

to the system.

0

1

0

X

HD

DR1

DR0

Execution Phase: Disk drive status information is detected

and reported.

27

4.0 FDC Command Set Description (Continued)

Result Phase

WRITE DELETED DATA

Status Register 0

Status Register 1

Status Register 2

Track Number

Command Phase

MT

IPS

MFM

X

0

1

0

1

X

HD

DR1

DR0

Track Number

Head Number

Drive Head Number

Sector Number

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Data Length

VERSION

Command Phase

0

1

0

Execution Phase: Data is transferred from the system to

the controller via DMA or Non-DMA modes and written to

the disk.

Result Phase

1

0

Result Phase

Status Register 0

Status Register 1

Status Register 2

Track Number

WRITE DATA

Command Phase

MT

IPS

MFM

X

0

1

0

1

X

HD

DR1

DR0

Head Number

Track Number

Sector Number

Bytes per Sector

Drive Head Number

Sector Number

4.2 COMMAND DESCRIPTION

4.2.1 Configure Command

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Data Length

The Configure Command will control some operation modes

of the controller. It should be issued during the initialization

of the FDC after power up. The function of the bits in the

Configure registers are described below. These bits are set

to their default values after a hardware reset. The value of

each bit after a software reset is explained. The default val-

ue of each bit is denoted by a ‘‘bullet’’ to the left of each

item.

Execution Phase: Data is transferred from the system to

the controller via DMA or Non-DMA modes and written to

the disk.

Result Phase

Status Register 0

Status Register 1

Status Register 2

Track Number

EIS: Enable Implied Seeks. Default after a software reset.

e

0

1

Implied seeks disabled through Configure command.

Implied seeks can still be enabled through the Mode

#

e

command when EIS

0. (default)

Head Number

Implied seeks enabled for a read, write, scan, or veri-

fy operation. A seek and sense interrupt operation

will be performed prior to the execution of the read,

write, scan, or verify operation. The IPS bit does not

need to be set.

Sector Number

Bytes per Sector

28

4.0 FDC Command Set Description (Continued)

FIFO: Enable FIFO for Execution Phase data transfers. De-

fault after a software reset if the LOCK bit is 0. If the LOCK

bit is 1, then the FIFO bit will retain its previous value after a

software reset.

The sixth byte of the result phase varies depending on what

commands have been previously executed.

If a format command has previously been issued, and no

reads or writes have been issued since then, this byte will

contain the sectors per track value. If a read or write com-

mand has been executed more recently than a format com-

mand, this byte will contain the end of track value. The

LOCK bit is set in the Lock command. The eighth result byte

also contains the bits programmed in the Perpendicular

Mode command. The last two bytes of the Dumpreg Result

Phase are set in the Configure command. After a hardware

or software reset, the parameters in the result bytes will be

set to their appropriate default values.

e

0

FIFO enabled for both reads and writes.

FIFO disabled. (default)

e

1

#

POLL: Disable for Drive Polling Mode. Default after a soft-

ware reset.

e

0

Enable polling mode. An interrupt is generated after a

reset. (default)

#

e

1

Disable drive polling mode. If the Configure command

is issued within 500 ms of a hardware or software reset,

then an interrupt will not be generated. In addition, the

four Sense Interrupt commands to clear the ‘‘Ready

Changed State’’ of the four logical drives will not be

required.

Note: Some of these parameters are unaffected by a software reset, de-

pending on the state of the LOCK bit.

4.2.3 Format Track Command

This command will format one track on the disk in IBM, ISO,

or Perpendicular Format. After the index hole is detected,

data patterns are written on the disk including all gaps, ad-

dress marks, Address Fields, and Data Fields. The exact

format is determined by the following parameters:

THRESH: The FIFO threshold in the Execution Phase of

read and write data transfers. Programmable from 00 to 0F

hex. Defaults to 00 after a software reset if the LOCK bit is

0. If the LOCK bit is 1, then THRESH will retain its value. A

high value of THRESH is suited for slow response systems,

and a low value of THRESH is better for fast response sys-

tems.

1. The MFM bit in the Opcode (first command) byte, which

determines the format of the Address Marks and the en-

coding scheme.

PRETRK: Starting track number for write precompensation.

Programmable from track 0 (‘‘00’’) to track 255 (‘‘FF’’). De-

faults to track 0 (‘‘00’’) after a software reset if the LOCK bit

is 0. If the LOCK bit is 1, then PRETRK will retain its value.

2. The IAF bit in the Mode command, which selects be-

tween IBM and ISO format.

3. The WGATE and GAP bits in the Perpendicular Mode

command, which select between the conventional and

Toshiba Perpendicular format.

4.2.2 Dumpreg Command

The Dumpreg command is designed to support system run-

time diagnostics and application software development and

debug. This command has a one byte command phase and

a ten byte result phase, which return the values of parame-

ters set in other commands. That is, the PTR (Present Track

Register) contains the least significant byte of the track the

microcode has stored for each drive. The Step Rate Time,

Motor Off and Motor On Times, and the DMA bit are all set

in the Specify command.

4. The Bytes per Sector code, which determines the sector

size.

5. The Sector per Track parameter, which determines how

many sectors will be formatted on the track.

6. The Data Pattern byte, which is used as the filler byte in

the Data Field of each sector.

29

4.0 FDC Command Set Description (Continued)

To allow for flexible formatting, the mP must supply the four

Address Field bytes (track, head, sector, bytes per sector

code) for each sector formatted during the Execution

Phase. This allows for non-sequential sector interleaving.

This transfer of bytes from the mP to the controller can be

done in the DMA or Non-DMA mode, with the FIFO enabled

or disabled.

The Format command terminates when the index hole is

detected a second time, at which point an interrupt is gener-

ated. Only the first three status bytes in the Result Phase

are significant. The Format Gap byte in the Command

Phase is dependent on the data rate and type of disk drive,

and will control the length of GAP3. Some typical values for

the programmable GAP3 are given in Table 4-1 (next page).

Figure 4-1 shows the track format for the three types of

formats supported by the floppy controller.

TL/F/11362–5

Notes:

e

FE*

FC*

FB*

F8*

A1*

C2*

Data Pattern of FE, Clock Pattern of C7

Data Pattern of FC, Clock Pattern of D7

Data Pattern of FB, Clock Pattern of C7

Data Pattern of F8, Clock Pattern of C7

Data Pattern of A1, Clock Pattern of 0A

Data Pattern of C2, Clock Pattern of 14

All byte counts in decimal

All byte values in hex

16

12

5

a a

x

a

CRC uses standard polynomial x

x

1

e

Perpendicular Format GAP2

All other data rates use GAP2

FM mode is not guaranteed through functional testing.

41 bytes for 1 Mb/s.

e

22 bytes

FIGURE 4-1. IBM, Perpendicular, and ISO Formats Supported by Format Command

30

4.0 FDC Command Set Description (Continued)

TABLE 4-1. Typical Format Gap Length Values

Sector

Size

Sector

Gap

Format

GAP3

Mode

EOT

Hex

Code

Decimal

Hex

125 kb/s

FM

128

00

01

02

03

04

12

10

08

04

02

01

07

10

18

46

C8

09

19

30

87

FF

256

512

1024

2048

250 kb/s

MFM

256

01

02

03

04

05

12

10

08

09

04

02

01

0A

20

2A

80

C8

0C

32

50

F0

FF

512

1024

2048

4096

250 kb/s

FM

128

256

00

01

02

03

04

05

1A

0F

08

04

02

01

07

0E

1B

47

C8

1B

2A

3A

8A

FF

512

1024

2048

4096

500 kb/s

MFM

256

512

01

02

03

04

05

06

1A

0F

12

08

04

02

01

0E

1B

35

99

C8

36

54

6C

74

FF

512

1024

2048

4096

8192

Note: FM mode is not guaranteed through functional testing.

Typical Values for PC Compatible Diskette Media

Media

Type

Sector

Size

Sector

EOT

Code

Sector

Gap

Format

GAP3

Decimal

Hex

360k

512

02

09

0F

09

12

24

2A

1B

50

54

50

6C

53

1.2M

720k

1.44M

2.88M

Note 1: Sector Gap refers to the Intersector Gap Length parameter specified in the Command Phase of the Read, Write, Scan, and Verify commands. Although this

is the recommended value, the FDC treats this byte as a don’t care in the Read, Write, Scan, and Verify commands.

Note 2: Format Gap is the suggested value to use in the Format Gap parameter of the Format command. This is the programmable GAP3 as shown in Figure 4-1.

Note 3: The 2.88M diskette media is a Barium Ferrite media intended for use in Perpendicular Recording drives at the data rate of up to 1 Mb/s.

31

4.0 FDC Command Set Description (Continued)

4.2.4 Invalid Command

LOW PWR: Low Power mode. Default after a software re-

set.

If an invalid command (Illegal Opcode byte in the Command

Phase) is received by the controller, the controller will re-

spond with ST0 in the Result Phase. The controller does not

generate an interrupt during this condition. Bits 6 and 7 in

the MSR are both set to a 1, indicating to the mP that the

controller is in the Result Phase and the contents of ST0

must be read. The system will read an 80 (hex) value from

ST0, indicating an invalid command was received.

e

00

Completely disable the low power mode. (default)

#

01

Automatic low power. Go into low power mode

512 ms after the head unload timer times out. (This

assumes a 500 kb/s data rate.) For 250 kb/s the

timeout period is doubled to 1 ms.

e

10

11

Manual low power. Go into low power mode now.

Not used.

4.2.5 Lock Command

ETR: Extended Track Range. Default after a software reset.

The Lock command allows the user full control of the FIFO

parameters after a software reset. If the LOCK bit is set to 1,

then the FIFO, THRESH, and PRETRK bits in the Configure

command are not affected by a software reset. In addition,

the FWR, FRD, and BST bits in the Mode command will be

unaffected by a software reset. If the LOCK is 0 (default

after a hardware reset), then the above bits will be set to

their default values after a software reset. This command is

useful if the system designer wishes to keep the FIFO en-

abled and retain the other FIFO parameter values (such as

THRESH) after a software reset.

e

0

Track number is stored as a standard 8-bit value

compatible with the IBM, ISO, and Perpendicular for-

mats. This will allow access of up to 256 tracks dur-

ing a seek operation.

#

e

1

Track number is stored as a 12-bit value. The upper

four bits of the track value are stored in the upper

four bits of the head number in the sector Address

Field. This allows access of up to 4096 tracks during

a seek operation. With this bit set, an extra byte is

required in the Seek Command Phase and Sense In-

terrupt Result Phase.

After the command byte is written, the result byte must be

read before continuing to the next command. The execution

of the Lock command is not performed until the result byte

is read by the mP. If the part is reset after the command byte

is written but before the result byte is read, then the Lock

command execution will not be performed. This is done to

prevent accidental execution of the Lock command.

FWR: FIFO Write Disable for mP write transfers to control-

ler. Default after a software reset if LOCK is 0. If LOCK is 1,

FWR will retain its value after a software reset.

Note: This bit is only valid if the FIFO is enabled in the Configure command.

If the FIFO is not enabled in the Configure command, then this bit is a

don’t care.

e

0

Enable FIFO. Execution Phase mP write transfers use

the internal FIFO. (default)

#

4.2.6 Mode Command

e

This command is used to select the special features of the

controller. The bits for the Command Phase bytes are

shown in Section 4.1, Command Set Summary, and their

function is described below. These bits are set to their de-

fault values after a hardware reset. The default value of

each bit is denoted by a ‘‘bullet’’ to the left of each item. The

value of each parameter after a software reset will be ex-

plained.

1

Disable FIFO. All write data transfers take place with-

out the FIFO.

FRD: FIFO Read Disable for mP read transfers from control-

ler. Default after a software reset if LOCK is 0. If LOCK is 1,

FRD will retain its value after a software reset.

Note: This bit is only valid if the FIFO is enabled in the Configure command.

If the FIFO is not enabled in the Configure command, then this bit is a

don’t care.

e

TMR: Motor Timer mode. Default after a software reset.

0

Enable FIFO. Execution Phase mP read transfers use

the internal FIFO. (default)

#

e

0

Timers for motor on and motor off are defined for

Mode 1. (See Specify command.) (default)

#

e

1

Disable FIFO. All read data transfers take place with-

out the FIFO.

e

1

Timers for motor on and motor off are defined for

Mode 2. (See Specify command.)

BST: Burst Mode Disable. Default after a software reset if

LOCK is 0. If LOCK is 1, BST will retain its value after a

software reset.

IAF: Index Address Format. Default after a software reset.

e

0

The controller will format tracks with the Index Ad-

dress Field included. (IBM and Perpendicular format.)

#

Note: This bit is only valid if the FIFO is enabled in the Configure command.

If the FIFO is not enabled in the Configure command, then this bit is a

don’t care.

e

1

The controller will format tracks without including the

Index Address Field. (ISO format.)

e

0

Burst mode enabled for FIFO Execution Phase data

transfers. (default)

#

IPS: Implied Seek. Default after a software reset.

e

0

The implied seek bit in the command byte of a read,

write, scan, or verify is ignored. Implied seeks could

still be enabled by the EIS bit in the Configure com-

mand.

1

Non-Burst mode enabled. The DRQ or IRQ6 pin will

be strobed once for each byte to be transferred while

the FIFO is enabled.

#

e

1

The IPS bit in the command byte of a read, write,

scan, or verify is enabled so that if it is set, the con-

troller will perform seek and sense interrupt opera-

tions before executing the command.

32

4.0 FDC Command Set Description (Continued)

R255: Recalibrate Step Pulses. The bit will determine the

maximum number of recalibrate step pulses the controller

will issue before terminating with an error. Default after a

software reset.

Data Rate

kbits/s

Multiplier

4 Bits

Head Settle

Time (ms)

c

250

300

N

8

0–120

0–100

0–60

e

1,

0

85 maximum recalibrate step pulses. If ETR

#

6.666

controller will issue 3925 recalibrate step pulses max-

imum.

500

4

2

1000

0–30

e

1

255 maximum recalibrate step pulses. If ETR

1,

controller will issue 4095 maximum recalibrate step

pulses.

RG: Read Gate Diagnostic.

e

0

Enable DSKCHG disk interface input for normal oper-

ation. (default)

#

DENSEL: Density Select Pin Configuration. This two bit val-

ue will configure the Density Select output to one of three

possible modes. The default mode will configure the

DENSEL pin according to the state of the IDENT input pin

after a data rate has been selected. That is, if IDENT is high,

the DENSEL pin is active high for the 500 kbs/1 Mbs data

rates. If IDENT is low, the DENSEL pin is active low for the

500 kbs/1 Mbs data rates. In addition to these modes, the

DENSEL output can be set to always low or always high, as

shown in Table 4-2. This will allow the user more flexibility

with new drive types.

e

1

Enable DSKCHG to act as an external Read Gate

input signal to the Data Separator. This is intended as

a test mode to aid in evaluation of the Data Separa-

tor.

PU: PUMP Pulse Output Diagnostic.

e

0

Enable MFM output pin for normal operation.

(default)

#

e

1

Enable the MFM output to act as the active low out-

put of the Data Separator charge pump. This signal

consists of a series of pulses indicating when the

phase comparator is making a phase correction. This

Pump output will be active low for a pump up or pump

down signal from the phase comparator, and is in-

tended as a test mode to aid in the evaluation of the

Data Separator.

TABLE 4-2. DENSEL Encoding

DENSEL

Bit 1

Bit 0

Pin Definition

0

1

0

1

0

1

Pin Low

Pin High

4.2.7 NSC Command

Undefined

DEFAULT

The NSC command can be used to distinguish between the

FDC versions and the 82077. The Result Phase byte

uniquely identifies the floppy controller as a PC87311A/12,

which returns a value of 72h. The 82077 and DP8473 return

a value of 80h, signifying an invalid command. The lower

four bits of this result byte are subject to change by NSC,

and will reflect the particular version of the floppy disk con-

troller part.

TABLE 4-3. DENSEL Default Encoding

DENSEL (default)

Data Rate

e

0

IDENT

1

IDENT

250 kb/s

300 kb/s

500 kb/s

1 Mb/s

Low

High

Low

4.2.8 Perpendicular Mode Command

The Perpendicular Mode command is designed to support

the unique Format and Write Data requirements of Perpen-

dicular (Vertical) Recording disk drives (4 Mbytes unformat-

ted capacity). The Perpendicular Mode command will con-

figure each of the four logical drives as a perpendicular or

conventional disk drive. Configuration of the four logical disk

drives is done via the D3–D0 bits, or with the GAP and WG

control bits. This command should be issued during the ini-

tialization of the floppy controller.

BFR: CMOS Disk Interface Buffer Enable.

e

0

Drive output signals configured as standard 4 mA

push-pull outputs (actually 40 mA sink, 4 mA source).

(default)

#

e

1

Drive output signals configured as 40 mA open-drain

outputs.

Perpendicular Recording drives operate in ‘‘Extra High Den-

sity’’ mode at 1 Mb/s, and are downward compatible with

1.44 Mbyte and 720 kbyte drives at 500 kb/s (High Density)

and 250 kb/s (Double Density) respectively. If perpendicular

drives are present in the system, this command should be

issued during initialization of the floppy controller, which will

configure each drive as perpendicular or conventional.

Then, when a drive is accessed for a Format or Write Data

command, the floppy controller will adjust the Format or

Write Data parameters based on the data rate (see Table

4-4).

WLD: Scan Wild Card.

e

0

An FF (hex) from either the mP or the disk during a

Scan command is interpreted as a wildcard character

that will always match true. (default)

#

e

1

The Scan commands do not recognize FF (hex) as a

wildcard character.

Head Settle: Time allowed for read/write head to settle af-

ter a seek during an Implied Seek operation. This is con-

trolled as shown in table in next column, by loading a 4-bit

value for N (the default value for N is 8).

33

4.0 FDC Command Set Description (Continued)

Looking at the second command byte, DC3–DC0 corre-

spond to the four logical drives. A 0 written to DCn sets

drive n to conventional mode, and a 1 sets drive n to per-

pendicular mode. Also, the OW (Overwrite) bit offers addi-

4.2.9 Read Data Command

The Read Data command reads logical sectors containing a

Normal Data AM from the selected drive and makes the

data available to the host mP. After the last Command

Phase byte is written, the controller will simulate the Motor

On time for the selected drive internally. The user must turn

on the drive motor directly by enabling the appropriate drive

and motor select disk interface outputs with the Digital Out-

put Register (DOR).

e

tional control. When OW

DC0 (drive configuration bits) is enabled. When OW

1, changing the values of DC3–

e

0,

the internal values of DC3–DC0 are unaffected, regardless

of what is written to DC3–DC0.

The function of the DCn bits must also be qualified by set-

ting both WG and GAP to 0. If WG and GAP are used (i.e.,

not set to 00), they will override whatever is programmed in

the DCn bits. Table 4-4a below indicates the operation of

the FDC based on the values of GAP and WG. Note that

when GAP and WG are both 0, the DCn bits are used to

configure each logical drive as conventional or perpendicu-

lar. DC3–DC0 are unaffected by a software reset, but WG

and GAP are both cleared to 0 after a software reset. A

hardware reset will reset all the bits to zero (conventional

mode for all drives). The Perpendicular Mode command bits

may be rewritten at any time.

If Implied Seeks are enabled, the controller will perform a

Seek operation to the track number specified in the Com-

mand Phase. The controller will also issue a Sense Interrupt

for the seek and wait the Head Settle time specified in the

Mode command.

The correct ID information (track, head, sector, bytes per

sector) for the desired sector must be specified in the com-

mand bytes. See Table 4-5 Sector Size Selection for details

on the bytes per sector code. In addition, the End of Track

Sector Number (EOT) should be specified, allowing the con-

troller to read multiple sectors. The Data Length byte is a

don’t care and should be set to FF (hex).

Note: When in the Perpendicular Mode for any drive at any data rate select-

ed by the DC0–3 bits, write precompensation is set to zero.

Perpendicular Recording type disk drives have a Pre-Erase

Head which leads the Read/Write Head by 200 mm, which

translates to 38 bytes at the 1 Mb/s data transfer rate (19

bytes at 500 kb/s). The increased spacing between the two

heads requires a larger GAP2 between the Address Field

and Data Field of a sector at 1 Mb/s. (See Perpendicular

Format in Table 4-1.) This GAP2 length of 41 bytes (at

1 Mb/s) will ensure that the Preamble in the Data Field is

completely ‘‘pre-erased’’ by the Pre-Erase Head. Also, dur-

ing Write Data operations to a perpendicular drive, a portion

of GAP2 must be rewritten by the controller to guarantee

that the Data Field Preamble has been pre-erased (see

Table 4-4).

TABLE 4-5. Sector Size Selection

Bytes per

Number of Bytes

in Data Field

Sector Code

0

1

2

3

4

5

6

7

128

256

512

1024

2048

4096

8192

16384

TABLE 4-4. Effect of Drive Mode and Data Rate on Format and Write Commands

GAP2 Length

Written during

Format

Portion of GAP2

Drive

Mode

Data Rate

250/300/500 kb/s

1 Mb/s

Re-Written by Write

Data Command

Conventional

Perpendicular

22 Bytes

0 Bytes

19 Bytes

Conventional

Perpendicular

22 Bytes

41 Bytes

0 Bytes

38 Bytes

TABLE 4-4a. Effect of GAP and WG on Format and Write Commands

GAP2 Length

Mode

Portion of GAP2

Re-Written by Write

Data Command

GAP

WG

Written during

Format

Description

0

1

Conventional

Perpendicular

22 Bytes

0 Bytes

19 Bytes

s

(

500 kb/s)

1

0

1

Reserved

22 Bytes

41 Bytes

0 Bytes

(Conventional)

Perpendicular

(1 Mb/s)

38 Bytes

34

4.0 FDC Command Set Description (Continued)

The controller then starts the Data Separator and waits for

the Data Separator to find the next sector Address Field.

The controller compares the Address Field ID information

(track, head, sector, bytes per sector) with the desired ID

specified in the Command Phase. If the sector ID bytes do

not match, then the controller waits for the Data Separator

to find the next sector Address Field. The ID comparison

process repeats until the Data Separator finds a sector Ad-

dress Field ID that matches it in the command bytes, or until

an error occurs. Possible errors are:

Having found the Data Field, the controller then transfers

data bytes from the disk drive to the host (described in Sec-

tion 5.3 Controller Phases) until the bytes per sector count

has been reached, or the host terminates the operation

(through TC, end of track, or implicitly through overrun). The

controller will then generate the CRC for the sector and

compares this value with the CRC at the end of the Data

Field.

Having finished reading the sector, the controller will contin-

ue reading the next logical sector unless one or more of the

following termination conditions occurred:

1. The mP aborted the command by writing to the FIFO. If

there is no disk in the drive, the controller will hang up.

The mP must then take the controller out of this hung

state by writing a byte to the FIFO. This will put the con-

troller into the Result Phase.

1. The DMA controller asserted TC. The IC bits in ST0 are

set to Normal Termination.

2. The last sector address (of side 1 if MT was set) was

equal to EOT. The EOT bit in ST1 is set. The IC bits in

ST0 are set to Abnormal Termination. This is the expect-

ed condition during Non-DMA transfers.

2. Two index pulses were detected since the search began,

and no valid ID has been found. If the track address ID

differs, the WT bit or BT bit (if the track address is FF hex)

will be set in ST2. If the head, sector, or bytes per sector

code did not match, the ND bit is set in ST1. If the Ad-

dress Field AM was never found, the MA bit is set in ST1.

3. Overrun error. The OR bit in ST1 is set. The IC bits in ST0

are set to Abnormal Termination. If the mP cannot service

a transfer request in time, the last correctly read byte will

be transferred.

3. The Address Field was found with a CRC error. The CE

bit is set in ST1.

4. CRC error. The CE bit in ST1 and CD bit in ST2 are set.

The IC bits in ST0 are set to Abnormal Termination.

Once the desired sector Address Field is found, the control-

ler waits for the Data Separator to find the subsequent Data

Field for that sector. If the Data Field (normal or deleted) is

not found within the expected time, the controller terminates

the operation and enters the Result Phase (MD is set in

ST2). If a Deleted Data Mark is found and SK was set in the

Opcode command byte, the controller skips this sector and

searches for the next sector Address Field as described

above. The effect of SK on the Read Data command is

summarized in Table 4-6.

If MT was set in the Opcode command byte, and the last

sector of side 0 has been transferred, the controller will then

continue with side 1.

Upon terminating the Execution Phase of the Read Data

command, the controller will assert IRQ6, indicating the be-

ginning of the Result Phase. The mP must then read the

result bytes from the FIFO. The values that will be read back

in the result bytes are shown in Table 4-7. If an error occurs,

the result bytes will indicate the sector read when the error

occurred.

TABLE 4-6. SK Effect on Read Data Command

Sector Read ? CM Bit (ST2)

SK

0

Data Type

Normal

Description of Results

Normal Termination

No Further Sectors Read

Normal Termination

Sector Skipped

Y

0

Deleted

Normal

Y

N

1

0

1

Deleted

TABLE 4-7. Result Phase Termination Values with No Error

ID Information at Result Phase

Last

MT

HD

Sector

Track

Head

Sector

Bytes/Sector

k

a

0

1

0

1

0

1

EOT

NC

1

S

1

NC

e

k

e

k

e

k

e

a

NC

EOT

T

1

a

1

a

NC

a

1

a

NC

0

T

1

e

EOT

End of Track Sector Number from Command Phase

S

T

Sector Number last operated on by controller

Track Number programmed in Command Phase

e

NC

No Change in Value

35

4.0 FDC Command Set Description (Continued)

4.2.10 Read Deleted Data Command

3. If the Address Field ID comparison fails, the controller

sets ND in ST1, but continues to read the sector. If there

is a CRC error in the Address Field, the controller sets CE

in ST1, but continues to read the sector.

The Read Deleted Data command reads logical sectors

containing a Deleted Data AM from the selected drive and

makes the data available to the host mP. This command is

identical to the Read Data command, except for the setting

of the CM bit in ST2 and the skipping of sectors. The effect

of SK on the Read Deleted Data command is summarized in

Table 4-8. See Table 4-7 for the state of the result bytes for

a Normal Termination of the command.

4. Multi-track and Skip operations are not allowed. SK and

MT should be set to 0.

5. If there is a CRC error in the Data Field, the controller

sets CE in ST1 and CD in ST2, but continues reading

sectors.

6. The controller reads a maximum of EOT physical sectors.

There is no support for multi-track reads.

4.2.11 Read ID Command

The Read ID command finds the next available Address

Field and returns the ID bytes (track, head, sector, bytes per

sector) to the mP in the Result Phase. There is no data

transfer during the Execution Phase of this command. An

interrupt will be generated when the Execution Phase is

completed.

4.2.13 Recalibrate Command

The Recalibrate command is very similar to the Seek com-

mand. The controller sets the Present Track Register (PTR)

of the selected drive to zero. It then steps the head of the

selected drive out until the TRK0 disk interface input signal

goes active, or until the maximum number of step pulses

have been issued. See Table 4-9 for the maximum recali-

brate step pulse values based on the R255 and ETR bits in

the Mode command. If the number of tracks on the disk

drive exceeds the maximum number of recalibrate step

pulses, another Recalibrate command may need to be is-

sued.

The controller first simulates the Motor On time for the se-

lected drive internally. The user must turn on the drive motor

directly by enabling the appropriate drive and motor select

disk interface outputs with the Digital Output Register

(DOR). The Read ID command does not perform an implied

seek.

After waiting the Motor On time, the controller starts the

Data Separator and waits for the Data Separator to find the

next sector Address Field. If an error condition occurs, the

IC bits in ST0 are set to Abnormal Termination, and the

controller enters the Result Phase. Possible errors are:

TABLE 4-9. Maximum Recalibrate Step Pulses

Based on R255 and ETR

Maximum Recalibrate

R255

ETR

1. The mP aborted the command by writing to the FIFO. If

there is no disk in the drive, the controller will hang up.

The mP must then take the controller out of this hung

state by writing a byte to the FIFO. This will put the con-

troller into the Result Phase.

Step Pulses

0

1

0

1

0

1

85 (default)

255

3925

2. Two index pulses were detected since the search began,

and no AM has been found. If the Address Field AM was

never found, the MA bit is set in ST1.

4095

After the last command byte is issued, the DRx BUSY bit is

set in the MSR for the selected drive. The controller will

simulate the Motor On time, and then enter the Idle Phase.

The execution of the actual step pulses occurs while the

controller is in the Drive Polling Phase. An interrupt will be

generated after the TRK0 signal is asserted, or after the

maximum number of recalibrate step pulses are issued.

There is no Result Phase. Recalibrates on more than one

drive at a time should not be issued for the same reason as

explained in the Seek command. No other command except

the Sense Interrupt command should be issued while a Re-

calibrate command is in progress.

4.2.12 Read A Track Command

The Read A Track command reads sectors in physical order

from the selected drive and makes the data available to the

host. This command is similar to the Read Data command

except for the following differences:

1. The controller waits for the index pulse before searching

for a sector Address Field. If the mP writes to the FIFO

before the index pulse, the command will enter the Result

Phase with the IC bits in ST0 set to Abnormal Termina-

tion.

2. A comparison of the sector Address Field ID bytes will be

performed, except for the sector number. The internal

sector address is set to 1, and then incremented for each

successive sector read.

4.2.14 Relative Seek Command

The Relative Seek command steps the selected drive in or

out a given number of steps. This command will step the

read/write head an incremental number of tracks, as op-

TABLE 4-8. SK Effect on Read Deleted Data Command

Sector Read ? CM Bit (ST2)

SK

0

Data Type

Normal

Description of Results

No Further Sectors Read

Normal Termination

Sector Skipped

Y

1

0

Deleted

Normal

Y

N

Y

0

1

0

1

Deleted

Normal Termination

36

4.0 FDC Command Set Description (Continued)

posed to comparing against the internal present track regis-

ter for that drive. The Relative Seek parameters are defined

as follows:

TABLE 4-10. Scan Command Termination Values

Status

Command

Register 2

Conditions

DIR: Read/Write Head Step Direction Control

e

D2

D3

0

1

Step Head Out

Step Head In

e

i

Scan Equal

0

1

0

Disk

mP

RTN: Relative Track Number. This value will determine how

many incremental tracks to step the head in or out from the

current track number.

Disk mP

e

mP

Scan Low

or Equal

0

1

0

Disk

k

Disk mP

The controller will issue RTN number of step pulses and

update the Present Track Register for the selected drive.

The one exception to this is if the TRK0 disk input goes

active, which indicates that the drive read/write head is at

the outermost track. In this case, the step pulses for the

Relative Seek are terminated, and the PTR value is set ac-

cording to the actual number of step pulses issued. The

arithmetic is done modulo 255. The DRx BUSY bit in the

MSR is set for the selected drive. The controller will simu-

late the Motor On time before issuing the step pulses. After

the Motor On time, the controller will enter the Idle Phase.

The execution of the actual step pulses occurs in the Idle

Phase of the controller.

l

Disk mP

e

mP

Scan High

or Equal

0

1

0

Disk

l

Disk mP

k

Disk mP

4.2.16 Seek Command

The Seek command issues step pulses to the selected drive

in or out until the desired track number is reached. During

the Execution Phase of the Seek command, the track num-

ber to seek to is compared with the present track number.

The controller will determine how many step pulses to issue

and the DIR disk interface output will indicate which direc-

tion the R/W head should move. The DRx BUSY bit is set in

the MSR for the appropriate drive. The controller will wait

the Motor On time before issuing the first step pulse.

After the step operation is complete, the controller will gen-

erate an interrupt. There is no Result Phase. Relative Seeks

on more than one drive at a time should not be issued for

the same reason as explained in the Seek command. No

other command except the Sense Interrupt command

should be issued while a Relative Seek command is in prog-

ress.

After the Motor On time, the controller will enter the Idle

Phase. The execution of the actual step pulses occurs in the

Drive Polling phase of the controller. The step pulse rate is

determined by the value programmed in the Specify com-

mand. An interrupt will be generated one step pulse period

after the last step pulse is issued. There is no Result Phase.

A Sense Interrupt command should be issued to determine

the cause of the interrupt.

4.2.15 Scan Commands

The Scan command allows data read from the disk to be

compared against data sent from the mP. There are three

Scan commands to choose from:

While the internal microengine is capable of multiple seek

on 2 or more drives at the same time, software should en-

sure that only one drive is seeking or recalibrating at a time.

This is because the drives are actually selected via the

DOR, which can only select one drive at a time. No other

command except a Sense Interrupt command should be is-

sued while a Seek command is in progress.

e

s

t

Scan Equal

Disk Data

mP Data

Scan Low or Equal Disk Data

Scan High or Equal Disk Data

Each sector is interpreted with the most significant bytes

first. If the Wildcard mode is enabled in the Mode command,

an FF (hex) from either the disk or the mP is used as a don’t

care byte that will always match equal. After each sector is

read, if the desired condition has not been met, the next

sector is read. The next sector is defined as the current

sector number plus the Sector Step Size specified. The

Scan command will continue until the scan condition has

been met, or the EOT has been reached, or if TC is assert-

ed.

If the extended track range mode is enabled with the ETR

bit in the Mode command, a fourth command byte should be

written in the Command Phase to indicate the four most

significant bits of the desired track number. Otherwise, only

three command bytes should be written.

4.2.17 Sense Drive Status Command

The Sense Drive Status command returns the status of the

selected disk drive in ST3. This command does not gener-

ate an interrupt.

Read errors on the disk will have the same error conditions

as the Read Data command. If the SK bit is set, sectors with

deleted data marks are ignored. If all sectors read are

skipped, the command will terminate with D3 of ST2 set

(Scan Equal Hit). The Result Phase of the command is

shown in Table 4-10.

4.2.18 Sense Interrupt Command

The Sense Interrupt command is used to determine the

cause of interrupt when the interrupt is a result of the

37

4.0 FDC Command Set Description (Continued)

change in status of any disk drive. Four possible causes of

the interrupt are:

If the WNR bit is a 0, a track register is to be read. In this

case, the Result Phase byte contains the value in the inter-

nal register specified, and the third byte in the Command

Phase is a dummy byte.

1. Upon entering the Result Phase of:

a. Read Data command

b. Read Deleted Data command

c. Read a Track command

d. Read ID command

If the WNR bit is a 1, data is written to a track register. In this

case the third byte of the Command Phase is written to the

specified internal track register, and the Result Phase byte

contains this new value.

e. Write Data command

f. Write Deleted Data command

g. Format command

The DS1 and DS0 bits select the Present Track Register for

the particular drive. The internal register address depends

on MSB, DS1, and DS0 as shown in Table 4-12. This com-

mand does not generate an interrupt.

h. Scan command

TABLE 4-12. Set Track Register Address

i. Verify command

2. During data transfers in the Execution Phase while in the

Non-DMA mode.

DS1

DS0

MSB

Register Addressed

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PTR0 (LSB)

PTR0 (MSB)

PTR1 (LSB)

PTR1 (MSB)

PTR2 (LSB)

PTR2 (MSB)

PTR3 (LSB)

PTR3 (MSB)

3. Ready Changed State during the polling mode for an in-

ternally selected drive. (Occurs only after a hardware or

software reset.)

4. Seek, Relative Seek, or Recalibrate termination.

An interrupt due to reasons 1 and 2 does not require the

Sense Interrupt command and is cleared automatically. This

interrupt occurs during normal command operations and is

easily discernible by the mP via the MSR. This interrupt is

cleared reading or writing information from/to the Data Reg-

ister (FIFO).

4.2.20 Specify Command

The Specify command sets the initial values for three inter-

nal timers. The function of these Specify parameters is de-

scribed below. The parameters of this command are unde-

fined after power up, and are unaffected by any reset. Thus,

software should always issue a Specify command as part of

an initialization routine. This command does not generate

an interrupt.

Interrupts caused by reasons 3 and 4 are identified with the

aid of the Sense Interrupt command. The interrupt is cleared

after the first result byte has been read. Use bits 5, 6, and 7

of ST0 to identify the cause of the interrupt as shown in

Table 4-11.

TABLE 4-11. Status Register 0 Termination Codes

Status Register 0

The Motor Off and Motor On timers are artifacts of the

mPD765. These timers determine the delay from selecting a

drive motor until a read or write operation is started, and the

delay of deselecting the drive motor after the command is

completed. Since the FDC enables the drive and motor se-

lect line directly through the DOR, these timers only provide

some delay from the initiation of a command until it is actu-

ally started.

Interrupt

Code

Seek

End

Cause

D7

D6

1

D5

0

1

0

Internal Ready Went True

Normal Seek Termination

Abnormal Seek Termination

0

1

Step Rate Time: These four bits define the time interval

between successive step pulses during a seek, implied

seek, recalibrate, or relative seek. The programming of this

step rate is shown in Table 4-13.

1

Issuing a Sense Interrupt command without an interrupt

pending is treated as an Invalid command. If the extended

track range mode is enabled, a third byte should be read in

the Result Phase, which will indicate the four most signifi-

cant bits of the present track number. Otherwise, only two

result bytes should be read.

TABLE 4-13. Step Rate Time (SRT) Values

Data Rate

Value

Range

Units

b

1 Mb/s

500 kb/s

300 kb/s

250 kb/s

(16 SRT)/2

0.5–8

1–16

ms

b

(16 SRT)

c

4.2.19 Set Track Command

b

(16 SRT) 1.67

c

2

1.67–26.7

2–32

This command is used to inspect or change the value of the

internal Present Track Register. This could be useful for re-

covery from disk mis-tracking errors, where the real current

track could be read through the Read ID command, and

then the Set Track command could be used to set the inter-

nal Present Track Register to the correct value.

b

(16 SRT)

Motor Off Time: These four bits determine the simulated

Motor Off time as shown in Table 4-14.

Motor On Time: These seven bits determine the simulated

Motor On time as shown in Table 4-15.

38

4.0 FDC Command Set Description (Continued)

TABLE 4-14. Motor Off Time (MFT) Values

e

1)

Mode 1 (TMR

Value

0)

Range

Mode 2 (TMR

Value

Units

Data Rate

Range

c

1 Mb/s

500 kb/s

300 kb/s

250 kb/s

MFT

8

8–128

16–256

26.7–427

32–512

MFT 512

512–8192

853–13653

ms

c

MFT 512

MFT 16

c

MFT 2560/3

MFT 80/3

c

MFT 32

c

MFT 1024

1024–16384

e

16.

Note: Motor Off Time

0 is treated as MFT

TABLE 4-15. Motor On Time (MNT) Values

e

1)

Mode 1 (TMR

Value

0)

Range

Mode 2 (TMR

Value

Units

Data Rate

Range

c

1 Mb/s

500 kb/s

300 kb/s

250 kb/s

MNT

1–128

MNT 32

32–4096

53–6827

64–8192

ms

c

MNT 32

c

MNT 160/3

MNT 10/3

3.3–427

4–512

c

MNT 64

MNT

4

e

128.

Note: Motor On Time

0 is treated as MNT

DMA: This bit selects the data transfer mode in the Execu-

tion Phase of a read, write, or scan operation.

4.2.23 Write Data Command

The Write Data command receives data from the host and

writes logical sectors containing a Normal Data AM to the

selected drive. The operation of this command is similar to

the Read Data command except that the data is transferred

from the mP to the controller instead of the other way

around.

e

0

1

DMA mode is selected.

Non-DMA mode is selected.

4.2.21 Verify Command

The Verify command reads logical sectors containing a Nor-

mal Data AM from the selected drive without transferring

the data to the host. This command is identical to the Read

Data command, except that no data is transferred during

the Execution Phase.

The controller will simulate the Motor On time before start-

ing the operation. If implied seeks are enabled, the seek and

sense interrupt functions are then performed. The controller

then starts the Data Separator and waits for the Data Sepa-

rator to find the next sector Address Field. The controller

compares the Address ID (track, head, sector, bytes per

sector) with the desired ID specified in the Command

Phase. If there is no match, the controller waits to find the

next sector Address Field. This process continues until the

desired sector is found. If an error condition occurs, the IC

bits in ST0 are set to Abnormal Termination, and the con-

troller enters the Result Phase. Possible errors are:

The Verify command is designed for post-format or post-

write verification. Data is read from the disk, as the control-

ler checks for valid Address Marks in the Address and Data

Fields. The CRC is computed and checked against the pre-

viously stored value on the disk. The EOT value should be

set to the final sector to be checked on each side. If EOT is

greater than the number of sectors per side, the command

will terminate with an error and no useful Address Mark or

CRC data will be given.

1. The mP aborted the command by writing to the FIFO. If

there is no disk in the drive, the controller will hang up.

The mP must then take the controller out of this hung

state by writing a byte to the FIFO. This will put the con-

troller into the Result Phase.

The TC pin cannot be used to terminate this command

since no data is transferred. The command can simulate a

TC by setting the EC bit to a 1. In this case, the command

will terminate when SC (Sector Count) sectors have been

e

0 then 256 sectors will be verified.) If EC

read. (If SC

2. Two index pulses were detected since the search began,

and no valid ID has been found. If the track address ID

differs, the WT bit or BT bit (if the track address is FF hex)

will be set in ST2. If the head, sector, or bytes per sector

code did not match, the ND bit is set in ST1. If the Ad-

dress Field AM was never found, the MA bit is set in ST1.

0, then the command will terminate when EOT is equal to

the last sector to be checked. In this case, the Data Length

parameter should be set to FF hex. Refer to Table 4-7 for

the Result Phase values for a successful completion of the

command. Also see Table 4-16 for further explanation of

the result bytes with respect to the MT and EC bits.

3. The Address Field was found with a CRC error. The CE

bit is set in ST1.

4.2.22 Version Command

4. If the controller detects the Write Protect disk interface

input is asserted, bit 1 of ST1 is set.

The Version command can be used to determine the floppy

controller being used. The Result Phase uniquely identifies

the floppy controller version. The FDC returns a value of

90 hex in order to be compatible with the 82077. The

DP8473 and other NEC765 compatible controllers will re-

turn a value of 80 hex (invalid command).

If the correct Address Field is found, the controller waits for

all (conventional mode) or part (perpendicular mode) of

GAP2 to pass. The controller will then write the preamble

field, address marks, and data bytes to the Data Field. The

data bytes are transferred to the controller by the mP.

39

4.0 FDC Command Set Description (Continued)

TABLE 4-16. Verify Command Result Phase Table

MT

EC

SC/EOT Value

DTL used (should be FF hex)

Termination Result

0

No Errors

s

Ý

EOT

Sectors per Side

0

1

DTL used (should be FF hex)

l

Abnormal Termination

No Errors

Ý

EOT

Sectors per Side

s

Ý

SC

Sectors per Side

AND

s

SC EOT

l

Ý

0

1

SC

Sectors Remaining

OR

Abnormal Termination

l

SC EOT

1

0

1

DTL used (should be FF hex)

s

No Errors

Abnormal Termination

No Errors

Ý

EOT

Sectors per Side

DTL used (should be FF hex)

l

Ý

EOT

Sectors per Side

s

Ý

SC

Sectors per Side

AND

s

SC EOT

s

SC (EOT 2)

c

1

No Errors

AND

s

Ý

EOT

Sectors per Side

l

SC (EOT 2)

c

1

Abnormal Termination

e

number of formatted sectors per each side of the disk.

Ý

Note 1:

Note 2:

Sectors per Side

e

Sectors Remaining

number of formatted sectors left which can be read, which includes side 1 of the disk if the MT bit is set to 1.

e

Note 3: If MT

1 and the SC value is greater than the number of remaining formatted sectors on side 0, verifying will continue on side 1 of the disk.

Having finished writing the sector, the controller will contin-

ue reading the next logical sector unless one or more of the

following termination conditions occurred:

5.0 FDC Functional Description

The PC87311A/12 is software compatible with the DP8473

and 82077 floppy disk controllers. Upon a power on reset,

the 16-byte FIFO will be disabled. Also, the disk interface

outputs will be configured as active push-pull outputs, which

are compatible with both CMOS inputs and open-collector

resistor terminated disk drive inputs. The FIFO can be en-

abled with the Configure command. The FIFO can be very

useful at the higher data rates, with systems that have a

large amount of DMA bus latency, or with multi-tasking sys-

tems such as the EISA or MCA bus structures.

1. The DMA controller asserted TC. The IC bits in ST0 are

set to Normal Termination.

2. The last sector address (of side 1 if MT was set) was

equal to EOT. The EOT bit in ST1 is set. The IC bits in

ST0 are set to Abnormal Termination. This is the expect-

ed condition during Non-DMA transfers.

3. Underrun error. The OR bit in ST1 is set. The IC bits in

ST0 are set to Abnormal Termination. If the mP cannot

service a transfer request in time, the last correctly writ-

ten byte will be written to the disk.

The FDC will support all the DP8473 Mode command fea-

tures as well as some additional features. These include

control over the enabling of the FIFO for reads and writes, a

Non-Burst mode for the FIFO, a bit that will configure the

disk interface outputs as open-drain outputs, and pro-

grammability of the DENSEL output.

If MT was set in the Opcode command byte, and the last

sector of side 0 has been transferred, the controller will then

continue with side 1.

4.2.24 Write Deleted Data

5.1 MICROPROCESSOR INTERFACE

The Write Deleted Data command receives data from the

host and writes logical sectors containing a Deleted Data

AM to the selected drive. This command is identical to the

Write Data command except that a Deleted Data AM is writ-

ten to the Data Field instead of a Normal Data AM.

The FDC interface to the microprocessor consists of the

A9–A3, AEN, RD, and WR lines, which access the chip for

reads and writes; the data lines D7–D0; the address lines

A2–A0, which select the appropriate register (see Table

3-1); the IRQ6 signal, and the DMA interface signals

40

5.0 FDC Functional Description (Continued)

DRQ, DACK, and TC. It is through this microprocessor inter-

face that the floppy controller receives commands, transfers

data, and returns status information.

command byte is written to the Data Register, the CMD

PROG bit (D4) will also be set and will remain set until the

last Result Phase byte is read. If there is no Result Phase,

the CMD PROG bit will be cleared after the last command

byte is written.

5.2 MODES OF OPERATION

The FDC has three modes of operation: PC-AT mode, PS/2

mode, and Model 30 mode, which are determined by the

state of the IDENT pin and MFM pin. IDENT can be tied

A new command may be initiated after reading all the result

bytes from the previous command. If the next command

requires selecting a different drive or changing the data rate,

the DOR and DSR or CCR should be updated. If the com-

mand is the last command, then the software should dese-

lect the drive.

directly to V

or GND. The MFM pin must be tied high or

DD

low with a 10 kX resistor (there is an internal 40 kX–50 kX

resistor on the MFM pin). The state of these pins is interro-

gated by the controller during a chip reset to determine the

mode of operation. See Section 3.0 Register Description for

more details on the register set used for each mode of oper-

ation. After chip reset, the state of IDENT can be changed

to change the polarity of DENSEL (see Section 2.0 Pin De-

scription).

Note: As a general rule, the operation of the controller core is independent

of how the mP updates the DOR, DSR, and CCR. The software must

ensure that the manipulation of these registers is coordinated with the

controller operation.

5.3.2 Execution Phase

During the Execution Phase, the disk controller performs

the desired command. Commands that involve data trans-

fers, such as read, write, or format operation, will require the

mP to write or read data to or from the Data Register at this

time. Some commands such as a Seek or Recalibrate will

control the read/write head movement on the disk drive dur-

ing the Execution Phase via the disk interface signals. The

execution of other commands does not involve any action

by the mP or disk drive, and consists of an internal operation

by the controller.

PC-AT ModeÐ(IDENT tied high, MFM is a don’t care): The

PC-AT register set is enabled. The DMA enable bit in the

Digital Output Register becomes valid (IRQ6 and DRQ can

be TRI-STATE). TC and DENSEL become active high sig-

nals (defaults to a 5.25 floppy drive).

×

PS/2 ModeÐ(IDENT tied low, MFM pulled high internally):

This mode supports the PS/2 Models 50/60/80 configura-

tion and register set. The DMA enable bit in the Digital Out-

put Register becomes a don’t care (IRQ6 and DRQ signals

will always be valid). TC and DENSEL become active low

If there is data to be transferred between the mP and the

controller during the Execution, there are three methods

that can be used, DMA mode, interrupt transfer mode, and

software polling mode. The last two modes are called the

Non-DMA modes. The DMA mode is used if the system has

a DMA controller. This allows the mP to do other tasks while

the data transfer takes place during the Execution Phase. If

the Non-DMA mode is used, an interrupt is issued for each

byte transferred during the Execution Phase. Also, instead

of using the interrupt during Non-DMA mode, the Main

Status Register can be polled by software to indicate when

a byte transfer is required. All of these data transfer modes

will work with the FIFO enabled or disabled.

signals (default to 3.5 floppy drive).

×

Model 30 ModeÐ(IDENT tied low, MFM pulled low exter-

nally): This mode supports the PS/2 Model 30 configuration

and register set. The DMA enable bit in the Digital Output

Register becomes valid (IRQ6 and DRQ can be

TRI-STATE). TC is active high and DENSEL becomes ac-

tive low (default to 3.5 floppy drive).

×

5.3 CONTROLLER PHASES

The FDC has three separate phases of a command, the

Command Phase, the Execution Phase, and the Result

Phase. Each of these controller phases will determine how

data is transferred between the floppy controller and the

host microprocessor. In addition, when no command is in

progress, the controller is in the Idle Phase or Drive Polling

Phase.

5.3.2.1 DMA ModeÐFIFO Disabled

The DMA mode is selected by writing a 0 to the DMA bit in

the Specify command and by setting the DMA enabled bit

(D3) in the DOR. With the FIFO disabled, a DMA request

(DRQ) is generated in the Execution Phase when each byte

is ready to be transferred. The DMA controller should re-

spond to the DRQ with a DMA acknowledge (DACK) and a

read or write strobe. The DRQ will be cleared by the leading

edge of the active low DACK input signal. After the last byte

is transferred, an interrupt is generated, indicating the begin-

ning of the Result Phase. During DMA operations the chip

select input (CS) must be held high. The DACK signal will

act as the chip select for the FIFO in this case, and the state

of the address lines A2–A0 is a don’t care. The Terminal

Count (TC) signal can be asserted by the DMA controller to

terminate the data transfer at any time. Due to internal gat-

ing, TC is only recognized when DACK is low.

5.3.1 Command Phase

During the Command Phase, the mP writes a series of bytes

to the Data Register. The first command byte contains the

opcode for the command, and the controller will know how

many more bytes to expect based on this opcode byte. The

remaining command bytes contain the particular parameters

required for the command. The number of command bytes

will vary for each particular command. All the command

bytes must be written in the order specified in the Command

Description Table. The Execution Phase starts immediately

after the last byte in the Command Phase is written. Prior to

performing the Command Phase, the Digital Output Register

should be set and the data rate should be set with the Data

Rate Select Register or Configuration Control Register.

PC-AT Mode. When in the PC-AT interface mode with the

FIFO disabled, the controller will be in single byte transfer

mode. That is, the system will have one byte time to service

a DMA request (DRQ) from the controller. DRQ will be deas-

serted between each byte.

The Main Status Register controls the flow of command

bytes, and must be polled by the software before writing

each Command Phase byte to the Data Register. Prior to

writing a command byte, the RQM bit (D7) must be set and

the DIO bit (D6) must be cleared in the MSR. After the first

41

5.0 FDC Functional Description (Continued)

PS/2 and Model 30 Modes. When in the PS/2 or Model 30

modes, DMA transfers with the FIFO disabled are per-

formed differently. Instead of a single byte transfer mode,

another sector is to be written will DRQ be asserted again.

Also, since DRQ is deasserted immediately after the last

byte of a sector is written to the FIFO, the system does not

need to tolerate any DRQ deassertion delay and is free to

do other work.

e

the FIFO will actually be enabled with THRESH

0F (hex).

Thus, DRQ will be asserted when one byte has entered the

FIFO during reads, and when one byte can be written to the

FIFO during writes. DRQ will be deasserted by the leading

edge of the DACK input, and will be reasserted when DACK

goes inactive high. This operation is very similar to Burst

mode transfer with the FIFO enabled except that DRQ is

deasserted between each byte.

DRQ Deassertion

The DACK input signal from the DMA controller may be held

active during an entire burst or it may be strobed for each

byte transferred during a read or write operation. If DACK is

strobed for each byte, the leading edge of this strobe is

used to deassert DRQ. If DACK is strobed, RD or WR are

not required. This is the case during the Read-Verify mode

of the DMA controller. If DACK is held active during the

entire burst, the leading edge of the RD or WR strobe is

used to deassert DRQ.

5.3.2.2 DMA ModeÐFIFO Enabled

Read Data Transfers

Whenever the number of bytes in the FIFO is greater than

b

or equal to (16 THRESH), a DRQ is generated. This is the

trigger condition for the FIFO read data transfers from the

Overrun Errors

An overrun or underrun error will terminate the execution of

the command if the system does not transfer data within the

allotted data transfer time (see Section 3.7), which will put

the controller into the Result Phase. During a read overrun,

the mP is required to read the remaining bytes of the sector

before the controller will assert IRQ6, signifying the end of

execution. During a write operation, an underrun error will

terminate the Execution Phase after the controller has writ-

ten the remaining bytes of the sector with the last correctly

written byte to the FIFO and generated the CRC bytes.

Whether there is an error or not, an interrupt is generated at

the end of the Execution Phase, and is cleared by reading

the first Result Phase byte.

floppy controller to the mP.

Burst Mode. DRQ will remain active until enough bytes

have been read from the controller to empty the FIFO.

Non-Burst Mode. DRQ will be deasserted after each read

transfer. If the FIFO is not completely empty, DRQ will be

reasserted after a 350 ns delay. This will allow other higher

priority DMA transfers to take place between floppy trans-

fers. In addition, this mode will allow the controller to work

correctly in systems where the DMA controller is put into a

read verify mode, where only DACK signals are sent to the

FDC, with no RD pulses. This read verify mode of the DMA

controller is used in some PC software. The FIFO Non-Burst

mode allows the DACK input from the DMA controller to be

strobed, which will correctly clock data from the FIFO.

DACK asserted by itself without a RD or WR strobe is also

counted as a transfer. If RD or WR are not being strobed for

each byte, then DACK must be strobed for each byte so that

the floppy controller can count the number of bytes correct-

ly. A new command, the Verify command, has been added

to allow easier verification of data written to the disk without

the need of actually transferring the data on the data bus.

For both the Burst and Non-Burst modes, when the last byte

in the FIFO has been read, DRQ will go inactive. DRQ will

then be reasserted when the FIFO trigger condition is satis-

fied. After the last byte of a sector has been read from the

disk, DRQ is again generated even if the FIFO has not yet

reached its threshold trigger condition. This will guarantee

that all the current sector bytes are read from the FIFO

before the next sector byte transfer begins.

5.3.2.3 Interrupt ModeÐFIFO Disabled

If the Interrupt (Non-DMA) mode is selected, IRQ6 is assert-

ed instead of DRQ when each byte is ready to be trans-

ferred. The Main Status Register should be read to verify

that the interrupt is for a data transfer. The RQM and NON

DMA bits (D7 and D5) in the MSR will be set. The interrupt

will be cleared when the byte is transferred to or from the

Data Register. CS and RD or CS and WR must be used to

transfer the data in or out of the Data Register (A2–A0 must

be valid). CS asserted by itself is not significant. CS must be

asserted with RD or WR for a read or write transfer to be

recognized.

Write Data Transfers

Whenever the number of bytes in the FIFO is less than or

equal to THRESH, a DRQ is generated. This is the trigger

condition for the FIFO write data transfers from the mP to

the floppy controller.

Burst Mode. DRQ will remain active until enough bytes

have been written to the controller to completely fill the

FIFO.

Non-Burst Mode. DRQ will be deasserted after each write

transfer. If the FIFO is not full yet, DRQ will be reasserted

after a 350 ns delay. This deassertion of DRQ will allow

other higher priority DMA transfers to take place between

floppy transfers.

The mP should transfer the byte within the data transfer

service time (see Section 3.7). If the byte is not transferred

within the time allotted, an Overrun Error will be indicated in

the Result Phase when the command terminates at the end

of the current sector.

The FIFO has a byte counter which will monitor the number

of bytes being transferred to the FIFO during write opera-

tions for both Burst and Non-Burst modes. When the last

byte of a sector is transferred to the FIFO, DRQ will be

deasserted even if the FIFO has not been completely filled.

In this way, the FIFO will be cleared after each sector is

written. Only after the floppy controller has determined that

An interrupt will also be generated after the last byte is

transferred. This indicates the beginning of the Result

Phase. The RQM and DIO bits (D7 and D6) in the MSR will

be set, and the NON DMA bit (D5) will be cleared. This

interrupt is cleared by reading the first result byte.

42

5.0 FDC Functional Description (Continued)

5.3.2.4 Interrupt ModeÐFIFO Enabled

ress the controller will be in the Idle Phase. The controller

will be waiting for a command byte to be written to the Data

Register. The RQM bit will be set and the DIO bit will be

cleared in the MSR. After receiving the first command (op-

code) byte, the controller will enter the Command Phase.

When the command is completed the controller again en-

ters the Idle Phase. The Data Separator will remain synchro-

nized to the reference frequency while the controller is idle.

While in the Idle Phase, the controller will periodically enter

the Drive Polling Phase (see below).

The Interrupt (Non-DMA) mode with the FIFO enabled is

very similar to the Non-DMA mode with the FIFO disabled.

In this case, IRQ6 is asserted instead of DRQ under the

exact same FIFO threshold trigger conditions. The MSR

should be read to verify that the interrupt is for a data trans-

fer. The RQM and NON DMA bits (D7 and D5) in the MSR

will be set. CS and RD or CS and WR must be used to

transfer the data in or out of the Data Register (A2–A0 must

be valid). CS asserted by itself is not significant. CS must be

asserted with RD or WR for a read or write transfer to be

recognized.

5.3.5 Drive Polling Phase

While in the Idle Phase the controller will enter a Drive Poll-

ing Phase every 1 ms (based on the 500 kb/s data rate).

While in the Drive Polling Phase, the controller will interro-

gate the Ready Changed status for each of the four logical

drives. The internal Ready changed status for each drive is

toggled only after a hardware or software reset, and an in-

terrupt will be generated for drive 0. At this point, the soft-

ware must issue four Sense Interrupt commands to clear

the Ready Changed State status for each drive. This re-

quirement can be eliminated if drive polling is disabled via

the POLL bit in the Configure command. The Configure

command must be issued within 500 ms (worst case ) of the

hardware or software reset for drive polling to be disabled.

The Burst mode may be used to hold the IRQ6 pin active

during a burst, or the Non-Burst mode may be used to tog-

gle the IRQ6 pin for each byte of a burst. The Main Status

Register is always valid from the mP point of view. For ex-

ample, during a read command, after the last byte of data

has been read from the disk and placed in the FIFO, the

MSR will still indicate that the Execution Phase is active,

and that data needs to be read from the Data Register. Only

after the last byte of data has been read by the mP from the

FIFO will the Result Phase begin.

The same overrun and underrun error procedures from the

DMA mode apply to the Non-DMA mode. Also, whether

there is an error or not, an interrupt is generated at the end

of the Execution Phase, and is cleared by reading the first

Result Phase byte.

The controller uses the Drive Polling Phase to control the

Automatic Low Power mode. Even if drive polling is dis-

abled, drive stepping and delayed power down will occur in

the Drive Polling Phase. The controller will check the status

of each drive and if necessary it will issue a step pulse on

the STEP output with the DIR signal at the appropriate logic

level. When the Motor Off time has expired, the controller

will wait 512 ms based on the 500 kb/s and 1 Mb/s data

rate before automatic powering down if this function is en-

abled via the Mode command.

5.3.2.5 Software Polling

If the Non-DMA mode is selected and interrupts are not

suitable, the mP can poll the MSR during the Execution

Phase to determine when a byte is ready to be transferred.

The RQM bit (D7) in the MSR reflects the state of the IRQ6

signal. Otherwise, the data transfer is similar to the Interrupt

Mode described above. This is true for the FIFO enabled or

disabled.

5.4 DATA SEPARATOR

The internal data separator consists of an analog PLL and

its associated circuitry. The PLL synchronizes the raw data

signal read from the disk drive. The synchronized signal is

used to separate the encoded clock and data pulses. The

data pulses are deserialized into bytes and then sent to the

mP by the controller.

5.3.3 Result Phase

During the Result Phase, the mP reads a series of bytes

from the data register. These bytes indicate the status of the

command. This status may indicate whether the command

executed properly, or contain some control information (see

the Command Description Table and Status Register De-

scription). These Result Phase bytes are read in the order

specified for that particular command. Some commands will

not have a result phase. Also, the number of result bytes

varies with each command. All of the result bytes must be

read from the Data Register before the next command can

be issued.

The main PLL consists of five main components, a phase

comparator, a charge pump, a filter, a voltage controlled

oscillator (VCO), and a programmable divider. The phase

comparator detects the difference between the phase of the

divider’s output and the phase of the raw data being read

from the disk. This phase difference is converted to a cur-

rent by the charge pump, which either charges or discharg-

es one of three filters which is selected based on the data

rate. The resulting voltage on the filter changes the frequen-

cy of the VCO and the divider output to reduce the phase

difference between the input data and the divider’s output.

The PLL is ‘‘locked’’ when the frequency of the divider is

exactly the same as the average frequency of the data read

from the disk. A block diagram of the data separator is

Like the Command Phase, the Main Status Register con-

trols the flow of result bytes, and must be polled by the

software before reading each Result Phase byte from the

Data Register. The RQM bit (D7) and DIO bit (D6) must both

be set before each result byte can be read. After the last

result byte is read, the COM PROG bit (D4) in the MSR will

be cleared, and the controller will be ready for the next com-

mand.

shown in

Figure 5-1.

5.3.4 Idle Phase

To ensure optimal performance, the data separator incorpo-

rates several additional circuits. The quarter period delay

line is used to determine the center of each bit cell, and to

disable the phase comparator when the raw data signal is

After a hardware or software reset, or after the chip has

recovered from the power down mode, the controller enters

the Idle Phase. Also, when there are no commands in prog-

43

5.0 FDC Functional Description (Continued)

missing a clock or data pulse in the MFM or FM pattern. A

secondary PLL is used to automatically calibrate the quarter

period delay line. The secondary PLL also calibrates the

center frequency of the VCO.

MSV is shown on the x-axis of the dynamic window margin

graph. MSV is translated directly to the actual data rate of

the data as it is read from the disk by the data separator.

That is, a faster than nominal motor will result in a higher

frequency in the actual data rate.

To eliminate the logic associated with controlling multiple

data rates, the FDC supports each of the four data rates

(250, 300, 500 kb/s, and 1 Mb/s) with a separate, optimized

internal filter. The appropriate filter for each data rate is au-

tomatically switched into the data separator circuit when the

data rate is selected via the Data Rate Select or Configura-

tion Control Register. These filters have been optimized

through lab experimentation, and are designed into the con-

troller to reduce the external component cost associated

with the floppy controller.

The dynamic window margin performance curves also indi-

cate how much bit jitter (or window margin) can be tolerated

by the data separator. This parameter is shown on the y-ax-

is of the graphs. Bit jitter is caused by the magnetic interac-

tion of adjacent data pulses on the disk, which effectively

shifts the bits away from their nominal positions in the mid-

dle of the bit window. Window margin is commonly mea-

sured as a percentage. This percentage indicates how far a

data bit can be shifted early or late with respect to its nomi-

nal bit position, and still be read correctly by the data sepa-

rator. If the data separator cannot correctly decode a shifted

bit, then the data will be misread and a CRC will result.

The FDC has a dynamic window margin and lock range per-

formance capable of handling a wide range of floppy disk

drives. Also, the data separator will work well under a variety

of conditions, including the high motor speed fluctuations of

floppy compatible tape drives.

The dynamic window margin performance curves contain

two pieces of information: 1) the maximum range of MSV

(also called ‘‘lock range’’) that the data separator can han-

dle with no read errors, and 2) the maximum percentage of

window margin (or bit jitter) that the data separator can han-

dle with no read errors. Thus, the area under the dynamic

window margin curves inFigure 5-2 is the range of MSV and

bit jitter that the FDC can handle with no read errors.

Figure 5-2 shows the floppy disk controller dynamic window

margin performance at the four different data rates. Dynam-

ic window margin is the primary indicator of the quality and

performance level of the data separator. This measurement

indicates how much motor speed variation (MSV) of the

drive spindle motor and bit jitter (or window margin) can be

tolerated by the data separator.

TL/F/11362–10

FIGURE 5-1. FDC Data Separator Block Diagram

44

5.0 FDC Functional Description (Continued)

The FDC internal analog data separator has a much better

performance than comparable digital data separator de-

signs, and does not require any external components.

5.5 CRYSTAL OSCILLATOR

The FDC is clocked by a single 24 MHz signal. An on-chip

oscillator is provided to enable the attachment of a crystal

or a clock signal.

Note: The dynamic window margin curves were generated using a FlexStar

FS-540 Floppy Disk Simulator and a proprietary dynamic window mar-

gin test program written by National Semiconductor.

A parallel resonant crystal is preferred if at all possible. In

some cases, a series resonant crystal can be used, but care

must be taken to ensure that the crystal does not oscillate

at a sub-harmonic frequency. The oscillator is able to work

with high profile, low profile, and surface mount type crystal

enclosures. External bypass capacitors (5 pF to 10 pF)

should be connected from XTAL1 and XTAL2 to GND. If an

external oscillator circuit is used, it must have a duty cycle of

at least 40%–60%, and minimum input levels of 2.4V and

The controller takes best advantage of the internal analog

data separator by implementing a sophisticated read algo-

rithm. This ID search algorithm, shown in Figure 5-3, en-

hances the PLL’s lock characteristics by forcing the PLL to

relock to the crystal reference frequency any time the data

separator attempts to lock to a non-preamble pattern. This

algorithm ensures that the PLL is not thrown way out of lock

by write splices or bad data fields.

250 kb/s

300 kb/s

TL/F/11362–6

TL/F/11362–7

500 kb/s

1 Mb/s

TL/F/11362–8

TL/F/11362–9

FIGURE 5-2. PC87311A/12 Dynamic Window Margin Performance

e

(Typical performance at V

5.0V, 25 C)

§

CC

45

5.0 FDC Functional Description (Continued)

0.4V. The controller should be configured so that the exter-

nal oscillator clock is input into the X1/OSC pin, and XTAL2

is left unconnected.

The 2.88M drive has unique format and write data timing

requirements due to its read/write head and pre-erase head

design (see Figure 5-4 ). Unlike conventional disk drives

which have only a read/write head, the 2.88M drive has

both a pre-erase head and read/write head. With conven-

tional disk drives, the read/write head by itself is able to

rewrite the disk without problems. For 2.88M drives, a pre-

erase head is needed to erase the magnetic flux on the disk

surface before the read/write can write to the disk surface.

The pre-erase head is activated during disk write operations

only, i.e., Format and Write Data commands.

5.6 PERPENDICULAR RECORDING MODE

The FDC is fully compatible with perpendicular recording

mode disk drives at all data rates. These perpendicular

mode drives are also called 4 Mbyte (unformatted) or

2.88 Mbyte (formatted) drives, which refers to their maxi-

mum storage capacity. Perpendicular recording will orient

the magnetic flux changes (which represent bits) vertically

on the disk surface, allowing for a higher recording density

than the conventional longitudinal recording methods. With

this increase in recording density comes an increase in the

data rate of up to 1 Mb/s, thus doubling the storage capaci-

ty. In addition, the perpendicular 2.88M drive is read/write

compatible with 1.44M and 720k diskettes (500 kb/s and

250 kb/s respectively).

In 2.88M drives, the pre-erase head leads the read/write

head by 200 mm, which translates to 38 bytes at 1 Mb/s (19

bytes at 500 kb/s). For both conventional and perpendicular

drives, WGATE is asserted with respect to the position of

the read/write head. With conventional drives, this means

that WGATE is asserted when the read/write head is locat-

ed at the beginning of the Data Field preamble. With the

TL/F/11362–11

FIGURE 5-3. Read Data AlgorithmÐState Diagram

TL/F/11362–12

FIGURE 5-4. Perpendicular Recording Drive R/W Head and Pre-Erase Head

46

5.0 FDC Functional Description (Continued)

2.88M drives, since the preamble must be pre-erased be-

fore it is rewritten, WGATE should be asserted when the

pre-erase head is located at the beginning of the Data Field

preamble. This means that WGATE should be asserted

when the read/write head is at least 38 bytes (at 1 Mb/s)

before the preamble. See Table 4-4 for a description of the

WGATE timing for perpendicular drives at the various data

rates.

will be used (see Table 3-5). The programmer can choose a

different value of write precomp with the DSR register if

desired (see Table 3-4). Also on power up, the default start-

ing track number for write precomp is track zero. This start-

ing track number for write precomp can be changed with the

Configure command.

5.9 FDC LOW POWER MODE LOGIC

The FDC section of the PC87311A/12 supports two low

power modes described here in detail. Other low power

modes of the PC87311A/12 described in Section 2.6 are

covered below and in section 3.6 and 4.2.6. The microcode

is driven from the clock, so it will be disabled while the clock

is off. The FDC clock is always disabled upon entering this

mode, however, the oscillator is only disabled when PTR1

Because of the 38 byte spacing between the read/write

head and the pre-erase head at 2 Mb/s, the GAP2 length of

22 bytes used in the standard IBM disk format is not long

enough. There is a new format standard for 2.88M drives at

1 Mb/s called the Perpendicular Format, which increases

the GAP2 length to 41 bytes (see Figure 4-1 ).

The Perpendicular Mode command will put the floppy con-

troller into perpendicular recording mode, which allows it to

read and write perpendicular media. Once this command is

invoked, the read, write and format commands can be exe-

cuted in the normal manner. The perpendicular mode of the

floppy controller will work at all data rates, adjusting the

format and write data parameters accordingly. See Section

4.2.8 for more details.

e

1. Upon entering the power down state, the RQM (Re-

quest For Master) bit in the MSR will be cleared.

There are two modes of low power in the floppy controller:

manual low power and automatic low power. Manual low

power is enabled by writing a 1 to bit 6 of the DSR. The chip

will go into low power immediately. This bit will be cleared to

0 after the chip is brought out of low power. Manual low

power can also be accessed via the Mode command. The

function of the manual low power mode is a logical OR func-

tion between the DSR low power bit and the Mode com-

mand manual low power bit setting.

5.7 DATA RATE SELECTION

The data rate can be chosen two different ways with the

FDC. For PC compatible software, the Configuration Control

Register at address 3F7 (hex) is used to program the data

rate for the floppy controller. The lower bits D1 and D0 are

used in the CCR to set the data rate. The other bits should

be set to zero. See Table 3-6 for the data rate select encod-

ing.

Automatic low power mode will switch the controller into low

power 500 ms (at the 500 kb/s MFM data rate) after it has

entered the idle state. Once the auto low power mode is set,

it does not have to be set again, and the controller will auto-

matically go into low power mode after it has entered the

idle state. Automatic low power mode can only be set with

the Mode command.

The data rate can also be set using the Data Rate Select

Register at address 4. Again, the lower two bits of the regis-

ter are used to set the data rate. The encoding of these bits

is exactly the same as those in the CCR. The remainder of

the bits in the DSR are used for other functions. Consult the

Register Description (Section 5.1) for more details.

There are two ways the FDC section can recover from the

power down state. The part will power up after a software

reset via the DOR or DSR. Since a software reset requires

reinitialization of the controller, this method can be undesir-

able. The part will also power up after a read or write to

either the Data Register or Main Status Register. This is the

preferred method of power up since all internal register val-

ues are retained. It may take a few milliseconds for the os-

cillator to stabilize, and the mP will be prevented from issu-

ing commands during this time through the normal Main

Status Register protocol. That is, the RQM bit in the MSR

will be a 0 until the oscillator has stabilized. When the con-

troller has completely stabilized from power up, the RQM bit

in the MSR is set to 1 and the controller can continue where

it left off.

The data rate is determined by the last value that is written

to either the CCR or the DSR. In other words, either the

CCR or the DSR can override the data rate selection of the

other register. When the data rate is selected, the micro-

engine and data separator clocks are scaled appropriately.

Also, the DRATE0 and DRATE1 output pins will reflect the

state of the data select bits that were last written to either

the CCR or the DSR.

5.8 WRITE PRECOMPENSATION

Write precompensation is

a way of preconditioning the

WDATA output signal to adjust for the effects of bit shift on

the data as it is written to the disk surface. Bit shift is caused

by the magnetic interaction of data bits as they are written

to the disk surface, and has the effect of shifting these data

bits away from their nominal position in the serial MFM or

FM data pattern. Data that is subject to bit shift is much

harder to read by a data separator, and can cause soft read

errors. Write precompensation predicts where bit shift could

occur within a data pattern. It then shifts the individual data

bits early, late, or not at all such that when they are written

to the disk, the resultant shifted data bits will be back in their

nominal position.

The Data Rate Select, Digital Output, and Configuration

Control Registers are unaffected by the power down mode.

They will remain active. It is up to the user to ensure that the

Motor and Drive Select signals are turned off.

Note: If the power to an external oscillator driving the PC87311A/12 is to be

independently removed during the FDC low power mode, it must not

be done until 2 ms after the FDC low power command is issued.

5.10 RESET OPERATION

The floppy controller can be reset by hardware or software.

Hardware reset is enacted by pulsing the Master Reset in-

put pin. A hardware reset will set all of the user addressable

registers and internal registers to their default values. The

The FDC supports software programmable write precom-

pensation. Upon power up, the default write precomp values

47

TABLE 6-1. PC87311A UART

e

5.0 FDC Functional Description

(Continued)

Register Addresses (AEN

0)

Specify command values will be don’t cares, so they must

be reinitialized. The major default conditions are: FIFO dis-

DLAB

1

A2 A1 A0

Selected Register

e

abled, FIFO threshold

Drive Polling enabled.

0, Implied Seeks disabled, and

0

Receiver Buffer (Read),

Transmitter Holding (Write)

A software reset can be performed through the Digital Out-

put Register or Data Rate Select Register. The DSR reset

bit is self-clearing, while the DOR reset bit is not self-clear-

ing. If the LOCK bit in the Lock command was set to a 1

previous to the software reset, the FIFO, THRESH, and

PRETRK parameters in the Configure command will be re-

tained. In addition, the FWR, FRD, and BST parameters in

the Mode command will be retained if LOCK is set to 1. This

function eliminates the need for total reinitialization of the

controller after a software reset.

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Interrupt Enable

Interrupt Identification (Read)

Line Control

MODEM Control

Line Status

MODEM Status

Scratch (Note 1)

After a hardware (assuming the FDC is enabled in the FER)

or software reset, the Main Status Register is immediately

available for read access by the mP. It will return a 00 hex

value until all the internal registers have been updated and

the data separator is stabilized. When the controller is ready

to receive a command byte, the MSR will return a value of

80 hex (Request for Master bit is set). The MSR is guaran-

teed to return the 80 hex value within 2.5 ms after a hard-

ware or software reset. All other user addressable registers

other than the Main Status Register and Data Register

(FIFO) can be accessed at any time, even while the part is

in reset.

Divisor Latch

(Least Significant Byte)

1

0

1

Divisor Latch

(Most Significant Byte)

Note: This register is only present when operating in the AT, NS16450 mode

(XTSEL is low during reset).

6.2.2 Line Control Register (LCR)

The system programmer uses the Line Control Register

(LCR) to specify the format of the asynchronous data com-

munications exchange and set the Divisor Latch Access bit.

This is a read and write register. Table 6-2 shows the con-

tents of the LCR. Details on each bit follow:

6.0 Serial Ports

6.1 INTRODUCTION

Each of these serial ports functions as a serial data input/

output interface in a microcomputer system. The system

software determines the functional configuration of the

UARTs via a 8-bit bidirectional data bus.

TL/F/11362–13

FIGURE 6-1. PC87311A Composite Serial Data

The UARTs are completely independent. They perform seri-

al-to-parallel conversion on data characters received from a

peripheral device or a MODEM, and parallel-to-serial con-

version on data characters received from the CPU. The

CPU can read the complete status of either UART at any

time during the functional operation. Status information re-

ported includes the type and condition of the transfer opera-

tions being performed by the UART, as well as any error

conditions (parity, overrun, framing, or break interrupt).

Bits 0,1 These two bits specify the number of data bits in

each transmitted or received serial character. The

encoding of bits 0 and 1 is as follows:

Bit 1

Bit 0

Data Length

5 Bits

0

1

0

1

0

1

6 Bits

7 Bits

The UARTs have programmable baud rate generators that

are capable of dividing the internal reference clock by divi-

sors of 1 to (2**16–1), and producing a 16 x clock for driv-

ing the transmitter logic. Provisions are also included to use

this 16 x clock to drive the receiver logic. The UARTs have

complete MODEM-control capability and a prioritized inter-

rupt system. Interrupts can be programmed to the user’s

requirements, minimizing the computing required to handle

the communications link.

8 Bits

Bit 2

This bit specifies the number of Stop bits transmit-

ted with each serial character. If bit 2 is a logic 0,

one Stop bit is generated in the transmitted data.

If bit 2 is a logic 1 when a 5-bit data length is

selected, one and a half Stop bits are generated.

If bit 2 is a logic 1 when either a 6-, 7-, or 8-bit

word length is selected, two Stop bits are generat-

ed. The receiver checks the first Stop bit only, re-

gardless of the number of Stop bits selected.

The PC87311A UARTs can operate in the INS8250-B mode

(XT) or the NS16450 mode (AT), depending on the state of

the XTSEL pin during reset.

6.2 PC87311A SERIAL PORTS

6.2.1 Serial Port Registers

Bit 3

This bit is the Parity Enable bit. When bit 3 is a

logic 1, a Parity bit is generated (transmit data) or

checked (receive data) between the last data bit

and Stop bit of the serial data. (The Parity bit is

used to produce an even or odd number of 1s

when the data bits and the Parity bit are summed.)

Two identical register sets, one for each channel, are in the

PC87311A. All register descriptions in this section apply to

the register sets in both channels.

48

6.0 Serial Ports (Continued)

TABLE 6-2. PC87311A Register Summary for an Individual UART Channel

Register Address

e

1DLAB 1

0DLAB

0

0DLAB

0

1DLAB

0

2

3

4

5

6

7

0DLAB

1

Receiver

Buffer

Transmitter

Holding

Register

(Write

Interrupt

Ident.

Scratch

Pad

Interrupt

Enable

Line

MODEM

Control

Register

Line

MODEM

Status

Divisor

Latch

(LS)

Divisor

Latch

(MS)

Bit

Register

(Read

Register

(Read

Control

Register

Status

No.

Register

(Note 4)

Register

Only)

RBR

THR

IER

IIR

LCR

MCR

LSR

MSR

SCR

Bit 0

DLL

Bit 0

DLM

Bit 8

0

1

Data Bit 0

(Note 1)

Data Bit 0

Enable

Received

Data

‘‘0’’ if

Word

Length

Select

Bit 0

Data

Terminal

Ready

(DTR)

Data

Ready

(DR)

Delta

Clear

Interrupt

Pending

to Send

Available

Interrupt

Data Bit 1

Enable

Transmitter

Holding

Interrupt

ID

Word

Length

Select

Bit 1

Request

to Send

(RTS)

Overrun

Error

Delta

Data

Set

Bit 1

Bit 9

Bit

(OE)

Register

Empty

Ready

Interrupt

2

3

Data Bit 2

Data Bit 3

Data Bit 2

Data Bit 3

Enable

Receiver

Line Status

Interrupt

ID

Number of

Stop Bits

Out1

Bit

Parity

Error

(PE)

Trailing

Edge Ring

Indicator

Bit 2

Bit 3

Bit 2

Bit 3

Bit 10

Bit 11

Bit

Enable

MODEM

Status

0

Parity

IRQ

Framing

Error

Delta

Data

Enable

(Note 3)

(FE)

Carrier

Detect

Interrupt

4

5

Data Bit 4

Data Bit 5

Data Bit 4

Data Bit 5

0

Even Parity

Select

Loop

0

Break

Interrupt

(BI)

Clear to

Send

Bit 4

Bit 5

Bit 4

Bit 5

Bit 12

Bit 13

(CTS)

0

Stick

Transmitter

Holding

Data

Set

Parity

Register

(THRE)

Ready

(DSR)

6

7

Data Bit 6

Data Bit 7

Data Bit 6

Data Bit 7

0

Set

0

Transmitter

Empty

Ring

Indicator

(RI)

Bit 6

Bit 7

Bit 6

Bit 7

Bit 14

Bit 15

Break

(TEMT)

(Note 2)

Divisor

Latch

0

Data

Carrier

Detect

(DCD)

Access Bit

(DLAB)

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.

Note 3: This bit no longer has a pin associated with it.

Note 4: When operating in the XT mode, this register is not available.

49

6.0 Serial Ports (Continued)

TABLE 6-3. PC87311A UART Reset Configuration

Register Signal

l

Reset Control

Master Reset

Reset State

0000 0000 (Note 1)

0000 0001

Interrupt Enable Register

Interrupt Identification Register

Line Control Register

MODEM Control Register

Line Status Register

MODEM Status Register

SOUT

0000 0000

0110 0000

XXXX 0000 (Note 2)

High

INTR (RCVR Errs)

INTR (RCVR Data Ready)

INTR (THRE)

Read LSR MR

l

Read RBR MR

Low/TRI-STATE

Low

l

Read IIR Write THR MR

l

Read MSR MR

l

INTR (Modem Status Changes)

Interrupt Enable Bit

RTS

l

Master Reset

High

DTR

High

Note 1: Boldface bits are permanently low.

Note 2: Bits 7–4 are driven by the input signals.

Bit 4

This bit is the Even Parity Select bit. When parity is

enabled and bit 4 is a logic 0, an odd number of

Control bit acts only on SOUT and has no effect

on the transmitter logic.

logic 1s is transmitted or checked in the data word

bits and Parity bit. When parity is enabled and bit 4

is a logic 1, an even number of logic 1s is transmit-

ted or checked.

Note: This feature enables the CPU to alert a terminal. If the

following sequence is used, no erroneous characters will

be transmitted because of the break.

e

1. Wait for the transmitter to be idle, (TEMT

1).

2. Set break for the appropriate amount of time. If

the transmitter will be used to time the break

Bit 5

This bit is the Stick Parity bit. When parity is en-

abled it is used in conjunction with bit 4 to select

Mark or Space Parity. When LCR bits 3, 4 and 5

e

duration, then check that TEMT

clearing the Break Control bit.

1 before

are logic

1 the Parity bit is transmitted and

checked as a logic 0 (Space Parity). If bits 3 and 5

are 1 and bit 4 is a logic 0 then the Parity bit is

transmitted and checked as a logic 1 (Mark Pari-

ty). If bit 5 is a logic 0 Stick Parity is disabled.

3. Clear break when normal transmission has to

be restored.

During the break, the Transmitter can be used as

a character timer to accurately establish the break

duration by sending characters and monitoring

THRE and TEMT.

Bit 6

This bit is the Break Control bit. It causes a break

condition to be transmitted to the receiving UART.

When it is set to a logic 1, the serial output (SOUT)

is forced to the Spacing state (logic 0). The break

is disabled by setting bit 6 to a logic 0. The Break

Bit 7

This bit is the Divisor Latch Access Bit (DLAB). It

must be set high (logic 1) to access the Divisor

Latches of the Baud rate Generator during a Read

or Write operation or to have the BOUT signal ap-

pear on the BOUT pin. It must be set low (logic 0)

to access any other register.

50

6.0 Serial Ports (Continued)

6.2.3 Programmable Baud Rate Generator

Bit 1 This bit is the Overrun Error (OE) indicator. Bit 1 indi-

cates that data in the Receiver Buffer Register was

not read by the CPU before the next character was

transferred into the Receiver Buffer Register, there-

by destroying the previous character. The OE indica-

tor is set to a logic 1 upon detection of an overrun

condition and reset whenever the CPU reads the

contents of the Line Status Register.

The PC87311A contains two independently programmable

Baud rate Generators. The 24 MHz crystal oscillator fre-

quency input is divided by 13, resulting in a frequency of

1.8462 MHz. This is sent to each Baud rate Generator and

divided by the divisor of the associated UART. The output

c

frequency of the Baud rate Generator (BOUT1,2) is 16

the baud rate.

Bit 2 This bit is the Parity Error (PE) indicator. Bit 2 indi-

cates that the received data character does not have

the correct even or odd parity, as selected by the

even-parity select bit. The PE bit is set to a logic 1

upon detection of a parity error and is reset to a logic

0 whenever the CPU reads the contents of the Line

Status Register.

e

c

(frequency input) (baud rate 16)

Ý

divisor

The output of each Baud rate Generator drives the transmit-

ter and receiver sections of the associated serial channel.

Two 8-bit latches per channel store the divisor in a 16-bit

binary format. These Divisor Latches must be loaded during

initialization to ensure proper operation of the Baud rate

Generator. Upon loading either of the Divisor Latches, a

16-bit Baud Counter is loaded. Table 6-4 provides decimal

divisors to use with crystal frequencies of 24 MHz. The os-

cillator input to the chip should always be 24 MHz to ensure

that the Floppy Disk Controller timing is accurate and that

the UART divisors are compatible with existing software.

Using a divisor of zero is not recommended.

Bit 3 This bit is the Framing Error (FE) indicator. Bit 3 indi-

cates that the received character did not have a val-

id Stop bit. Bit 3 is set to a logic 1 whenever the Stop

bit following the last data bit or parity bit is a logic 0

(Spacing level). The FE indicator is reset whenever

the CPU reads the contents of the Line Status Reg-

ister. The UART will try to resynchronize after a

framing error. To do this it assumes that the framing

error was due to the next start bit, so it samples this

‘‘start’’ bit twice and then takes in the bits following it

as the rest of the frame.

TABLE 6-4. PC87311A UART Divisors,

Baud Rates and Clock Frequencies

24 MHz Input Divided to 1.8432 MHz

Decimal Divisor

for 16 x Clock

Percent

Error

Bit 4 This bit is the Break Interrupt (BI) indicator. Bit 4 is

set to a logic 1 whenever the received data input is

held in the Spacing (logic 0) state for longer than a

full word transmission time (that is, the total time of

Baud Rate

50

2304

1536

1047

857

768

384

192

96

0.1

75

a

Parity Stop bits). The BI

Start bit

data bits

110

indicator is reset whenever the CPU reads the con-

tents of the Line Status Register. Restarting after a

break is received requires the SIN pin to be logical 1

for at least (/2 bit time.

134.5

150

0.4

Ð

0.5

Ð

300

Note: Bits

1 through 4 are the error conditions that produce a

600

Receiver Line Status interrupt whenever any of the corre-

sponding conditions are detected and the interrupt is en-

abled.

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

57600

115200

64

58

Bit 5 This bit is the Transmitter Holding Register Empty

(THRE) indicator. Bit 5 indicates that the UART is

ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an inter-

rupt to the CPU when the Transmiter Holding Regis-

ter Empty Interrupt enable is set high. The THRE bit

is set to a logic 1 when a character is transferred

from the Transmitter Holding Register into the

Transmitter Shift Register. The bit is reset to logic 0

whenever the CPU loads the Transmitter Holding

Register.

48

32

24

16

12

6

3

2

1

Bit 6 This bit changes its function depending on whether

the device is operating in the XT or AT mode. When

operating in the AT mode, this bit is the Transmitter

Empty (TEMT) indicator. Bit 6 is set to a logic 1

whenever the Transmitter Holding Register (THR)

and the Transmitter Shift Register (TSR) are both

empty. It is reset to a logic 0 whenever either the

THR or TSR contains a data character. When oper-

ating in the XT mode this bit is set whenever the

Transmitter Shift Register is empty. It is cleared

whenever a byte is loaded into the Transmit Shift

Register.

Note: The percent error for all baud rates, except where indicated otherwise

is 0.2%.

6.2.4 Line Status Register

This 8-bit register provides status information to the CPU

concerning the data transfer. Table 6-2 shows the contents

of the Line Status Register. Details on each bit follow:

Bit 0 This bit is the receiver Data Ready (DR) indicator. Bit

0 is set to logic 1 whenever a complete incoming

character has been received and transferred into the

Receiver Buffer Register. Bit 0 is reset to a logic 0 by

reading the data in the Receiver Buffer Register.

51

6.0 Serial Ports (Continued)

Bit 7 This bit is permanently set to logic 0.

ner, including the setting of the Line Status and MODEM

Status Registers. Table 6-2 shows the contents of the IER.

Details on each bit follow. See MODEM Control Register bit

3 for more information on enabling the interrupt pin.

Note: The Line Status Register is intended for read operations

only. Writing to this register is not recommended as this

operation is only used for factory testing.

6.2.5 Interrupt Identification Register (IIR)

Bit 0

Bit 1

Bit 2

Bit 3

This bit enables the Received Data Available Inter-

rupt when set to logic 1.

In order to provide minimum software overhead during data

character transfers, the UART prioritizes interrupts into four

levels and records these in the Interrupt Identification Reg-

ister. The four levels of interrupt conditions in order of priori-

ty are Receiver Line Status; Received Data Ready; Trans-

mitter Holding Register Empty; and MODEM Status.

This bit enables the Transmitter Holding Register

Empty Interrupt when set to logic 1.

This bit enables the Receiver Line Status Interrupt

when set to logic 1.

This bit enables the MODEM Status Interrupt

when set to logic 1.

When the CPU accesses the IIR, the UART freezes all inter-

rupts and indicates the highest priority pending interrupt to

the CPU. While this CPU access is occurring, the UART

records new interrupts, but does not change its current indi-

cation until the current access is complete. Table 6-2 shows

the contents of the IIR. Details on each bit follow:

Bits 4–7 These four bits are always logic 0.

6.2.7 Modem Control Register (MCR)

This register controls the interface with the MODEM or data

set (or a peripheral device emulating a MODEM). The con-

tents of the MODEM Control Register (MCR) are indicated

in Table 6-2 and are described below.

Bit 0

This bit can be used in an interrupt environment to

indicate whether an interrupt condition is pending.

When bit 0 is a logic 0, an interrupt is pending and

the IIR contents may be used as a pointer to the

appropriate interrupt service routine. When bit 0 is

a logic 1, no interrupt is pending.

Bit 0

This bit controls the Data Terminal Ready (DTR)

output. When bit 0 is set to a logic 1, the DTR

output is forced to a logic 0. When bit 0 is reset to

a logic 0, the DTR output is forced to a logic 1. In

Local Loopback Mode, this bit controls bit 5 of the

MODEM Status Register.

Bits 1, 2 These two bits of the IIR are used to identify the

highest priority interrupt pending as indicated in

Table 6-5.

Note: The DTR and RTS output of the UART may be applied to

an EIA inverting line driver (such as the DS1488) to ob-

tain the proper polarity input at the MODEM or data set.

Bits 3–7 These five bits of the IIR are always logic.

6.2.6 Interrupt Enable Register (IER)

Bit 1

Bit 2

This bit controls the Request to Send (RTS) out-

put. Bit 1 affects the RTS output in a manner iden-

tical to that described above for bit 0. In Local

This register enables the four types of UART interrupts.

Each interrupt can individually activate the appropriate inter-

rupt (IRQ3 or IRQ4) output signal. It is possible to totally

disable the interrupt system by resetting bits 0 through 3 of

the Interrupt Enable Register (IER). Similarly, setting bits of

this register to a logic 1 enables the selected interrupt(s).

Disabling an interrupt prevents it from being indicated as

active in the IIR and from activating the interrupt output sig-

nal. All other system functions operate in their normal man-

Loopback Mode, this bit controls bit

MODEM Status Register.

4 of the

This bit is the OUT1 bit. It does not have an output

pin associated with it. It can be written to and read

by the CPU. In Local Loopback Mode, this bit con-

trols bit 6 of the MODEM Status Register.

TABLE 6-5. PC87311A Interrupt Control Functions

Interrupt Set and Reset Functions

Interrupt Identification

Register

Priority

Level

Bit 2

Bit 1

Bit 0

Interrupt Type

None

Interrupt Source

None

Interrupt Reset Control

0

1

0

1

0

Ð

Highest

Receiver Line Status

Overrun Error, Parity Error,

Framing Error or Break

Interrupt

Reading the Line

Status Register

1

0

1

0

Second

Third

Received Data Available

Receiver Data Available

Read Receiver Buffer

Transmitter Holding

Register Empty

Transmitter Holding

Register Empty

Reading the IIR Register

(if Source of Interrupt) or

Writing the Transmitter

Holding Register

0

Fourth

MODEM Status

Clear to Send or Data Set

Ready or Ring Indicator

or Data Carrier Detect

Reading the MODEM

Status Register

52

6.0 Serial Ports (Continued)

Bit 3

This bit enables the interrupt when set. No exter-

Bit 3 This bit is the Delta Data Carrier Detect (DDCD) in-

dicator. Bit 3 indicates that the DCD input to the

chip has changed state.

nal pin is associated with this bit. In Local Loop-

back Mode, this bit controls bit 7 of the MODEM

Status Register.

Note: Whenever bit 0, 1, 2 or 3 is set to logic 1, a MODEM Status

Interrupt is generated.

Bit 4

This bit provides a Local loopback feature for diag-

nostic testing of the UART. When bit 4 is set to

logic 1, the following occur: the transmitter Serial

Output (SOUT) is set to the Marking (logic 1) state;

the receiver Serial Input (SIN) is disconnected; the

output of the Transmitter Shift Register is ‘‘looped

back’’ (connected) to the Receiver Shift Register;

the four MODEM Control inputs (DSR, CTS, RI

and DCD) are disconnected; and the DTR, RTS,

OUT1, IRQ ENABLE bits in MCR are internally

connected to DSR, CTS, RI and DCD in MSR, re-

spectively. When operating in the AT mode the

MODEM Control output pins are forced to their

high (inactive) states. When operating in the XT

mode the Modem Control output pins remain con-

nected to their corresponding bits in the MCR. In

the Loopback Mode, data that is transmitted is im-

mediately received. This feature allows the proc-

essor to verify the transmit-and-received-data

paths of the serial port.

Bit 4 This bit is the complement of the Clear to Send

(CTS) input. If bit 4 (loopback) of the MCR is set to a

1, this bit is equivalent to RTS in the MCR.

Bit 5 This bit is the complement of the Data Set Ready

(DSR) input. If bit 4 of the MCR is set to a 1, this bit

is equivalent to DTR in the MCR.

Bit 6 This bit is the complement of the Ring Indicator (RI)

input. If bit 4 of the MCR is set to a 1, this bit is

equivalent to OUT1 in the MCR.

Bit 7 This bit is the complement of the Data Carrier De-

tect (DCD) input. If bit 4 of the MCR is set to a 1, this

bit is equivalent to IRQ ENABLE in the MCR.

6.2.9 Scratchpad Register (SCR)

This 8-bit Read/Write Register does not control the UART

in any way. It is intended as a scratchpad register to be used

by the programmer to hold data temporarily. When operat-

ing in the XT mode, this register is unavailable.

6.3 PC87312 SERIAL PORTS

6.3.1 Serial Port Registers

In the Loopback Mode, the receiver and transmit-

ter interrupts are fully operational. The MODEM

Status Interrupts are also operational, but the in-

terrupts’ sources are the lower four bits of MCR

instead of the four MODEM control inputs. Writing

a 1 to any of these 4 MCR bits will cause an inter-

rupt. In Loopback Mode the interrupts are still con-

trolled by the Interrupt Enable Register. The IRQ3

and 4 pins respond as follows in Loopback mode:

(1) If AT mode is set (see XTSEL pin) then the

IRQ3 and 4 pins are TRI-STATE. If XT mode is set

then the IRQ3 and 4 pins will be TRI-STATE only if

the MCR3 bit is low.

Two identical register sets, one for each channel, are in the

PC87312. All register descriptions in this section apply to

the register sets in both channels.

TABLE 6-6. PC87312 UART Register Addresses

e

(AEN

0)

DLAB

1

A2 A1 A0

Selected Register

0

Receiver Buffer (Read),

Transmitter Holding (Write)

Bits 5–7 These bits are permanently set to logic 0.

0

1

0

Interrupt Enable

6.2.8 Modem Status Register (MSR)

Interrupt Identification (Read)

FIFO Control (Write)

This register provides the current state of the control lines

from the MODEM (or peripheral device) to the CPU. In addi-

tion to this current-state information, four bits of the MO-

DEM Status Register provide change information. These

bits are set to a logic 1 whenever a control input from the

MODEM changes state. They are reset to logic 0 whenever

the CPU reads the MODEM Status Register. Table 6-2

shows the contents of the MSR. Details on each bit follow.

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Line Control

MODEM Control

Line Status

MODEM Status

Scratch

Bit 0 This bit is the Delta Clear to Send (DCTS) indicator.

Bit 0 indicates that the CTS input to the chip has

changed state since the last time it was read by the

CPU.

Divisor Latch

(Least Significant Byte)

Bit 1 This bit is the Delta Data Set Ready (DDSR) indica-

tor. Bit 1 indicates that the DSR input to the chip has

changed state since the last time it was read by the

CPU.

1

0

1

Divisor Latch

(Most Significant Byte)

6.3.2 Line Control Register (LCR)

Bit 2 This bit is the Trailing Edge of Ring Indicator (TERI)

detector. Bit 2 indicates that the RI input to the chip

has changed from a low to a high state.

The system programmer uses the Line Control Register

(LCR) to specify the format of the asynchronous data com-

munications exchange and set the Divisor Latch Access bit.

53

6.0 Serial Ports (Continued)

This is a read and write register. Table 6-7 shows the con-

tents of the LCR. Details on each bit follow:

Bits 0, 1 These two bits specify the number of data bits in

each transmitted or received serial character. The

encoding of bits 0 and 1 is as follows:

Bit 1

Bit 0

Data Length

5 Bits

TL/F/11362–14

0

1

0

1

0

1

FIGURE 6-2. PC87312 Composite Serial Data

6 Bits

7 Bits

8 Bits

TABLE 6-7. PC87312 Register Summary for an Individual UART Channel

Register Address

e

1DLAB 1

0DLAB

0

0DLAB

0

1DLAB

0

2

3

4

5

6

7

0DLAB

1

Receiver Transmitter

Interrupt

Ident.

FIFO

Buffer

Register

(Read

Holding

Register

(Write

Interrupt

Enable

Control

Line

MODEM

Control

Line

MODEM Scratch

Status Pad

Register Register

Bit

Register Register

Control

Status

(LS)

(MS)

No.

Register

(Read

Only)

(Write

Only)

Register Register Register

Only)

RBR

THR

IER

IIR

FCR

LCR

MCR

LSR

MSR

SCR

Bit 0

DLL

Bit 0

DLM

Bit 8

0

1

Data Bit 0

(Note 1)

Data Bit 0

Enable

Received

Data

‘‘0’’ if

FIFO

Word

Length

Select

Bit 0

Data

Terminal

Ready

(DTR)

Data

Ready

(DR)

Delta

Clear

Interrupt

Pending

Enable

to Send

Available

Interrupt

Data Bit 1

Enable

Transmitter

Holding

Interrupt

ID

RCVR

FIFO

Word

Length

Select

Bit 1

Request

to Send

(RTS)

Overrun

Error

Delta

Data

Set

Bit 1

Bit 9

Bit

Reset

(OE)

Register

Empty

Ready

Interrupt

2

3

Data Bit 2

Data Bit 3

Data Bit 2

Data Bit 3

Enable

Receiver

Line Status

Interrupt

ID

XMIT

FIFO

Reset

Number of

Stop Bits

Out 1

Bit

Parity

Error

(PE)

Trailing

Edge Ring

Indicator

Bit 2

Bit 3

Bit 2

Bit 3

Bit 10

Bit 11

Bit

(Note 3)

Enable

MODEM

Status

Interrupt

ID

DMA

Mode

Select

Parity

IRQ

Framing

Error

Delta

Data

Enable

Bit

(FE)

Carrier

Detect

Interrupt

(Note 2)

4

5

Data Bit 4

Data Bit 5

Data Bit 4

Data Bit 5

0

Reserved Even Parity

Select

Loop

0

Break

Interrupt

(BI)

Clear to

Send

Bit 4

Bit 5

Bit 4

Bit 5

Bit 12

Bit 13

0

Reserved

Stick

Transmitter

Holding

Data

Set

Parity

Register

(THRE)

Ready

6

7

Data Bit 6

Data Bit 7

Data Bit 6

Data Bit 7

0

FIFOs

Enabled

(Note 2)

RCVR

Trigger

(LSB)

Set

0

Transmitter

Empty

Ring

Bit 6

Bit 7

Bit 6

Bit 7

Bit 14

Bit 15

Break

Indicator

(TEMT)

FIFOs

Enabled

(Note 2)

RCVR

Trigger

(MSB)

Divisor

Latch

Error in

RCVR

FIFO

Data

Carrier

Detect

Access Bit

(DLAB)

(Note 2)

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

Note 2: These bits are always 0 in the NS16450 Mode.

Note 3: This bit no longer has a pin associated with it.

54

6.0 Serial Ports (Continued)

Bit 2

This bit specifies the number of Stop bits transmit-

Bit 6

This bit is the Break Control bit. It causes a break

condition to be transmitted to the receiving UART.

When it is set to a logic 1, the serial output (SOUT)

is forced to the Spacing state (logic 0). The break

is disabled by setting bit 6 to a logic 0. The Break

Control bit acts only on SOUT and has no effect

on the transmitter logic.

ted with each serial character. If bit 2 is a logic 0,

one Stop bit is generated in the transmitted data.

If bit 2 is a logic 1 when a 5-bit data length is

selected, one and a half Stop bits are generated.

If bit 2 is a logic 1 when either a 6-, 7-, or 8-bit

word length is selected, two Stop bits are generat-

ed. The receiver checks the first Stop bit only, re-

gardless of the number of Stop bits selected.

Note: This feature enables the CPU to alert a terminal. If the

following sequence is used, no erroneous characters will

be transmitted because of the break.

Bit 3

Bit 4

Bit 5

This bit is the Parity Enable bit. When bit 3 is a

logic 1, a Parity bit is generated (transmit data) or

checked (receive data) between the last data bit

and Stop bit of the serial data. (The Parity bit is

used to produce an even or odd number of 1s

when the data bits and the Parity bit are summed.)

e

1. Wait for the transmitter to be idle (TEMT

1).

2. Set break for the appropriate amount of time. If

the transmitter will be used to time the break

e

duration, then check that TEMT

clearing the Break Control bit.

1 before

3. Clear break when normal transmission has to

be restored.

This bit is the Even Parity Select bit. When parity is

enabled and bit 4 is a logic 0, an odd number of

logic 1s is transmitted or checked in the data word

bits and Parity bit. When parity is enabled and bit 4

is a logic 1, an even number of logic 1s is transmit-

ted or checked.

During the break, the Transmitter can be used

as a character timer to accurately establish the

break duration by sending characters and moni-

toring THRE and TEMT.

This bit is the Stick Parity bit. When parity is en-

abled it is used in conjuction with bit 4 to select

Mark or Space Parity. When LCR bits 3, 4 and 5

Bit 7

This bit is the Divisor Latch Access Bit (DLAB). It

must be set high (logic 1) to access the Divisor

Latches of the Baud rate Generator during a Read

or Write operation or to have the BOUT signal ap-

pear on the BOUT pin. It must be set low (logic 0)

to access any other register.

are logic

1 the Parity bit is transmitted and

checked as a logic 0 (Space Parity). If bits 3 and 5

are 1 and bit 4 is a logic 0 then the Parity bit is

transmitted and checked as a logic 1 (Mark Pari-

ty). If bit 5 is a logic 0 Stick Parity is disabled.

TABLE 6-8. PC87312 UART Reset Configuration

Register Signal

l

Interrupt Enable

Reset Control

Master Reset

Reset State

0000 0000 (Note 1)

0000 0001

Interrupt Identification

FIFO Control

0000 0000

Line Control

0000 0000

MODEM Control

Line Status

0000 0000

0110 0000

MODEM Status

SOUT

XXXX 0000 (Note 2)

High

INTR (RCVR Errs)

INTR (RCVR Data Ready)

INTR (THRE)

Read LSR MR

l

Read RBR MR

Low/TRI-STATE

Low

l

Read IIR Write THR MR

l

Read MSR MR

l

INTR (Modem Status Changes)

Interrupt Enable Bit

RTS

l

Master Reset

High

DTR

High

RCVR FIFO

MR/FCR1 FCR0/DFCR0

All Bits Low

#

XMIT FIFO

MR/FCR1 FCR0/DFCR0

#

Note 1: Boldface bits are permanently low.

Note 2: Bits 7–4 are driven by the input signals.

55

6.0 Serial Ports (Continued)

6.3.3 Programmable Baud Rate Generator

Bit 1 This bit is the Overrun Error (OE) indicator. Bit 1 indi-

cates that data in the Receiver Buffer Register was

not read by the CPU before the next character was

transferred into the Receiver Buffer Register, there-

by destroying the previous character. The OE indica-

tor is set to a logic 1 upon detection of an overrun

condition and reset whenever the CPU reads the

contents of the Line Status Register. If the FIFO

mode data continues to fill the FIFO beyond the trig-

ger level, an Overrun error will occur only after the

FIFO is completely full and the next character has

been received in the shift register. OE is indicated to

the CPU as soon as it happens. The character in the

shift register is overwritten, but it is not transferred to

the FIFO.

The PC87312 contains two independently programmable

Baud rate Generators. The 24 MHz crystal oscillator fre-

quency input is divided by 13, resulting in a frequency of

1.8462 MHz. This is sent to each Baud rate Generator and

divided by the divisor of the associated UART. The output

c

frequency of the Baud rate Generator (BOUT1,2) is 16

the baud rate.

e

c

(frequency input) (baud rate 16)

Ý

divisor

The output of each Baud rate Generator drives the transmit-

ter and receiver sections of the associated serial channel.

Two 8-bit latches per channel store the divisor in a 16-bit

binary format. These Divisor Latches must be loaded during

initialization to ensure proper operation of the Baud rate

Generator. Upon loading either of the Divisor Latches, a

16-bit Baud Counter is loaded. Table 6-9 provides decimal

divisors to use with crystal frequencies of 24 MHz. The os-

cillator input to the chip should always be 24 MHz to ensure

that the Floppy Disk Controller timing is accurate and that

the UART divisors are compatible with existing software.

Using a divisor of zero is not recommended.

Bit 2 This bit is the Parity Error (PE) indicator. Bit 2 indi-

cates that the received data character does not have

the correct even or odd parity, as selected by the

even-parity select bit. The PE bit is set to a logic 1

upon detection of a parity error and is reset to a logic

0 whenever the CPU reads the contents of the Line

Status Register. In the FIFO mode this error is asso-

ciated with the particular character in the FIFO that it

applies to. This error is revealed to the CPU when its

associated character is at the top of the FIFO.

TABLE 6-9. PC87312 UART Divisors,

Baud Rates and Clock Frequencies

24 MHz Input Divided to 1.8461 MHz

Bit 3 This bit is the Framing Error (FE) indicator. Bit 3 indi-

cates that the received character did not have a val-

id Stop bit. Bit 3 is set to a logic 1 whenever the Stop

bit following the last data bit or parity bit is a logic 0

(Spacing level). The FE indicator is reset whenever

the CPU reads the contents of the Line Status Reg-

ister. In the FIFO mode this error is associated with

the particular character in the FIFO that it applies to.

This error is revealed to the CPU when its associat-

ed character is at the top of the FIFO. The UART will

try to resynchronize after a framing error. To do this

it assumes that the framing error was due to the next

start bit, so it samples this ‘‘start’’ bit twice and then

takes in the bits following it as the rest of the frame.

Decimal Divisor

Percent

Error

Baud Rate

c

for 16 Clock

50

2304

1536

1047

857

768

384

192

96

0.1

75

110

134.5

150

0.4

Ð

0.5

Ð

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

57600

115200

64

58

Bit 4 This bit is the Break Interrupt (BI) indicator. Bit 4 is

set to a logic 1 whenever the received data input is

held in the Spacing (logic 0) state for longer than a

full word transmission time (that is, the total time of

48

32

24

a

Parity Stop bits). The BI

Start bit

data bits

16

indicator is reset whenever the CPU reads the con-

tents of the Line Status Register. In the FIFO mode

this error is associated with the particular character

in the FIFO that it applies to. This error is revealed to

the CPU when its associated character is at the top

of the FIFO. When break occurs only one character

is loaded into the FIFO. Restarting after a break is

received requires the SIN pin to be logical 1 for at

least (/2 bit time.

12

6

3

2

1

Note: The percent error for all baud rates, except where indicated otherwise

is 0.2%.

6.3.4 Line Status Register (LSR)

Note: Bits

1 through 4 are the error conditions that produce a

This 8-bit register provides status information to the CPU

concerning the data transfer. Table 6-7 shows the contents

of the Line Status Register. Details on each bit follow:

Receiver Line Status interrupt whenever any of the corre-

sponding conditions are detected and that interrupt is en-

abled.

Bit 5 This bit is the Transmitter Holding Register Empty

(THRE) indicator. Bit 5 indicates that the UART is

ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an inter-

rupt to the CPU when the Transmit Holding Register

Empty Interrupt enable is set high. The THRE bit is

Bit 0 This bit is the receiver Data Ready (DR) indicator. Bit

0 is set to a logic 1 whenever a complete incoming

character has been received and transferred into the

Receiver Buffer Register or the FIFO. Bit 0 is reset to

a logic 0 by reading the data in the Receiver Buffer

Register or the FIFO.

56

6.0 Serial Ports (Continued)

set to a logic 1 when a character is transferred from the

Transmitter Holding Register into the Transmitter Shift Reg-

ister. The bit is reset to logic 0 whenever the CPU loads the

Transmitter Holding Register. In the FIFO mode this bit is

set when the XMIT FIFO is empty; it is cleared when at least

1 byte is written to the XMIT FIFO.

FCR Bits

RCVR FIFO

7

0

1

6

0

1

0

1

Trigger Level (Bytes)

01

04

08

14

Bit 6 This bit is the Transmitter Empty (TEMT) indicator.

Bit 6 is set to a logic 1 whenever the Transmitter

Holding Register (THR) and the Transmitter Shift

Register (TSR) are both empty. It is reset to a logic 0

whenever either the THR or TSR contains a data

character. In the FIFO mode this bit is set to one

whenever the transmitter FIFO and the shift register

are both empty.

6.3.6 Interrupt Identification Register (IIR)

In order to provide minimum software overhead during data

character transfers, the UART prioritizes interrupts into four

levels and records these in the Interrupt Identification Reg-

ister. The four levels of interrupt conditions in order of priori-

ty are Receiver Line Status; Received Data Ready; Trans-

mitter Holding Register Empty; and MODEM Status.

Bit 7 In the NS16450 Mode this is a 0. In the FIFO Mode

LSR7 is set when there is at least one parity error,

framing error or break indication in the FIFO. LSR7 is

cleared when the CPU reads the LSR, if there are no

subsequent errors in the FIFO.

When the CPU accesses the IIR, the UART freezes all inter-

rupts and indicates the highest priority pending interrupt to

the CPU. While this CPU access is occurring, the UART

records new interrupts, but does not change its current indi-

cation until the current access is complete. Table 6-2 shows

the contents of the IIR. Details on each bit follow:

Note: The Line Status Register is intended for read operations

only. Writing to this register is not recommended as this

operation is only used for factory testing. In the FIFO mode

the software must load a data byte in the Rx FIFO via the

Loopback Mode in order to write to LSR2–LSR4. LSR0 and

LSR7 can’t be written to in FIFO Mode.

Bit 0

This bit can be used in an interrupt environment to

indicate whether an interrupt condition is pending.

When bit 0 is a logic 0, an interrupt is pending and

the IIR contents may be used as a pointer to the

appropriate interrupt service routine. When bit 0 is

a logic 1, no interrupt is pending.

6.3.5 FIFO Control Register (FCR)

This is a write only register at the same location as the IIR

(the IIR is a read only register). This register is used to en-

able the FIFOs, clear the FIFOs, set the RCVR FIFO trigger

level, and select the type of DMA signaling.

Bit 0

Writing a 1 to FCR0 enables both the XMIT and

RCVR FIFOs. Resetting FCR0 will clear all bytes in

both FIFOs. When changing from FIFO Mode to

NS16450 Mode and vice versa, data is automati-

cally cleared from the FIFOs. This bit must be a 1

when other FCR bits are written to or they will not

be programmed.

Bits 1, 2 These two bits of the IIR are used to identify the

highest priority interrupt pending as indicated in

Table 6-10.

Bit 3

In the 16450 mode this bit is 0. In the FIFO mode

this bit is set along with bit 2 when a timeout inter-

rupt is pending.

Bits 4, 5 These bits of the IIR are always logic 0.

Bit 1

Bit 2

Bit 3

Writing a 1 to FCR1 clears all bytes in the RCVR

FIFO and resets its counter logic to 0. The shift

register is not cleared. The 1 that is written to this

bit position is self-clearing.

e

Bits 6, 7 These two bits are set when FCR0

Mode enabled.)

1. (FIFO

6.3.7 Interrupt Enable Register (IER)

Writing a 1 to FCR2 clears all bytes in the XMIT

FIFO and resets its counter logic to 0. The shift

register is not cleared. The 1 that is written to this

bit position is self-clearing.

This register enables the five types of UART interrupts.

Each interrupt can individually activate the appropriate inter-

rupt (IRQ3 or IRQ4) output signal. It is possible to totally

disable the interrupt system by resetting bits 0 through 3 of

the Interrupt Enable Register (IER). Similarly, setting bits of

this register to a logic 1, enables the selected interrupt(s).

Disabling an interrupt prevents it from being indicated as

active in the IIR and from activating the interrupt output sig-

nal. All other system functions operate in their normal man-

ner, including the setting of the Line Status and MODEM

Status Registers. Table 6-7 shows the contents of the IER.

Details on each bit follow. See MODEM Control Register bit

3 for more information on enabling the interrupt pin.

Writing to FCR3 causes no change in UART opera-

tions.

NOTE THAT THE TXRDY AND RXRDY PINS ARE

NOT AVAILABLE IN THE PC87312.

Bits 4, 5 FCR4 to FCR5 are reserved for future use.

Bits 6, 7 FCR6 and FCR7 are used to designate the inter-

rupt trigger level. When the number of bytes in the

RCVR FIFO equals the designated interrupt trigger

level, a Received Data Available Interrupt is acti-

vated. This interrupt must be enabled by setting

IER0.

Bit 0

When set to logic 1 this bit enables the Received

Data Available Interrupt and Timeout Interrupt in

the FIFO Mode.

57

6.0 Serial Ports (Continued)

TABLE 6-10. PC87312 Interrupt Control Functions

FIFO

Mode

Only

Interrupt

Identification

Register

Interrupt Set and Reset Functions

Priority

Level

Bit 3

Bit 2

Bit 1

Bit 0

Interrupt Type

Interrupt Source

Interrupt Reset Control

0

1

0

1

0

Ð

None

Ð

Highest

Receiver Line

Status

Overrun Error, Parity Error,

Framing Error or Break Interrupt

Reading the Line

Status Register

0

1

0

Second

Received Data

Available

Receiver Data Available

Read Receiver Buffer

Character

Timeout

Indication

No Characters Have Been

Reading the Receiver

Buffer Register

Removed from or Input to the

RCVR FIFO during the Last 4

Char. Times and there is at

least 1 Char. in it during this Time

0

1

0

Third

Transmitter

Holding Register Register Empty

Empty

Transmitter Holding

Reading the IIR Register

(if Source of Interrupt) or

Writing the Transmitter

Holding Register

Fourth

MODEM Status

Clear to Send or Data Set

Ready or Ring Indicator or

Data Carrier Detect

Reading the MODEM

Status Register

Bit 1

Bit 2

Bit 3

This bit enables the Transmitter Holding Register

Empty Interrupt when set to logic 1.

Bit 3

This bit enables the interrupt when set. No exter-

nal pin is associated with this bit other than

IRQ3,4. In Local Loopback Mode, this bit controls

bit 7 of the MODEM Status Register.

This bit enables the Receiver Line Status Interrupt

when set to logic 1.

Bit 4

This bit provides a Local loopback feature for diag-

nostic testing of the UART. When bit 4 is set to

logic 1, the following occur: the transmitter Serial

Output (SOUT) is set to the Marking (logic 1) state;

the receiver Serial Input (SIN) is disconnected; the

output of the Transmitter Shift Register is ‘‘looped

back’’ (connected) to the Receiver Shift Register;

the four MODEM Control inputs (DSR, CTS, RI

and DCD) are disconnected; and the DTR, RTS,

OUT1, IRQ ENABLE bits in MCR are internally

connected to DSR, CTS, RI and DCD in MSR, re-

spectively. The MODEM Control output pins are

forced to their high (inactive) states. In the Loop-

back Mode, data that is transmitted is immediately

received. This feature allows the processor to veri-

fy the transmit-and-received-data paths of the seri-

al port.

This bit enables the MODEM Status Interrupt

when set to logic 1.

Bits 4–7 These four bits are always logic 0.

6.3.8 MODEM Control Register (MCR)

This register controls the interface with the MODEM or data

set (or a peripheral device emulating a MODEM). The con-

tents of the MODEM Control Register (MCR) are indicated

in Table 6-7 and are described below.

Bit 0

This bit controls the Data Terminal Ready (DTR)

output. When bit 0 is set to a logic 1, the DTR

output is forced to a logic 0. When bit 0 is reset to

a logic 0, the DTR output is forced to a logic 1. In

Local Loopback Mode, this bit controls bit 5 of the

MODEM Status Register.

Note: The DTR and RTS output of the UART may be applied to

an EIA inverting line driver (such as the DS1488) to ob-

tain the proper polarity input at the MODEM or data set.

In the Loopback Mode, the receiver and transmit-

ter interrupts are fully operational. The MODEM

Status Interrupts are also operational, but the in-

terrupts’ sources are the lower four bits of MCR

instead of the four MODEM control inputs. Writing

a 1 to any of these 4 MCR bits will cause an inter-

rupt. In Loopback Mode the interrupts are still con-

trolled by the Interrupt Enable Register. The IRQ3

and 4 pins will be TRI-STATE in the Loopback

Mode.

Bit 1

Bit 2

This bit controls the Request to Send (RTS) out-

put. Bit 1 affects the RTS output in a manner iden-

tical to that described above for bit 0. In Local

Loopback Mode, this bit controls bit 4 of the MO-

DEM Status Register.

This bit is the OUT1 bit. It does not have an output

pin associated with it. It can be written to and read

by the CPU. In Local Loopback Mode, this bit con-

trols bit 6 of the Modem Status Register.

Bits 5–7 These bits are permanently set to logic 0.

58

6.0 Serial Ports (Continued)

6.3.9 MODEM Status Register (MSR)

A special back voltage protection circuit is implemented

against damage that might be caused when the printer is

powered but the PC87311A or PC87312 device is not.

This register provides the current state of the control lines

from the MODEM (or peripheral device) to the CPU. In addi-

tion to this current-state information, four bits of the

MODEM Status Register provide change information. These

bits are set to a logic 1 whenever a control input from the

MODEM changes state. They are reset to logic 0 whenever

the CPU reads the MODEM Status Register. Table 6-7

shows the contents of the MSR. Details on each bit follow:

There are two modes of operation (see Table 7-2): Compati-

e

1). The Compatible

e

ble (PTR7

0) and Extended (PTR7

mode is the same as the basic operating mode for the

PC-AT and the Extended mode is identical to the PS/2 Ex-

tended mode. There are 3 features which distinguish Ex-

tended mode from Compatible Mode:

Bit 0 This bit is the Delta Clear to Send (DCTS) indicator.

Bit 0 indicates that the CTS input to the chip has

changed state since the last time it was read by the

CPU.

1. Port direction is controlled by the CTR5 bit.

2. The interrupt is latched on the rising edge of ACK rather

than following ACK continuously.

3. The STR2 bit monitors the interrupt status.

Bit 1 This bit is the Delta Data Set Ready (DDSR) indica-

tor. Bit 1 indicates that the DSR input to the chip has

changed state since the last time it was read by the

CPU.

In Compatible mode the direction of data flow is controlled

e

at reset time by the PDIR pin (PDIR

0

output direction,

e

input direction). A write operation in this

e

and PDIR

1

mode causes the data to be presented on pins PD0–7. The

read operation causes the Data Register to present the last

data written to it by the CPU.

Bit 2 This bit is the Trailing Edge of Ring Indicator (TERI)

detector. Bit 2 indicates that the RI input to the chip

has changed from a low to a high state.

TABLE 7-2. Data Register Read and Write Modes

Bit 3 This bit is the Delta Data Carrier Detect (DDCD) indi-

cator. Bit 3 indicates that the DCD input to the chip

has changed state.

PTR7 PDIR CTR5 RD WR

Result

0

1

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

Data Written to

PD0–PD7

Note: Whenever bit 0, 1, 2, or 3 is set to logic 1, a MODEM Status

Interrupt is generated.

Bit 4 This bit is the complement of the Clear to Send (CTS)

input. If bit 4 (loopback) of the MCR is set to a 1, this

bit is equivalent to RTS in the MCR.

Data Written is

Latched

Data Read from

the Output Latch

Bit 5 This bit is the complement of the Data Set Ready

(DSR) input. If bit 4 of the MCR is set to a 1, this bit is

equivalent to DTR in the MCR.

Data Read from

PD0–PD7

Bit 6 This bit is the complement of the Ring Indicator (RI)

input. If bit 4 of the MCR is set to a 1, this bit is

equivalent to OUT1 in the MCR.

Data Written to

PD0–PD7

Bit 7 This bit is the complement of the Data Carrier Detect

(DCD) input. If bit 4 of the MCR is set to a 1, this bit is

equivalent to IRQ ENABLE in the MCR.

Data Written is

Latched

Data Read from

the Output Latch

6.3.10 Scratchpad Register (SCR)

This 8-bit Read/Write Register does not control the UART

in any way. It is intended as a scratchpad register to be used

by the programmer to hold data temporarily.

Data Read from

PD0–PD7

In the Extended Mode, a write operation to the Data Regis-

ter causes the data to be latched. If the Data Port Direction

bit (CTR5) is 0, the latched data is presented to the pins; if it

is 1 the data is only latched. When Data Port Direction bit

(CTR5) is 0, a read operation from the Data Register allows

the CPU to read the last data it wrote to the port. In the

Extended Mode with the Data Port Direction bit set to 1

(read), a read from this register causes the port to present

the data on pins PD0–PD7.

7.0 Parallel Port

7.1 INTRODUCTION

This parallel interface is designed to provide all of the sig-

nals and registers needed to communicate through a stan-

dard parallel printer port as found in the IBM, PC, XT, AT,

PS/2 and Centronics systems. The address decoding of the

registers utilizing A0 and A1 is shown in Table 7-1. Table 7-3

shows the Reset states of Parallel port registers and pin

signals. All bits in these registers are located in the same

positions and have the same functions as the registers of

the systems listed above. These registers are shown in Sec-

tions 7-2–7-4.

TABLE 7-3. Parallel Port Mode of Operation

Port Function

Compatible

Extended

PTR7

POE

0

1

0

TABLE 7-1. Parallel Interface Register Addresses

A1

0

A0

0

Address

Register

Data

Access

Read/Write

Read

0

1

2

3

0

1

Status

1

0

Control

Read/Write

1

TRI-STATE

59

7.0 Parallel Port (Continued)

7.2 DATA REGISTER (DTR)

7.4 CONTROL REGISTER (CTR)

TL/F/11362–41

TL/F/11362–43

This is a bidirectional data port that transfers 8-bit data. The

direction is determined by the state of PDIR pin, PTR7 bit

and CTR5 bit. When PTR7 is low, the PDIR pin will be

sensed during reset and it will determine the port direction.

When PTR7 is high, the CTR5 bit will determine the port

direction in conjunction with the Read and Write strobes.

See PTR7 bit, CTR5, POE and DPIR pins for further infor-

mation.

This register provides all output signals to control the print-

er. It is a read and write register, except for bit 5, which is

a write-only bit.

Bit 0

This bit (STB) directly controls the data strobe sig-

nal to the printer via the STB pin. This bit is the

inverse of the STB pin.

Bit 1

This bit (AFD) directly controls the automatic feed

XT signal to the printer via the AFD pin. Setting this

bit high causes the printer to automatically feed

after each line is printed. This bit is the inverse of

the AFD pin.

7.3 STATUS REGISTER (STR)

Bit 2

Bit 3

Bit 4

This bit (INIT) directly controls the signal to initial-

ize the printer via the INIT pin. Setting this bit to

low initializes the printer. This bit follows the INIT

pin.

This bit (SLIN) directly controls the select in signal

to the printer via the SLIN pin. Setting this bit high

selects the printer. This bit is the inverse of the

SLIN pin.

TL/F/11362–42

This register provides status for the signals listed below. It is

a read only register. Writing to it is an invalid operation that

has no effect.

This bit enables the parallel port interrupt. Setting

this bit low puts the appropriate IRQ5 or 7 into

TRI-STATE. In the AT Compatible mode, when this

bit is set high the appropriate IRQ signal follows

the ACK signal level transitions. In the Extended

mode, when this bit is set low the IRQ signal goes

TRI-STATE and CLEARS any pending interrupts.

Setting it high, the appropriate IRQ signal follows

the ACK signal and latches high on a 0 to 1 ACK’s

edge transition.

Bits 0, 1 Reserved, these bits are always 1.

Bit 2

In the Compatible mode this bit is always one. In

the Extended mode (PTR7 bit is 1) this bit is the

e

IRQ STATUS bit. In Extended mode if CTR4

1,

then this bit is latched low when the ACK signal

makes a transition from 0 to 1. Reading this bit

sets it to a one. This bit is the inverse of the appro-

priate IRQ signal pin.

Bit 5

This bit determines the parallel port direction when

e

fault condition results in the parallel port being in

Bit 3

Bit 4

Bit 5

Bit 6

This bit represents the current state of the printer

error signal (ERROR). The printer sets this bit low

when there is a printer error. This bit follows the

state of the ERR pin.

Extended mode is selected (PTR7

1). The de-

e

0) this bit is reversed and reads 1.

the output direction (CTR5

0). In Compatible

e

mode (PTR7

This is a WRITE ONLY bit. See Table 7-2 for fur-

ther details.

This bit represents the current state of the printer

select signal (SLCT). The printer sets this bit high

when it is selected. This bit follows the state of the

SLCT pin.

Bits 6, 7 Reserved. These bits are always 1.

TABLE 7-4. Parallel Port Reset States

This bit represents the current state of the printer

paper end signal (PE). The printer sets this bit high

when it detects the end of the paper. This bit fol-

lows the state of the PE pin.

Signal

SLIN

INIT

Control Reset

State after Reset

TRI-STATE

ZERO

MR

This bit represents the current state of the printer

acknowledge signal (ACK). The printer pulses this

signal low after it has received a character and is

ready to receive another one. This bit follows the

state of the ACK pin.

AFD

TRI-STATE

STB

IRQ5, 7

Bit 7

This bit (BUSY) represents the current state of the

printer busy signal. The printer sets this bit low

when it is busy and cannot accept another charac-

ter. This bit is the inverse of the (BUSY) pin.

60

reads and writes. The IDED7 signal insures that the D7 data

bus signal line is disabled for address 3F7 (this bit is used

for the Disk Changed register on the floppy disk controller at

that address). The two ’LS245 chips are used to enable or

TRI-STATE the data bus signals. In the PC-AT mode the

PC87311A/12 provides the two hard disk chip selects

(HCS0, HCS1) for the IDE interface. The HCS0 output is

active low when the 1F0–1F7 (hex) I/O address space is

chosen and corresponds to the 1FX signal on the IDE head-

er. The HCS1 output is active low when the 3F6 or 3F7 I/O

addresses are chosen, and corresponds to 3FX on the IDE

header. These are the two address blocks used in the

PC-AT hard disk controller. The table below summarizes the

addresses used by the PC-AT hard disk controller.

7.0 Parallel Port (Continued)

NOTE: Normally when the Control Register is read, the bit values are

provided by the internal output data latch. These bit values can be

superseded by the logic level of the STB, AFD, INIT, and SLIN pins, if

these pins are forced high or low by an external voltage. In order to

force these pins high or low the corresponding bits should be set to

e

0, INIT 1).

their inactive state (e.g. AFD

STB

SLIN

8.0 Integrated Device Electronics

Interface (IDE)

8.1 INTRODUCTION

Another key interface design facilitated through the use of

the PC87311A/12 is the IDE (Intelligent Drive Electronics)

Hard Disk interface. Only three buffer chips are required to

construct the IDE Hard Disk Interface circuit (see Figure

10-3 ).

TABLE 8-1. IDE Registers and Their ISA Addresses

Address

1F0

Read Function

Data

Write Function

Data

The IDE interface is essentially the AT bus ported to the

hard drive. The hard disk controller resides on the hard drive

itself. So the IDE interface circuit must provide the AT bus

signals, including data bits D15–D0, address lines A3–A0,

as well as the common control signals. These signals are

shown on the 40-pin IDE interface header (see Figure

10-3 ).

1F1

Error

Features

(Write Precomp)

1F2

1F3

1F4

1F5

1F6

1F7

3F6

3F7

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive/Head

Status

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive/Head

8.2 IDE SIGNALS

Looking at the IDE interface circuit in more detail, the

’LS244 provides buffering of the control and address lines.

There are four control signals, IDEHI, IDELO, HCS0, HCS1,

one status signal, IOCS16, and one data signal, IDED7, re-

quired by the IDE interface. The PC87311A/12 provides all

of these signals. They are summarized below.

Command

Alternate Status

Device Control

IDEHI enables the ’LS245 octal bus transceiver for the up-

per data lines (D15–D8) during 16-bit read and write opera-

tions at addresses 1F0–1F7. IDEHI will activate the ’LS245

only if the IOCS16 output from the hard drive is active. IDLO

enables the other ’LS245 octal bus transceiver for the lower

data lines (D7–D0) during all (1F0–1F7, 3F6 and 3F7)

Drive Address

(Note)

Not Used.

Data Bus TRI-STATE

Note: Data bus bit D7 is dedicated to the floppy disk controller at this ad-

dress. When reading this address the floppy disk controller disk change

status will be provided by bit D7. There is no write function at this address in

the IDE associated with this bit.

The equations shown in Figure 10-2 define the signals of

the PC87311A/12 IDE pins. A complete IDE interface using

these pins is shown in Figure 10-3.

61

9.0 Device Description

9.1 DC ELECTRICAL CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

Min

4.5

0

Typ Max Units

ABSOLUTE MAXIMUM RATINGS (Notes 2 and 3)

Supply Voltage (V

)

5.0

5.5

V

C

DD

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

a

Operating Temperature (T )

A

70

§

ESD Tolerance

e

C

R

100 pF

b

a

0.5V to 7.0V

Supply Voltage (V , V

)

ZAP

DD DDA

1500

V

1.5 kX (Note 1)

ZAP

Supply Differential ( V –V

l

)

0.6V

DD

DDA

l

b

a

Input Voltage (V )

I

0.5 V to 0.5V

DD

a

Output Voltage (V

)

O

0.5 V to 0.5V

DD

b

a

65 C to 165 C

Storage Temperature (T

)

§

1W

STG

Power Dissipation (P )

D

Lead Temperature (T )

L

(Soldering, 10 seconds)

a

260 C

§

e

1 MHz

CAPACITANCE T

25 C, f

§

A

Symbol

Parameter

Min

Typ

5

Max

7

Units

pF

C

IN

C

IN1

C

IO

C

O

Input Pin Capacitance

Clock Input Capacitance

I/O Pin Capacitance

8

10

12

8

pF

10

6

pF

Output Pin Capacitance

pF

DC CHARACTERISTICS Under Recommended Operating Conditions

Symbol

Parameter

Input High Voltage

Input Low Voltage

Conditions

Min

Typ

Max

Units

V

2.0

V

DD

V

IH

b

0.5

0.8

IL

e

I

V

Average Supply Current

V

0.5V

2.4V

CC

DD

IL

15

6

25

mA

IH

No Load

e

V

DD

Quiescent Supply Current

V

SS

CCSB

CCA

CCASB

IL

in Low Power Mode

V

DD

13

10

IH

No Load

e

V

DDA

Average Supply Current

V

0.5V

2.4V

IL

7

IH

No Load

e

V

DDA

Quiescent Supply Current

V

SS

IL

in Low Power Mode

V

DD

5

500

10

mA

IH

No Load

e

Input Leakage Current

(Note 4)

V

IN

DD

b

10

IN

SS

Note 1: Value based on test complying with NSC SOP5-028 human body model ESD testing using the ETS-910 tester.

Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 3: Unless otherwise specified all voltages are referenced to ground.

b

Note 4: During reset the MFM pin is rated for 10 mA, 150 mA due to an internal pull-up resistor and the RTS1, 2 ; SOUT1, 2; DTR1, 2; HCS0, 1; IDEHI; IDEHLO

b

are rated for 100 mA and 10 mA leakage due to internal pull-down resistors. During normal operation the BUSY, PE, SLCT pins are rated for 100 mA, 10 mA due

b

to internal pull-down resistors and the ACK and ERR pins are rated for 10 mA, 100 mA due to internal pull-up resistors.

62

9.0 Device Description (Continued)

DC CHARACTERISTICS Under Recommended Operating Conditions (Continued)

Symbol

MICROPROCESSOR, PARALLEL PORT, AND IDE INTERFACE PINS

e b

15 mA on:

Parameter

Conditions

Min

Typ

Max

Units

V

OH

Output High Voltage

I

OH

D0–D7, IDED7, IRQ3–IRQ7, DRQ

e b

2.4

V

I

6 mA on:

OH

PD0–PD7, DTR, RTS, SOUT,

MFM, DRATE, CSOUT,

IDEHI, IDELO, HCS

e

D0–D7, IDED7, IRQ3–IRQ7, DRQ

V

OL

Output Low Voltage

I

24 mA on:

OL

e

I

16 mA on: PD0–PD7

12 mA on:

OL

0.4

V

DTR, RTS, SOUT, HCS,

AFD, INIT, SLIN, STB

(Note 5)

e

I

6 mA on:

OL

MFM, DRATE, CSOUT,

IDEHI, IDELO

e

I

Input TRI-STATE Leakage Current

(D7–D0, IRQ3–IRQ7, DRQ)

V

10

OZ

IN

DD

mA

b

10

IN

SS

DISK INTERFACE PINS

V

Input Hysteresis

250

mV

V

H

e b

Output High Voltage (Note 6)

Output Low Voltage

I

4 mA

2.4

OH

OL

OH

e

40 mA

0.4

10

V

OL

e

I

Output High Leakage Current (Note 6)

V

LKG

IN

DD

mA

b

10

IN

SS

OSCILLATOR PIN (XTAL1/CLK)

V

XTAL1 Input High Voltage

XTAL1 Input Low Voltage

XTAL1 Leakage

2.0

V

IH

0.4

IL

e

I

V

400

XLKG

IN

DD

mA

b

400

IN

SS

Note 5: The printer control pinsÐAFD, INIT, SLIN, STB are open drain pins. Use a 4.7 kX pull-up resistor.

Note 6: V for the disk interface pins is valid for CMOS buffered outputs only.

OH

63

9.0 Device Description (Continued)

9.2 AC ELECTRICAL CHARACTERISTICS

AC TESTING INPUT, OUTPUT WAVEFORM

e

9.2.1 AC Test Conditions T

e

g

0 C to 70 C,

§ §

A

e

V

5.0V

10%

DD

TL/F/11362–16

LOAD CIRCUIT (Notes 1, 2, 3)

TL/F/11362–15

e

Note 1: C

100 pF, includes jig and scope capacitance.

L

e

Note 2: S1

Open for push-pull outputs. S1

V

for high impedance to

e

DD

active low and active low to high impedance measurements. S1

high impedance to active high and active high to high impedance measure-

GND for

e

ments. R

1.0 kX for mP interface pins.

L

e

150X.

Note 3: For the FDC Open Drive Interface Pins S1

V

and R

DD

L

9.2.2 Clock Timing

Symbol

Parameter

Min

16

Max

Units

ns

t

Clock High Pulse Width

Clock Low Pulse Width

Clock Period

CH

16

ns

CL

40

43

ns

CP

Internal Clock Period (Table 9-1)

Data Rate Period (Table 9-1)

ICP

DRP

TABLE 9-1. Nominal t , t

ICP DRP

Values

MFM Data Rate

1 Mb/s

t

Value

Units

DRP

ICP

c

1000

2000

3333

4000

3

5

6

t

CP

t

CP

t

CP

t

CP

125

208

250

ns

500 kb/s

300 kb/s

250 kb/s

TL/F/11362–17

FIGURE 9-1. Clock Timing

64

9.0 Device Description (Continued)

9.2.3 Microprocessor Interface Timing

Symbol

Parameter

Valid Address to Read Active

Valid Address to Write Active

Data Hold

Min

18

0

Max

Units

ns

t

AR

AW

DH

Data Setup

18

13

10

0

DS

Read to Floating Data Bus

Port Setup

25

HZ

PS

Address Hold from Inactive Read

Read Cycle Update

RA

45

60

10

RCU

RD

Read Strobe Width

Read Data Hold

RDH

RI

Read Strobe to Clear IRQ6

Active Read to Valid Data

Address Hold from Inactive Write

Write Cycle Update

55

RVD

WA

WCU

WI

0

45

Write Strobe to Clear IRQ6

Write Data to Port Update

Write Strobe Width

55

40

WO

WR

60

e

a

t

RD RC

RC

Read Cycle

Write Cycle

t

123

AR

a

t

WC

t

AW

WR

TL/F/11362–18

FIGURE 9-2. Microprocessor Read Timing

65

9.0 Device Description (Continued)

TL/F/11362–19

FIGURE 9-3. Microprocessor Write Timing

9.2.4 Baudout Timing

Symbol

Parameter

Conditions

Min

Max

65535

56

Units

ns

N

Baud Divisor

1

e

t

Baud Output Positive Edge Delay

Baud Output Negative Edge Delay

CLK

24 MHz/2, 100 pF Load

ns

BHD

BLD

56

ns

TL/F/11362–20

FIGURE 9-4. Baudout Timing

66

9.0 Device Description (Continued)

9.2.5 Transmitter Timing

Symbol

Parameter

Min

Max

55

24

8

Units

ns

t

Delay from WR (WR THR) to Reset IRQ

Delay from RD (RD IIR) to Reset IRQ (THRE)

Delay from Initial IRQ Reset to Transmit Start

Delay from Initial Write to IRQ

HR

ns

IR

8

BAUDOUT Cycles

IRS

SI

16

Delay from Start Bit to IRQ (THRE)

STI

TL/F/11362–21

Note 1: See Write cycle timing, Figure 9-3.

Note 2: See Read cycle timing, Figure 9-2.

FIGURE 9-5. Transmitter Timing

67

9.0 Device Description (Continued)

9.2.6 Receiver Timing

Symbol

Parameter

Conditions

Min

Max

78

Units

ns

t

Delay from Active Edge of RD to Reset IRQ

Delay from Inactive Edge of RD (RD LSR) to Reset IRQ

Delay from RCLK to Sample Time

RAI

40

ns

RINT

SCD

SINT

(Note 1)

41

ns

Delay from Stop Bit to Set Interrupt

BAUDOUT

Cycles

2

Note 1: This is an internal timing and is therefore not tested.

TL/F/11362–22

FIGURE 9-6a. Receiver Timing

TL/F/11362–23

e

8 RCLKs.

SINT

Note 2: If SCR0

1, then t

3 RCLKs. For a Timeout interrupt, t

SINT

FIGURE 9-6b. PC87312 FIFO Mode Receiver Timing

68

9.0 Device Description (Continued)

TL/F/11362–24

e

8 RCLKs.

SINT

Note 3: If SCR0

1, then t

3 RCLKs. For a Timeout interrupt, t

SINT

FIGURE 9-6c. PC87312 Timeout Receiver Timing

9.2.7 MODEM Control Timing

Symbol

Parameter

Conditions

Min

Max

40

Units

ns

t

Delay from WR (WR MCR) to Output

Delay to Reset IRQ from RD (RD MSR)

Delay to Set IRQ from MODEM Input

MDO

RIM

SIM

78

ns

40

ns

TL/F/11362–25

Note 1: See Write cycle timing, Figure 9-3.

Note 2: See Read cycle timing, Figure 9-2.

FIGURE 9-7. MODEM Control Timing

69

9.0 Device Description (Continued)

9.2.8 DMA Timing

Symbol

Parameter

DACK Inactive Pulse Width

Min

25

Max

65

Units

ns

t

KI

DACK Active Pulse Width

65

ns

KK

KQ

QK

QP

QQ

QR

QW

DACK Active Edge to DRQ Inactive

DRQ to DACK Active Edge

ns

10

ns

c

DRQ Period (except Non-Burst DMA)

DRQ Inactive Non-Burst Pulse Width

DRQ to RD, WR Active

8

t

ms

ns

DRP

300

15

400

ns

DRQ to End of RD, WR (Note 2)

(DRQ Service Time)

c

b

c

(8

t

16

t

)

ms

DRP

ICP

t

QT

DRQ to TC Active (Note 2)

(DRQ Service Time)

DRP

ICP

t

RD, WR Active Edge to DRQ Inactive (Note 1)

TC Active Edge to DRQ Inactive

TC Active Pulse Width

65

75

ns

RQ

TQ

TT

50

Note 1: The active edge of RD or WR is recognized only when DACK is active.

e

c

8 t

DRP

Note 2: Values shown are with the FIFO disabled, or with FIFO enabled and THRESH

0. For non-zero values of THRESH, add (THRESH

) to the

values shown.

TL/F/11362–26

FIGURE 9-8. DMA Timing

70

9.0 Device Description (Continued)

9.2.9 Reset Timing

Symbol

Parameter

Min

Max

Units

ns

t

Reset Width (Note 1)

Reset to Control Inactive

100

RW

300

ns

RC

Note 1: The software reset pulse width is 100 ns. The hardware reset pulse width with an external 10 kX pull-up or pull-down resistor on the MFM pin is 100 ns.

When using the internal pull-up resistor on the MFM pin, the hardware reset pulse width is 170 ns (assumes no pF load).

TL/F/11362–27

Note 2: DRQ and IRQ6 will be TRI-STATE after time t

when in the AT or Model 30 mode.

RC

FIGURE 9-9. Reset Timing

9.2.10 Write Data Timing

Symbol

Parameter

Min

750

Max

Units

ms

t

HDSEL Hold from WGATE Inactive

HDSEL Setup to WGATE Active

Write Data Pulse Width

HDH

HDS

WDW

100

ms

Table 9-2

ns

TABLE 9-2. Minimum t

WDW

Values

Data Rate

1 Mb/s

t

Value

Units

ns

DRP

WDW

c

1000

2000

3333

4000

2

t

250

ICP

500 kb/s

300 kb/s

250 kb/s

250

375

500

ns

TL/F/11362–28

FIGURE 9-10. Write Data Timing

71

9.0 Device Description (Continued)

9.2.11 Drive Control Timing

Symbol

Parameter

DR0–DR3, MTR0–MTR3 from End of WR

DIR Setup to STEP Active

Min

Max

Units

ns

t

100

DRV

DST

IW

6

ms

Index Pulse Width

100

ns

DIR Hold from STEP Inactive

STEP Active High Pulse Width

STEP Rate Time (see Table 4-13)

t

ms

STD

STP

STR

8

1

ms

TL/F/11362–29

FIGURE 9-11. Drive Control Timing

9.2.12 Read Data Timing

Symbol

Parameter

Min

Max

Unit

t

Read Data Pulse Width

50

ns

RDW

TL/F/11362–30

FIGURE 9-12. Read Data Timing

9.2.13 IDE Timing

Symbol

Parameter

Min

Max

Units

ns

t

Delay from Address to Disable Strobe

Delay from Address to Enable Strobe

25

AD

ns

AE

TL/F/11362–31

FIGURE 9-13. IDE Timing

72

9.0 Device Description (Continued)

9.2.14 Parallel Port Timing

Symbol

Parameter

Port Data Hold

Port Data Setup

Port Interrupt

Strobe Width

Conditions

(Note 1)

Typ

500

Max

Units

ns

t

PDH

PDS

PI

(Note 1)

ns

33

ns

(Note 1)

500

ns

SW

Note 1: These times are system dependent and are therefore not tested.

TL/F/11362–32

FIGURE 9-14. Parallel Port Interrupt Timing (Compatible Mode)

TL/F/11362–33

FIGURE 9-15. Parallel Port Interrupt Timing (Extended Mode)

TL/F/11362–34

FIGURE 9-16. Typical Parallel Port Data Exchange

73

10.0 Reference

10.1 MNEMONIC DEFINITIONS FOR FDC COMMANDS

LOW PWR Low Power control bits used in the Mode com-

mand.

Symbol

Description

MFM

Modified Frequency Modulation control bit

used in the Read, Write, Format, Scan and

Verify commands. Selects MFM or FM data

encoding.

BFR

Buffer enable bit used in the Mode command.

Enabled open-collector output buffers.

BST

DC0

Burst Mode disable control bit used in Mode

command. Selects the Non-Burst FIFO mode if

the FIFO is enabled.

MFT

Motor Off Time programmed in the Specify

command.

Drive Configuration 0–3. Used to set DC1a

drive to conventional or perdendicular DC2

mode. Used in Perpendicular Mode DC3 com-

mand.

MNT

MT

Motor On Time programmed in the Specify

command.

Multi-Track enable bit used in the Read, Write,

Scan and Verify commands.

DENSEL

DIR

Density Select control bits used in the Mode

command.

OW

Overwrite control bit used in the Perpendicular

Mode command.

Direction control bit used in Relative Seek

command to indicate step in or out.

POLL

PRETRK

PTR

Enable Drive Polling bit used in the Configure

command.

DMA

DR0

DTL

DMA mode enable bit used in the Specify com-

mand.

Precompensation Track Number used in the

Configure command.

Drive Select 0–1 bits used in most commands.

Selects the logical drive.

Present Track Register. Contains the internal

track number for one of the four logical disk

drives.

Data Length parameter used in the Read,

Write, Scan and Verify commands.

PU

Pump diagnostic enable bit used in the Mode

command.

EC

Enable Count control bit used in the Verify

command. When this bit is 1, the DTL parame-

ter becomes SC (Sector Count).

R255

Recalibrate control bit used in Mode com-

mand. Sets maximum recalibrate step pulses

to 255.

EIS

Enable Implied Seeks. Used in the Configure

command.

RG

RTN

SC

Read Gate diagnostic enable bit used in the

Mode command.

EOT

ETR

FIFO

End of Track parameter set in the Read, Write,

Scan, and Verify commands.

Relative Track Number used in the Relative

Seek command.

Extended Track Range used with the Seek

command.

Sector Count control bit used in the Verify

command.

First-In First-Out buffer. Also a control bit used

in the Configure command to enable or disable

the FIFO.

SK

Skip control bit used in read and scan opera-

tions.

FRD

FWR

GAP

HD

FIFO Read disable control bit used in the

Mode command.

SRT

Step Rate Time programmed in the Specify

command. Determines the time between step

pulses for seek and recalibrates.

FIFO Write disable control bit used in the

Mode command.

ST0

Status Register 0–3. Contains status ST1 in-

formation about the execution of a ST2 com-

mand. Read in the Result Phase of ST3 some

commands.

GAP2 control bit used in the Perpendicular

Mode command.

Head Select control bit used in most com-

mands. Selects Head 0 or 1 of the disk.

THRESH

TMR

FIFO threshold parameter used in the Config-

ure command.

IAF

Index Address Field control bit used in the

Mode command. Enables the ISO Format dur-

ing the Format command.

Timer control bit used in the Mode command.

Affects the timers set in the Specify command.

IPS

Implied Seek enable bit used in the Mode,

Read, Write, and Scan commands.

WG

Write Gate control bit used in the Perpendicu-

lar Mode command.

LOCK

Lock enable bit in the Lock command. Used to

make certain parameters unaffected by a soft-

ware reset.

WLD

Wildcard bit in the Mode command used to en-

able or disable the wildcard byte (FF) during

Scan commands.

74

10.0 Reference (Continued)

10.2 EXAMPLE FOUR DRIVE CIRCUIT USING THE PC87311A/12

Hex Buffers

e

open collector

I

40 mA

CC

TL/F/11362–35

FIGURE 10-1. PC87311A/12 Four Floppy Drive Circuit

TABLE 10-1. PC87311A/12 Four Floppy Drive Encoding

MTR0 DR1 DR0

Result

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DRV0 and MTR0 Active

DRV1 and MTR1 Active

DRV2 and MTR2 Active

DRV3 and MTR3 Active

DRV0 Active and MTR0 Inactive

DRV1 Active and MTR1 Inactive

DRV2 Active and MTR2 Inactive

DRV3 Active and MTR3 Inactive

The equations shown inFigure 10-2 define the signals of the PC87311A/12 IDE pins for primary IDE addresses. A complete IDE

interface using these pins is shown in Figure 10-3.

Equations

Comments

Active at 1F0–1F7

e

HCS0

HCS1

IDELO

IDEHI

A9*A8*A7*A6*A5*A4*A3*AEN

A9*A8*A7*A6*A5*A4*A3*A2*A1*AEN

Active at 3F6, 3F7

e

a

a À

a

Ó

]

RD

[

]

[

HCS0*(RD

WR)

HCS1 * (WR*A0)

Write 1F0–1F7, 3F6; Read 1F0–1F7, 3F6, 3F7

Read or Write 1F0–1F7 in AT Mode

Sources D7 during Read 1F0–1F7 and 3F6

D7 during Write 1F0–1F7 and 3F6

e

a

WR)*SELAT

IOCS16*HCS0*(RD

e

a

[

]

[

]

(HCS1*A0)*RD

IDED7 (read)

IDED7 (write)

HCS0*RD

a

[

]

WR* HCS0

(HCS1*A0)

FIGURE 10-2. IDE Interface Signal Equations

75

10.0 Reference (Continued)

TL/F/11362–36

FIGURE 10-3. PC87311A/12 Adapter Card Schematic

76

10.0 Reference (Continued)

TL/F/11362–37

FIGURE 10-3. PC87311A/12 Adapter Card Schematic (Continued)

77

Physical Dimensions inches (millimeters)

Plastic Quad Flatpak, EIAJ

Order Number PC87311AVF or PC87312VF

NS Package Number VLJ100A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and whose

failure to perform, when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

National Semiconductor

Corporation

2900 Semiconductor Drive

P.O. Box 58090

Santa Clara, CA 95052-8090

Tel: 1(800) 272-9959

TWX: (910) 339-9240

National Semiconductor

GmbH

Livry-Gargan-Str. 10

D-82256 Furstenfeldbruck

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Tel: (81-41) 35-0

Telex: 527649

Fax: (81-41) 35-1

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Do Brazil Ltda.

Rue Deputado Lacorda Franco

120-3A

Sao Paulo-SP

Brazil 05418-000

Tel: (55-11) 212-5066

Telex: 391-1131931 NSBR BR

Fax: (55-11) 212-1181

National Semiconductor

(Australia) Pty, Ltd.

Building 16

Business Park Drive

Monash Business Park

Nottinghill, Melbourne

Victoria 3168 Australia

Tel: (3) 558-9999

Japan Ltd.

Hong Kong Ltd.

Sumitomo Chemical

Engineering Center

Bldg. 7F

13th Floor, Straight Block,

Ocean Centre, 5 Canton Rd.

Tsimshatsui, Kowloon

1-7-1, Nakase, Mihama-Ku Hong Kong

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Tel: (852) 2737-1600

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Ciba Prefecture 261

Tel: (043) 299-2300

Fax: (043) 299-2500

Fax: (3) 558-9998

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


型号：	PC87312
厂家：	ETC
描述：	(SuperI/O II/III) Floppy Disk Controller with Dual UARTs, Parallel Port, and IDE Interface （ SuperI / O II / III ）软盘控制器，双UART ，并行端口，以及IDE接口控制器
文件：	总78页 (文件大小：877K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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