PC87332_技术文档

PRELIMINARY

May 1995

PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V)

(SuperI/O^TMIII Premium Green)

Floppy Disk Controller, Dual UARTs, IEEE1284

Parallel Port, and IDE Interface

General Description

The PC87332VLJ and PC87332VLJ-5 are single chip solu-

Features

Y

Floppy Disk Controller:

Ð Software compatible with the DP8473, the 765A and

the N82077

Ð 16-byte FIFO (disabled by default)

tions for most commonly used I/O peripherals in ISA, EISA

and MicroChannel based computers. It incorporates a

Floppy Disk Controller (FDC), two full featured UARTs, an

IEEE 1284 compatible parallel port and all the necessary

É

Ð Burst and Non-Burst modes

Ð Perpendicular Recording drive support

Ð New high-performance internal digital data separator

(no external filter components required)

Ð Low-power CMOS with enhanced power-down mode

Ð Automatic media-sense support

control logic for an IDE interface. Standard PC-AT address

É

decoding for all the peripherals and a set of configuration

registers are also implemented in this highly integrated

member of the SuperI/O family. Advanced power manage-

ment features and mixed voltage operation in the VLJ ver-

sion make the PC87332 chips an ideal for low-power and/or

portable personal computer applications.

Ð Supports fast 2 Mbps and standard 1 Mbps/

500 kbps/250 kbps tape drives

Y

Bidirectional Parallel Port:

The PC87332 FDC uses a high performance digital data

separator eliminating the need for any external filter compo-

nents. It is fully compatible with the PC8477 and incorpo-

rates a superset of DP8473, NEC mPD765 and N82077 flop-

py disk controller functions. All popular 5.25 and 3.5 flop-

Ð Enhanced Parallel Port (EPP) compatible

Ð Extended Capabilities Port (ECP) compatible, includ-

ing level 2 support

Ð Bidirectional under either software or hardware

control

Ð Ability to multiplex FDC signals on parallel port pins

allows use of an external Floppy Disk Drive (FDD)

Ð Includes protection circuit to prevent damage to the

parallel port when a connected printer is powered up

×

py drives, including the 2.88 MB 3.5 floppy drive, are sup-

×

ported. In addition, automatic media sense and 2 Mbps tape

drive support are provided by the FDC.

The two UARTs are fully NS16450 and NS16550 compati-

(Continued)

ble. Both ports support MIDI baud rates.

or is operated at a higher voltage

(Continued)

Block Diagram

TL/C/11930–1

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

SuperI/O^TMis a trademark of National Semiconductor Corporation.

IBMÉ, MicroChannelÉ, PC-ATÉ and PS/2É are registered trademarks of International Business Machines Corporation.

C

1995 National Semiconductor Corporation

TL/C/11930

RRD-B30M65/Printed in U. S. A.

General Description (Continued)

Features (Continued)

UARTs:

Ð Software compatible with the PC16550A and

PC16450

Ð MIDI baud rate support

Y

The parallel port is fully IEEE 1284 level 2 compatible. The

SPP (Standard Parallel Port) is fully compatible with ISA,

EISA and MicroChannel parallel ports. In addition to the

SPP, EPP (Enhanced Parallel Port) and ECP (Extended Ca-

pabilities Port) modes are supported by the parallel port.

Y

IDE Control Logic:

Ð All IDE control signals. Only external signal buffers

required to implement full IDE interface

All IDE control signals are provided by the PC87332. Only

external signal buffers are required to implement a complete

IDE interface.

Y

Address Decoder:

Ð Provides selection of all primary and secondary ISA

addresses including COM1–4 and LPTA–C

A set of eight configuration registers are provided to control

various functions of the PC87332. These registers are ac-

cessed using two 8-bit wide index and data registers. The

ISA I/O address of the register pair can be relocated using a

power-up strapping option.

Y

Enhanced Power Management:

Ð Special configuration registers for power-down

Ð Enhanced programmable power-down FDC

command

When idle, advanced power management features allows

the PC87332 to enter extremely low power modes under

hardware or software control. The PC87332VLJ can oper-

ate from a 5V or a 3.3V power supply. An unique I/O cell

structure allows the PC87332VLJ to interface directly with

5V external components while operating from a 3.3V power

supply.

Ð Auto power-down and wake-up modes

Ð 3 special pins for power management

Ð Typical current consumption during power-down is

less than 10 mA

Ð Reduced pin leakage current

Y

Mixed Voltage Support:

Ð Supports standard 5V operation

Ð Supports 3.3V operation

Ð Supports mixed internal 3.3V operation with 3.3V/5V

external configuration

Y

General:

Ð 100% compatible with ISA, EISA, and MicroChannel

architectures

Ð 100-Pin PQFP package is pin compatible with the

PC87312 and PC87322VF

2

Table of Contents

1.0 PIN DESCRIPTION

4.0 FDC COMMAND SET DESCRIPTION

4.1 Command Description

4.1.1 Configure Command

4.1.2 Dumpreg Command

4.1.3 Format Track Command

4.1.4 Invalid Command

2.0 CONFIGURATION REGISTERS

2.1 Overview

2.2 Software Configuration

2.3 Hardware Configuration

2.4 Index and Data Registers

4.1.5 Lock Command

2.5 Base Configuration Registers

2.5.1 Function Enable Register (FER)

2.5.2 Function Address Register (FAR)

2.5.3 Power and Test Register (PTR)

2.5.4 Function Control Register (FCR)

2.5.5 Printer Control Register (PCR)

2.5.6 Power Management Control Register (PMC)

4.1.6 Mode Command

4.1.7 NSC Command

4.1.8 Perpendicular Mode Command

4.1.9 Read Data Command

4.1.10 Read Deleted Data Command

4.1.11 Read ID Command

4.1.12 Read A Track Command

4.1.13 Recalibrate Command

4.1.14 Relative Seek Command

4.1.15 Scan Commands

2.5.7 Tape, UARTs and Parallel Port

Configuration Register (TUP)

2.5.8 SIO Identification Register (SID)

2.6 Power-Down Options

4.1.16 Seek Command

2.6.1 Recommended Power-Down

MethodsÐGroup 1

4.1.17 Sense Drive Status Command

4.1.18 Sense Interrupt Command

4.1.19 Set Track Command

4.1.20 Specify Command

2.6.2 Recommended Power-Down

MethodsÐGroup 2

2.7 Power-Up Procedure and Considerations

2.7.1 Crystal Stabilization

4.1.21 Verify Command

4.1.22 Version Command

2.7.2 UART Power-Up

4.1.23 Write Data Command

4.1.24 Write Deleted Data

2.7.3 FDC Power-Up

3.0 FDC REGISTER DESCRIPTION

4.2 Command Set Summary

3.1 FDC Control Registers

4.3 Mnemonic Definitons for FDC Commands

3.1.1 Status Registger A (SRA) Read Only

3.1.2 Status Register B (SRB) Read Only

3.1.3 Digital Output Register (DOR) Read/Write

3.1.4 Tape Drive Register (TDR) Read/Write

3.1.5 Main Status Register (MSR) Read Only

3.1.6 Data Rate Select Register (DSR) Write Only

3.1.7 Data Register (FIFO) Read/Write

3.1.8 Digital Input Register (DIR) Read Only

3.1.9 Configuration Control Register (CCR) Write Only

3.2 Result Phase Status Registers

5.0 FDC FUNCTIONAL DESCRIPTION

5.1 Microprocessor Interface

5.2 Modes of Operation

5.3 Controller Phases

5.3.1 Command Phase

5.3.2 Execution Phase

5.3.2.1 DMA ModeÐFIFO Disabled

5.3.2.2 DMA ModeÐFIFO Enabled

5.3.2.3 Interrupt ModeÐFIFO Disabled

5.3.2.4 Interrupt ModeÐFIFO Enabled

5.3.2.5 Software Polling

3.2.1 Status Register 0 (ST0)

3.2.2 Status Register 1 (ST1)

3.2.3 Status Register 2 (ST2)

5.3.3 Result Phase

3.2.4 Status Register 3 (ST3)

5.3.4 Idle Phase

5.3.5 Drive Polling Phase

5.4 Data Separator

5.5 Crystal Oscillator

5.6 Perpendicular Recording Mode

5.7 Data Rate Selection

5.8 Write Precompensation

5.9 FDC Low Power Mode Logic

5.10 Reset Operation

3

Table of Contents (Continued)

6.0 SERIAL PORTS

8.0 INTEGRATED DEVICE ELECTRONICS

INTERFACE (IDE)

6.1 Serial Port Registers

8.1 Introduction

8.2 IDE Signals

6.2 Line Control Register (LCR)

6.3 Programmable Baud Rate Generator

6.4 Line Status Register (LSR)

6.5 FIFO Control Register

9.0 ELECTRICAL CHARACTERISTICS

9.1 DC Electrical Characteristics

9.2 DC Electrical Characteristics

9.3 AC Electrical Characteristics

9.3.1 AC Test Conditions

9.3.2 Clock Timing

6.6 Interrupt Identification Register (IIR)

6.7 Interrupt Enable Register (IER)

6.8 MODEM Control Register (MCR)

6.9 MODEM Status Register (MSR)

6.10 Scratchpad Register (SCR)

9.3.3 Microprocessor Interface Timing

9.3.4 Baud Out Timing

7.0 PARALLEL PORT

9.3.5 Transmitter Timing

9.3.6 Receiver Timing

7.1 Introduction

7.2 Data Register (DTR)

7.3 Status Register (STR)

7.4 Control Register (CTR)

7.5 Enhanced Parallel Port Operation

7.6 Extended Capabilities Parallel Port (ECP)

7.6.1 Introduction

9.3.7 MODEM Control Timing

9.3.8 DMA Timing

9.3.9 Reset Timing

9.3.10 Write Data Timing

9.3.11 Drive Control Timing

9.3.12 Read Data Timing

7.6.2 Software Operation

9.3.13 IDE Timing

7.7 Register Definitions

9.3.14 Parallel Port Timing

9.3.15 Enhanced Parallel Port Timing

9.3.16 Extended Capabilities Port Timing

7.8 Software Controlled Data Transfer

(Modes 000 and 001)

7.9 Automatic Data Transfer (Modes 010 and 011)

e

7.9.1 Forward Direction (Bit 5 of DCR 0)

7.9.2 ECP (Forward) Write Cycle

7.9.3 Backward Direction (bit 5 of DCR is 1)

7.9.4 ECP (Backward) Read Cycle

7.10 FIFO Test Access (Mode 110)

7.11 Configuration Registers Access (Mode 111)

7.12 Interrupt Generation

4

List of Figures

FIGURE 2-1

FIGURE 2-2

FIGURE 3-1

FIGURE 4-1

FIGURE 4-2

FIGURE 5-1

FIGURE 5-2

FIGURE 5-3

FIGURE 6-1

FIGURE 6-2

FIGURE 7-1

FIGURE 7-2

FIGURE 7-3

FIGURE 7-4

FIGURE 7-5

FIGURE 7-6

FIGURE 7-7

FIGURE 8-1

FIGURE 9-1

FIGURE 9-2

FIGURE 9-3

FIGURE 9-4

FIGURE 9-5

FIGURE 9-6a

FIGURE 9-6b

FIGURE 9-6c

FIGURE 9-6d

FIGURE 9-7

FIGURE 9-8

FIGURE 9-9

FIGURE 9-10

FIGURE 9-11

FIGURE 9-12

FIGURE 9-13

FIGURE 9-14

FIGURE 9-15

FIGURE 9-16

FIGURE 9-17

FIGURE 9-18

FIGURE 9-19

PC87332VLJ/PC87332VLJ-5 Configuration Registers

PC87332 Four Floppy Drive Circuit Example

FDC Functional Block Diagram

FDC Command Structure

IBM, Perpendicular, and ISO Formats Supported by the Format Command

PC87332 Dynamic Window Margin Performance

Read Data AlgorithmÐState Diagram

Perpendicular Recording Drive R/W Head and Pre-Erase Head

PC87332 Composite Serial Data

Reciever FIFO Trigger Level

EPP 1.7 Address Write

EPP 1.7 Address Read

EPP Write with ZWS

EPP 1.9 Address Write

EPP 1.9 Address Read

ECP (Forward) Write Cycle

ECP (Backward) Read Cycle

IDE Interface Signal Equations (Non-DMA)

Clock Timing

Microprocessor Read Timing

Microprocessor Write Timing

Baud Out Timing

Transmitter Timing

Sample Clock Timing

Receiver Timing

Mode Receiver Timing

Timeout Receiver Timing

MODEM Control Timing

DMA Timing

Reset Timing

Write Data Timing

Drive Control Timing

Read Data Timing

IDE Timing

Compatible Mode Parallel Port Interrupt Timing

Extended Mode Parallel Port Interrupt Timing

Typical Parallel Port Data Exchange

Enhanced Parallel Port Timing

ECP Parallel Port Forward Timing Diagram

ECP Parallel Port Backward Timing Diagram

5

List of Tables

TABLE 1-1

TABLE 2-1

TABLE 2-2

TABLE 2-3

TABLE 2-4

TABLE 2-5

TABLE 2-6

TABLE 2-7

TABLE 2-8

TABLE 2-9

Pin Descriptions (Alphabetical)

Default Configurations Controlled by Hardware

Index and Data Register Optional Locations

Encoded Drive and Motor Pin Information

Primary and Secondary Drive Address Selection

Parallel Port Addresses

COM Port Selection for UART1

COM Port Selection for UART2

Address Selection for COM3 and COM4

Logical Drive Exchange

TABLE 2-10 Parallel Port Mode

TABLE 2-11 Methods to Achieve Group 1 Power-Down Modes

TABLE 3-1

TABLE 3-2

TABLE 3-3

TABLE 3-4

TABLE 3-5

TABLE 3-6

TABLE 3-7

TABLE 4-1

TABLE 4-2

TABLE 4-3

TABLE 4-4

TABLE 4-5

TABLE 4-6

TABLE 4-7

TABLE 4-8

TABLE 4-9

Register Description and Addresses

Drive Enable Values

Media ID Bit Functions

Tape Drive Assignment Values

Write Precompensation Delays

Default Precompensation Delays

Data Rate Select Encoding

Typical Format Gap Length Values

Typical Format GAP3 Length Values Based on PC Compatible Diskette Media

DENSEL Default Encoding

DENSEL Encoding

Head Settle Time Calculation

Effect of Drive Mode and Data Rate on Format and Write Commands

Effect of GAP and WG on Format and Write Commands

Sector Size Selection

SK Effect on the Read Data Command

TABLE 4-10 Result Phase Termination Values with No Error

TABLE 4-11 SK Effect on the Read Deleted Data Command

TABLE 4-12 Maximum Recalibrate Step Pulses Based on R255 and ETR

TABLE 4-13 Scan Command Termination Values

TABLE 4-14 Status Register 0 Termination Codes

TABLE 4-15 Set Track Register Address

TABLE 4-16 Step Rate Time (SRT) Values

TABLE 4-17 Motor Off Time (MFT) Values

TABLE 4-18 Motor On Time (MNT) Values

TABLE 4-19 Verify Command Result Phase

e

0)

TABLE 6-1

TABLE 6-2

TABLE 6-3

TABLE 6-4

TABLE 6-5

TABLE 7-1

TABLE 7-2

TABLE 7-3

TABLE 7-4

TABLE 7-5

TABLE 7-6

TABLE 7-7

TABLE 8-1

TABLE 9-1

TABLE 9-2

PC87332 UART Register Addresses (AEN

PC87332 Register Summary for an Individual UART Channel

PC87332 UART Reset Configuration

PC87332 UART Divisors, Baud Rates and Clock Frequencies

PC87332 Interrupt Control Functions

Parallel Interface Register Addresses

Standard Parallel Port Modes Selection

SPP Data Register Read and Write Modes

Parallel Port Reset States

EPP Registers

Parallel Port Pin Out

ECP Registers Summary

IDE Registers and Their ISA Addresses

Nominal t , t

ICP DRP

Values

Minimum t Values

WDW

6

Basic Configuration

TL/C/11930–2

7

1.0 Pin Description

Connection Diagrams

Plastic Quad Flatpak (PQFP), EIAJ

TL/C/11930–3

Order Number PC87332VLJ or PC87332VLJ-5

See NS Package Number VLJ100A

8

1.0 Pin Description (Continued)

TABLE 1-1. Pin Descriptions (Alphabetical)

Symbol

I/O

Function

A10–A0

21–31

I

Address. These microprocessor address lines determine which internal register is accessed. A0–

A10 are don’t cares during a DMA transfer.

ACK

AFD

85

78

I

Acknowledge. This input is pulsed low by a connected printer to indicate that it has received data

from the parallel port. This pin has a nominal 25 kX pull-up resistor attached to it. (This pin is

shared with DR1. See Table 7-5 for further information.)

I/O Automatic Feed XT. When this signal is low the connected printer should automatically line feed

after each line is printed. This pin is in a TRI-STATE condition 10 ns after a 0 is loaded into the

É

corresponding Control Register bit. The system should pull this pin high using a 4.7 kX resistor.

(See DSTRB and Table 7-5 for further information.)

AEN

20

81

I

O

I

Address Enable. This input disables function selection via A10–A0 when it is high. Access during

DMA transfer is NOT affected by this pin.

ASTRB

BADDR0,1

Address Strobe. This signal is used in EPP mode as an address strobe. It is active low. (See

SLIN and Table 7-5 for further information.)

55, 58

Base Address. These bits determine one of four base addresses from which the Index and Data

Registers are offset (See Table 2-2). An internal pull-down resistor of 30 kX is present on this pin.

Use a 10 kX resistor to pull this pin to V

.

CC

BOUT1,2

73, 65

O

BAUD Output. This multi-function pin provides the associated serial channel Baud Rate generator

output signal, when test mode is selected in the Power and Test Configuration Register and the

DLAB bit (LCR7) is set. After Master Reset this pin provides the SOUT function. (See SOUT and

CFG0–4 for further information.)

BUSY

84

I

Busy. This pin is set high by the printer when it cannot accept another character. It has a nominal

25 kX pull-down resistor attached to it. (See WAIT and Table 7-5 for further information.)

CFG0–4

65, 66, 71

73, 74

Configuration on Power-up. These CMOS inputs select 1 of 32 default configurations in which

the PC87334VLJ/PC87334VJG powers-up (See Table 2-1). An internal pull-down resistor of 30

kX is present on each pin. Use a 10 kX resistor to pull these pins to V

.

CC

CLK48

CTS1,2

57

I

Clock 48. This pin is the CLK48 reset strap option. During reset the value of this pin is latched into

bit 0 of TUP (CLK48 bit). A 30 kX internal pull-down resistor is present on this pin. Use a 10 kX

resistor to pull it high during reset.

72, 64

Clear to Send. When low this indicates that the MODEM or data set is ready to exchange data.

The CTS signal is a MODEM status input whose condition the CPU can test by reading bit 4 (CTS)

of the MODEM Status Register (MSR) for the appropriate serial channel. Bit 4 is the complement

of the CTS signal. Bit 0 (DCTS) of the MSR indicates whether the CTS input has changed state

since the previous reading of the MSR. CTS has no effect on the transmitter.

Note: Whenever the DCTS bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled.

D7–D0

10–17

I/O Data. Bi-directional data lines to the microprocessor. D0 is the LSB and D7 is the MSB. These

signals all have 24 mA (sink) buffered outputs.

9

1.0 Pin Description (Continued)

Symbol

I/O

Function

DCD1,2

77, 69

I

Data Carrier Detect. When low this signal indicates that the MODEM or data set has detected the

data carrier.The DCD signal is a MODEM status input whose condition the CPU can test by reading bit

7 (DCD) of the MODEM Status Register (MSR) for the appropriate serial channel. Bit 7 is the

complement of the DCD signal. Bit 3 (DDCD) of the MSR indicates whether the DCD input has

changed state since the previous reading of the MSR.

Note: Whenever the DDCD bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.

DENSEL

Normal

Mode

48

O

Density Select. Indicates that a high FDC density data rate (500 kbps, 1 Mbps or 2 Mbps) or a low

density data rate (250 kbps or 300 kbps) is selected. DENSEL is active high for high density (5.25

×

drives) when IDENT is high, and active low for high density (3.5 drives) when IDENT is low. DENSEL

×

is also programmable via the Mode command (see Section 4.2.6).

DENSEL

PPM

e

0.

78

41

O

Density Select. This pin provides an additional Density Select signal in PPM Mode when PNF

(See AFD and Table 7-5 for further information.)

Mode

DIR

Normal

Mode

Direction. This output determines the direction of the floppy disk drive (FDD) head movement (active

e

step out) during a seek operation. During reads or writes, DIR is inactive.

e

step in, inactive

DIR

e

0. (See INIT and

PPM

Mode

80

Direction. This pin provides an additional direction signal in PPM Mode when PNF

Table 7-5 for further information.)

DR0,1

Normal

Mode

44, 45

Drive SeIect 0,1. These are the decoded Drive Select outputs that are controlled by the Digital Output

Register bits D0, D1. The Drive Select outputs are gated with DOR bits 4–7. These are active low

outputs. They are encoded with information to control four FDDs when bit 4 of the Function Enable

Register (FER) is set. (See MTR0,1 for more information.) DR0 exchanges logical drive values with

DR1 when bit 4 of Function Control Register (FCR) is set. (See Table 7-5 for further information.)

DR1

e

0. It is

PPM

Mode

85

O

I

Drive Select 1. This pin provides an additional Drive Select signal in PPM Mode when PNF

drive select 1 when bit 4 of FCR is 0. It is drive select 0 when bit 4 of FCR is 1. This signal is active low.

(See ACK and Table 7-5 for further information.)

DRATE0,1 52, 51

Data Rate 0,1. These outputs reflect the currently selected FDC data rate (bits 0 and 1 in the

Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written

to last). The pins are totem-pole buffered outputs (6 mA sink, 6 mA source).

DRV2

49

Drive2. This input indicates whether a second floppy disk drive has been installed. The state of this

pin is available from Status Register A in PS/2 mode. (See PNF for further information.)

É

10

1.0 Pin Description (Continued)

Symbol

I/O

Function

DSKCHG

Normal

Mode

32

I

Disk Change. This input indicates if the drive door has been opened. The state of this pin is available

from the Digital Input register. This pin can also be configured as the Read Gate (RGATE) data

separator diagnostic input via the Mode command (see Section 4.2.6).

DSKCHG

PPM

e

0. (See

89

I

Disk Change. This pin provides an additional Disk Change signal in PPM Mode when PNF

PD4 and Table 7-5 for further information.)

Mode

DSR1,2

76, 68

Data Set Ready. When low this signal indicates that the data set or MODEM is ready to establish a

communications link. The DSR signal is a MODEM status input whose condition the CPU can test by

reading bit 5 (DSR) of the MODEM Status Register (MSR) for the appropriate channel. Bit 5 is the

complement of the DSR signal. Bit 1 (DDSR) of the MSR indicates whether the DSR input has changed

states since the previous reading of the MSR. (See IRRX for further information.)

Note: Whenever the DDSR bit of the MSR is set, an interrupt is generated If MODEM Status interrupts are enabled.

DSTRB

DTR1,2

78

O

Data Strobe. This signal is used in EPP mode as a data strobe. It is active low. (See AFD and Table 7-5

for further information.)

71, 63

Data Terminal Ready. When low, this output indicates to the MODEM or data set that the UART is

ready to establish a communications link. The DTR signal can be set to an active low by programming

bit 0 (DTR) of the MODEM Control Register to a high level. A Master Reset operation sets this signal to

its inactive (high) state. Loop mode operation holds this signal to its inactive state. (See CFG4–0 for

further information.)

ERR

79

5

I

Error. A connected printer sets this input low when it has detected an error. This pin has a nominal 25

kX pull-up resistor attached to it. (See HDSEL and Table 7-5 for further information.)

FDACK

DMA Acknowledge. Active low input to acknowledge the FDC DMA request and enable the RD and

WR inputs during a DMA transfer. When in PC-AT or Model 30 mode, this signal is enabled by bit D3

É

of the Digital Output Register (DOR). When in PS/2 mode, FDACK is always enabled, and bit D3 of the

DOR is reserved. FDACK should be held high during I/O accesses.

FDRQ

HCS0

4

O

DMA Request. Active high output to signal the DMA controller that a FDC data transfer is needed.

When in PC-AT or Model 30 mode, this signal is enabled by bit D3 of the DOR. When in PS/2 mode,

FDRQ is always enabled, and bit D3 of the DOR is reserved.

58

Hard Drive Chip Select 0. This output is active in the AT mode when 1) the hard drive registers from

1F0–1F7h are selected and the primary address is used or 2) the hard drive registers from 170–177h

are selected and the secondary address is used. This output is inactive if the IDE interface is disabled

via the Configuration Register. (See BADDR1 for further information.)

HCS1

57

34

O

Hard Drive Chip Select 1. This output is active in the AT mode when 1) the hard drive registers from

3F6–7 are selected and the primary address is used or 2) the hard drive registers from 376–377 are

selected and the secondary address is used. This output is also inactive, if the IDE interface is disabled

via the Configuration Register. (See CLK48 for further information.)

HDSEL

Normal

Mode

O

Head Select. This output determines which side of the FDD is accessed. When active, the head

selects side 1. When inactive, the head selects side 0.

HDSEL

PPM

e

0. (See

79

60

Head Select. This pin provides an additional Head Select signal in PPM Mode when PNF

ERR and Table 7-5 for further information.)

Mode

IDED7

I/O IDE Bit 7. This pin provides the data bus bit 7 signal to the IDE hard drive during accesses in the

address range 1F0–1F7h, 170–177h, 3F6h and 376h. This pin is in TRI-STATE during read or write

accesses to 3F7h and 377h.

11

1.0 Pin Description (Continued)

Symbol

I/O

Function

IDEHI

56

O

IDE High Byte. This output enables the high byte data latch during a read or write to the hard drive if

the hard drive returns IOCS16. This output is inactive if the IDE interface is disabled via the

Configuration Register. (See VLD0 for further information.)

IDELO

IDENT

55

54

O

I

IDE Low Byte. This output enables the low byte data latch during a read or write to the hard drive. This

output is inactive if the IDE interface is disabled via the Configuration Register. (See BADDR0 for

further information.)

Identity. During chip reset, the IDENT and MFM pins are sampled to determine the desired mode of

operation according to the following table:

IDENT

MFM

MODE

1

0

1 or NC

PC-AT Mode

Illegal

0

1 or NC

0

PS/2 Mode

Model 30 Mode

AT ModeÐThe DMA enable bit in the DOR is valid. TC is active high. Status Registers A and B are

disabled (TRI-STATE).

Model 30 ModeÐThe DMA enable bit in the DOR is valid. TC is active high. Status Registers A and B

are enabled.

PS/2 ModeÐThe DMA enable bit in the DOR is a don’t care, and the FDRQ and IRQ6 signals are

always enabled. TC is active low. Status Registers A and B are enabled.

After chip reset, the state of IDENT determines the polarity of the DENSEL output. When IDENT is a

logic ‘‘1’’, DENSEL is active high for the 500 kbps/1 Mbps/2 Mbps data rates. When IDENT is a logic

‘‘0’’, DENSEL is active low for the 500 kbps/1 Mbps/2 Mbps data rates. (See Mode command for

further explanation of DENSEL.)

IDLE

43

47

O

IDLE. This pin is IDLE output when bit 4 of PMC is 1. IDLE indicates that the FDC is in the IDLE state

and can be powered down. Whenever the FDC is in IDLE state, or whenever the FDC is in power-down

state, the pin is active high. This bit is MTR1 when bit 4 of the Power Management Control Register

(PMC) is 0.

INDEX

Normal

Mode

I

Index. This input signals the beginning of a FDD track.

INDEX

PPM

e

0.

94

80

Index. This pin provides an additional Index signal in PPM Mode when PNF

Mode

(See PD0 and Table 7-5 for further information.)

INIT

I/O Initialize. When this signal is low it causes the printer to be initialized. This pin is in a TRI-STATE

condition 10 ns after a 1 is loaded into the corresponding Control Register bit. The system should pull

this pin high using a 4.7 kX resistor. (See DIR and Table 7-5 for further information.)

IOCHRDY

53

O

I/O Channel Ready. This is the I/O Channel Ready open drain output when bit 7 of FCR is 0. When

IOCHRDY is driven low, the EPP extends the host cycle. This pin is the MFM output pin when bit 7 of

FCR is 1. (See MFM pin for further information.)

IOCS16

IRQ3,4

59

I

I/O Chip Select 16-bit. This input is driven by the peripheral device when it can accommodate a 16-bit

access.

1, 100

O

Interrupt 3 and 4. These are active high interrupts associated with the serial ports. IRQ3 presents the

signal if the serial port has been designated as COM2 or COM4. IRQ4 presents the signal if the serial

port is designated as COM1 or COM3. The appropriate interrupt goes active whenever it is enabled via

the Interrupt Enable Register (IER), the associated Interrupt Enable bit (Modem Control Register bit 3,

MCR3), and any of the following conditions are active: Receiver Error, Receive Data available,

Transmitter Holding Register Empty, or a Modem Status Flag is set. The interrupt is reset low (inactive)

after the appropriate interrupt service routine is executed, after being disabled via the IER, or after a

Master Reset. Either interrupt can be disabled, putting them into TRI-STATE, by setting the MCR3 bit

low.

12

1.0 Pin Description (Continued)

Symbol

I/O

Function

IRQ5

98

I/O Interrupt 5. Active high output that indicates a parallel port interrupt. When enabled this bit follows the

ACK signal input. When bit 4 in the parallel port Control Register is set and the parallel port address is

designated as shown in Table 2-5, this interrupt is enabled. When it is not enabled this signal is TRI-

STATE. This pin is I/O only when ECP is enabled, and IRQ5 is configured. For ECP operation, refer to

the interrupt ECP Section 7.11.1.

IRQ6

IRQ7

97

96

O

Interrupt 6. Active high output to signal the completion of the execution phase for certain FDC

commands. Also used to signal when a data transfer is ready during a Non-DMA operation. When in

PC-AT or Model 30 mode, this signal is enabled by bit D3 of the DOR. When in PS/2 mode, IRQ6 is

always enabled, and bit D3 of the DOR is reserved.

I/O Interrupt 7. Active high output that indicates a parallel port interrupt. When enabled this bit follows the

ACK signal input. When bit 4 in the parallel port Control Register is set and the parallel port address is

designated as shown in Table 2-5, this interrupt is enabled. When it is not enabled this signal is

TRI-STATE. This pin is I/O only when ECP is enabled, and IRQ7 is configured. For ECP operation,

refer to the interrupt ECP Section 7.11.1.

MR

2

I

Master Reset. Active high input that resets the controller to the idle state, and resets all disk interface

outputs to their inactive states. The DOR, DSR, CCR, Mode command, Configure command, and Lock

command parameters are cleared to their default values. The Specify command parameters are not

affected. The Configuration Registers are set to their selected default values.

MFM

53

I/O MFM (Modified Frequency Modulation). During a chip reset, when lDENT is low, this pin is sampled

to select the PS/2 mode (MFM high), or the Model 30 mode (MFM low). An internal pull-up or external

pull-down 10k resistor selects between the two PS/2 modes. When the PC-AT mode is desired

(lDENT high), MFM should be left pulled high internally. MFM reflects the current data encoding

e

format when RESET is inactive. MFM

further information.)

high. Defaults to low after a chip reset. (See IOCHRDY for

MTR0,1

Normal

Mode

46, 43

O

Motor Select 0,1. These are the motor enable lines for drives 0 and 1, and they are controlled by bits

D7–D4 of the Digital Output register. They are active low outputs. They are encoded with information

to control four FDDs when bit 4 of the Function Enable Register (FER) is set. MTR0 exchanges logical

motor values with MTR1 when bit 4 of FCR is set. (See DR0,1).

MTR1

PPM

e

0.

84

O

Motor Select 1. This pin provides an additional Motor Select 1 signal in PPM Mode when PNF

This pin is the motor enable line for drive 1 when bit 4 of FCR is 0. It is the motor enable line for drive 0

when bit 4 of FCR is 1. This signal is active low. (See BUSY and Table 7-5 for further information.)

Mode

MSEN0,1

Normal

Mode

52, 51

I

Media Sense. These pins are Media Sense input pins when bit 0 of FCR is 0. Each pin has a 10 kX

internal pull-up resistor. When bit 0 of FCR is 1, these pins are Data Rate output pins, and the pull-up

resistors are disabled. (See DRATE0,1 for further information.)

MSEN0,1

PPM

e

0. (See

88, 86

45

I

Media Sense. These pins provide additional Media Sense signals for PPM Mode and PNF

PD5, 7 and Table 7-5 for further information.)

Mode

PD

O

Power-Down. This pin is PD output when bit 4 of PMC is 1. It is DR1 when bit 4 of PMC is 0. PD is

active high whenever the FDC is in power-down state, either via bit 6 of DSR (or bit 3 of FER, or bit 0

of PTR), or via the mode command. See DR1 for further information.

PD0–7

94–91, I/O Parallel Port Data. These bidirectional pins transfer data to and from the peripheral data bus and the

parallel port Data Register. These pins have high current drive capability. (See DC Electrical

Characteristics.)

89–86

(See MSEN0,1 INDEX, TRK0, WP, RDATA, DSKCHG and Table 7-5 for further information.)

13

1.0 Pin Description (Continued)

Symbol

I/O

Function

PDACK

54

I

Printer DMA Acknowledge. Active low input to acknowledge the printer DMA request, and enable the

RD and WR inputs during a DMA transfer. This pin is PDACK input pin when bit 3 of PMC is 1. It is

IDENT when bit 3 of PMC is 0. PDACK input pin is ECP DMA acknowledge.

PDACK is assumed to be 1 when bit 3 of PMC is 0.

IDENT is assumed to be 1 when bit 3 of PMC is 1.

This input is valid only in ECP mode.

PDRQ

PWDN

33

3

O

I

Printer DMA Request. Active high output to signal the DMA controller that a printer data transfer is

required. This pin is in TRI-STATE when ECP is disabled (bit 2 of PCR is 0), or configured with no DMA

(bit 3 of PMC is 0). This output is valid only in ECP mode.

Power Down. This multi-function pin stops the clocks and/or the external crystal based on the

selections made in the Power and Test Register bits 1-2. This pin also affects the FDC, UARTs, IDE

and Parallel Port pins, when the relevant PMC register bits are set. (See ZWS for further information.)

PE

83

49

I

Paper End. This input is set high by the printer when it is out of paper. This pin has a nominal 25 kX

pull-down resistor attached to it. (See WDATA and Table 7-5 for further information.)

PNF

Printer Not Floppy. PNF is the Printer Not Floppy pin when bit 2 of FCR is 1. It selects the device

e

0. This pin is the DRV2 input pin when bit 2 of FCR is 0. (See DRV2 for

which is connected to the PPM pins. A parallel printer is connected when PNF

e

1, and a floppy disk

drive is connected when PNF

further information.)

RD

19

35

I

Read. Active low input to signal data read by the microprocessor.

RDATA

Normal

Mode

Read Data. This input is the raw serial data read from the floppy disk drive.

RDATA

PPM

e

0. (See PD3

91

I

Read Data. This pin provides an additional Read Data signal in PPM Mode when PNF

and Table 7-5 for further information.)

Mode

RI1,2

70, 62

Ring Indicator. When low this indicates that a telephone ring signal has been received by the MODEM.

The RI signal is a MODEM status input whose condition the CPU can test by reading bit 6 (RI) of the

MODEM Status Register (MSR) for the appropriate serial channel. Bit 6 is the complement of the RI

signal. Bit 2 (TERI) of the MSR indicates whether the RI input has changed from low to high since the

previous reading of the MSR.

Note: When the TERI bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.

RTS1,2

74, 66

O

Request to Send. When low, this output indicates to the MODEM or data set that the UART is ready to

exchange data. The RTS signal can be set to an active low by programming bit 1 (RTS) of the MODEM

Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state.

Loop mode operation holds this signal to its inactive state. (See CFG0–4 for further information.)

SIN1,2

SLCT

SLIN

75, 67

82

I

Serial Input. This input receives composite serial data from the communications link (e.g. peripheral

device, MODEM, or data set).

Select. When a printer is connected, it sets this input high. This pin has a nominal 25 kX pull-down

resistor attached to it.

81

I/O Select Input. When this signal is low it selects the printer. This pin is in a TRI-STATE condition 10 ns

after a 0 is loaded into the corresponding Control Register bit. The system should pull this pin high

using a 4.7 kX resistor. (See ASTRB, STEP and Table 7-5 for further information.)

SOUT1,2 73, 65

O

Serial Output. This output signal sends composite serial data to the communications link (e.g.

peripheral device, MODEM, or data set). The SOUT signal is set to a marking state (logic 1) after a

Master Reset operation. (See BOUT and CFG0–4 for further information.)

14

1.0 Pin Description (Continued)

Symbol

STB

I/O

Function

95

I/O Data Strobe. This output signal indicates to the printer that valid data is available at the printer port.

This pin is in a TRl-STATE condition 10 ns after a 0 is loaded into the corresponding Control Register

bit. The system should pull this pin high using a 4.7 kX resistor. (See WRlTE for further information.)

STEP

Normal

Mode

40

O

Step. This output signal issues pulses to the disk drive at a software programmable rate to move the

head during a seek operation.

STEP

e

0. (See SLIN, ASTRB

PPM

81

6

O

I

Step. This pin provides an additional step signal in PPM Mode when PNF

and Table 7-5 for further information.)

Mode

TC

TerminaI Count. Control signal from the DMA controller to indicate the termination of a DMA

transfer. TC is accepted only when FDACK is active. TC is active high in PC-AT and Model 30

modes, and active low in PS/2 mode.

TRK0

Normal

Mode

37

I

Track 0. This input indicates to the controller that the head of the selected floppy disk drive is at

track zero.

TRK0

e

0. (See PD1 and

PPM

93

Track 0. This pin provides an additional Track 0 signal in PPM Mode when PNF

Table 7-5 for further information.)

Mode

V

,

50, 99

56, 63

Power Supply. This is the 3.3V or 5V supply voltage for the PC87332 circuitry.

DDB

DDC

VLD0,1

I

Valid Data. These input pins are sensed during reset, and indicate the state of bit 5 in the FDC Tape

Drive Register (3F3h). They indicate whether bits 6 and 7 of this register contain valid media ID

information for floppy drives 0 and 1. If VLD0 is sensed low at reset, then whenever drive 0 is

accessed, bit 5 of the Tape Drive Register is a 0 indicating that bits 6 and 7 contain valid media ID

information. If VLD0 is sensed high at reset, then whenever drive 0 is accessed, bit 5 of the Tape

Drive Register is a 1 indicating that bits 6 and 7 do not contain valid media ID information. The same

is true of VLD1 relative to the media ID information for drive 1.

If bit 0 of FCR is 1, the VLD bits have no meaning. VLD0 value during reset is loaded into bit 0 of

FCR (to select between media sense or DRATE). A 30 kX internal pull-down resistor is on each pin.

Use a 10 kX resistor to pull these pins to high during reset.

V

, V

SSB SSC

,

42, 9,

Ground. This is the ground for the PC87332 circuitry.

V , V

SSD SSE

90, 61

WAIT

84

18

39

I

Wait. This signal is used, in EPP mode, by the parallel port device to extend its access cycle. It is

active low. (See BUSY and Table 7-5 for further information.)

WR

Write. Active low input signal to indicate a write from the microprocessor to the controller.

WDATA

Normal

Mode

O

Write Data. This output is the write precompensated serial data that is written to the selected floppy

disk drive. Precompensation is software selectable.

WDATA

PPM

e

0. (See PE

83

38

O

Write Data. This pin provides an additional Write Data signal in PPM Mode when PNF

and Table 7-5 for further information.)

Mode

WGATE

Normal

Mode

Write Gate. This output signal enables the write circuitry of the selected disk drive. WGATE has

been designed to prevent glitches during power up and power down. This prevents writing to the disk

when power is cycled.

WGATE

PPM

e

0. (See

82

O

Write Gate. This pin provides an additional Write Gate signal in PPM Mode when PNF

SLCT and Table 7-5 for further information.)

Mode

15

1.0 Pin Description (Continued)

Symbol

Pin I/O

Function

WP

Normal 36

I

Write Protect. This input indicates that the floppy disk in the selected drive is write protected.

Mode

WP

e

0. (See

PPM

Mode

92

95

7

I

O

I

Write Protect. This pin provides an additional Write Protect signal in PPM Mode when PNF

PD2 and Table 7-5 for further information.)

WRITE

Write Strobe. This signal is used in EPP mode as a write strobe. It is active low. (See STB and Table 7-5

for further information.)

X1/OSC

Crystal1/Clock. One side of an external 24 MHz/48 MHz crystal is attached here. The other side of the

crystal is connected to X2. If a crystal is not used, a TTL or CMOS compatible clock is connected to this

pin.

X2

8

3

O

Crystal2. One side of an external 24 MHz/48 MHz crystal is attached here. The other side of the crystal is

connected to X1/OSC. This pin is left unconnected if an external clock is used.

ZWS

Zero Wait State. This pin is the Zero Wait State open drain output pin when bit 6 of FCR is 0. ZWS is

driven low when the EPP or ECP is written, and the access can be shortened. This pin is PWDN when bit 6

of FCR is 1. (See the PWDN pin for further information.)

16

2.0 Configuration Registers

2.1 OVERVIEW

1. Determine the default location of the PC87332 Index

Register.

Eight registers constitute the Base Configuration Register

set, and control the PC87332 set-up. In general, these reg-

isters control the enabling of major functions (FDC, UARTs,

parallel port, pin functionality, etc.), the I/O addresses of

these functions, and whether they power-down via hard-

ware control or not. These registers are the Function Enable

Register (FER), Function Address Register (FAR), Power

and Test Register (PTR), Function Control Register (FCR),

the Printer Control Register (PCR), the Power Management

Control Register (PMC), the Tape, UARTs and Parallel Port

Configuration Register (TUP), and the SuperI/O (SIO) Iden-

tification Register (SID).

Check the four possible locations (see Table 2-1) by

reading them twice. The first byte is the ID byte 88h, al-

though read-after-write always brings the value of the

written byte. The second byte read is always 00h. Com-

pare the data read with the ID byte and then 00h. A

match occurs at the correct location. Note that the ID

byte is only issued from the Index Register during the first

read after a reset. Subsequent reads return the value

loaded into the Index Register. Bits 4-6 are reserved and

always read 0.

2. Load the Configuration Registers.

A. Disable CPU interrupts.

During reset, the PC87332 loads a set of default values se-

lected by a hardware strapping option into the FER, FAR,

and PTR Configuration Registers. The FCR, PCR, PMC,

TUP and SID registers can only be accessed by software.

B. Write the index of the Configuration Register (00h–

0Eh) to the Index Register one time.

C. Write the correct data for the Configuration Register in

two consecutive write accesses to the Data Register.

An index and data register pair are used to read and write

the configuration registers. Each Configuration Register is

pointed to the value loaded into the Index Register. The

data to be written into the Configuration Register is trans-

ferred via the Data register. A Configuration Register is read

in a similar way (i.e., by pointing to it via the Index Register

and then reading its contents via the Data Register).

D. Enable CPU interrupts.

3. Load the Configuration Registers (read-modify-write).

A. Disable CPU interrupts.

B. Write the index of the Configuration Register (00h–

0Eh) to the Index Register one time.

Accessing the Configuration Registers in this way requires

only two system I/O addresses. Since I/O address space is

shared by other devices, the Index and Data Registers can

still be inadvertently accessed. To reduce the chances of an

inadvertent access, a simple procedure has been devel-

oped. It is described in Section 2.2.

C. Read the configuration data in that register via the

Data Register.

D. Modify the configuration data.

E. Write the changed data for the Configuration Register

in two consecutive writes to the Data Register. The

register updates on the second consecutive write.

2.2 SOFTWARE CONFlGURATlON

F. Enable CPU interrupts.

If the system requires access to the Configuration Registers

after reset, the following procedure must be used to change

data in the registers.

A single read access to the Index and Data Registers can

be done at any time without disabling CPU interrupts. When

the Index Register is read, the last value loaded into the

Index Register is returned. When the Data Register is read,

the Configuration Register data pointed to by the Index Reg-

ister is returned.

17

2.0 Configuration Registers (Continued)

TL/C/11930–4

FIGURE 2-1. PC87332VLJ/PC87332VLJ-5 Configuration Registers

18

2.0 Configuration Registers (Continued)

2.3 HARDWARE CONFIGURATION

Most of the variability available is through the FAR. Ad-

dresses controlled by the FAR are coded as follows:

During reset, one of 32 possible sets of default values are

loaded into the first three Configuration Registers. A strap-

ping option on five pins (CFG0–4) selects the set of values

that is loaded. This allows for automatic configuration with-

out software intervention. Table 2-1 shows the 32 possible

default configurations. The default configuration can be

modified by software at any time after reset by using the

access procedure described in the Software Configuration

Section.

PRI:

is the PRImary floppy or IDE address (i.e., 3F0–7h

or 1F0–7, 3F6, 7h).

SEC: is the SECondary IDE address (170–7, 376, 7h).

COM1: is the UART address at 3F8–Fh.

COM2: is the UART address at 2F8–Fh.

COM3: is the UART address at 3E8–Fh.

COM4: is the UART address at 2E8–Fh.

Table 2-1 is organized as follows. The logic values of the

five external Configuration Pins are associated with the re-

sulting Configuration Register Data and the activated func-

tions. The activated functions are grouped into seven cate-

gories based on the data in the FER. In some cases the

data in the FER is given as one of two options. This is be-

cause the primary or secondary IDE address is chosen via

the FER.

LPTA: is the parallel port (

3BEh.

PORT ) address at 3BC–

ll

LPTB: is the PORT address at 378–37Fh.

ll

The chosen addresses are given under active functions and

are in the same order as the active functions with which

they are associated. In other words, if the active functions

are given as FDC, IDE, UART1, UART2, PORT and the

ll

addresses are given as PRI, PRI, COM1, COM2, LPTB, then

the functions and the addresses are associated as follows:

The PTR has one value associated with the active functions

in the FER. This value allows the power-down of all clocks

when the PWDN pin goes active. In the last case where no

functions are active after reset, activating the PWDN pin

also stops the crystal.

e

FDC

UART2

PRI, IDE

COM2, PORT

PRI, UART1

e

LPTB.

COM1,

ll

TABLE 2-1. Default Configurations Controlled by Hardware

Configuration Pins (CFGn)

Data

Activated Functions

(Hex)

4

3

2

1

0

e

FER

PTR

FAR

FER

PTR

FAR

FER

PTR

FAR

4F, CF

00, 80

10

FDC, IDE, UART1, UART2, PORT

ll

Power-Down Clocks Option

PRI, PRI, COM1, COM2, LPTB

PRI, PRI, COM1, COM2, LPTA

PRI, SEC, COM1, COM2, LPTA

PRI, PRI, COM3, COM4, LPTA

PRI, PRI, COM2, COM3, LPTB

PRI, SEC, COM3, COM4, LPTB

0

1

0

1

0

1

0

1

0

1

11

39

24

38

4B, CB

00, 80

00

FDC, IDE, UART1, PORT

ll

Power-Down Clocks Option

PRI, PRI, COM1, LPTB

PRI, PRI, COM1, LPTA

PRI, SEC, COM1, LPTA

PRI, PRI, COM3, LPTA

PRI, PRI, COM3, LPTB

PRI, SEC, COM3, LPTB

0

1

0

1

0

1

0

1

0

1

0

1

01

09

08

0F

FDC, UART1, UART2, PORT

ll

00, 80

10

Power-Down Clocks Option

PRI, COM1, COM2, LPTB

PRI, COM1, COM2, LPTA

PRI, COM3, COM4, LPTA

PRI, COM2, COM3, LPTB

0

1

0

1

0

1

0

1

11

39

24

19

2.0 Configuration Registers (Continued)

TABLE 2-1. Default Configurations Controlled by Hardware (Continued)

Configuration Pins (CFGn)

Data

Activated Functions

(Hex)

4

3

2

1

0

e

FER

PTR

FAR

FER

PTR

FAR

FER

PTR

FAR

FER

PTR

FAR

FER

PTR

FAR

49, C9

00, 80

00

FDC, IDE, PORT

ll

Power-Down Clocks Option

1

0

1

0

1

0

1

PRI, PRI, LPTB

01

PRI, PRI, LPTA

01

PRI, SEC, LPTA

00

PRI, SEC, LPTB

07

UART1, UART2, PORT

ll

00, 80

10

Power-Down Clocks Option

COM1, COM2, LPTB

COM1, COM2, LPTA

COM3, COM4, LPTA

COM2, COM3, LPTB

1

0

1

0

1

0

1

0

1

11

39

24

47, C7

00, 80

10

IDE, UART1, UART2, PORT

ll

Power-Down Clocks Option

PRI, COM1, COM2, LPTB

PRI, COM1, COM2, LPTA

SEC, COM1, COM2, LPTA

PRI, COM3, COM4, LPTA

PRI, COM2, COM3, LPTB

SEC, COM3, COM4, LPTB

FDC

1

0

1

0

1

0

1

0

1

0

1

11

39

24

38

08

00, 80

10

Power-Down Clocks Option

PRI

1

0

1

00

None

02, 82

10

Power-Down XTAL and Clocks

NA

20

2.0 Configuration Registers (Continued)

2.4 INDEX AND DATA REGISTERS

Another general aspect of the Configuration Registers is

that the Index and the Data Register pair can be relocated

to one of four locations. This is controlled through a hard-

ware strapping option on pins (BADDR0,1) and it allows the

registers to avoid conflicts with other adapters in the I/O

address space. Table 2-2 shows the address options.

Bit 2 When this bit is 1, UART2 can be accessed at the

address specified in the FAR. When this bit is 0, ac-

cess to UART2 is blocked and it is in power-down

mode. The UART2 registers retain all data in power-

down mode.

Caution: Any UART2 interrupt that is enabled and

active or becomes active after UART2 is disabled as-

serts the associated IRQ pin. If disabling UART2 via

software, clear the IRQ Enable bit (MCR3) to 0 be-

fore clearing FER 1. This is not an issue after reset

because MCR3 is 0 until it is written.

TABLE 2-2. Index and Data Register

Optional Locations

BADDR1

BADDR0

Index Addr.

Data Addr.

399

0

1

0

1

0

1

398

26E

15C

2E

Bit 3 When this bit is 1, the FDC can be accessed at the

address specified in the FER bits. When this bit is 0

access to the FDC is blocked and it is in power-down

mode. The FDC registers retain all data in power-

down mode.

26F

15D

2F

Bit 4 When this bit is 0 the PC87332 can control two floppy

disk drives directly without an external decoder.

When this bit is 1 the two drive select signals and two

motor enable signals from the FDC are encoded so

that four floppy disk drives can be controlled (see

Table 2-3 and Figure 2-2 ). Controlling four FDDs re-

quires an external decoder. The pin states shown in

Table 2-3 are a direct result of the bit patterns shown.

All other bit patterns produce pin states that should

not be decoded to enable any drive or motor.

2.5 BASE CONFIGURATION REGISTERS

2.5.1 Function Enable Register (FER, Index 00h)

This register enables and disables major chip functions (e.g.

UARTs, parallel ports, FDC, etc.). Disabled functions have

their clocks automatically powered-down, but the data in

their registers remains intact. It also selects whether the

FDC and the IDE controller is located at their primary or

secondary address.

Bit 0 When this bit is 1 the parallel port can be accessed at

the address specified in the FAR.

Bit 5 This bit selects the primary or secondary FDC ad-

dress. (See Table 2-4.)

Bit 1 When this bit is 1, UART1 can be accessed at the

address specified in the FAR. When this bit is 0, ac-

cess to UART1 is blocked and it is in power-down

mode. The UART1 registers retain all data in power-

down mode.

Bit 6 When this bit is a 1 the IDE drive interface can be

accessed at the address specified by FER bit 7.

When it is 0, access to the IDE interface is blocked,

the IDE control signals (i.e., HCS0, HCS1, IDELO,

IDEHI) are held in the inactive state, and the IDED7

signal is in TRI-STATE.

Caution: Any UART1 interrupt that is enabled and

active or becomes active after UART1 is disabled,

asserts the associated IRQ pin. If disabling UART1

via software, clear the IRQ Enable bit (MCR3) to 0

before clearing FER 1. This is not an issue after reset

because MCR3 is 0 until it is written.

Bit 7 This bit selects the primary or secondary IDE ad-

dress. (See Table 2-4.)

TL/C/11930–5

FIGURE 2-2. PC87332 Four Floppy Drive Circuit Example

21

2.0 Configuration Registers (Continued)

e

TABLE 2-3. Encoded Drive and Motor Pin Information (FER 4

Digital Output Register Drive Control Pins

1)

Decoded Functions

7

X

1

6

X

1

5

X

1

4

1

3

X

2

X

1

0

1

0

1

0

1

0

1

0

1

0

1

MTR1

(Note)

MTR0

DR1

0

DR0

0

1

Activate Drive 0 and Motor 0

X

0

1

Activate Drive 1 and Motor 1

X

0

1

0

Activate Drive 2 and Motor 2

X

0

1

Activate Drive 3 and Motor 3

X

0

Activate Drive 0 and Deactivate Motor 0

Activate Drive 1 and Deactivate Motor 1

Activate Drive 2 and Deactivate Motor 2

Activate Drive 3 and Deactivate Motor 3

X

0

1

X

1

0

X

1

e

or 372h takes place. This pulse is delayed by 25 ns–80 ns after the leading edge of IOW and its leading edge can be used to clock data into an external latch

Note: When FER4

1, MTR1 presents a pulse that is the inverted image of the IOW strobe. This inverted pulse is active whenever an I/O write to address 3F2h

e

(e.g., 74LS175). Address 3F2h is used if the FDC is located at the primary address (FER5

e

0) and address 372h is used if the FDC is located at the

secondary address (FER5

1).

TABLE 2-6. COM Port Selection for UART1

FAR UART1

TABLE 2-4. Primary and Secondary

Drive Address Selection

Ý

COM

Bit 5

Bit 7

Drive

PC-AT Mode

Bit 3

Bit 2

0

X

FDC

Primary,

3F0–7h

0

1

0

1

0

1

1 (3F8-F)

2 (2F8-F)

1

X

0

1

FDC

IDE

Secondary,

3F0–7h

3 (Table 2-8)*

4 (Table 2-8)*

Primary,

1F0–7h, 3F6–7h

TABLE 2-7. COM Port Selection for UART2

Secondary

170–7h, 376–7h

FAR UART2

Ý

COM

Bit 5

Bit 4

e

2.5.2 Function Address Register (FAR, Index

01h)

0

1

0

1

0

1

1 (3F8-F)

This register selects the ISA I/O address range to which

each peripheral function responds.

2 (2F8-F)

3 (Table 2-8)*

4 (Table 2-8)*

Bits 0,1 These bits select the parallel port address as

shown in Table 2-5:

*Note: COM3 and COM4 addresses are determined by Bits 6 and 7.

TABLE 2-5. Parallel Port Addresses

Bits 6,7 These bits select the addresses that are used for

COM3 and COM4 (see Table 2-8).

Parallel

Port

Address

Bit

1

Bit

0

PC-AT

Interrupt

TABLE 2-8. Address Selection for COM3 and COM4

0

1

0

1

0

1

LPTB (378–37F)

LPTA (3BC–3BE)

LPTC (278–27F)

Reserved

IRQ5 (Note)

IRQ7

Bit 7

Bit 6

COM3 IRQ4

3E8–Fh

338–Fh

COM4 IRQ3

2E8–Fh

238–Fh

0

1

0

1

0

1

IRQ5

TRI-STATE

e

2E8–Fh

220–7h

2E0–7h

(CTR4

0)

228–Fh

Note: The interrupt assigned to this address can be changed to IRQ7 by

setting Bit 3 of the Power and Test Register (PTR).

Bits 2–5 These bits determine which ISA I/O address range

is associated with each UART (see Table 2-6 and

Table 2-7).

22

2.0 Configuration Registers (Continued)

e

2.5.3 Power and Test Register (PTR, Index

02h)

e

2.5.4 Function Control Register (FCR, Index

03h)

This register determines the power-down method used

when the power-down pin (PWDN) is asserted (crystal and

clocks vs. clocks only) and whether hardware power-down

is enabled. It also provides a bit for software power-down of

all enabled functions. It selects whether IRQ7 or IRQ5 is

associated with LPTB. It puts the enabled UARTs into their

test mode.

This register determines several pin options:

It selects between Data Rate output and automatic media

sense inputs.

It enables the Parallel Port Multiplexor (PPM), and switches

between internal and external drives.

For Enhanced Parallel Port operation it enables the

IOCHRDY and ZWS options, and pins.

On reset bits 2–7 of FCR are cleared.

Bit 0 Media Sense/Data Rate select bit. When this bit is 0,

the MSEN0–1 pins are Media Sense inputs and bits

5–7 of TDR are valid. When this bit is 1, the

DRATE0–1 pins are Data Rate outputs and bits 2–7

of TDR are TRI-STATE during read. On reset, the

VLD0 pin is sampled and its value placed into this bit.

Bit 1 Reserved.

Independent of this register the floppy disk controller can

enter low power mode via the Mode Command or the Data

Rate Select Register.

Bit 0 Setting this bit causes all enabled functions to be

powered-down.

If the crystal power-down option is selected (see Bit 1)

the crystal is also powered-down. All register data is

retained when the crystal or clocks are stopped. The

FDC, UARTs, IDE and Parallel Port pins are affected

by this bit when the relevant PMC register bits are set.

Bit 2 Printer/Floppy Parallel Port Multiplexor (PPM) enable

bit. When this bit is 0, the port is configured as a paral-

lel port. When this bit is 1, the port is configured as a

floppy drive port. See PNF pin description for further

information. The DRV2/PNF pin is read as DRV2 bit,

regardless of bit 2 of FCR.

Note: Bits 2 and 3 of PCR can affect the function of the parallel port

power-down mode.

Bit 1 When the Power-Down pin or Bit 0 is asserted this bit

determines whether the enabled functions have their

e

1) is stopped. Stopping the crystal is

internal clocks stopped (Bit 1

e

crystal (Bit 1

the lowest power consumption state of the part. How-

0) or the external

Bit 3 Parallel Port Multiplexor (PPM) float control bit. When

this bit is 0, the PPM pins are driven. When this bit is

1, the PPM pins are in TRI-STATE mode and the pull-

ups are disconnected.

ever, if the crystal is stopped, a finite amount of time

E

(

8 ms) is required for crystal stabilization once the

Bit 3 is functional whether or not the PPM is config-

ured (when bit 2 of FCR is 0).

Power-Down pin (PWDN) or Bit 0 is deasserted. If all

internal clocks are stopped, but the crystal continues

to oscillate, no stabilization period is required after the

Power-Down pin or Bit 0 is deasserted.

e

When bit 3

1 the PPM outputs are in TRI-STATE

and the inputs are blocked to reduce their leakage

current. The values of the blocked inputs are:

Bit 2 Reserved. This bit must be set to 0.

e

BUSY 1, PE 0, SLCT 0, ACK 1 and ERR 1.

e

Bit 3 Setting this bit associates the parallel port with IRQ7

when the address for the parallel port is 378–37Fh

(LPTB). This bit is a ‘‘don’t care’’ when the parallel

port address is 3BC–3BEh (LPTA) or 278–27Fh

(LPTC).

Bit 4 Setting this bit puts UART1 into a test mode, which

causes its Baud Out clock to be present on its SOUT1

pin if the Line Control Register bit 7 is set to 1.

Bit 5 Setting this bit puts UART2 into a test mode, which

causes its Baud Out clock to be present on its SOUT2

pin if the Line Control Register bit 7 is set to 1.

Bit 6 Setting this bit to 1 prevents all further write accesses

to the Configuration Registers. Once it is set by soft-

ware it can only be cleared by a hardware reset. After

the initial hardware reset it is zero.

Note: To avoid undefined FDC inputs the PPM can be disabled be-

fore this bit is set.

Bit 4 Logical Drive Exchange bit. This bit allows software to

exchange the physical floppy-disk control signals, as-

signed to drives 0 and 1, thus exchanging the logical

drives A and B.

This is accomplished by exchanging control of the

DR0 and MTR0 pins with the DR1 and MTR1 pins.

The result is undefined if four drive mode is selected

e

(FER4

1). Table 2-9 shows the associations be-

tween the Configuration Register bit, the Digital Out-

put Register bits (DRVSEL0,1 and MTR0,1) and the

drive and motor control pins (DR0,1 and MTR0,1).

TABLE 2-9. Logical Drive Exchange

Bit 7 When not in EPP or ECP modes, this bit selects Com-

patible or Extended mode operation and thus controls

whether Pulse or Level interrupts are used.

FCR

Bit 4

Digital Output Register (FDC)

Asserted

FDC Pins

MTR1 MTR0 DRVSEL1 DRVSEL0

Set this bit to 0 for Compatible mode, Pulse interrupt.

Set this bit to 1 for Extended mode, Level interrupt.

In EPP mode this bit selects Regular or Automatic

bidirectional mode, thus determining the direction

control method:

Set this bit to 0 for Automatic mode, Host RD and WR

signals control the direction.

Set this bit to 1 for Regular mode, bit 5 of CTR con-

trols the direction.

After the initial hardware reset, this bit is 0.

0

1

0

1

0

1

0

1

0

1

0

1

DR0,

MTR0

DR1,

MTR1

DR1,

MTR1

DR0,

MTR0

23

2.0 Configuration Registers (Continued)

Bit 5 Zero Wait State enable bit. If this bit is 1, (and pin 3/1

(PQFP/TQFP) is configured as ZWS) ZWS is driven

low when the Enhanced Parallel Port (EPP) or the

ECP can accept a short host read/write-cycle, other-

wise the ZWS open drain output is not driven. EPP

ZWS operation should be configured when the sys-

tem is fast enough to support it.

When this bit is 0, the interrupt polarity is as already

defined, and the ECP interrupt is level high or nega-

tive pulse.

When this bit is 1, the interrupt polarity is inverted.

Bit 6 Parallel port interrupt (IRQ5 or IRQ7) open drain con-

trol bit.

When this bit is 0, the configured interrupt line (IRQ5

or IRQ7) has a totem-pole TRI-STATE output.

Bit 6 ZWS/PWDN select bit. When this bit is 0, the ZWS

pin is Zero Wait State output.

When this bit is 1, the configured interrupt line has an

open drain output (drive low or TRI-STATE, no drive

high, no internal pullup).

When this bit is 1, the PWDN/CSOUT pin option is

selected.

Bit 7 IOCHRDY/MFM select bit. When this bit is 0, the

IOCHRDY pin is the IOCHRDY open drain output that

extends the host-EPP cycle when required.

Bit 7 Reserved. To maintain compatibility with future

SuperI/O devices, this bit must not be modified when

this register is written. Use read-modify-write to pre-

serve the value of this bit.

When this bit is 1, the MFM pin is selected.

e

2.5.5 Printer Control Register (PCR, Index

04h)

2.5.6 Power Management Control Register

e

This register enables the EPP, ECP, version modes, and

interrupt options. On reset all the PCR bits are cleared to 0.

(PMC, Index

06h)

This register controls the TRI-STATE and input pins. The

PMC Register is accessed through Index 06h. The PMC

Register is cleared to 0 on reset.

The parallel port mode is software configurable as follows:

TABLE 2-10. Parallel Port Mode

Bit 0 IDE TRI-STATE control bit. When this bit is 1, and ei-

ther the IDE is disabled or the SuperI/O is in power-

down mode, HCS0 and HCS1 are in TRI-STATE.

IDED7 input is also blocked to reduce leakage current

and its value is undefined when IDE is disabled.

Operation

Mode

FER

Bit 0

PTR

Bit 7

PCR

Bit 0

PCR

Bit 2

None

0

1

X

0

1

X

0

1

0

X

0

1

Compatible

Extended

EPP

Bit 1 FDC TRI-STATE control bit. When this bit is 1 and the

FDC is powered-down, the FDC outputs are in TRI-

STATE (except IRQ6, PD, IDLE and the PPM outputs,

even if the PPM is used as FDC pins), and the FDC

inputs (except DSKCHG) are blocked to reduce their

leakage current.

ECP

Bit 0 EPP enable bit. When this bit is 0, the EPP is disabled,

and the EPP registers are not accessible (access ig-

nored).

Bit 2 UARTs TRI-STATE control bit. When this bit is 1, and

any UART is powered-down, the outputs of that UART

are in TRI-STATE (except IRQ3 and IRQ4), and the

inputs are blocked to reduce their leakage current.

When this bit is 1, and bit 2 of PCR is 0, the EPP is

enabled. Note that the EPP should not be configured

with base address 3BCh.

e

The values of the blocked inputs are: SIN 1, CTS 1,

e

DSR 1, DCD 1 and RI 1.

Bit 1 EPP version select bit. When this bit is 0, Version 1.7 is

supported.

Bit 3 ECP DMA configuration bit. When this bit is 0, ECP

DMA is not configura ble: IDENT/PDACK is assumed

to be 1 and PDRQ is in TRI-STATE.

When this bit is 1, Version 1.9 is supported (IEEE

1284).

Bit 2 ECP enable bit. When this bit is 0, the ECP is disabled

and in power mode. The ECP registers are not acces-

sible (access ignored), the ECP interrupt is inactive

and the DMA request pin is in TRI-STATE. The IRQ5,7

inputs are blocked to reduce their leakage currents.

When this bit is 1, ECP DMA is configurable via an

ECP control register. Pins 54 and 33 are PDACK and

PDRQ respectively. IDENT is assumed to be 1.

Note: This bit must not be set when the PC87332 is assembled into

PC87312/PC87322 socket, in which pin 33 is V A.

a

DD

When this bit is 1, the ECP is enabled. The software

should change this bit to 1 only when bits 0, 1, and 2 of

the existing CTR are 1, 0, and 0 respectively.

Bit 4 PD and IDLE (FDC power management output pins)

enable bit.

When this bit is 0, pins 43 and 45 are MTR1 and DR1

respectively.

Bit 3 ECP Clock Freeze Control Bit. In power-down modes

2 and 3: When this bit is 0, the clock provided to the

ECP is stopped; and

When this bit is 1, pins 43 and 45 are IDLE and PD

respectively.

When this bit is 1, the clock provided to the ECP is not

stopped.

Bit 5 Selective Lock bit. This bit enables locking of the fol-

lowing configuration bits: bit 5 of PMC, bit 4 of FER,

bits 0–7 of FAR, bits 2–3 of PTR, bits 6–7 of FCR,

and bit 0 of TUP. Unlike bit 6 of PTR, it does not lock

all the configuration bits.

Note: When either this bit or the ECP enable bit is 0, there is no

change in the PC87334 crystal stopping mechanism.

Bit 4 Reserved. This bit must be set to 0.

Bit 5 Parallel port interrupt (IRQ5 or IRQ7) polarity control

bit.

Once this bit is set by software it can only be cleared

by a hardware reset. This bit should be used instead of

bit 6 of PTR if a configuration bit should be dynamically

modified by software (like PMC bits).

24

Bit 4 UART 2 clock divisor control (MlDI baud rate configu-

ration) bit.

2.0 Configuration Registers (Continued)

When this bit is 0, bit 6 of PTR can be used to lock all

configuration registers.

When this bit is 0, the UART 2 Baud Rate Generator is

fed by the master clock divided by 13.

When this bit is 1, the above configuration bits cannot

be modified. A hardware reset clears this bit.

When this bit is 1, the UART 2 Baud Rate Generator is

fed by the master clock divided by 12. This bit should

be set to 1 to support MIDI baud rates.

Bit 6 Parallel Port Multiplexor (PPM) TRI-STATE enable bit.

This bit enables reduction in power consumption,

(when the SuperI/O is in power-down mode or the par-

allel port is disabled) by placing the PPM outputs in

TRI-STATE, and blocking the PPM inputs.

Bit 5 PD status bit. This bit holds the FDC power-down

state, as defined for the PD pin, even when pin 45 is

not configured as PD. This bit is read only.

Bit 6 IDLE status bit. This bit holds the FDC idle state, as

defined for the IDLE pin, even when pin 43 is not con-

figured as IDLE, and when IDLE is masked by bit 7 of

TUP. This bit is read only.

When this bit is 0, the parallel port pins are enabled.

When this bit is 1, and either the parallel port is dis-

abled or the SuperI/O is in power-down mode, the out-

puts of the Parallel Port, pins (except IRQ5 and IRQ7)

are in TRI-STATE, and the inputs are blocked to re-

duce their leakage currents.

Bit 7 IDLE pin mask bit. This bit masks the IDLE output pin

(but not the IDLE status bit). This bit is ignored when

pin 43 is not configured as idle.

e

The values of the blocked inputs are: BUSY 1,

When this bit is 0, the IDLE output pin is unmasked.

The IDLE pin drives the value of the FDC idle state.

e

PE 0, SLCT 0, ACK 1 and ERR 1.

e

Bit 7 Reserved. To maintain compatibility with future

SuperI/O devices, this bit must not be modified when

this register is written. Use read-modify-write to pre-

serve the value of this bit.

When this bit is 1, the IDLE output pin is masked. The

IDLE pin is driven low.

2.5.8 SuperI/O Identification Register

e

(SID, Index

08h)

2.5.7 Tape, UARTs and Parallel Port Configuration

e

The SID Register is accessed, like the other configuration

registers, through the Index Register. This read-only register

is used to identify the PC87332 device.

Register (TUP, Index

07h)

The TUP Register is cleared to 0XX0000X on reset.

Bit 0 CLK48. Clock divider enable bit.

7

6

5

4

3

2

1

0

When a 48 MHz clock is used this bit should be 1.

When a 24 MHz clock is used this bit should be 0.

0

1

X

Super I/O Identification

Reg. (SID)

When this bit is 0, the clock for all the PC87332 mod-

ules is X1/OSC (i.e., 24 MHz).

e

Index

08h

When this bit is 1, the clock of all PC87332 modules,

2.6 POWER-DOWN OPTIONS

e

except the FDC, is X1/OSC divided by 2 (i.e., 48/2

24 MHz), and the FDC clock depends on bit 1 of TUP.

The PC87332 places special emphasis on power manage-

ment. Power management methods can be divided into two

major groups:

During reset the value of CLK48 pin (pin 57) is latched

into this bit.

Group 1: Full device power-downÐthe entire PC87332

SuperI/O is powered-down and thus disabled.

This bit should not be modified by the user.

Group 2: Specific function power-downÐspecific SuperI/O

modules (FDC, UART1, UART2, IDE, ECP or Par-

allel Port) are powered-down and thus disabled.

All power-down modes are enhanced by a new feature

which allows the output pins associated with a specific func-

tion (FDC, UART1, UART2, IDE, Parallel Port) to be TRI-

STATE pins, and reduces current leakage by blocking their

inputs.

Bit 1 FDC’s 2 Mbps enable bit.

When this bit is 0, a 2 Mbps data rate is not supported

by the FDC, and the FDC clock is 24 MHz (X1/OSC

when bit 0 of TUP is 0, or X1/OSC divided by 2 when

bit 0 of TUP is 1).

When this bit is 1, 2 Mbps is supported by the FDC,

and the FDC clock is 48 MHz (X1/OSC when bit 0 of

TUP is 1). Bit 0 of TUP must be set to 1, and a 48 MHz

clock must be used to support a 2 Mbps data rate. The

operating voltage should be 5V. (See Section 5.0 FDC

Functional Description.)

Four modules in the PC87332 are operated by the internal

clockÐFDC, UART1, UART2 and ECP. These modules can

be powered-down or disabled by stopping their associated

internal clocks. In addition, all four modules can be

powered-down or disabled by stopping the external crystal

oscillator.

Bit 2 EPP Timeout Interrupt Enable bit.

When this bit is 0, the EPP timeout interrupt is masked.

When this bit is 1, the EPP timeout interrupt is generat-

ed on the selected IRQ line (IRQ5 or IRQ7), according

to PCR 6.

Modules which do not use a clock, the IDE and Parallel Port

(SPP/EPP), can be powered-down or disabled by simply

blocking access to them.

Bit 3 UART 1 clock divisor control (MIDI baud rate configu-

ration) bit.

All the above power-down modes can be achieved using

the power-down methods from Group 1 or Group 2, as de-

scribed in the following sections.

When this bit is 0, the UART 1 Baud Rate Generator is

fed by the master clock divided by 13.

When this bit is 1, the UART 1 Baud Rate Generator is

fed by the master clock divided by 12. This bit should

be set to 1 to support MIDI baud rates.

25

2.7 POWER-UP PROCEDURE AND CONSIDERATIONS

2.7.1 Crystal Stabilization

2.0 Configuration Registers (Continued)

2.6.1 Recommended Power-Down MethodsÐGroup 1

If the crystal is stopped by putting either the FDC or both

UARTs into low power mode, then a finite amount of time

Use the power-down methods in Group 1 to place the

PC87332 in one of the following modes:

E

(

8 ms) must be allowed for crystal stabilization during

Mode 1: The entire chip is powered-down, the crystal osci-

IIator is stopped, pins are TRI-STATE and the in-

puts are blocked.

subsequent power-up. The stabilization period can be

sensed by reading the Main Status Register in the FDC, if

the FDC is being powered up. (The Request for Master bit is

E

In this mode the maximum current saving can be

achieved.

not set for

8 ms.) If either one of the UARTs are being

powered up, but the FDC is not, then the software must

E

determine the 8 ms crystal stabilization period. Stabiliza-

Mode 2: The entire chip is powered-down, the crystal os-

cillator is stopped. Pins are driven.

tion of the crystal can also be sensed by putting the UART

into local loopback mode and sending bytes until they are

received correctly.

Mode 3: The entire chip is powered-down, pins are TRI-

STATE, and the inputs are blocked. The crystal

oscillator operates, and provides fast wake-up.

2.7.2 UART Power-Up

Mode 4: The entire chip is powered-down. Pins are driven.

The crystal oscillator operates.

The clock signal to the UARTs is controlled through the

Configuration Registers (FER, PTR). In order to restore the

clock signal to one or both UARTs the following conditions

must exist:

There are 13 methods to reach the above four operating

modes. See Table 2-11.

1. The appropriate enable bit (FER1,2) for the UART(s)

must be set.

2.6.2 Recommended Power-Down MethodsÐGroup 2

Use the power-down modes in Group 2 to place the

PC87332 in any desired combination of the following power-

down modes:

2. The Power-Down bit (PTR0) must not be set.

3. If the PWDN pin option (PTR2 and FCR6) is used the

CSOUT/PWDN/ZWS pin must be inactive.

Mode 1: Parallel Port (SPP/EPP/ECP) is powered-down,

providing a savings of up to 5 mA.

If the crystal has been stopped follow the guidelines in

Section 2.7.1 before sending data or signaling that the re-

ceiver channel is ready.

Mode 2: UARTs are powered-down providing a savings of

up to 5 mA.

Mode 3: FDC is powered-down, providing a savings of up

to 4 mA.

Mode 4: IDE is powered-down, providing a savings of up

to 0.1 mA.

See also the PMC register.

TABLE 2-11. Methods to Achieve Group 1 Power-Down Modes

Typical Current

Consumption

(Notes 4, 5)

Pin 3

Method

PTR Bits 012

FER Bits 01236

PCR Bit 2

PMC Bits 0126

Mode

(Note 3)

Ý

1

2

3

11x

x10

x1x

x

0

x

xxxxx

00000

x

0

1111

1

2

10 mA

4

5

6

7

11x

x10

x1x

x

0

x

xxxxx

00000

xxx1x

x

0

x

0000

30 mA

(Notes 1, 2)

Ý

8

9

10x

x00

x0x

x

0

x

xxxxx

00000

x

0

1111

3

4 mA

10

Ý

11

12

13

10x

x00

x0x

x

0

x

xxxxx

00000

x

0

0000

4

(Note 1)

Note 1: The PC87332 can also be placed in Mode 2, or Mode 4, using the strap configuration pins CFG0–4 (see Table 2-1).

Ý

Note 2: The PC87332 can also be placed in Mode 2 by using method 7, and entering FDC Low Power by executing Mode Command or by setting bit 6 of DSR to

high.

Ý

Note 3: Pin 3 is PDWN input (configured when bit 2 of PTR is 0 and bit 6 of FCR is 1).

Note 4: These values are measured under the following conditions:

1. No load on outputs

2. Inputs are stable

e

V

3. V

4. V

V

, V

SS IH

IL

DD

e

3.3V

DD

5. Using a crystal for the 24 MHz clock.

Note 5: UARTS should be in 16550 (FIFO) mode; bit 0 of FIFO Control Register should be 1.

26

The FDC supports fast 2 Mbps data rate drives and stan-

dard 1 Mbps, 250/500 kbps and 300/500 kbps data rate

drives. The 1 Mbps data rate is used by the high perform-

ance tape and floppy disk drives. The 2 Mbps data rate is

used in very high performance tape drives. The FDC also

supports the perpendicular recording mode, a new format

used with some high performance, high capacity disk drives

at the 1 Mbps data rate.

2.0 Configuration Registers (Continued)

2.7.3 FDC Power-Up

The clock signal to the FDC is controlled through the Con-

figuration Registers, the FDC Mode Command and the Data

Rate Select Register. In order to restore the clock signal to

the FDC the following conditions must exist:

1. The appropriate enable bit (FER3) must be set.

2. The Power-Down bit (PTR0) must not be set.

The high performance internal digital data separator needs

no external components. It improves on the window margin

performance standards of the DP8473, and is compatible

with the strict data separator requirements of floppy disk

and floppy-tape drives.

3. If the PWDN pin option (PTR2 and FCR 6) is used, the

PWDN/ZWS pin must be inactive.

In addition to these conditions, one of the following actions

must be taken to initiate recovery from the Power-Down

mode:

The FDC contains write precompensation circuitry that de-

faults to 125 ns for 250 kbps, 300 kbps, and 500 kbps, to

41.67 ns for 1 Mbps and to 20.8 ns for 2 Mbps. These

values can be overridden in software to disable write pre-

compensation or to provide levels of precompensation up to

250 ns.

1. Read the Main Status Register until the RQM bit (MSR7)

is set OR

2. Write to the Data Rate Select Register and set the Soft-

ware Reset bit (DSR7) OR

The FDC has internal 24 mA data bus buffers which allow

direct connection to the system bus. The internal 40 mA

totem-pole disk interface buffers are compatible with both

CMOS drive inputs and 150X resistor terminated disk drive

inputs.

3. Write to the Digital Output Register, clear and then set

the Reset bit (DOR2) OR

4. Read the Data Register and the Main Status Register

until the RQM bit is set.

If the crystal has been stopped, read the RQM bit in the

Main Status Register until it is set. The RQM bit is not set

until the crystal has stabilized.

3.1 FDC CONTROL REGISTERS

The following FDC registers are mapped into the addresses

shown in Table 3-1 and described in the following sections.

The base address range is provided by the on-chip address

decoder pin. For PC-AT or PS/2 applications, the diskette

controller primary address range is 3F0h to 3F7h, and the

secondary address range is 370h to 377h. The FDC sup-

ports three different register modes: the PC-AT mode, PS/2

mode (MicroChannel systems), and the Model 30 mode.

See Section 5.2 for more details on how each register mode

is enabled. When applicable, the register definition for each

mode of operation is given.

3.0 FDC Register Description

The floppy disk controller (FDC) is suitable for all PC-AT,

EISA, PS/2, and general purpose applications. The opera-

tional mode (PC-AT, PS/2, or Model 30) of the FDC is deter-

mined by hardware strapping of the IDENT and MFM pins.

DP8473 and N82077 software compatibility is provided. Key

features include a 16-byte FIFO, PS/2 diagnostic register

support, perpendicular recording mode, CMOS disk inter-

face, and a high performance digital data separator. See

Figure 3-1.

If no special notes are made, then the register is valid for all

three register modes.

TL/C/11930–6

FIGURE 3-1. FDC Functional Block Diagram

27

3.0 FDC Register Description (Continued)

TABLE 3-1. Register Description and Addresses

D4

D3

D2

D1

D0

Track 0: Active high status of TRK0 disk interface

input.

A2 A1 A0 IDENT R/W

Register

Head Select: Active low status of the HDSEL disk

interface output.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

R

Status Register A*

Status Register B*

SRA

SRB

DOR

TDR

MSR

DSR

FIFO

Index: Active high status of the INDEX disk inter-

face input.

X

R/W Digital Output Register

R/W Tape Drive Register

R

Main Status Register

Write Protect: Active high status of the WP disk

interface input.

W

Data Rate Select Register

R/W Data Register (FIFO)

Direction: Active low status of the DIR disk inter-

face output.

X

R

None (Bus TRI-STATE)

Digital Input Register

DIR

W

Configuration Control Register CCR

3.1.2 Status Register B (SRB)

Read Only

e

*Note: SRA and SRB are enabled by IDENT

0 during a chip reset only.

This read-only diagnostic register is part of the PS/2 floppy

controller register set, and is enabled when in the PS/2 or

Model 30 mode. The SRB can be read at any time when in

PS/2 mode. In the PC-AT mode, D7–D0 are TRI-STATE

during a mP read.

3.1.1 Status Register A (SRA)

Read Only

This read-only diagnostic register is part of the PS/2 floppy

controller register set, and is enabled when in the PS/2 or

Model 30 mode. This register monitors the state of the IRQ6

pin and some of the disk interface signals. The SRA can be

read at any time when in PS/2 mode. In the PC-AT mode,

D7–D0 are TRI-STATE during a mP read.

SRBÐPS/2 Mode

D7

D6

D5

D4

D3

D2

D1

D0

DESC

1

DR0 WDATA RDATA WGATE MTR1 MTR0

SRAÐPS/2 Mode

RESET

COND

N/A N/A

0

D7

D6

D5

D4

D3

D2

D1

D0

IRQ6

DESC

DRV2 STEP TRK0 HDSEL INDX WP DIR

D7

D6

D5

Reserved: Always 1.

PEND

RESET

COND

0

N/A

0

N/A

0

N/A N/A

0

Drive Select 0: Reflects the status of the Drive Se-

lect 0 bit in the DOR (address 2, bit 0). It is cleared

after a hardware reset, not a software reset.

D7

Interrupt Pending: This active high bit reflects the

state of the IRQ6 pin.

D4

D3

Write Data: Every inactive edge transition of the

WDATA disk interface output causes this bit to

change states.

D6

2nd Drive Installed: Active low status of the

DRV2 disk interface input, indicating if a second

drive has been installed.

Read Data: Every inactive edge transition of the

RDATA disk interface output causes this bit to

change states.

D5

D4

D3

D2

D1

D0

Step: Active high status of the STEP disk interface

output.

Track 0: Active low status of the TRK0 disk inter-

face input.

D2

D1

Write Gate: Active high status of the WGATE disk

interface output.

Head Select: Active high status of the HDSEL disk

interface output.

Motor Enable 1: Active high status of the MTR1

disk interface output. Low after a hardware reset,

unaffected by a software reset.

Index: Active low status of the INDEX disk interface

input.

D0

Motor Enable 0: Active high status of the MTR0

disk interface output. Low after a hardware reset,

unaffected by a software reset.

Write Protect: Active low status of the WP disk in-

terface input.

Direction: Active high status of the DIR disk inter-

face output.

SRBÐModel 30 Mode

D7

D6

D5

D4

D3

D2

D1

D0

SRAÐ Model 30 Mode

DESC

DRV2 DR1 DR0 WDATA RDATA WGATE DR3 DR2

D7

D6

D5

D4

D3

D2

D1

D0

RESET

COND

N/A

1

0

1

IRQ6

DESC

DRQ STEP TRK0 HDSEL INDX WP DIR

PEND

D7

2nd Drive Installed: Active low status of the

DRV2 disk interface input.

RESET

COND

0

N/A

1

N/A N/A

1

D6

D5

Drive Select 1: Active low status of the DR1 disk

interface output.

D7

Interrupt Pending: This active high bit reflects that

state of the IRQ6 pin.

Drive Select 0: Active low status of the DR0 disk

interface output.

D6

D5

DMA Request: Active high status of the DRQ signal.

Step: Active high status of the latched STEP disk

interface output. This bit is latched with the STEP

output going active, and is cleared with a read from

the DIR, or with a hardware or software reset.

28

3.0 FDC Register Description (Continued)

D4

Write Data: Active high status of latched WDATA

signal. This bit is latched by the inactive going edge

of WDATA and is cleared by a read from the DIR.

This bit is not gated by WGATE.

scription). The minimum time that this bit must be

low is 100 ns. Thus, toggling the Reset Controller bit

during consecutive writes to the DOR is an accept-

able method of issuing a software reset.

D3

D2

D1

Read Data: Active high status of latched RDATA

signal. It is latched by the inactive going edge of

RDATA and is cleared by a read from the DIR.

D1,D0 Drive Select: These two bits are binary encoded for

the four drive selects DR0–DR3, so that only one

drive select output is active at a time. (See bit 4 of

FCR for further information.)

Write Gate: Active high status of latched WGATE

signal. This bit is latched by the active going edge of

WGATE and is cleared by a read from the DIR.

It is common programming practice to enable both the mo-

tor enable and drive select outputs for a particular drive.

Table 3-2 below shows the DOR values which enable each

of the four drives.

Drive Select 3: Active low status of the DR3 disk

interface output.

Note: The MTR3, MTR2, DRV3, DRV2 pins are only available in

TABLE 3-2. Drive Enable Values

four drive mode (bit 4 of FER is 1) and require external logic.

D0

Drive Select 2: Active low status of the DR2 disk

interface output.

Drive

DOR Value

0

1

2

3

1Ch

2Dh

4Eh

8Fh

Note: The MTR3, MTR2, DRV3, DRV2 pins are only available in

four drive mode (bit 4 of FER is 1) and require external logic.

3.1.3 Digital Output Register (DOR)

Read/Write

The DOR controls the drive select and motor enable disk

interface outputs, enables the DMA logic, and contains a

software reset bit. The contents of the DOR are set to 00h

after a hardware reset, and is unaffected by a software re-

set. The DOR can be written to at any time.

Note: The MTR3, MTR2, DRV3, DRV2 pins are only available in four drive

mode (bit 4 of FER is 1) and require external logic.

3.1.4 Tape Drive Register (TDR)

Read/Write

This register is used to assign a particular drive number to

the tape drive support mode of the data separator. All other

logical drives can be assigned as floppy drive support. Any

future reference to the assigned tape drive invokes tape

drive support. The TDR is unaffected by a software reset.

This register holds the media sense information of the flop-

py disk drive. When bit 0 of FCR is 1, bits 2–7 of TDR are

TRI-STATE during read.

DOR

D7

D6

D5

D4

D3

D2

D1

D0

DRIVE DRIVE

SEL 1 SEL 0

DESC MTR3 MTR2 MTR1 MTR0 DMAEN RESET

RESET

0

COND

TDR

D7

Motor Enable 3: This bit controls the MTR3 disk

interface output. A 1 in this bit causes the MTR3 pin

to go active.

D7

D6

D5

D4

D3

D2

D1

D0

Valid

Data

TAPE

SEL 1

TAPE

SEL 0

DESC

ED

HD

X

D6

D5

D4

D3

Motor Enable 2: Same function as D7 except for

MTR2.

RESET

COND

X

N/A

0

Motor Enable 1: Same function as D7 except for

MTR1. (See bit 4 of FCR for further information.)

D7

Extra Density: When bit 5 is 0, this media ID bit is

used with bit 6 to indicate the type of media currently

in the active floppy drive. If bit 5 is 1, it is invalid. This

bit holds MSEN1 pin value. When PPM is enabled

and PNF is 0, it holds the PD7 pin value. See Table

3-3 for details regarding bits 5–7.

Motor Enable 0: Same function as D7 except for

MTR0. (See bit 4 of FCR for further information.)

DMA Enable: This bit has two modes of operation.

PC-AT mode or Model 30 mode: Writing a 1 to this

bit enables the DRQ, DACK, TC, and IRQ6 pins.

Writing a 0 to this bit disables the DACK and TC pins

and puts the DRQ and the IRQ6 pins in TRI-STATE.

D3 is a 0 after a reset when in these modes.

D6

High Density; When bit 5 is 0, this media ID bit is

used with bit 7 to indicate the type of media currently

in the active floppy drive. If bit 5 is 1, it is invalid. This

bit holds MSEN0/DRATE0 pin value. When PPM is

enabled and PNF is 0, it holds the PD5 pin value.

See Table 3-3 for details regarding bits 5–7.

PS/2 mode: This bit is reserved, and the DRQ,

DACK, TC, and IRQ6 pins are always enabled. Dur-

ing a reset, the DRQ, DACK, TC, and IRQ6 lines

remain enabled, and D3 is 0.

Note: Bits 6 and 7 of TDR are undefined when DRID0,1 pins are

configured as DRATE0,1.

D2

Reset Controller: Writing a 0 to this bit resets the

controller. It remains in the reset condition until a 1

is written to this bit. A software reset does not affect

the DSR, CCR, and other bits of the DOR. A soft-

ware reset affects the Configure and Mode com-

mand bits (See Section 4.0 FDC Command Set De-

D5

Valid Data: The state of bit 5 is determined by the

state of the VLD0,1 pins during reset. If this bit is 0,

there is valid media ID sense data in bits 7 and 6 of

this register. Bit 5 holds VLD0 when drive 0 is ac-

cessed, and media sense is configured. It holds

VLD1 when drive 1 is accessed, and media sense is

configured. Otherwise, it is set to 1 to indicate that

media information is not available. See Table 3-3 for

details regarding bits 5–7.

29

3.0 FDC Register Description (Continued)

D4–2 Reserved. These bits are ignored.

D6

D5

Data I/O (Direction): Indicates whether the con-

troller is expecting a byte to be written to (0) or read

from (1) the Data Register.

D1, 0 Tape Select 1,0: These bits assign a logical drive

number to a tape drive. Drive 0 is not available as a

tape drive, and is reserved as the floppy disk boot

drive. See Table 3-4 for the tape drive assignment

values.

Non-DMA Execution: Indicates that the controller

is in the Execution Phase of a byte transfer opera-

tion in the Non-DMA mode. This mode can be used

for multiple byte transfers by the mP in the Execu-

tion Phase via interrupts or software polling.

TABLE 3-3. Media ID Bit Functions

Bit 7

Bit 6

Bit 5

Media Type

D4

D3

Command in Progress: This bit is set after the first

byte of the Command Phase is written. This bit is

cleared after the last byte of the Result Phase is

read. If there is no Result Phase in a command, the

bit is cleared after the last byte of the Command

Phase is written.

X

0

1

X

0

1

0

1

0

Invalid Data

5.25

×

2.88M

1.44M

720k

Drive 3 Busy: Set after the last byte of the Com-

mand Phase when a Seek or Recalibrate command

is issued for drive 3. Cleared after reading the first

byte in the Result Phase of the Sense Interrupt

Command for this drive.

TABLE 3-4. Tape Drive Assignment Values

Drive

D2

D1

D0

Drive 2 Busy: Same as D3 above, but for drive 2.

Drive 1 Busy: Same as D3 above, but for drive 1.

Drive 0 Busy: Same as D3 above, but for drive 0.

TAPESEL1

TAPESEL0

Selected

0

1

0

1

0

1

None

1

2

3

3.1.6 Data Rate Select Register (DSR)

Write Only

This write-only register is used to program the data rate,

amount of write precompensation, power-down mode and

software reset. The data rate is programmed via the CCR,

not the DSR, for PC-AT, Model 30 and MicroChannel appli-

cations. Other applications can set the data rate in the DSR.

The data rate of the floppy controller is determined by the

most recent write to either the DSR or CCR. The DSR is

unaffected by a software reset. A hardware reset sets the

DSR to 02h, which corresponds to the default write precom-

pensation setting and a 250 kbps data rate.

3.1.5 Main Status Register (MSR)

Read Only

The read-only Main Status Register (MSR) indicates the cur-

rent status of the disk controller. The MSR is always avail-

able to be read. One of its functions is to control the flow of

data to and from the Data Register (FIFO). The MSR indi-

cates when the disk controller is ready to send or receive

data through the Data Register. It should be read before

each byte is transferred to or from the Data Register except

during a DMA transfer. No delay is required when reading

this register after a data transfer.

DSR

D7

D6

D5

D4

D3

D2

D1

D0

After a hardware or software reset, or recovery from a pow-

er-down state, the MSR is immediately available to be read

by the mP. It contains a value of 00h until the oscillator

circuit has stabilized, and the internal registers have been

initialized. When the FDC is ready to receive a new com-

mand, it reports an 80h to the mP. The system software can

poll the MSR until it is ready. The worst case time allowed

for the MSR to report an 80h value (RQM set) is 2.5 ms after

reset or power-up.

S/W

LOW

PRE-

DESC

0

DRATE1 DRATE0

RESET POWER

COMP2 COMP1 COMP0

RESET

COND

0

1

0

D7

D6

Software Reset: This bit has the same function as

the DOR RESET (D2, see Section 3.3) except that

this software reset is self-clearing.

Low Power: Placing a 1 in this bit puts the control-

ler into the Manual Low Power mode. The oscillator

and data separator circuits are turned off. Manual

Low Power can also be accessed via the Mode

command. The chip comes out of low power after a

software reset, or access to the Data Register or

Main Status Register.

MSR

D7

D6

D5

D4

D3

D2

D1

D0

NON

CMD

DRV3 DRV2 DRV1 DRV0

DESC

RQM DIO

DMA PROG BUSY BUSY BUSY BUSY

RESET

COND

0

D5

Undefined. Should be set to 0.

D7

Request for Master: Indicates that the controller is

ready to send or receive data from the mP through

the FIFO. This bit is cleared immediately after a byte

transfer and is set again as soon as the disk con-

troller is ready for the next byte. During a Non-DMA

Execution phase, the RQM indicates the status of

the interrupt pin.

30

3.0 FDC Register Description (Continued)

D4–2 Precompensation Select: These three bits select

the amount of write precompensation the floppy

controller uses on the WDATA disk interface output.

Table 3-5 shows the amount of precompensation

used for each bit pattern. In most cases, the default

values (Table 3-6) can be used; however, alternate

values can be chosen for specific types of drives

and media. Track 0 is the default starting track num-

ber for precompensation. The starting track number

can be changed in the Configure command.

TABLE 3-7. Data Rate Select Encoding

Data Rate Select

TUP

Bit 1

MFM

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 Mbps

500 kbps

300 kbps

250 kbps

2 Mbps*

Illegal

TABLE 3-5. Write Precompensation Delays

Precompensation Delay

Bits 4, 3, 2

e

1

TUP Bit 0

1

TUP Bit 1

Illegal

24 MHz

0.0 ns

48 MHz

0.0 ns

Illegal

111

001

010

011

100

101

110

000

*This feature is not tested.

41.7 ns

20.8 ns

41.7 ns

62.5 ns

83.3 ns

104.2 ns

125.0 ns

DEFAULT

3.1.7 Data Register (FIFO)

Read/Write

83.3 ns

The FIFO (read/write) is used to transfer all commands,

data, and status between the mP and the FDC. During the

Command Phase, the mP writes the command bytes into the

FIFO after polling the RQM and DIO bits in the MSR. During

the Result Phase, the mP reads the result bytes from the

FIFO after polling the RQM and DIO bits in the MSR.

125.0 ns

166.7 ns

208.3 ns

250.0 ns

DEFAULT

Enabling the FIFO, and setting the FIFO threshold, is done

via the Configure command. If the FIFO is enabled, only the

Execution Phase byte transfers use the 16-byte FIFO. The

FIFO is always disabled during the Command and Result

Phases of a controller operation. A software reset will not

disable enabled FIFO if the Lock bit is set in the Lock Com-

mand. After a hardware reset, the FIFO is disabled to main-

tain compatibility with PC-AT systems.

TABLE 3-6. Default Precompensation Delays

Precompensation Delay

Data Rate

(24 MHz and 48 MHz)

2 Mbps

1 Mbps

20.8 ns

41.7 ns

The 16-byte FIFO can be used for DMA, Interrupt, or soft-

ware polling type transfers during the execution of a read,

write, format, or scan command. In addition, the FIFO can

be put into a Burst or Non-Burst mode with the Mode com-

mand. In the Burst mode, DRQ or IRQ6 remains active until

all of the bytes have been transferred to or from the FIFO. In

the Non-Burst mode, DRQ or IRQ6 is deasserted for 350 ns

to allow higher priority transfer requests to be serviced.

500 kbps

300 kbps

250 kbps

125.0 ns

D1–0 Data Rate Select 1,0: These bits determine the

data rate for the floppy controller. See Table 3-7 for

the corresponding data rate for each D1,0 value

pair. The data rate select bits are unaffected by a

software reset, and are set to 250 kbps after a hard-

ware reset.

31

3.0 FDC Register Description (Continued)

The Mode command can also disable the FIFO for either

reads or writes separately. The FIFO allows the system a

larger latency without causing a disk overrun/underrun er-

ror. The FIFO is typically utilized with multitasking operating

DIRÐPS/2 Mode

D7

D6

D5

D4

D3

D2

D1

D0

HIGH

DEN

DESC

DSKCHG

1

DRATE1 DRATE0

systems and/or when running systems at or above

a

1 Mbps data rate. In its default state, the FIFO is disabled

and contains a zero threshold. The default state is entered

after a hardware reset.

RESET

COND

N/A

N/A N/A N/A N/A

N/A

1

D7

Disk Changed: Active high status of DSKCHG disk

interface input. During power-down this bit is invalid

if it is read by the software.

Data Register (FIFO)

D7

D6

D5

D4

D3

D2

D1

D0

[

Data 7:0

]

D6–3 Reserved: Always 1.

DESC

D2–1 Data Rate Select 1,0: These bits indicate the

status of the DRATE1–0 bits programmed through

the DSR or CCR.

RESET

COND

Byte Mode

During the Execution Phase of a command involving a data

transfer to/from the FIFO, the system must respond

to a data transfer service request based on the following

formula:

D0

High Density: This bit is low when the 1 Mbps/

2 Mbps or 500 kbps data rate is chosen, and high

when the 300 kbps or 250 kbps data rate is chosen.

This bit is independent of the IDENT value.

Maximum Allowable Data Transfer Service Time

DIRÐModel 30 Mode

a

c

b

]

c

(16 t

ICP

[

(THRESH

1)

8

t

)

DRP

D7

D6 D5 D4

D3

D2

D1

D0

This formula is good for all data rates with the FIFO enabled

or disabled. THRESH is a four bit value programmed in the

Configure command, which sets the FIFO threshold. If the

FIFO is disabled, THRESH is zero in the above formula. The

DESC DSKCHG

0

DMAEN NOPRE DRATE1 DRATE0

RESET

N/A

COND

0

1

0

c

to the microcode overhead required by the FDC. This delay

last term of the formula, (16

t

) is an inherent delay due

ICP

D7

Disk Changed: Active low status of DSKCHG disk

interface input. During power-down this bit is invalid

if it is read by the software.

is also data rate dependent. See Table 9-1 for the t

and

DRP

t

times. See Section 9.3.2 for a description of t

ICP

.

D6–4 Reserved: Always 0.

The programmable FIFO threshold (THRESH) is useful in

adjusting the floppy controller to the speed of the system. In

other words, a slow system with a sluggish DMA transfer

capability uses a high value of THRESH, giving the system

more time to respond to a data transfer service request

(DRQ for DMA mode or IRQ6 for Interrupt mode). Converse-

ly, a fast system with quick response to a data transfer serv-

ice request uses a low value of THRESH.

D3

DMA Enable: Active high status of the DMAEN bit

in the DOR.

D2

No Precompensation: Active high status of the

NOPRE bit in the CCR.

D1–0 Data Rate Select 1,0: These bits indicate the

status of the DRATE 1–0 bits programmed through

the DSR or CCR.

3.1.9 Configuration Control Register (CCR) Write Only

3.1.8 Digital Input Register (DIR)

Read Only

This is the write-only data rate register commonly used in

PC-AT applications. This register is not affected by a soft-

ware reset and is set to 250 kbps after a hardware reset.

The data rate of the floppy controller is determined by the

last write to either the CCR or DSR.

This diagnostic register is used to detect the state of the

DSKCHG disk interface input and some diagnostic signals.

The function of this register depends on its mode of opera-

tion. When in the PC-AT mode, the D6–0 are TRI-STATE to

avoid conflict with the fixed disk status register at the same

address. DIR is unaffected by a software reset.

CCRÐPC-AT and PS/2 Modes

DIRÐPC-AT Mode

D7

D6

D5

D4

D3

D2

D1

D0

DESC

0

DRATE1 DRATE0

D7

D6

D5

D4

D3

D2

D1

D0

RESET

COND

DESC

DSKCHG

X

N/A N/A N/A N/A N/A N/A

1

0

RESET

COND

N/A

N/A N/A N/A N/A N/A N/A N/A

D7–2 Reserved: Should be set to 0.

D1–0 Data Rate Select 1,0: These bits determine the

data rate of the floppy controller. See Table 3-7 for

the appropriate values.

D7

Disk Changed: Active high status of DSKCHG disk

interface input. During power-down this bit is invalid

if it is read by the software.

D6–0 Unused by the FDC (at TRI-STATE). The bits are

used by the Hard Disk Controller Status Register.

32

3.0 FDC Register Description (Continued)

CCRÐModel 30 Mode

3.2.2 Status Register 1 (ST1)

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

DESC

0

NOPRE DRATE1 DRATE0

DESC

ET

0

CE

OR

0

ND

NW

MA

RESET

COND

RESET

COND

N/A N/A N/A N/A N/A

N/A

1

0

D7–3 Reserved: Should be set to 0.

D7

End of Track: Controller transferred the last byte of

the last sector without the Terminal Count (TC) pin

6/4 (PQFP/TQFP) becoming active. The last sector

is the End of Track sector number programmed in

the Command Phase.

D2

No Precompensation: This bit can be set by soft-

ware, to indicate no precompensation. It can be

read by bit D2 of the DIR when in the Model 30

register mode. This bit is unaffected by a software

reset.

D6

D5

Not Used. Always 0.

D1–0 Data Rate Select 1,0: These bits determine the

data rate of the floppy controller. See Table 3-7 for

the appropriate values.

CRC Error: If this bit is set and bit 5 of ST2 is clear,

then there was a CRC error in the Address Field of

the correct sector. If bit 5 of ST2 is also set, then

there was a CRC error in the Data Field.

3.2 RESULT PHASE STATUS REGISTERS

D4

Overrun: Controller was not serviced by the mP

soon enough during a data transfer in the Execution

Phase. For read operations, indicates a data over-

run. For write operations, indicates a data underrun.

The Result Phase of a command contains bytes that hold

status information. The format of these bytes are described

below. Do not confuse these status bytes with the Main

Status Register, which is a read only register that is always

valid. The Result Phase status registers are read from the

Data Register (FIFO) only during the Result Phase of certain

commands (see Section 4.1 Command Set Summary). The

status of each register bit is indicated when the bit is a 1.

D3

D2

Not Used. Always 0.

No Data: Three possible problems:

1. Controller cannot find the sector specified in the

Command Phase during the execution of a Read,

Write, Scan, or Verify command. An address

mark was found however, so it is not a blank disk.

3.2.1 Status Register 0 (ST0)

D7

D6

D5

D4

D3

D2

D1

D0

2. Controller cannot read any Address Fields with-

out a CRC error during a Read ID command.

DESC

IC

SE

EC

0

HDS

DS1

DS0

RESET

COND

3. Controller cannot find starting sector during exe-

cution of Read A Track command.

0

D1

D0

Not Writable: Write Protect pin is active when a

Write or Format command is issued.

D7–6 Interrupt Code:

e

00

01

Normal Termination of Command.

Missing Address Mark: If bit 0 of ST2 is clear then

the controller cannot detect any Address Field Ad-

dress Mark after two disk revolutions. If bit 0 of ST2

is set then the controller cannot detect the Data

Field Address Mark after finding the correct Ad-

dress Field.

Abnormal Termination of Command. Execu-

tion of command was started, but was not

successfully completed.

e

10

11

Invalid Command Issued. Command issued

was not recognized as a valid command.

Internal drive ready status changed state dur-

ing the drive polling mode. Only occurs after a

hardware or software reset.

3.2.3 Status Register 2 (ST2)

D7

D6

D5

D4

D3

D2

D1

D0

D5

D4

Seek End: Seek, Relative Seek, or Recalibrate

command completed by the controller. (Used during

a Sense Interrupt command.)

DESC

0

CM

CD

WT

SEH

SNS

BT

MD

RESET

COND

0

Equipment Check: After a Recalibrate command,

Track 0 signal failed to occur. (Used during Sense

Interrupt command.)

D7

Not Used. Always 0.

D6

Control Mark: Controller tried to read a sector

which contained a deleted data address mark dur-

ing execution of Read Data or Scan commands. Or,

if a Read Deleted Data command was executed, a

regular address mark was detected.

D3

D2

Not Used. Always 0.

Head Select: Indicates the active high status of the

HDSEL pin at the end of the Execution Phase.

D1–0 Drive Select 1,0: These two binary encoded bits

indicate the logical drive selected at the end of the

Execution Phase.

D5

D4

CRC Error in Data Field: Controller detected a

CRC error in the Data Field. Bit 5 of ST1 is also set.

e

Wrong Track: Only set if desired sector is not

found, and the track number recorded on any sector

of the current track is different from the track ad-

dress specified in the Command Phase.

00

01

10

11

Drive 0 selected.

Drive 1 selected.

Drive 2 selected.

Drive 3 selected.

e

D3

Scan Equal Hit: ‘‘Equal’’ condition satisfied during

any Scan command.

33

3.0 FDC Register Description (Continued)

D2

Scan Not Satisfied: Controller cannot find a sector

on the track which meets the desired condition dur-

ing any Scan command.

Command Phase:

0

1

0

1

0

1

0

D1

Bad Track: Only set if the desired sector is not

found, the track number recorded on any sector on

EIS

FIFO

POLL

PRETRK

THRESH

the track is FFh indicating a hard error in IBM for-

mat, and is different from the track address speci-

fied in the Command Phase.

É

Execution Phase: Internal registers written.

Result Phase: None.

D0

Missing Address Mark in Data Field: Controller

cannot find the Data Field Address Mark (AM) dur-

ing a Read, Scan, or Verify command. Bit 0 of ST1

is also set.

EIS: Enable Implied Seeks. Default after a software reset.

e

0

1

Implied seeks disabled through Configure com-

mand. Implied seeks can still be enabled through

the Mode command when EIS

#

3.2.4 Status Register 3 (ST3)

e

0.

D7

D6

D5

D4

D3

D2

D1

D0

Implied seeks enabled for a read, write, scan, or

verify operation. A seek and sense interrupt oper-

ation is performed prior to the execution of the

read, write, scan, or verify operation. The IPS bit

does not need to be set.

DESC

0

WP

1

TK0

1

HDS

DS1

DS0

RESET

COND

0

1

0

1

0

D7

Not Used. Always 0.

FIFO: Enable FIFO for Execution Phase data transfers. De-

fault after a software reset if the LOCK bit is 0. If the

LOCK bit is 1, then the FIFO bit retains its previous

value after a software reset.

D6

Write Protect: Indicates active high status of the

WP pin.

D5

D4

Not Used. Always 1.

Track 0: Indicates active high status of the TRK0

pin.

e

0

1

FIFO enabled for both reads and writes.

FIFO disabled.

#

D3

D2

Not Used. Always 1.

POLL: Disable for Drive Polling Mode. Default after a soft-

ware reset.

Head Select: Indicates the active high status of the

HD bit in the Command Phase.

e

0

1

Enable drive polling mode. An interrupt is gener-

ated after a reset.

#

D1–0 Drive Select 1,0: These two binary encoded bits

indicate the DS1–0 bits in the Command Phase.

e

Disable drive polling mode. If the Configure

command is issued within 500 ms of a hardware

or software reset, then an interrupt is not gener-

ated. In addition, the use of the four Sense In-

terrupt commands to clear the ‘‘Ready Changed

State’’ of the four logical drives is not required.

4.0 FDC Command Set Description

This section presents the FDC command setÐfull descrip-

tion in Section 4.1 and a working summary in Section 4.2.

Each command contains a unique first command byte, the

opcode byte, which tells the controller how many (0 or

more) command bytes to expect. The information for each

command is displayed using the structure shown in Figure

4-1.

THRESH: The FIFO threshold in the Execution Phase of

read and write data transfers. Programmable

from 00h to 0Fh. Defaults to 00h after a software

reset if the LOCK bit is 0. If the LOCK bit is 1,

If an invalid command byte is issued to the controller, it

immediately enters the Result Phase and the status is 80h

signifying an Invalid Command.

THRESH retains its value.

A high value of

THRESH is suited for slow response systems,

and a low value of THRESH is better for fast re-

sponse systems.

I/O Operation

Opcode

PRETRK: Starting track number for write precompensation.

Programmable from track 0 (‘‘00’’) to track 255

(‘‘FF’’). Defaults to track 0 (‘‘00’’) after a software

reset if the LOCK bit is 0. If the LOCK bit is 1,

then PRETRK retains its value.

Command Byte 1

Command Byte 2

.

4.1.2 Dumpreg Command

The Dumpreg command is designed to support system run-

time diagnostics, application software development and de-

bug. This command has a one-byte command phase and a

10-byte result phase. The Result Phase returns the values

of parameters set in other commands. That is, the PTR

(Present Track Register) contains the least significant byte

of the track the microcode has stored for each drive. The

Step Rate Time, Motor Off and Motor On Times, and the

DMA bit are all set in the Specify command.

Command Byte n

FIGURE 4-1. FDC Command Structure

4.1 COMMAND DESCRIPTIONS

4.1.1 Configure Command

The Configure Command controls some operation modes of

the controller. It should be issued during the initialization of

the FDC after power-up. These bits are set to their default

values after a hardware reset. The value of each bit after a

software reset is explained. The default value of each bit is

denoted by a ‘‘bullet’’ to the left of each item.

34

4.0 FDC Command Set Description (Continued)

The sixth byte of the result phase varies depending on what

commands have been previously executed. If a format com-

mand has previously been issued, and no reads or writes

have been issued since then, this byte contains the Sectors

per track value. If a read or a write command has been

executed more recently than a format command, this byte

contains the End of Track value. The LOCK bit is set in the

Lock command. The eighth result byte also contains the bits

programmed in the Perpendicular Mode command. The last

two bytes of the Dumpreg Result Phase are set in the Con-

figure command. After a hardware or software reset, the

parameters in the result bytes are set to their appropriate

default values.

4. The Bytes per Sector code, which determines the sector

size.

5. The Sector per Track parameter, which determines how

many sectors are formatted on the track.

6. The Data Pattern byte, which is used as the filler byte in

the Data Field of each sector.

Command Phase:

0

MFM

X

0

1

0

1

X

HD

DR1

DR0

Bytes per Sector

Sectors per Track

Format Gap

Note: Some of these parameters are unaffected by a software reset, de-

pending on the state of the LOCK bit. See the Lock Command for

further information.

Data Pattern

Command Phase:

Execution Phase: System transfers four ID bytes (track,

head, sector, bytes/sector) per sector to the floppy control-

ler via DMA or Non-DMA modes. The entire track is format-

ted. The data block in the Data Field of each sector is filled

with the data pattern byte.

0

1

0

Execution Phase: Internal registers read.

Result Phase:

Status Register 0

Status Register 1

Status Register 2

Undefined

PTR Drive 0

PTR Drive 1

PTR Drive 2

PTR Drive 3

Step Rate Time

Motor On Time

Sector per Track/End of Track (Note)

Motor Off Time

Undefined

DMA

WG

Undefined

LOCK

0

DC3

DC2

DC1

DC0

GAP

To allow for flexible formatting, the mP must supply the four

Address Field bytes (track, head, sector, bytes per sector

code) for each sector formatted during the Execution

Phase. This allows for non-sequential sector interleaving.

This transfer of bytes from the mP to the controller can be

done in the DMA or Non-DMA mode, with the FIFO enabled

or disabled.

EIS

FIFO

POLL

THRESH

PRETRK

Note: Sectors per Track parameter returned if last command issued was

Format. End of Track parameter returned if last command issued was

Read or Write.

4.1.3 Format Track Command

The Format Gap byte in the Command Phase is dependent

on the data rate and type of disk drive, and controls the

length of GAP3. Some typical values for the programmable

GAP3 are given in Table 4-1. Figure 4-2 shows the track

format for each of the formats recognized by the format

command. Table 4-2 shows some typical values for the For-

mat GAP3 based on media type. The Format command ter-

minates when the index hole is detected a second time, at

which point an interrupt is generated. Only the first three

status bytes in the Result Phase are significant.

This command formats one track on the disk in IBM, ISO, or

Perpendicular format. After the index hole is detected, data

patterns are written on the disk including all gaps, Address

Marks, Address Fields, and Data Fields. The exact format is

determined by the following parameters:

1. The MFM bit in the Opcode (first command) byte, which

determines the format of the Address Marks and the en-

coding scheme.

2. The IAF bit in the Mode command, which selects be-

tween IBM and ISO format.

3. The WGATE and GAP bits in the Perpendicular Mode

command, which select between the conventional and

Toshiba Perpendicular format.

35

4.0 FDC Command Set Description (Continued)

TABLE 4-1. Typical Format GAP3 Length Values based on Drive Data Rate

Sector

Size

Sector

Code

(Hex)

Sector

Gap

Format

GAP3

EOT

Mode

(Hex)

(Decimal)

(Hex) (Note 1)

(Hex) (Note 2)

250 kbps

MFM

256

01

02

03

04

05

12

10

08

09

04

02

01

0A

20

2A

80

C8

0C

32

50

F0

FF

512

1024

2048

4096

500 kbps

MFM

256

512

01

02

03

04

05

06

1A

0F

12

08

04

02

01

0E

1B

35

99

C8

36

54

6C

74

FF

512

1024

2048

4096

8192

TABLE 4-2. Typical Format GAP3 Length Values Based on PC Compatible Diskette Media

Sector

Size

Sector

Code

Hex

Sector

Gap

Format

GAP3

Hex

Media

Type

EOT

Hex

Decimal

Hex

360k

1.2M

720k

512

02

09

0F

09

12

24

2A

1B

50

54

50

6C

53

1.44M

2.88M (Note 3)

Note 1: Sector Gap refers to the Intersector Gap Length parameter specified in the Command Phase of the Read, Write, Scan, and Verify commands. Although

this is the recommended value, the FDC treats this byte as a don’t care in the Read, Write, Scan, and Verify commands.

Note 2: Format Gap is the suggested value to use in the Format Gap parameter of the Format command. This is the programmable GAP3 as shown in Figure 4-1.

Note 3: The 2.88M diskette media is a Barium Ferrite media intended for use in Perpendicular Recording drives at data rates up to 1 Mbps.

36

4.0 FDC Command Set Description (Continued)

TL/C/11930–7

Notes:

16

12

5

a a

x

e

a

A1*

C2*

Data Pattern of A1, Clock Pattern of 0A

Data Pattern of C2, Clock Pattern of 14

CRC uses standard polynomial x

x

1

e

Perpendicular Format GAP2

All other data rates use GAP2

41 bytes for 1 Mbps and 2 Mbps.

e

All byte counts in decimal

All byte values in hex

22 bytes

FIGURE 4-2. IBM, Perpendicular, and ISO Formats Supported by the Format Command

37

4.0 FDC Command Set Description (Continued)

4.1.4 Invalid Command

TMR: Motor Timer mode. Default after a software reset.

e

If an invalid command (illegal Opcode byte in the Command

Phase) is received by the controller, the controller responds

with ST0 in the Result Phase. The controller does not gen-

erate an interrupt during this condition. Bits 6 and 7 in the

MSR are both set to a 1, indicating to the mP that the con-

troller is in the Result Phase and the contents of ST0 must

be read. The system reads an 80h value from ST0 indicating

an invalid command was received.

0

Timers for motor on and motor off are defined

for Mode 1. (See Specify command.)

#

e

1

Timers for motor on and motor off are defined

for Mode 2. (See Specify command.)

IAF: Index Address Format. Default after a software reset.

e

0

The controller formats tracks with the Index Ad-

dress Field included. (IBM and Perpendicular for-

mat.)

#

Command Phase:

e

1

The controller formats tracks without including

the Index Address Field. (ISO format.)

Invalid Op Codes

IPS: Implied Seek. Default after a software reset.

Execution Phase: None.

Result Phase:

e

0

The implied seek bit in the command byte of a

read, write, scan, or verify is ignored. Implied

seeks could still be enabled by the EIS bit in the

Configure command.

#

Status Register 0 (80h)

e

1

The IPS bit in the command byte of a read, write,

scan, or verify is enabled so that if it is set, the

controller performs seek and sense interrupt op-

erations before executing the command.

4.1.5 Lock Command

The Lock command allows the user full control of the FIFO

parameters after a software reset. If the LOCK bit is set to 1,

then the FIFO, THRESH, and PRETRK bits in the Configure

command are not affected by a software reset. In addition,

the FWR, FRD, and BST bits in the Mode command are

unaffected by a software reset. If the LOCK is 0 (default

after a hardware reset), then the above bits are set to their

default values after a software reset. This command is use-

ful if the system designer wishes to keep the FIFO enabled

and retain the other FIFO parameter values (such as

THRESH) after a software reset.

LOW

PWR: Low Power mode. Default after a software reset.

e

00

01

Completely disable the low power mode.

#

e

Automatic low power. For 500 kbps operation,

go into low power mode 512 ms after the head

unload timer times out. For 250 kbps operation

the timeout period is doubled to 1s.

e

10

11

Manual low power. Go into low power mode

now.

After the command byte is written, the result byte must be

read before continuing to the next command. The execution

of the Lock command is not performed until the result byte

is read by the mP. If the part is reset after the command byte

is written but before the result byte is read, then the Lock

command execution is not performed. This is done to pre-

vent accidental execution of the Lock command.

Not used.

ETR: Extended Track Range. Default after a software re-

set.

e

0

Track number is stored as a standard 8-bit value

compatible with the IBM, ISO, and Perpendicular

formats. This allows access of up to 256 tracks

during a seek operation.

#

Command Phase:

LOCK

0

1

0

1

0

1

Track number is stored as a 12-bit value. The

upper four bits of the track value are stored in

the upper four bits of the head number in the

sector Address Field. This allows access of up to

4096 tracks during a seek operation. With this bit

set, an extra byte is required in the Seek Com-

mand Phase and Sense Interrupt Result Phase.

Execution Phase: Internal Lock register is written.

Result Phase:

0

LOCK

0

4.1.6 Mode Command

FWR: FIFO Write Disable for mP write transfers to control-

ler. Default after a software reset if LOCK is 0. If

LOCK is 1, FWR retains its value after a software

reset.

This command is used to select the special features of the

controller. The bits for the Command Phase bytes are

shown in Section 4.1, Command Set Summary, and their

function is described below. These bits are set to their de-

fault values after a hardware reset. The default value of

each bit is denoted by a ‘‘bullet’’ to the left of each item. The

value of each parameter after a software reset is explained.

Note: This bit is only valid if the FIFO is enabled in the Configure

command. If the FIFO is not enabled in the Configure com-

mand, then this bit is a don’t care.

e

0

Enable FIFO. mP write transfers druing the Exe-

cution Phase use the internal FIFO.

#

Command Phase:

e

1

Disable FIFO. All write data transfers take place

without the FIFO.

0

1

0

1

ETR

0

TMR

FWR

IAF

FRD

IPS

BST

BFR

0

LOW PWR

R255

WLD

0

DENSEL

Head Settle

RG

0

PU

Execution Phase: Internal registers are written.

Result Phase: None.

38

4.0 FDC Command Set Description (Continued)

FRD: FIFO Read Disable for mP read transfers from con-

troller. Default after a software reset if LOCK is 0. If

LOCK is 1, FRD retains its value after a software re-

set.

TABLE 4-4. DENSEL Encoding

DENSEL

Pin Definition

Bit 1

Bit 0

0

1

0

1

0

1

Pin Low

Pin High

Undefined

DEFAULT

Note: This bit is only valid if the FIFO is enabled in the Configure

command. If the FIFO is not enabled in the Configure com-

mand, then this bit is a don’t care.

e

0

Enable FIFO. mP read transfers during the Exe-

cution Phase use the internal FIFO.

#

BFR: CMOS Disk Interface Buffer Enable.

e

1

Disable FIFO. All read data transfers take place

without the FIFO.

e

0

Drive output signals configured as standard 4 mA

push-pull outputs (actually 40 mA sink, 4 mA

source).

#

BST: Burst Mode Disable. Default after a software reset if

LOCK is 0. If LOCK is 1, BST retains its value after a

software reset.

e

1

Drive output signals configured as 40 mA open-

drain outputs.

Note: This bit is only valid if the FIFO is enabled in the Configure

command. If the FIFO is not enabled in the Configure com-

mand, then this bit is a don’t care.

WLD: Scan Wild Card.

e

0

An FFh from either the mP or the disk during a

Scan command is interpreted as

character that always matches true.

#

e

0

Burst mode enabled for FIFO Execution Phase

data transfers.

#

a wildcard

e

1

Non-Burst mode enabled. The DRQ or IRQ6 pin

is strobed once for each byte to be transferred

while the FIFO is enabled.

e

1

The Scan commands do not recognize FFh as a

wildcard character.

Head

R255: Recalibrate Step Pulses. The bit determines the

maximum number of recalibrate step pulses the con-

troller issues before terminating with an error. De-

fault after a software reset.

Settle: Time allowed for read/write head to settle after a

seek during an Implied Seek operation. This is con-

trolled as shown in Table 4-5 by loading a 4-bit value

for N. (The default value for N is 8.)

e

0

Maximum of 85 recalibrate step pulses. If ETR

e

1, controller issues 3925 recalibrate step

pulses maximum.

#

TABLE 4-5. Head Settle Time Calculation

Data Rate

(kbits/sec)

Multiplier

(4 Bit Value)

Head Settle

Time (ms)

e

1

Maximum of 255 recalibrate step pulses. If ETR

e

c

6.666

250

300

500

1000

N

c

N

8

0–120

0–100

0–60

1, controller issues 4095 maximum recali-

brate step pulses.

N

c

4

2

DENSEL: Density Select Pin Configuration. This 2-bit value

configures the Density Select output to one of

three possible modes. The default mode config-

ures the DENSEL pin according to the state of

the IDENT input pin after a data rate has been

selected. That is, if IDENT is high, the DENSEL

pin is active high for the 500 kbps/

1 Mbps/2 Mbps data rates. If IDENT is low, the

0–30

RG: Read Gate Diagnostic.

e

0

Enable DSKCHG disk interface input for normal

operation.

#

e

1

Enable DSKCHG to act as an external Read Gate

input signal to the Data Separator. This is intend-

ed as a test mode to aid in evaluation of the Data

Separator.

DENSEL

is

active

low

for

the

500 kbps/1 Mbps/2 Mbps data rates. See Table

4-3. In addition to these modes, the DENSEL out-

put can be set to always low or always high, as

shown in Table 4-4. This allows the user more

flexibility with new drive types.

PU: PUMP Pulse Output Diagnostic.

e

0

1

Enable MFM output pin for normal operation.

#

Enable the MFM output to act as an internal serial

data in signal.

TABLE 4-3. DENSEL Default Encoding

DENSEL Pin Definition

4.1.7 NSC Command

The NSC command can be used to distinguish between the

FDC versions and the 82077. The Result Phase byte

uniquely identifies the floppy controller as a PC87334, which

returns a value of 73h. The 82077 and DP8473 return a

value of 80h, signifying an invalid command. The lower four

bits of this result byte are subject to change by National,

and reflects the particular version of the floppy disk control-

ler part.

Data Rate

e

0

IDENT

1

IDENT

250 kbps

300 kbps

500 kbps

1 Mbps*

2 Mbps**

Low

High

Low

Command Phase:

e

*When TUP bit 1

**When TUP bit 1

0, a Data Rate of 1 Mbps is selected.

1, a Data Rate of 2 Mbps is selected.

0

1

0

Execution Phase: None.

Result Phase:

0

1

0

1

39

4.0 FDC Command Set Description (Continued)

4.1.8 Perpendicular Mode Command

Perpendicular Recording drives operate in ‘‘Extra High Den-

sity’’ mode at 1 Mbps and 2 Mbps, and are downward com-

patible with 1.44 Mbyte and 720 kbyte drives at 500 kbps

(High Density) and 250 kbps (Double Density) respectively.

If perpendicular drives are present in the system, this com-

mand should be issued during initialization of the floppy con-

troller, which configures each drive as perpendicular or con-

ventional. Then, when a drive is accessed for a Format or

Write Data command, the floppy controller adjusts the For-

mat or Write Data parameters based on the data rate select-

ed (see Table 4-6).

The Perpendicular Mode command is designed to support

the unique Format and Write Data requirements of Perpen-

dicular (Vertical) Recording disk drives (4 Mbyte unformat-

ted capacity). The Perpendicular Mode command config-

ures each of the four logical drives as a perpendicular or

conventional disk drive. Configuration of the four logical disk

drives is done via the D3–0 bits, or with the GAP and WG

control bits. This command should be issued during the ini-

tialization of the floppy controller.

Command Phase:

0

1

0

1

0

OW

DC3

DC2

DC1

DC0

GAP

WG

Execution Phase: Internal registers are written.

Result Phase: None.

TABLE 4-6. Effect of Drive Mode and Data Rate on Format and Write Commands

GAP2 Length

Written during

Format

Portion of GAP2

Drive

Mode

Data Rate

250 kbps/300 kbps/500 kbps

1 Mbps/2 Mbps

Re-Written by

Write Data Command

Conventional

Perpendicular

22 Bytes

0 Bytes

19 Bytes

Conventional

Perpendicular

22 Bytes

41 Bytes

0 Bytes

38 Bytes

TABLE 4-7. Effect of GAP and WG on Format and Write Commands

GAP2 Length

Portion of GAP2

Re-Written by

Mode

GAP

WG

Written during

Description

Format

Write Data Command

0

1

Conventional

22 Bytes

0 Bytes

Perpendicular

(500 kbps)

19 Bytes

1

0

1

Reserved

22 Bytes

41 Bytes

0 Bytes

(Conventional)

Perpendicular

38 Bytes

(1 Mbps/2 Mbps)

40

4.0 FDC Command Set Description (Continued)

Looking at the second command byte, DC3–0 corresponds

to the four logical drives.

on the bytes per sector code. In addition, the End of Track

Sector Number (EOT) should be specified, allowing the con-

troller to read multiple sectors. The Data Length byte is a

don’t care and should be set to FFh.

A 0 written to DCn sets drive n to conventional mode, and a

1 sets drive n to perpendicular mode. The OW (Overwrite)

e

bit offers additional control. When OW

DC3–0 (drive configuration bits) are changeable. When OW

1, the values of

TABLE 4-8. Sector Size Selection

e

0, the internal values of DC3–0 are unaffected, regard-

less of what is written to DC3–0.

Bytes per

Number of Bytes

in Data Field

Sector Code

The function of the DCn bits must also be qualified by set-

ting both WG and GAP to 0. If WG and GAP are used (i.e.,

not set to 00), they override whatever is programmed in the

DCn bits. Table 4-7 indicates the operation of the FDC

based on the values of GAP and WG. Note that when GAP

and WG are both 0, the DCn bits are used to configure each

logical drive as conventional or perpendicular. DC3–0 is un-

affected by a software reset, but WG and GAP are both

cleared to 0 after a software reset. A hardware reset resets

all the bits to zero (conventional mode for all drives). The

Perpendicular Mode command bits may be rewritten at any

time.

0

1

2

3

4

5

6

7

128

256

512

1024

2048

4096

8192

16384

The controller then starts the Data Separator and waits for

the Data Separator to find the next sector Address Field.

The controller compares the Address Field ID information

(track, head, sector, bytes per sector) with the desired ID

specified in the Command Phase. If the sector ID bytes do

not match, then the controller waits for the Data Separator

to find the next sector Address Field. The ID comparison

process repeats until the Data Separator finds a sector Ad-

dress Field ID that matches that in the command bytes, or

until an error occurs. Possible errors are:

Note: When in the Perpendicular Mode for any drive at any data rate select-

ed by the DC3–0 bits, write precompensation is set to zero.

Perpendicular Recording type disk drives have a Pre-Erase

Head which leads the Read/Write Head by 200 mm, which

translates to 38 bytes at the 1 Mbps data transfer rate (19

bytes at 500 kbps). The increased spacing between the two

heads requires a larger GAP2 between the Address Field

and Data Field of a sector at 1 Mbps/2 Mbps. (See Perpen-

dicular Format in Table 4-1.) This GAP2 length of 41 bytes

(at 1 Mbps/2 Mbps) ensures that the Preamble in the Data

Field is completely ‘‘pre-erased’’ by the Pre-Erase Head.

Also, during Write Data operations to a perpendicular drive,

a portion of GAP2 must be rewritten by the controller to

guarantee that the Data Field Preamble has been pre-

erased (see Table 4-6).

1. The mP aborted the command by writing to the FIFO. If

there is no disk in the drive, the controller hangs up. The

mP must then take the controller out of this hung state by

writing a byte to the FIFO. This puts the controller into the

Result Phase.

2. Two index pulses were detected since the search began,

and no valid ID has been found. If the track address ID

differs, the WT bit or BT bit (if the track address is FFh) is

set in ST2. If the head, sector, or bytes per sector code

did not match, the ND bit is set in ST1. If the Address

Field AM was never found, the MA bit is set in ST1.

4.1.9 Read Data Command

The Read Data command reads logical sectors containing a

Normal Data Address Mark (AM) from the selected drive

and makes the data available to the host mP. After the last

Command Phase byte is written, the controller simulates the

Motor On time for the selected drive internally. The user

must turn on the drive motor directly by enabling the appro-

priate drive and motor select disk interface outputs with the

Digital Output Register (DOR).

3. The Address Field was found with a CRC error. The CE

bit is set in ST1.

Once the desired sector Address Field is found, the control-

ler waits for the Data Separator to find the subsequent Data

Field for that sector. If the Data Field (normal or deleted) is

not found within the expected time, the controller terminates

the operation and enters the Result Phase (MD is set in

ST2). If a Deleted Data Mark is found and Skip Flag (SK)

was set in the Opcode command byte, the controller skips

this sector and searches for the next sector Address Field

as described above. The effect of SK on the Read Data

command is summarized in Table 4-9.

If Implied Seeks are enabled, the controller performs a Seek

operation to the track number specified in the Command

Phase. The controller also issues a Sense Interrupt for the

seek and waits the Head Settle time specified in the Mode

command.

The correct ID information (track, head, sector, bytes per

sector) for the desired sector must be specified in the com-

mand bytes. See Table 4-8 Sector Size Selection for details

41

4.0 FDC Command Set Description (Continued)

Having found the Data Field, the controller then transfers

data bytes from the disk drive to the host (described in

Section 5.3 Controller Phases) until the bytes per sector

count has been reached, or the host terminates the opera-

tion (through TC, end of track, or implicitly through overrun).

The controller then generates the CRC for the sector and

compares this value with the CRC at the end of the Data

Field.

Command Phase:

MT

IPS

MFM

X

SK

X

0

1

0

X

HD

DR1

DR0

Track Number

Drive Head Number

Sector Number

Bytes per Sector

Having finished reading the sector, the controller continues

reading the next logical sector unless one or more of the

following termination conditions occurred:

End of Track Sector Number

Intersector Gap Length

Data Length

1. The DMA controller asserted TC. The IC bits in ST0 are

set to Normal Termination.

Execution Phase: Data read from disk drive is transferred

to system via DMA or Non-DMA modes.

2. The last sector address (of side 1 if MT was set) was

equal to EOT. The EOT bit in ST1 is set. The IC bits in

ST0 are set to Abnormal Termination. This is the expect-

ed condition during Non-DMA transfers.

Result Phase:

Status Register 0

Status Register 1

Status Register 2

Track Number

3. Overrun error. The OR bit in ST1 is set. The IC bits in ST0

are set to Abnormal Termination. If the mP cannot service

a transfer request in time, the last correctly read byte is

transferred.

4. CRC error. The CE bit in ST1 and the CD bit in ST2 are

set. The IC bits in ST0 are set to Abnormal Termination.

Head Number

Sector Number

Bytes per Sector

If Multi-Track Selector (MT) was set in the Opcode com-

mand byte, and the last sector of side 0 has been trans-

ferred, the controller then continues with side 1.

Upon terminating the Execution Phase of the Read Data

command, the controller asserts IRQ6, indicating the begin-

ning of the Result Phase. The mP must then read the result

bytes from the FIFO. The values that are read back in the

result bytes are shown in Table 4-10. If an error occurs, the

result bytes indicate the sector read when the error oc-

curred.

TABLE 4-9. SK Effect on the Read Data Command

Sector Read ? CM Bit (ST2)

SK

0

Data Type

Normal

Description of Results

Normal Termination

No Further Sectors Read

Normal Termination

Sector Skipped

Y

0

Deleted

Normal

Y

N

1

0

1

Deleted

TABLE 4-10. Result Phase Termination Values with No Error

ID Information at Result Phase

Last

MT

HD

Sector

Track

Head

NC

1

Sector

Bytes/Sector

k

a

0

1

0

1

0

1

EOT

NC

S

1

NC

e

k

e

k

e

k

e

a

EOT

T

1

a

NC

a

1

a

NC

a

1

a

NC

0

T

1

e

EOT

End of Track Sector Number from Command Phase

S

T

Sector Number last operated on by controller

Track Number programmed in Command Phase

e

NC

No Change in Value

42

4.0 FDC Command Set Description (Continued)

TABLE 4-11. SK Effect on the Read Deleted Data Command

SK

0

Data Type

Normal

Sector Read ?

CM Bit (ST2)

Description of Results

No Further Sectors Read

Normal Termination

Sector Skipped

Y

N

Y

1

0

1

0

Deleted

Normal

1

Deleted

Normal Termination

4.1.10 Read Deleted Data Command

After waiting the Motor On time, the controller starts the

Data Separator and waits for the Data Separator to find the

next sector Address Field. If an error condition occurs, the

The Read Deleted Data command reads logical sectors

containing a Deleted Data AM from the selected drive and

makes the data available to the host mP. This command is

identical to the Read Data command, except for the setting

of the CM bit in ST2 and the skipping of sectors. The effect

of SK on the Read Deleted Data command is summarized in

Table 4-11. See Table 4-10 for the state of the result bytes

for a Normal Termination of the command.

IC bits in ST0 are set to Abnormal Termination, and the

controller enters the Result Phase. Possible errors are:

1. The mP aborted the command by writing to the FIFO. If

there is no disk in the drive, the controller hangs up. The

mP must then take the controller out of this hung state by

writing a byte to the FIFO. This puts the controller into the

Result Phase.

Command Phase:

2. Two index pulses were detected since the search began,

and no AM has been found. If the Address Field AM was

never found, the MA bit is set in ST1.

MT

IPS

MFM

X

SK

X

0

1

0

X

HD

DR1

DR0

Track Number

Command Phase:

Drive Head Number

Sector Number

0

MFM

X

0

1

0

1

0

X

HD

DR1

DR0

Bytes per Sector

Execution Phase: Controller reads first ID Field header

bytes it can find and reports these bytes to the system in the

result bytes.

End of Track Sector Number

Intersector Gap Length

Data Length

Result Phase:

Execution Phase: Data read from disk drive is transferred

to system via DMA or Non-DMA modes.

Status Register 0

Status Register 1

Status Register 2

Track Number

Result Phase:

Status Register 0

Status Register 1

Status Register 2

Track Number

Head Number

Sector Number

Bytes per Sector

Head Number

4.1.12 Read A Track Command

Sector Number

Bytes per Sector

The Read A Track command reads sectors in physical order

from the selected drive and makes the data available to the

host. This command is similar to the Read Data command

with the following exceptions:

4.1.11 Read ID Command

1. The controller waits for the index pulse before searching

for a sector Address Field. If the mP writes to the FIFO

before the index pulse, the command enters the Result

Phase with the IC bits in ST0 set to Abnormal Termina-

tion.

The Read ID command finds the next available Address

Field and returns the ID bytes (track, head, sector, bytes per

sector) to the mP in the Result Phase. There is no data

transfer during the Execution Phase of this command. An

interrupt is generated when the Execution Phase is complet-

ed.

2. A comparison of the sector Address Field ID bytes will be

performed, except for the sector number. The internal

sector address is set to 1, and then incremented for each

successive sector read.

The controller first simulates the Motor On time for the se-

lected drive internally. The user must turn on the drive motor

directly by enabling the appropriate drive and motor select

disk interface outputs with the Digital Output Register

(DOR). The Read ID command does not perform an implied

seek.

43

4.0 FDC Command Set Description (Continued)

3. If the Address Field ID comparison fails, the controller

sets ND in ST1, but continues to read the sector. If there

is a CRC error in the Address Field, the controller sets CE

in ST1, but continues to read the sector.

After the last command byte is issued, the DRx BUSY bit is

set in the MSR for the selected drive. The controller will

simulate the Motor On time, and then enter the Idle Phase.

The execution of the actual step pulses occur while the con-

troller is in the Drive Polling Phase. An interrupt will be gen-

erated after the TRK0 signal is asserted, or after the maxi-

mum number of recalibrate step pulses are issued. There is

no Result Phase. Recalibrates should not be issued on

more than one drive at a time. This is because the drives are

actually selected via the DOR, which can only select one

drive at a time. No other command except the Sense Inter-

rupt command should be issued while a Recalibrate com-

mand is in progress.

4. Multi-track and Skip operations are not allowed. SK and

MT should be set to 0.

5. If there is a CRC error in the Data Field, the controller

sets CE in ST1 and CD in ST2, but continues reading

sectors.

6. The controller reads a maximum of EOT physical sectors.

There is no support for multi-track reads.

Command Phase:

0

MFM

X

0

1

0

IPS

X

HD

DR1

DR0

0

1

0

1

Track Number

DR1

DR0

Drive Head Number

Sector Number

Execution Phase: Disk drive head is stepped out to Track 0.

Result Phase: None.

Bytes per Sector

4.1.14 Relative Seek Command

End of Track Sector Number

Intersector Gap Length

Data Length

The Relative Seek command steps the selected drive in or

out a given number of steps. This command will step the

read/write head an incremental number of tracks, as op-

posed to comparing against the internal present track regis-

ter for that drive.

Execution Phase: Data read from disk drive is transferred

to system via DMA or non-DMA modes.

Command Phase:

Result Phase:

1

DIR

X

0

1

Status Register 0

Status Register 1

Status Register 2

Track Number

X

HD

DR1

DR0

Execution Phase: Disk drive head stepped in or out a pro-

grammable number of tracks.

Result Phase: None.

Head Number

The Relative Seek parameters are defined as follows:

Sector Number

Bytes per Sector

DIR: Read/Write Head Step Direction Control

e

0

1

Step Head Out

Step Head In

4.1.13 Recalibrate Command

RTN: Relative Track Number. This value will determine how

many incremental tracks to step the head in or out

from the current track number.

The Recalibrate command is very similar to the Seek com-

mand. The controller sets the Present Track Register (PTR)

of the selected drive to zero. It then steps the head of the

selected drive out until the TRK0 disk interface input signal

goes active, or until the maximum number of step pulses

have been issued. See Table 4-12 for the maximum recali-

brate step pulse values based on the R255 and ETR bits in

the Mode command. If the number of tracks on the disk

drive exceeds the maximum number of recalibrate step

pulses, another Recalibrate command may need to be is-

sued.

The controller will issue RTN number of step pulses and

update the Present Track Register for the selected drive.

The one exception to this is if the TRK0 disk input goes

active, which indicates that the drive read/write head is at

the outermost track. In this case, the step pulses for the

Relative Seek are terminated, and the PTR value is set ac-

cording to the actual number of step pulses issued. The

arithmetic is done modulo 255. The DRx BUSY bit in the

MSR is set for the selected drive. The controller will simu-

late the Motor On time before issuing the step pulses. After

the Motor On time, the controller will enter the Idle Phase.

The execution of the actual step pulses occurs in the Idle

Phase of the controller.

TABLE 4-12. Maximum Recalibrate

Step Pulses Based on R255 and ETR

Maximum Recalibrate

R255

ETR

Step Pulses

85 (default)

255

After the step operation is complete, the controller will gen-

erate an interrupt. There is no Result Phase. Relative Seeks

should not be issued on more than one drive at a time. This

is because the drives are actually selected via the DOR,

which can only select one drive at a time. No other com-

mand except the Sense Interrupt command should be is-

sued while a Relative Seek command is in progress.

0

1

0

1

0

1

3925

4095

44

4.0 FDC Command Set Description (Continued)

4.1.15 Scan Commands

SCAN EQUAL

The Scan commands allow data read from the disk to be

compared against data sent from the mP, using ones com-

plement arithmetic, sector by sector.

Command Phase:

MT

IPS

MFM

X

SK

X

1

0

1

X

HD

DR1

DR0

There are three Scan commands to choose from:

Track Number

1. Scan Equal: checks to see if the scanned value of the

disk data is equal to that of the mP data. The scan con-

Drive Head Number

Sector Number

e

dition is therefore: disk data

mP data?

2. Scan Low or Equal: checks to see if the scanned val-

ue of the disk data is equal to or less than that of the mP

Bytes per Sector

s

data. The scan condition is therefore: disk data data?

End of Track Sector Number

Intersector Gap Length

Sector Step Size

3. Scan High or Equal: checks to see if the scanned val-

ue of the disk data is equal to or greater than that of the

t

mP data. The scan condition is therefore: disk data

mP data?

Execution Phase: Data transferred from system to control-

ler is compared to data read from disk.

The results of these comparisons are indicated in the Status

Register bits 3 and 2, see Table 4-13, and the structure of

the three commands follows.

Result Phase:

MT

IPS

MFM

X

SK

X

1

0

1

Each sector is compared starting with the most significant

bytes first, and where the next sector is defined as the cur-

rent Sector Number plus the Sector Step Size. Reading of

sectors continues until either the scan condition is met, the

End of Track (EOT) has been reached, or the Terminal

Count (TC) is asserted.

X

HD

DR1

DR0

Status Register 0

Status Register 1

Status Register 2

Track Number

If the Wildcard mode is enabled in the Mode command, an

FFh from either the disk or the mP is used as a don’t care

byte that will always match equal. Read errors on the disk

will have the same error conditions as the Read Data com-

mand.

Head Number

Sector Number

Bytes per Sector

Additionally, if the Skip Flag (SK) bit is set, sectors with

deleted data marks will be ignored. If all sectors read are

skipped, the command will terminate with bit 3 of the Status

Register set (mimicking a Scan Equal Hit).

SCAN HIGH OR EQUAL

Command Phase:

MT

IPS

MFM

X

SK

X

1

0

1

TABLE 4-13. Scan Command Termination Values

X

HD

DR1

DR0

Status

Comparison

Condition

Condition Indicated

Track Number

Command

Met?

Result

D3 D2

Drive Head Number

Sector Number

e

s

e

i

Scan Equal Disk Data

mP Data?

1

0

1

0

1

0

1

0

1

0

1

Yes

Disk Data

mP Data

Bytes per Sector

No

Yes

No

Disk Data

mP Data

End of Track Sector Number

Intersector Gap Length

Sector Step Size

e

k

l

e

l

k

Scan Low Disk Data

mP Data?

Disk Data

mP Data

or Equal

Disk Data

mP Data

Execution Phase: Data transferred from system to control-

ler is compared to data read from disk.

Disk Data

mP Data

Result Phase:

Status Register 0

Status Register 1

Status Register 2

Track Number

t

Scan High Disk Data

or Equal mP Data?

Yes

No

Disk Data

mP Data

Disk Data

mP Data

Head Number

Disk Data

mP Data

Sector Number

Bytes per Sector

45

4.0 FDC Command Set Description (Continued)

SCAN LOW OR EQUAL

Command Phase:

0

1

X

HD

DR1

DR0

MT

IPS

MFM

X

SK

X

1

0

1

New Track Number

MSN of Track Number

X

HD

DR1

DR0

0

Track Number

Note: The last Command Phase byte is required only if ETR is set in Mode

Drive Head Number

Sector Number

Command.

Execution Phase: Disk drive head is stepped in or out to a

programmed track.

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Sector Step Size

Result Phase: None.

4.1.17 Sense Drive Status Command

The Sense Drive Status command returns the status of the

selected disk drive in ST3. This command does not gener-

ate an interrupt.

Execution Phase: Data transferred from system to control-

ler is compared to data read from disk.

Result Phase:

Command Phase:

Status Register 0

Status Register 1

Status Register 2

Track Number

0

1

0

X

HD

DR1

DR0

Execution Phase: Disk drive status information is detected

and reported.

Head Number

Result Phase:

Sector Number

Bytes per Sector

Status Register 3

4.1.16 Seek Command

4.1.18 Sense Interrupt Command

The Seek command steps the selected drive in or out until

the desired track number is reached. During the Execution

Phase of the Seek command, the track number to seek to is

compared with the present track number. The controller will

determine how many step pulses to issue, and the DIR disk

interface output will indicate which direction the R/W head

should move. The DRx BUSY bit is set in the MSR for the

appropriate drive. The controller will wait the Motor On time

before issuing the first step pulse.

The Sense Interrupt command is used to determine the

cause of an interrupt when the interrupt is a result of the

change in status of any disk drive.

Command Phase:

0

1

0

Execution Phase: Status of interrupt is reported.

Result Phase:

After the Motor On time, the controller will enter the Idle

Phase. The execution of the actual step pulses occurs in the

Drive Polling phase of the controller. The step pulse rate is

determined by the value programmed in the Specify com-

mand. An interrupt will be generated one step pulse period

after the last step pulse is issued. A Sense Interrupt com-

mand should be issued to determine the cause of the inter-

rupt. There is no Result Phase.

Status Register 0

Present Track Number (PTR)

MSN of PTR

0

Note: The third Result Phase byte can only be read if ETR is set in the Mode

Command.

Four possible causes for the interrupt are:

1. Entry into the Result Phase of any of the following com-

mands:

While the internal microengine is capable of performing

seek commands on 2 or more drives at the same time, soft-

ware should ensure that only one drive is seeking at a time.

This is because the drives are actually selected via the

DOR, which can only select one drive at a time. No other

command except a Sense Interrupt command should be is-

sued while a Seek command is in progress.

a. Read Data

b. Read Deleted Data

c. Read a Track

d. Read ID

e. Write Data

f. Write Deleted Data

g. Format

If the extended track range mode is enabled with the ETR

bit in the Mode command, a fourth command byte should be

written in the Command Phase to indicate the four most

significant bits of the desired track number. Otherwise, only

three command bytes should be written.

h. Scan

i. Verify

2. Occurrence of a data transfer in the Execution Phase

while in the Non-DMA mode.

46

4.0 FDC Command Set Description (Continued)

3. The Ready Signal changed state during the polling mode

for an internally selected drive. (Occurs only after a hard-

ware or software reset.)

TABLE 4-15. Set Track Register Address

DS1

DS0

MSB

Register Addressed

4. A Seek, Relative Seek, or Recalibrate command termi-

nates.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PTR0 (LSB)

PTR0 (MSB)

PTR1 (LSB)

PTR1 (MSB)

PTR2 (LSB)

PTR2 (MSB)

PTR3 (LSB)

PTR3 (MSB)

An interrupt due to reasons 1 or 2 does not require the

Sense Interrupt command and is cleared automatically. This

type of interrupt occurs during normal command operations

and is easily discernible by the mP via the MSR. It is cleared

when reading or writing information from or to the Data Reg-

ister (FIFO).

An interrupt caused by reasons 3 or 4 is identified with the

aid of the Sense Interrupt command. This type of interrupt is

Command Phase:

cleared after the first result byte has been read. Use bits 5,

6, and 7 of ST0 to identify the cause of the interrupt as

shown in Table 4-14.

0

WNR

0

1

0

1

MSB

DS1

DS0

Issuing a Sense Interrupt command without an interrupt

pending is treated as an Invalid command. If the extended

track range mode is enabled, a third byte should be read in

the Result Phase, which will indicate the four most signifi-

cant bits of the present track number. Otherwise, only two

result bytes should be read.

Present Track Number (PTR)

Execution Phase: Internal register selected by MSB of DS1

or DS0 is read or written.

Result Phase:

Value

TABLE 4-14. Status Register 0 Termination Codes

Status Register 0

4.1.20 Specify Command

Interrupt

Code

Seek

End

The Specify command sets the initial values for three inter-

nal timers. The parameters of this command are undefined

after power-up, and are unaffected by any reset. Thus, soft-

ware should always issue a Specify command as part of an

initialization routine. This command does not generate an

interrupt.

Cause

D7

D6

1

D5

0

1

0

Internal Ready Went True

Normal Seek Termination

Abnormal Seek Termination

0

1

Command Phase:

1

0

1

4.1.19 Set Track Command

Step Rate Time

Motor On Time

Motor Off Time

This command is used to inspect or change the value of the

internal Present Track Register. This can be useful for re-

covery from disk mistracking errors, where the real current

track can be read through the Read ID command, and then

the Set Track command can be used to set the internal

Present Track Register to the correct value.

DMA

Execution Phase: Internal registers are written.

Result Phase: None.

Step Rate Time: These four bits define the time interval

between successive step pulses during a seek, implied

seek, recalibrate, or relative seek. The programming of this

step rate is shown in Table 4-16.

If the WNR bit is a 0, a track register is to be read. In this

case, the Result Phase byte contains the value in the inter-

nal register specified, and the third byte in the Command

Phase is a dummy byte.

TABLE 4-16. Step Rate Time (SRT) Values

If the WNR bit is a 1, data is written to a track register. In this

case the third byte of the Command Phase is written to the

specified internal track register, and the Result Phase byte

contains this new value.

Data Rate

Value

Range

Units

b

1 Mbps

500 kbps

300 kbps

250 kbps

(16 SRT)/2

0.5–8

1–16

ms

(16 SRT)

c

(16 SRT) 1.67

1.67–26.7

2–32

The DS1 and DS0 bits select the Present Track Register for

the particular drive. The internal register address depends

on MSB, DS1, and DS0 as shown in Table 4-15. This com-

mand does not generate an interrupt.

b

(16 SRT)

c

2

Motor Off Time: These four bits determine the simulated

Motor Off time as shown in Table 4-17.

Motor On Time: These seven bits determine the simulated

Motor On time as shown in Table 4-18.

DMA: This bit selects the data transfer mode in the Execu-

tion Phase of a read, write, or scan operation.

e

0

1

DMA mode is selected

Non-DMA mode is selected

47

4.0 FDC Command Set Description (Continued)

TABLE 4-17. Motor Off Time (MFT) Values

e

1)

Mode 1 (TMR

Value

0)

Range

Mode 2 (TMR

Value

Units

Data Rate

Range

c

MFT 512

1 Mbps

500 kbps

MFT

8

8–128

16–256

26.7–427

32–512

512–8192

853–13653

ms

c

MFT 16

c

MFT 512

c

MFT 80/3

c

MFT 2560/3

300 kbps

c

MFT 32

c

MFT 1024

250 kbps

1024–16384

e

16.

Note: Motor Off Time

0 is treated as MFT

TABLE 4-18. Motor On Time (MNT) Values

e

1)

Mode 1 (TMR

Value

0)

Range

Mode 2 (TMR

Value

Units

Data Rate

Range

c

MNT 32

1 Mbps

500 kbps

MNT

1–128

32–4096

53–6827

64–8192

ms

c

MNT 32

c

MNT 10/3

c

MNT 160/3

300 kbps

3.3–427

4–512

c

MNT 64

250 kbps

MNT

4

e

128.

Note: Motor On Time

0 is treated as MNT

The Motor Off and Motor On timers are artifacts of the NEC

mPD765. These timers determine both the delay from se-

lecting a drive motor until a read or write operation is start-

ed, and the delay of deselecting the drive motor after the

command is completed. Since the FDC enables the drive

and motor select line directly through the DOR, these timers

only provide some delay from the initiation of a command

until it is actually started.

EOT is equal to the last sector to be checked. In this case,

the Data Length parameter should be set to FFh. Refer to

Table 4-10 for the Result Phase values for a successful

completion of the command. Also see Table 4-19 for further

explanation of the result bytes with respect to the MT and

EC bits.

Command Phase:

MT

EC

MFM

X

SK

X

1

0

1

0

4.1.21 Verify Command

X

HD

DR1

DR0

The Verify command reads logical sectors containing a Nor-

mal Data AM from the selected drive without transferring

the data to the host. This command is identical to the Read

Data command, except that no data is transferred during

the Execution Phase.

Track Number

Drive Head Number

Sector Number

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

The Verify command is designed for post-format or post-

write verification. Data is read from the disk, as the control-

ler checks for valid Address Marks in the Address and Data

Fields. The CRC is computed and checked against the pre-

viously stored value on the disk. The EOT value should be

set to the final sector to be checked on each side. If EOT is

greater than the number of sectors per side, the command

will terminate with an error and no useful Address Mark or

CRC data will be given.

Data Length/Sector Count

Execution Phase: Data is read from disk but not transferred

to the system.

Result Phase:

Status Register 0

Status Register 1

Status Register 2

Track Number

The TC pin cannot be used to terminate this command

since no data is transferred. The verify command can simu-

late a TC by setting the EC bit to a 1. In this case, the

command will terminate when SC (Sector Count) sectors

Head Number

Sector Number

Bytes per Sector

e

0, then the command will terminate when

have been read. (If SC

e

0 then 256 sectors will be veri-

fied.) If EC

48

4.0 FDC Command Set Description (Continued)

TABLE 4-19. Verify Command Result Phase

MT

EC

SC/EOT Value (Notes 1, 2)

Termination Result

0

DTL used (should be FFh)

s

No Errors

Ý

EOT

Sectors per Side

0

1

DTL used (should be FFh)

l

Abnormal Termination

No Errors

Ý

EOT

Sectors per Side

s

Ý

SC

Sectors per Side

AND

s

SC EOT

l

Ý

0

1

SC

Sectors Remaining

OR

Abnormal Termination

l

SC EOT

1

0

1

DTL used (should be FFh)

s

No Errors

Abnormal Termination

No Errors

Ý

EOT

Sectors per Side

DTL used (should be FFh)

l

Ý

EOT

Sectors per Side

s

Ý

SC

Sectors per Side

AND

s

SC EOT

s

SC (EOT 2)

c

1

No Errors

AND

s

Ý

EOT

Sectors per Side

l

SC (EOT 2)

c

Abnormal Termination

e

number of formatted sectors per each side of the disk.

Ý

Note 1:

Note 2:

Sectors per Side

e

Sectors Remaining

number of formatted sectors remaining which can be read, which includes side 1 of the disk if the MT bit is set to 1.

1 and the SC value is greater than the number of remaining formatted sectors on side 0, verifying will continue on side 1 of the disk.

e

Note 3: If MT

49

4.0 FDC Command Set Description (Continued)

4.1.22 Version Command

The mP must then take the controller out of this hung

state by writing a byte to the FIFO. This will put the con-

troller into the Result Phase.

The Version command can be used to determine the floppy

controller being used. The Result Phase uniquely identifies

the floppy controller version. The FDC returns a value of

90h in order to be compatible with the 82077. The DP8473

and other NEC765 compatible controllers will return a value

of 80h (invalid command).

2. Two index pulses were detected since the search began,

and no valid ID has been found. If the track address ID

differs, the WT bit or BT bit (if the track address is FFh)

will be set in ST2. If the head, sector, or bytes per sector

code did not match, the ND bit is set in ST1. If the Ad-

dress Field AM was never found, the MA bit is set in ST1.

Command Phase:

0

1

0

3. The Address Field was found with a CRC error. The CE

bit is set in ST1.

Execution Phase: None.

4. If the controller detects the Write Protect disk interface

input is Asserted. Bit 1 of ST1 is set.

Result Phase:

If the correct Address Field is found, the controller waits for

all (conventional mode) or part (perpendicular mode) of

GAP2 to pass. The controller will then write the preamble

field, address marks, and data bytes to the Data Field. The

data bytes are transferred to the controller by the mP.

1

0

1

0

4.1.23 Write Data Command

The Write Data command receives data from the host and

writes logical sectors containing a Normal Data AM to the

selected drive. The operation of this command is similar to

the Read Data command except that the data is transferred

from the mP to the controller instead of the other way

around.

Having finished writing the sector, the controller will contin-

ue reading the next logical sector unless one or more of the

following termination conditions has occurred:

1. The DMA controller asserted TC. The IC bits in ST0 are

set to Normal Termination.

The controller will simulate the Motor On time before start-

ing the operation. If implied seeks are enabled, the seek and

sense interrupt functions are then performed. The controller

then starts the Data Separator and waits for the Data Sepa-

rator to find the next sector Address Field. The controller

compares the Address ID (track, head, sector, bytes per

sector) with the desired ID specified in the Command

Phase. If there is no match, the controller waits to find the

next sector Address Field. This process continues until the

desired sector is found. If an error condition occurs, the IC

bits in ST0 are set to Abnormal Termination, and the con-

troller enters the Result Phase. Possible errors are:

2. The last sector address (of side 1 if MT was set) was

equal to EOT. The EOT bit in ST1 is set. The IC bits in

ST0 are set to Abnormal Termination. This is the expect-

ed condition during Non-DMA transfers.

3. Underrun error. The OR bit in ST1 is set. The IC bits in

ST0 are set to Abnormal Termination. If the mP cannot

service a transfer request in time, the last correctly writ-

ten byte will be written to the disk.

If MT was set in the Opcode command byte, and the last

sector of side 0 has been transferred, the controller will then

continue with side 1.

1. The mP aborted the command by writing to the FIFO. If

there is no disk in the drive, the controller will hang up.

50

4.0 FDC Command Set Description (Continued)

Command Phase:

4.1.24 Write Deleted Data

The Write Deleted Data command receives data from the

host and writes logical sectors containing a Deleted Data

AM to the selected drive. This command is identical to the

Write Data command except that a Deleted Data AM is writ-

ten to the Data Field instead of a Normal Data AM.

MT

IPS

MFM

X

0

1

0

1

X

HD

DR1

DR0

Track Number

Drive Head Number

Sector Number

Command Phase:

Bytes per Sector

MT

IPS

MFM

X

0

1

0

1

End of Track Sector Number

Intersector Gap Length

Data Length

X

HD

DR1

DR0

Track Number

Drive Head Number

Sector Number

Execution Phase: Data is transferred from the system to

the controller via DMA or Non-DMA modes and written to

the disk.

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Data Length

Result Phase:

Status Register 0

Status Register 1

Status Register 2

Track Number

Execution Phase: Data is transferred from the system to

the controller via DMA or Non-DMA modes and written to

the disk.

Head Number

Result Phase:

Sector Number

Bytes per Sector

Status Register 0

Status Register 1

Status Register 2

Track Number

Head Number

Sector Number

Bytes per Sector

51

4.0 FDC Command Set Description (Continued)

4.2 COMMAND SET SUMMARY

Result Phase:

Status Register 0

Status Register 1

Status Register 2

Undefined

CONFIGURE

Command Phase:

0

1

0

1

0

1

0

Undefined

EIS

FIFO

POLL

PRETRK

THRESH

Undefined

Execution Phase: Internal registers written.

Result Phase: None.

INVALID

Command Phase:

Invalid Op Codes

DUMPREG

Command Phase:

Execution Phase: None.

Result Phase:

0

1

0

Status Register 0 (80h)

Execution Phase: Internal registers read.

Result Phase:

LOCK

PTR Drive 0

PTR Drive 1

PTR Drive 2

PTR Drive 3

Command Phase:

LOCK

0

1

0

1

0

Execution Phase: Internal Lock register is written.

Step Rate Time

Motor On Time

Sector per Track/End of Track (Note)

Motor Off Time

Result Phase:

DMA

WG

0

LOCK

0

LOCK

0

DC3

DC2

DC1

DC0

GAP

MODE

EIS

FIFO

POLL

THRESH

PRETRK

Command Phase:

Note: Sectors per Track parameter returned if last command issued was

Format. End of Track parameter returned if last command issued was

Read or Write.

0

1

ETR

0

TMR

FWR

IAF

FRD

IPS

BST

BFR

0

LOW PWR

1

0

R255

WLD

0

FORMAT TRACK

Command Phase:

DENSEL

Head Settle

RG

0

PU

Execution Phase: Internal registers are written.

Result Phase: None.

0

MFM

X

0

1

0

1

X

HD

DR1

DR0

Bytes per Sector

NSC

Sectors per Track

Format Gap

Command Phase:

Data Pattern

0

1

0

1

0

1

Execution Phase: System transfers four ID bytes (track,

head, sector, bytes/sector) per sector to the floppy control-

ler via DMA or Non-DMA modes. The entire track is format-

ted. The data block in the Data Field of each sector is filled

with the data pattern byte.

Execution Phase: None.

Result Phase:

0

1

PERPENDICULAR MODE

Command Phase:

0

1

0

1

0

OW

DC3

DC2

DC1

DC0

GAP

WG

Execution Phase: Internal registers are written.

Result Phase: None.

52

4.0 FDC Command Set Description (Continued)

READ DATA

READ ID

Command Phase:

MT

IPS

MFM

X

SK

X

0

1

0

MFM

X

0

1

0

1

0

X

HD

DR1

DR0

X

HD

DR1

DR0

Track Number

Execution Phase: Controller reads first ID Field header

bytes it can find and reports these bytes to the system in the

result bytes.

Drive Head Number

Sector Number

Result Phase:

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Data Length

Status Register 0

Status Register 1

Status Register 2

Track Number

Execution Phase: Data read from disk drive is transferred

to system via DMA or Non-DMA modes.

Head Number

Sector Number

Bytes per Sector

Result Phase:

Status Register 0

Status Register 1

Status Register 2

Track Number

READ A TRACK

Command Phase:

Head Number

0

MFM

X

0

1

0

Sector Number

Bytes per Sector

IPS

X

HD

DR1

DR0

Track Number

Drive Head Number

Sector Number

READ DELETED DATA

Command Phase:

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Data Length

MT

IPS

MFM

X

SK

X

0

1

0

X

HD

DR1

DR0

Track Number

Execution Phase: Data read from disk drive is transferred

to system via DMA or non-DMA modes.

Drive Head Number

Sector Number

Result Phase:

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Data Length

Status Register 0

Status Register 1

Status Register 2

Track Number

Execution Phase: Data read from disk drive is transferred

to system via DMA or Non-DMA modes.

Head Number

Sector Number

Bytes per Sector

Result Phase:

Status Register 0

Status Register 1

Status Register 2

Track Number

RECALIBRATE

Command Phase:

0

1

0

1

Head Number

DR1

DR0

Sector Number

Bytes per Sector

Execution Phase: Disk drive head is stepped out to Track 0.

Result Phase: None.

53

4.0 FDC Command Set Description (Continued)

RELATIVE SEEK

Result Phase:

Command Phase:

Status Register 0

Status Register 1

Status Register 2

Track Number

1

DIR

X

0

1

X

HD

DR1

DR0

Execution Phase: Disk drive head stepped in or out a pro-

grammable number of tracks.

Head Number

Sector Number

Bytes per Sector

Result Phase: None.

SCAN EQUAL

SCAN LOW OR EQUAL

Command Phase:

MT

IPS

MFM

X

SK

X

1

0

1

MT

IPS

MFM

X

SK

X

1

0

1

X

HD

DR1

DR0

X

HD

DR1

DR0

Track Number

Drive Head Number

Sector Number

Drive Head Number

Sector Number

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Sector Step Size

End of Track Sector Number

Intersector Gap Length

Sector Step Size

Execution Phase: Data transferred from system to control-

ler is compared to data read from disk.

Execution Phase: Data transferred from system to control-

ler is compared to data read from disk.

Result Phase:

MT

IPS

MFM

X

SK

X

1

0

1

Status Register 0

Status Register 1

Status Register 2

Track Number

X

HD

DR1

DR0

Status Register 0

Status Register 1

Status Register 2

Track Number

Head Number

Sector Number

Bytes per Sector

Head Number

Sector Number

Bytes per Sector

SEEK

SCAN HIGH OR EQUAL

Command Phase:

0

1

X

HD

DR1

DR0

MT

IPS

MFM

X

SK

X

1

0

1

New Track Number

MSN of Track Number

X

HD

DR1

DR0

0

Track Number

Note: The last Command Phase byte is required only if ETR is set in Mode

Drive Head Number

Sector Number

Command.

Execution Phase: Disk drive head is stepped in or out to a

programmed track.

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Sector Step Size

Result Phase: None.

Execution Phase: Data transferred from system to control-

ler is compared to data read from disk.

54

4.0 FDC Command Set Description (Continued)

SENSE DRIVE STATUS

VERIFY

Command Phase:

0

1

0

MT

EC

MFM

X

SK

X

1

0

1

0

X

HD

DR1

DR0

X

HD

DR1

DR0

Track Number

Execution Phase: Disk drive status information is detected

and reported.

Drive Head Number

Sector Number

Result Phase:

Bytes per Sector

Status Register 3

End of Track Sector Number

Intersector Gap Length

SENSE INTERRUPT

Command Phase:

Data Length/Sector Count

Execution Phase: Data is read from disk but not transferred

to the system.

0

1

0

Execution Phase: Status of interrupt is reported.

Result Phase:

Status Register 0

Status Register 1

Status Register 2

Track Number

Status Register 0

Present Track Number (PTR)

MSN of PTR

0

Note: The third Result Phase byte can only be read if ETR is set in the Mode

Head Number

Command.

Sector Number

Bytes per Sector

SET TRACK

Command Phase:

VERSION

0

WNR

0

1

0

1

0

1

Command Phase:

MSB

DS1

DS0

0

1

0

Present Track Number (PTR)

Execution Phase: None.

Execution Phase: Internal register selected by MSB of DS1

or DS0 is read or written.

Result Phase:

1

0

Value

SPECIFY

Command Phase:

0

1

Step Rate Time

Motor On Time

Motor Off Time

DMA

Execution Phase: Internal registers are written.

Result Phase: None.

55

4.0 FDC Command Set Description (Continued)

WRITE DATA

WRITE DELETED DATA

Command Phase:

MT

IPS

MFM

X

0

1

0

1

MT

IPS

MFM

X

0

1

0

1

X

HD

DR1

DR0

X

HD

DR1

DR0

Track Number

Drive Head Number

Sector Number

Drive Head Number

Sector Number

Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Data Length

End of Track Sector Number

Intersector Gap Length

Data Length

Execution Phase: Data is transferred from the system to

the controller via DMA or Non-DMA modes and written to

the disk.

Execution Phase: Data is transferred from the system to

the controller via DMA or Non-DMA modes and written to

the disk.

Result Phase:

Status Register 0

Status Register 1

Status Register 2

Track Number

Status Register 0

Status Register 1

Status Register 2

Track Number

Head Number

Sector Number

Bytes per Sector

Sector Number

Bytes per Sector

56

4.0 FDC Command Set Description (Continued)

4.3 MNEMONIC DEFINITIONS FOR FDC COMMANDS

LOW PWR Low Power control bits used in the Mode com-

mand.

Symbol

Description

MFM

Modified Frequency Modulation control bit

used in the Read, Write, Format, Scan and

Verify commands. Selects MFM or FM data

encoding.

BFR

Buffer enable bit used in the Mode command.

Enabled open-collector output buffers.

BST

Burst Mode disable control bit used in Mode

command. Selects the Non-Burst FIFO mode if

the FIFO is enabled.

MFT

Motor Off Time programmed in the Specify

command.

DC0–3

Drive Configuration 0–3. Used to set DC1a

drive to conventional or perpendicular DC2

mode. Used in Perpendicular Mode DC3 com-

mand.

MNT

MT

Motor On Time programmed in the Specify

command.

Multi-Track enable bit used in the Read, Write,

Scan and Verify commands.

DENSEL

DIR

Density Select control bits used in the Mode

command.

OW

Overwrite control bit used in the Perpendicular

Mode command.

Direction control bit used in Relative Seek

command to indicate step in or out.

POLL

PRETRK

PTR

Enable Drive Polling bit used in the Configure

command.

DMA

DR0–1

DTL

DMA mode enable bit used in the Specify com-

mand.

Precompensation Track Number used in the

Configure command.

Drive Select 0–1 bits used in most commands.

Selects the logical drive.

Present Track Register. Contains the internal

track number for one of the four logical disk

drives.

Data Length parameter used in the Read,

Write, Scan and Verify commands.

PU

Pump diagnostic enable bit used in the Mode

command.

EC

Enable Count control bit used in the Verify

command. When this bit is 1, the DTL parame-

ter becomes SC (Sector Count).

R255

Recalibrate control bit used in Mode com-

mand. Sets maximum recalibrate step pulses

to 255.

EIS

Enable Implied Seeks. Used in the Configure

command.

RG

RTN

SC

Read Gate diagnostic enable bit used in the

Mode command.

EOT

ETR

FIFO

End of Track parameter set in the Read, Write,

Scan, and Verify commands.

Relative Track Number used in the Relative

Seek command.

Extended Track Range used with the Seek

command.

Sector Count control bit used in the Verify

command.

First-In First-Out buffer. Also a control bit used

in the Configure command to enable or disable

the FIFO.

SK

Skip control bit used in read and scan opera-

tions.

FRD

FWR

GAP

HD

FIFO Read disable control bit used in the

Mode command.

SRT

Step Rate Time programmed in the Specify

command. Determines the time between step

pulses for seek and recalibrates.

FIFO Write disable control bit used in the

Mode command.

ST0–3

Status Register 0–3. Contains status ST1 in-

formation about the execution of an ST2 com-

mand. Read in the Result Phase of some ST3

commands.

GAP2 control bit used in the Perpendicular

Mode command.

Head Select control bit used in most com-

mands. Selects Head 0 or 1 of the disk.

THRESH

TMR

FIFO threshold parameter used in the Config-

ure command.

IAF

Index Address Field control bit used in the

Mode command. Enables the ISO Format dur-

ing the Format command.

Timer control bit used in the Mode command.

Affects the timers set in the Specify command.

IPS

Implied Seek enable bit used in the Mode,

Read, Write, and Scan commands.

WG

Write Gate control bit used in the Perpendicu-

lar Mode command.

LOCK

Lock enable bit in the Lock command. Used to

make certain parameters be unaffected by a

software reset.

WLD

Wildcard bit in the Mode command used to en-

able or disable the wildcard byte (FF) during

Scan commands.

57

5.0 FDC Functional Description

The PC87332 is software compatible with the DP8473 and

82077 floppy disk controllers. Upon a power-on reset, the

16 byte FIFO will be disabled. Also, the disk interface out-

puts will be configured as active push-pull outputs, which

are compatible with both CMOS inputs and open-collector

resistor terminated disk drive inputs. The FIFO can be en-

abled with the Configure command. The FIFO can be very

useful at the higher data rates, with systems that have a

large amount of DMA bus latency, or with multi-tasking sys-

tems such as the EISA or MicroChannel bus structures.

5.3 CONTROLLER PHASES

The FDC has three separate phases of a command, the

Command Phase, the Execution Phase, and the Result

Phase. Each of these controller phases determine how data

is transferred between the floppy controller and the host

microprocessor. In addition, when no command is in prog-

ress, the controller is in the Idle Phase or Drive Polling

Phase.

5.3.1 Command Phase

The FDC will support all the DP8473 Mode command fea-

tures as well as some additional features. Additional fea-

tures include control over the enabling of the FIFO for reads

and writes, a Non-Burst mode for the FIFO, a bit that will

configure the disk interface outputs as open-drain outputs,

and programmability of the DENSEL output.

During the Command Phase, the mP writes a series of bytes

to the Data Register. The first command byte contains the

opcode for the command, and the controller knows how

many more bytes to expect based on this opcode byte. The

remaining command bytes contain the particular parameters

required for the command. The number of command bytes

varies for each particular command. All the command bytes

must be written in the order specified in the Command De-

scription Table. The Execution Phase starts immediately af-

ter the last byte in the Command Phase is written. Prior to

performing the Command Phase, both the Digital Output

Register and the data rate should be set with the Data Rate

Select Register or Configuration Control Register.

5.1 MICROPROCESSOR INTERFACE

The FDC interface to the microprocessor consists of the

A9–3, AEN, RD, and WR lines, which access the chip for

reads and writes; the data lines D7–0; the address

lines A2–0, which select the appropriate register (see

Table 3-1); the IRQ6 signal, and the DMA interface signals

DRQ, DACK, and TC. It is through this microprocessor inter-

face that the floppy controller receives commands, transfers

data, and returns status information.

The Main Status Register controls the flow of command

bytes, and must be polled by the software before writing

each Command Phase byte to the Data Register. Prior to

writing a command byte, the RQM bit (D7) must be set and

the DIO bit (D6) must be cleared in the MSR. After the first

command byte is written to the Data Register, the CMD

PROG bit (D4) is also set and remains set until the last

Result Phase byte is read. If there is no Result Phase, the

CMD PROG bit is cleared after the last command byte is

written.

5.2 MODES OF OPERATION

The FDC has three modes of operation: PC-AT mode, PS/2

mode, and Model 30 mode, which are determined by the

state of the IDENT pin and MFM pin. IDENT can be tied

directly to V

or GND. The MFM pin must be tied high or

DD

low with a 10k resistor (there is an internal 40k–50k resistor

on the MFM pin). The state of these pins is interrogated by

the controller during a chip reset to determine the mode of

operation. See Section 3.0 FDC Register Description, for

more details on the register set used for each mode of oper-

ation. After chip reset, the state of IDENT can be changed

to change the polarity of DENSEL (see Section 1.0 Pin De-

scription).

A new command may be initiated after reading all the result

bytes from the previous command. If the next command

requires selecting a different drive or changing the data rate,

the DOR and DSR or CCR should be updated. If the com-

mand is the last command, the software should deselect the

drive.

Note: As a general rule, the operation of the controller core is independent

of how the mP updates the DOR, DSR, and CCR. The software must

ensure that the manipulation of these registers is coordinated with the

controller operation.

PC-AT ModeÐ(IDENT tied high, MFM is a don’t care): The

PC-AT register set is enabled. The DMA enable bit in the

Digital Output Register becomes valid (IRQ6 and DRQ can

be TRI-STATE). TC and DENSEL become active high sig-

5.3.2 Execution Phase

nals (defaults to a 5.25 floppy drive).

×

During the Execution Phase, the disk controller performs

the desired command. Commands that involve data trans-

fers (e.g., read, write, or format operation) require the mP to

write or read data to or from the Data Register at this time.

Some commands such as a Seek or Recalibrate control the

read/write head movement on the disk drive during the Exe-

cution Phase via the disk interface signals. Execution of oth-

er commands does not involve any action by the mP or disk

drive, and consists of an internal operation by the controller.

PS/2 ModeÐ(IDENT tied low, MFM pulled high internally):

This mode supports the PS/2 Models 50/60/80 configura-

tion and register set. The DMA enable bit in the Digital Out-

put Register becomes a don’t care (IRQ6 and DRQ signals

are always valid). TC and DENSEL become active low sig-

nals (default to 3.5 floppy drive).

×

Model 30 ModeÐ(IDENT tied low, MFM pulled low exter-

nally): This mode supports the PS/2 Model 30 configuration

and register set. The DMA enable bit in the Digital Output

Register becomes valid (IRQ6 and DRQ can be

TRI-STATE). TC is active high and DENSEL becomes ac-

If there is data to be transferred between the mP and the

controller during the Execution Phase, there are three meth-

ods that can be used: DMA mode, interrupt transfer mode,

and software polling mode. The last two modes are called

the Non-DMA modes. The DMA mode is used if the system

has a DMA controller. This allows the mP to do other tasks

while the data transfer takes place during the Execution

Phase. If the Non-DMA mode is used, an interrupt is issued

for each byte transferred during the Execution Phase. Also,

tive low (default to 3.5 floppy drive).

×

58

5.0 FDC Functional Description (Continued)

instead of using the interrupt during Non-DMA mode, the

Main Status Register can be polled by software to indicate

when a byte transfer is required. All of these data transfer

modes work with the FIFO enabled or disabled.

threshold trigger condition. This guarantees that all the cur-

rent sector bytes are read from the FIFO before the next

sector byte transfer begins.

Write Data Transfers

Whenever the number of bytes in the FIFO is less than or

equal to THRESH, a DRQ is generated. This is the trigger

condition for the FIFO write data transfers from the mP to

the floppy controller.

5.3.2.1 DMA ModeÐFIFO Disabled

The DMA mode is selected by writing a 0 to the DMA bit in

the Specify command and by setting the DMA enabled bit

(D3) in the DOR. With the FIFO disabled, a DMA request

(DRQ) is generated in the Execution Phase when each byte

is ready to be transferred. The DMA controller should re-

spond to the DRQ with a DMA acknowledge (DACK) and a

read or write strobe. The DRQ is cleared by the leading

edge of the active low DACK input signal. After the last byte

is transferred, an interrupt is generated, indicating the begin-

ning of the Result Phase. During DMA operations the chip

select input (CS) must be held high. The DACK signal acts

as the chip select for the FIFO in this case, and the state of

the address lines A2–A0 is a don’t care. The Terminal

Count (TC) signal can be asserted by the DMA controller to

terminate the data transfer at any time. Due to internal gat-

ing, TC is only recognized when DACK is low.

Burst Mode. DRQ remains active until enough bytes have

been written to the controller to completely fill the FIFO.

Non-Burst Mode. DRQ is deasserted after each write

transfer. If the FIFO is not full DRQ is reasserted after a 350

ns delay. This deassertion of DRQ allows other higher priori-

ty DMA transfers to take place between floppy transfers.

The FIFO has a byte counter which monitors the number of

bytes being transferred to the FIFO during write operations

for both Burst and Non-Burst modes. When the last byte of

a sector is transferred to the FIFO, DRQ is deasserted even

if the FIFO has not been completely filled. Thus, the FIFO is

cleared after each sector is written. Only after the floppy

controller has determined that another sector is to be writ-

ten is DRQ asserted again. Also, since DRQ is deasserted

immediately after the last byte of a sector is written to the

FIFO, the system does not need to tolerate any DRQ deas-

sertion delay and is free to do other work.

PC-AT Mode. When in the PC-AT interface mode with the

FIFO disabled, the controller is in single byte transfer mode.

That is, the system has one byte time to service a DMA

request (DRQ) from the controller. DRQ is deasserted be-

tween each byte.

Read and Write Data Transfers

PS/2 and Model 30 Modes. When in the PS/2 or Model 30

modes, DMA transfers with the FIFO disabled are per-

formed differently. Instead of a single byte transfer mode,

The DACK input signal from the DMA controller may be held

active during an entire burst or it may be strobed for each

byte transferred during a read or write operation. When in

the Burst mode, the floppy controller deasserts DRQ as

soon as it recognizes that the last byte of a burst was trans-

ferred. If DACK is strobed for each byte, the leading edge of

this strobe is used to deassert DRQ. If DACK is strobed, RD

or WR is not required. This is the case during the Read-Veri-

fy mode of the DMA controller. If DACK is held active during

the entire burst, the trailing edge of the RD or WR strobe is

used to deassert DRQ. DRQ is deasserted within 50 ns of

the leading edge of DACK, RD, or WR. This quick response

should prevent the DMA controller from transferring extra

bytes in most applications.

e

the FIFO is actually enabled with THRESH

0Fh. Thus,

DRQ is asserted when one byte has entered the FIFO dur-

ing reads, and when one byte can be written to the FIFO

during writes. DRQ is deasserted by the leading edge of the

DACK input, and is reasserted when DACK goes inactive

high. This operation is very similar to Burst mode transfer

with the FIFO enabled except that DRQ is deasserted be-

tween each byte.

5.3.2.2 DMA ModeÐFIFO Enabled

Read Data Transfers

Whenever the number of bytes in the FIFO is greater than

b

or equal to (16 THRESH), a DRQ is generated. This is the

trigger condition for the FIFO read data transfers from the

Overrun Errors

An overrun or underrun error terminates the execution of

the command if the system does not transfer data within the

allotted data transfer time (see Section 3.7), which puts the

controller into the Result Phase. During a read overrun, the

mP is required to read the remaining bytes of the sector

before the controller asserts IRQ6, signifying the end of ex-

ecution. During a write operation, an underrun error termi-

nates the Execution Phase after the controller has written

the remaining bytes of the sector with the last correctly writ-

ten byte to the FIFO and generated the CRC bytes. Whether

there is an error or not, an interrupt is generated at the end

of the Execution Phase, and is cleared by reading the first

Result Phase byte.

floppy controller to the mP.

Burst Mode. DRQ remains active until enough bytes have

been read from the controller to empty the FIFO.

Non-Burst Mode. DRQ is deasserted after each read trans-

fer. If the FIFO is not completely empty, DRQ is reasserted

after a 350 ns delay. This allows other higher priority DMA

transfers to take place between floppy transfers. In addition,

this mode allows the controller to work correctly in systems

where the DMA controller is put into a read verify mode,

where only DACK signals are sent to the FDC, with no RD

pulses. This read verify mode of the DMA controller is used

in some PC software. The FIFO Non-Burst mode allows the

DACK input from the DMA controller to be strobed, which

correctly clocks data from the FIFO.

DACK asserted alone without a RD or WR strobe is also

counted as a transfer. If RD or WR are not being strobed for

each byte, then DACK must be strobed for each byte so that

the floppy controller can count the number of bytes correct-

ly. A new command, the Verify command, has been added

to allow easier verification of data written to the disk without

the need of actually transferring the data on the data bus.

For both the Burst and Non-Burst modes, when the last byte

in the FIFO has been read, DRQ goes inactive. DRQ is then

reasserted when the FIFO trigger condition is satisfied. After

the last byte of a sector has been read from the disk, DRQ

is again generated even if the FIFO has not yet reached its

59

5.0 FDC Functional Description (Continued)

5.3.2.3 Interrupt ModeÐFIFO Disabled

tion (see the Command Description Section 4.1 and Status

Register Description Section 3.0). These Result Phase

bytes are read in the order specified for that particular com-

mand. Some commands do not have a result phase. Also,

the number of result bytes varies with each command. All of

the result bytes must be read from the Data Register before

the next command can be issued.

If the Interrupt (Non-DMA) mode is selected, IRQ6 is assert-

ed instead of DRQ when each byte is ready to be trans-

ferred. The Main Status Register should be read to verify

that the interrupt is for a data transfer. The RQM and non-

DMA bits (D7 and D5) in the MSR are set. The interrupt is

cleared when the byte is transferred to or from the Data

Register. CS and RD or CS and WR must be used to trans-

fer the data in or out of the Data Register (A2–A0 must be

valid). CS asserted by itself is not significant. CS must be

asserted with RD or WR for a read or write transfer to be

recognized.

Like the Command Phase, the Main Status Register con-

trols the flow of result bytes, and must be polled by the

software before reading each Result Phase byte from the

Data Register. The RQM bit (D7) and DIO bit (D6) must both

be set before each result byte can be read. After the last

result byte is read, the COM PROG bit (D4) in the MSR is

cleared, and the controller is ready for the next command.

The mP should transfer the byte within the data transfer

service time (see Section 3.7). If the byte is not transferred

within the time allotted, an Overrun Error is indicated in the

Result Phase when the command terminates at the end of

the current sector.

5.3.4 Idle Phase

After a hardware or software reset, or after the chip has

recovered from the power-down mode, the controller enters

the Idle Phase. Also, when there are no commands in prog-

ress the controller is in the Idle Phase. The controller waits

for a command byte to be written to the Data Register. The

RQM bit is set and the DIO bit is cleared in the MSR. After

receiving the first command (opcode) byte, the controller

enters the Command Phase. When the command is com-

pleted the controller again enters the Idle Phase. The Data

Separator remains synchronized to the reference frequency

while the controller is idle. While in the Idle Phase, the con-

troller periodically enters the Drive Polling Phase (see

Section 5.3.5).

An interrupt is also generated after the last byte is trans-

ferred. This indicates the beginning of the Result Phase.

The RQM and DIO bits (D7 and D6) in the MSR are set, and

the non-DMA bit (D5) is cleared. This interrupt is cleared by

reading the first Result Phase byte.

5.3.2.4 Interrupt ModeÐFIFO Enabled

The Interrupt (Non-DMA) mode with the FIFO enabled is

very similar to the Non-DMA mode with the FIFO disabled.

In this case, IRQ6 is asserted instead of DRQ under the

exact same FIFO threshold trigger conditions. The MSR

should be read to verify that the interrupt is for a data trans-

fer. The RQM and non-DMA bits (D7 and D5) in the MSR

are set. CS and RD or CS and WR must be used to transfer

the data in or out of the Data Register (A2–A0 must be

valid). CS asserted by itself is not significant. CS must be

asserted with RD or WR for a read or write transfer to be

recognized.

5.3.5 Drive Polling Phase

The National FDC supports the polling mode of the old gen-

eration 8-inch drives as a means of monitoring any change

in status for each disk drive present in the system. This

mode is supported for the sole purpose of providing back-

ward compatibility with software that expects its presence.

The Burst mode may be used to hold the IRQ6 pin active

during a burst, or the Non-Burst mode may be used to tog-

gle the IRQ6 pin for each byte of a burst. The Main Status

Register is always valid from the mP point of view. For ex-

ample, during a read command, after the last byte of data

has been read from the disk and placed in the FIFO, the

MSR still indicates that the Execution Phase is active, and

that data needs to be read from the Data Register. Only

after the last byte of data has been read by the mP from the

FIFO does the Result Phase begin.

While in the Idle Phase the controller enters a Drive Polling

Phase every 1 ms (based on a 500 kbps data rate). While in

the Drive Polling Phase, the controller interrogates the

Ready Changed status for each of the four logical drives.

The internal Ready line for each drive is toggled only after a

hardware or software reset, and an interrupt is generated for

drive 0. At this point, the software must issue four Sense

Interrupt commands to clear the Ready Changed State

status for each drive. This requirement can be eliminated if

drive polling is disabled via the POLL bit in the Configure

command. The Configure command must be issued within

500 ms (worst case) of the hardware or software reset for

drive polling to be disabled.

The same overrun and underrun error procedures from the

DMA mode apply to the Non-DMA mode. Also, whether

there is an error or not, an interrupt is generated at the end

of the Execution Phase, and is cleared by reading the first

Result Phase byte.

Even if drive polling is disabled, drive stepping and delayed

power-down occur in the Drive Polling Phase. The controller

checks the status of each drive and if necessary it issues a

step pulse on the STEP output with the DIR signal at the

appropriate logic level. Also, the controller uses the Drive

Polling Phase to control the Automatic Low Power mode.

When the Motor Off time has expired, the controller waits

512 ms, based on a 500 kbps or 1 Mbps data rate, before

powering down if this function is enabled via the Mode com-

mand.

5.3.2.5 Software Polling

If the Non-DMA mode is selected and interrupts are not

suitable, the mP can poll the MSR during the Execution

Phase to determine when a byte is ready to be transferred.

The RQM bit (D7) in the MSR reflects the state of the IRQ6

signal. Otherwise, the data transfer is similar to the Interrupt

Mode described above. This is true for the FIFO enabled or

disabled.

If a new command is issued when the FDC is in the middle

of a polling routine, the MSR will not indicate a ready status

for the next parameter byte until the polling sequence com-

pletes the loop. This can cause a delay between the first

and second bytes of up to 500 ms at 250 kbps.

5.3.3 Result Phase

During the Result Phase, the mP reads a series of bytes

from the data register. These bytes indicate the status of the

command. This status may indicate whether the command

executed properly, or it may contain some control informa-

60

5.0 FDC Functional Description (Continued)

5.4 DATA SEPARATOR

middle of the bit window. Window margin is commonly mea-

sured as a percentage. This percentage indicates how far a

data bit can be shifted early or late with respect to its nomi-

nal bit position, and still be read correctly by the data sepa-

rator. If the data separator cannot correctly decode a shifted

bit, then the data is misread and a CRC error results.

The internal data separator is a Fully Digital PLL (FDPLL).

The FDPLL synchronizes the raw data signal read from the

disk drive. The synchronized signal is used to separate the

encoded clock and data pulses. The data pulses are deseri-

alized into bytes, and then sent to the mP by the controller.

The dynamic window margin performance curves contain

two pieces of information:

The FDC supports five data rates: 250 kbps, 300 kbps,

500 kbps, 1 Mbps and 2 Mbps.

1. the maximum range of MSV (also called ‘‘lock range’’)

that the data separator can handle with no read errors,

and

The FDC has a dynamic window margin and lock range per-

formance capable of handling a wide range of floppy disk

drives. In addition, the data separator operates well under a

variety of conditions, including the high motor speed fluctua-

tions of floppy-compatible tape drives.

2. the maximum percentage of window margin (or bit jitter)

that the data separator can handle with no read errors.

Figure 5-1 shows the floppy disk controller dynamic window

margin performance at the four different data rates. Dynam-

ic window margin is the primary indicator of the quality and

performance level of the data separator. This measurement

indicates how much motor speed variation (MSV) of the

drive spindle motor and bit jitter (or window margin) can be

tolerated by the data separator.

Thus, the area under the dynamic window margin curves in

Figure 5-1 is the range of MSV and bit jitter that the FDC

can handle with no read errors. The FDC internal digital data

separator has a much better performance than comparable

digital data separator designs, and does not require any ex-

ternal components.

Note: The dynamic window margin curves were generated using a FlexStar

FS-540 Floppy Disk Simulator and a proprietary dynamic window mar-

gin test program written by National Semiconductor.

MSV is shown on the x-axis of the dynamic window margin

graph. MSV is translated directly to the actual data rate of

the data as it is read from the disk by the data separator.

That is, a faster than nominal motor results in a higher fre-

quency in the actual data rate.

The controller takes best advantage of the internal digital

data separator by implementing a sophisticated read algo-

rithm.

This ID search algorithm, shown inFigure 5-2, enhances the

FDPLL’s lock characteristics by forcing the FDPLL to relock

to the crystal reference frequency any time the data separa-

tor attempts to lock to a non-preamble pattern. This algo-

rithm ensures that the FDPLL is not thrown way out of lock

by write splices or bad data fields.

The dynamic window margin performance curves also indi-

cate how much bit jitter (or window margin) can be tolerated

by the data separator. This parameter is shown on the

y-axis of the graphs. Bit jitter is caused by the magnetic

interaction of adjacent data pulses on the disk, which effec-

tively shifts the bits away from their nominal positions in the

250/300/500 kbps and 1 Mbps

TL/C/11930–8

FIGURE 5-1. PC87332 Dynamic Window Margin Performance

e

(Typical Performance at V

DD

5.0V, 25 C)

§

61

5.0 FDC Functional Description (Continued)

TL/C/11930–9

FIGURE 5-2. Read Data AlgorithmÐState Diagram

5.5 CRYSTAL OSCILLATOR

tional disk drives, the read/write head by itself is able to

rewrite the disk without problems. For 2.88M drives, a pre-

erase head is needed to erase the magnetic flux on the disk

surface before the read/write can write to the disk surface.

The pre-erase head is activated during disk write operations

only, i.e., Format and Write Data commands.

The FDC is clocked by a single 24 MHz signal. An on-chip

oscillator is provided to enable the attachment of a crystal

or a clock signal.

A parallel resonant crystal is preferred if at all possible. In

some cases, a series resonant crystal can be used, but care

must be taken to ensure that the crystal does not oscillate

at a sub-harmonic frequency. The oscillator is able to work

with high profile, low profile, and surface mount type crystal

enclosures. External bypass capacitors (5 pF to 10 pF)

should be connected from XTAL1 and XTAL2 to GND. If an

external oscillator circuit is used, it must have a duty cycle of

at least 40%–60%, and minimum input levels of 2.4V and

0.4V. The controller should be configured so that the exter-

nal oscillator clock is input into the X1/OSC pin, and XTAL2

is left unconnected.

In 2.88M drives, the pre-erase head leads the read/write

head by 200 mm, which translates to 38 bytes at 1 Mbps

(19 bytes at 500 kbps). For both conventional and perpen-

dicular drives, WGATE is asserted with respect to the posi-

tion of the read/write head. With conventional drives, this

means that WGATE is asserted when the read/write head is

located at the beginning of the Data Field preamble. With

the 2.88M drives, since the preamble must be pre-erased

before it is rewritten, WGATE should be asserted when the

pre-erase head is located at the beginning of the Data Field

preamble. This means that WGATE should be asserted

when the read/write head is at least 38 bytes (at 1 Mbps)

before the preamble. See Table 4-6 for a description of the

WGATE timing for perpendicular drives at the various data

rates.

5.6 PERPENDICULAR RECORDING MODE

The FDC is fully compatible with perpendicular recording

mode disk drives at all data rates. These perpendicular

mode drives are also called 4 Mbyte (unformatted) or

2.88 Mbyte (formatted) drives, which refers to their maxi-

mum storage capacity. Perpendicular recording will orient

the magnetic flux changes (which represent bits) vertically

on the disk surface, allowing for a higher recording density

than the conventional longitudinal recording methods. With

this increase in recording density comes an increase in the

data rate of up to 1 Mbps, thus doubling the storage capaci-

ty. In addition, the perpendicular 2.88M drive is read/write

compatible with 1.44M and 720k diskettes (500 kbps and

250 kbps respectively).

Because of the 38 byte spacing between the read/write

head and the pre-erase head at 1 Mbps, the GAP2 length of

22 bytes used in the standard IBM disk format is not long

enough. There is a new format standard for 2.88M drives at

1 Mbps called the Perpendicular Format, which increases

the GAP2 length to 41 bytes (see Figure 4-7 ). The Perpen-

dicular Mode command will put the floppy controller into

perpendicular recording mode, which allows it to read and

write perpendicular media. Once this command is invoked,

the read, write and format commands can be executed in

the normal manner. The perpendicular mode of the floppy

controller will work at all data rates, adjusting the format and

write data parameters accordingly. See Section 4.1.8 for

more details.

The 2.88M drive has unique format and write data timing

requirements due to its read/write head and pre-erase head

design (see Figure 5-3 ). Unlike conventional disk drives

which have only a read/write head, the 2.88M drive has

both a pre-erase head and read/write head. With conven-

62

5.0 FDC Functional Description (Continued)

TL/C/11930–10

FIGURE 5-3. Perpendicular Recording Drive R/W Head and Pre-Erase Head

5.7 DATA RATE SELECTION

Command are covered in this section, in Section 3.1.6 and

Section 4.1.6. The microcode is driven from the clock, so it

will be disabled while the clock is off. The FDC clock is

always disabled upon entering this mode, however, the os-

The data rate can be chosen two different ways with the

FDC. For PC compatible software, the Configuration Control

Register at address 3F7h is used to program the data rate

for the floppy controller. The lower bits D1 and D0 are used

in the CCR to set the data rate. The other bits should be set

to zero. See Table 3-7 for the data rate select encoding.

e

cillator is only disabled when PTR1

1. Upon entering the

power-down state, the RQM (Request For Master) bit in the

MSR will be cleared.

There are two modes of low power in the floppy controller:

manual low power and automatic low power. Manual low

power is enabled by writing a 1 to bit 6 of the DSR. The chip

will go into low power immediately. This bit will be cleared to

0 after the chip is brought out of low power. Manual low

power can also be accessed via the Mode command. The

function of the manual low power mode is a logical OR func-

tion between the DSR low power bit and the Mode com-

mand manual low power bit setting.

The data rate can also be set using the Data Rate Select

Register at address 4. Again, the lower two bits of the regis-

ter are used to set the data rate. The encoding of these bits

is exactly the same as those in the CCR. The remainder of

the bits in the DSR are used for other functions. Consult the

Register Description (Section 3.1.6) for more details.

The data rate is determined by the last value that is written

to either the CCR or the DSR. In other words, either the

CCR or the DSR can override the data rate selection of the

other register. When the data rate is selected, the micro-

engine and data separator clocks are scaled appropriately.

Also, the DRATE0 and DRATE1 output pins will reflect the

state of the data select bits that were last written to either

the CCR or the DSR.

Automatic low power mode will switch the controller into low

power 500 ms (at the 500 kbps MFM data rate) after it has

entered the idle state. Once the auto low power mode is set,

it does not have to be set again, and the controller will auto-

matically go into low power mode after it has entered the

idle state. Automatic low power mode can only be set with

the Mode command.

5.8 WRITE PRECOMPENSATION

There are two ways the FDC section of the SuperI/O can

recover from the power-down state. 1) The part will power-

up after a software reset via the DOR or DSR. Since a soft-

ware reset requires reinitialization of the controller, this

method can be undesirable. 2) The part will also power-up

after a read or write to either the Data Register or Main

Status Register. This is the preferred method of power-up

since all internal register values are retained. It may take a

few milliseconds for the oscillator to stabilize, and the mP

will be prevented from issuing commands during this time

through the normal Main Status Register protocol. That is,

the RQM bit in the MSR will be a 0 until the oscillator has

stabilized. When the controller has completely stabilized

from power-up, the RQM bit in the MSR is set to 1 and the

controller can continue where it left off.

Write precompensation is

a way of preconditioning the

WDATA output signal to adjust for the effects of bit shift on

the data as it is written to the disk surface. Bit shift is caused

by the magnetic interaction of data bits as they are written

to the disk surface, and has the effect of shifting these data

bits away from their nominal position in the serial MFM data

pattern. Data that is subject to bit shift is much harder to

read by a data separator, and can cause soft read errors.

Write precompensation predicts where bit shift could occur

within a data pattern. It then shifts the individual data bits

early, late, or not at all such that when they are written to

the disk, the resultant shifted data bits will be back in their

nominal position.

The FDC supports software programmable write precom-

pensation. Upon power-up, the default write precomp val-

ues will be used (see Table 3-6). The programmer can

choose a different value of write precomp with the DSR

register if desired (see Table 3-7). Also on power-up, the

default starting track number for write precomp is track zero.

This starting track number for write precomp can be

changed with the Configure command.

The Data Rate Select, Digital Output, and Configuration

Control Registers are unaffected by the power-down mode.

They will remain active. It is up to the user to ensure that the

Motor and Drive Select signals are turned off.

Note: If the power to an external oscillator driving the PC87334 is to be

independently removed during the FDC low power mode, it must not

be done until 2 ms after the FDC low power command is issued.

5.9 FDC LOW POWER MODE LOGIC

5.10 RESET OPERATION

The FDC section of the PC87332 supports two low power

modes described here in detail. Other low power modes of

the PC87332 are described in Section 2.6. Details concern-

ing entering and exiting low power mode via setting Data

Rate Select Register bit 6 or by executing the FDC Mode

The floppy controller can be reset by hardware or software.

Hardware reset is enacted by pulsing the Master Reset in-

put pin. A hardware reset will set all of the user addressable

registers and internal registers to their default values. The

63

5.0 FDC Functional Description (Continued)

Specify command values will be don’t cares, so they must

be reinitialized. The major default conditions are: FIFO dis-

TABLE 6-1. PC87332 UART

e

Register Addresses (AEN

0)

e

abled, FIFO threshold

Drive Polling enabled.

0, Implied Seeks disabled, and

DLAB A2 A1 A0

Selected Register

A software reset can be performed through the Digital Out-

put Register or Data Rate Select Register. The DSR reset

bit is self-clearing, while the DOR reset bit is not self-clear-

ing. If the LOCK bit in the Lock command was set to a 1

previous to the software reset, the FIFO, THRESH, and

PRETRK parameters in the Configure command will be re-

tained. In addition, the FWR, FRD, and BST parameters in

the Mode command will be retained if LOCK is set to 1. This

function eliminates the need for total reinitialization of the

controller after a software reset.

0

Receiver Buffer (Read),

Transmitter Holding (Write)

0

1

0

Interrupt Enable

Interrupt Identification (Read)

FIFO Control (Write)

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Line Control

MODEM Control

Line Status

After a hardware (assuming the FDC is enabled in the FER)

or software reset, the Main Status Register is immediately

available for read access by the mP. It will return a 00h value

until all the internal registers have been updated and the

data separator is stabilized. When the controller is ready to

receive a command byte, the MSR will return a value of 80h

(Request for Master bit is set). The MSR is guaranteed to

return the 80h value within 2.5 ms after a hardware or soft-

ware reset. All other user addressable registers other than

the Main Status Register and Data Register (FIFO) can be

accessed at any time, even while the part is in reset.

MODEM Status

Scratch

Divisor Latch

(Least Significant Byte)

1

0

1

Divisor Latch

(Most Significant Byte)

Bits 0,1 These two bits specify the number of data bits in

each transmitted or received serial character. The

encoding of bits 0 and 1 is as follows:

6.0 Serial Ports

Bit 1

Bit 0

Data Length

5 Bits

Each of these serial ports functions as a serial data input/

output interface in a microcomputer system. The system

software determines the functional configuration of the

UARTs via an 8-bit bidirectional data bus.

0

1

0

1

0

1

6 Bits

7 Bits

The UARTs are completely independent. They perform

serial-to-parallel conversion on data characters received

from a peripheral device or a MODEM, and parallel-to-serial

conversion on data characters received from the CPU. The

CPU can read the complete status of either UART at any

time during the functional operation. Status information re-

ported includes the type and condition of the transfer opera-

tions being performed by the UART, as well as any error

conditions (parity, overrun, framing, or break interrupt).

8 Bits

Bit 2

This bit specifies the number of Stop bits transmit-

ted with each serial character. If it is 0, one Stop

bit is generated in the transmitted data. If it is 1

when a 5-bit data length is selected, one and a

half Stop bits are generated. If it is 1 when either a

6-, 7-, or 8-bit word length is selected, two Stop

bits are generated. The receiver checks the first

Stop bit only, regardless of the number of Stop

bits selected.

The UARTs have programmable baud rate generators that

are capable of dividing the internal reference clock by divi-

16

sors of 1 to (2 –1), and producing a 16x clock for driving

the transmitter logic. Provisions are also included to use this

16x clock to drive the receiver logic. The UARTs have com-

plete MODEM-control capability and a prioritized interrupt

system. Interrupts can be programmed to the user’s require-

ments, minimizing the computing required to handle the

communications link.

Bit 3

Bit 4

Bit 5

This bit is the Parity Enable bit. When it is 1, a

Parity bit is generated (transmit data) or checked

(receive data) between the last data bit and the

following Stop bit of the serial data. (The Parity bit

is used to produce an even or odd number of 1s

when the data bits and the Parity bit are summed.)

6.1 SERIAL PORT REGISTERS

This bit is the Even Parity Select bit. When parity is

enabled and bit 4 is 0, an odd number of logic 1s

Two identical register sets, one for each channel, are in the

PC87332. All register descriptions in this section apply to

the register sets in both channels. See Table 6-1.

is transmitted or checked in the data word bits and

Parity bit. When parity is enabled and bit 4 is a 1,

an even number of logic 1s is transmitted or

checked.

6.2 LINE CONTROL REGISTER (LCR)

Read/Write

The system programmer uses the Line Control Register

(LCR) to specify the format of the asynchronous data com-

munications exchange and set the Divisor Latch Access bit.

This is a read and write register. Table 6-2 shows the con-

tents of the LCR. Details on each bit follow.

This bit is the Stick Parity bit. When parity is en-

abled it is used in conjunction with bit 4 to select

Mark or Space Parity. When LCR bits 3, 4 and 5

are 1 the Parity bit is transmitted and checked as a

0 (Space Parity). If bits 3 and 5 are 1 and bit 4 is a

0, then the Parity bit is transmitted and checked as

1 (Mark Parity). If bit 5 is 0, Stick Parity is disabled.

TL/C/11930–11

FIGURE 6-1. PC87332 Composite Serial Data

64

6.0 Serial Ports (Continued)

3. Clear break when normal transmission has to be

restored.

Bit 6 This bit is the Break Control bit. It causes a break

condition to be transmitted to the receiving UART.

When it is set to 1, the serial output (SOUT) is forced

to the Spacing state (0). The break is disabled by set-

ting bit 6 to 0. The Break Control bit acts only on

SOUT and has no effect on the transmitter logic.

During the break, the Transmitter can be used as a

character timer to accurately establish the break dura-

tion by sending characters and monitoring THRE and

TEMT.

Bit 7 This bit is the Divisor Latch Access Bit (DLAB). It must

be set high (logic 1) to access the Divisor Latches of

the Baud rate Generator during a Read or Write opera-

tion or to have the Baud Out (BOUT) signal appear on

the BOUT pin. It must be set low (logic 0) to access

any other register.

Note that this feature enables the CPU to alert a terminal. If

the following sequence is used, no erroneous characters

will be transmitted because of the break.

e

1. Wait for the transmitter to be idle (TEMT 1).

2. Set break for the appropriate amount of time. If the

transmitter will be used to time the break duration

e

then check that TEMT

Break Control bit.

1 before clearing the

TABLE 6-2. PC87332 Register Summary for an Individual UART Channel

Register Address

e

A0–2 1

e

DLAB 1

A0–2

0

A0–2

0

A0–2

1

A0–2

0

2

3

4

5

6

7

e

DLAB

0

DLAB

0

DLAB

0

DLAB

1

Receiver Transmitter

Interrupt

Ident.

FIFO

Bit

Interrupt

Enable

Line

MODEM

Control

Line

MODEM

Status

Scratch

Pad

Divisor

Latch

(LSB)

Divisor

Latch

Buffer

Register

(Read

Holding

Register

(Write

Control

No.

Control

Status

Register Register

Register

Register Register

Register

Register Register

(MSB)

(Read

Only)

(Write

Only)

RBR

THR

IER

IIR

FCR

LCR

MCR

LSR

MSR

SCR

DLL

DLM

0

1

Data Bit 0

(Note 1)

Data Bit 0

Enable

Received

Data

‘‘0’’ if

FIFO

Word

Length

Select

Bit 0

Data

Terminal

Ready

(DTR)

Data

Ready

(DR)

Delta

Clear

Bit 0

Bit 8

Interrupt

Pending

Enable

to Send

Available

Interrupt

Data Bit 1

Enable

Transmitter

Holding

Interrupt

ID

RCVR

FIFO

Word

Length

Select

Bit 1

Request

to Send

(RTS)

Overrun

Error

Delta

Data

Set

Bit 1

Bit 9

Bit

Reset

(OE)

Register

Interrupt

Empty

Ready

2

3

Data Bit 2

Data Bit 3

Data Bit 2

Data Bit 3

Enable

Receiver

Line Status

Interrupt

ID

XMIT

FIFO

Reset

Number of

Stop Bits

Out 1

Bit

Parity

Error

(PE)

Trailing

Edge Ring

Indicator

Bit 2

Bit 3

Bit 2

Bit 3

Bit 10

Bit 11

Bit

(Note 3)

Enable

MODEM

Status

Interrupt Reserved

Parity

IRQ

Framing

Error

Delta

Data

ID

Bit

Enable

(FE)

Carrier

Detect

Interrupt

(Note 2)

4

5

Data Bit 4

Data Bit 5

Data Bit 4

Data Bit 5

0

Reserved Even Parity

Select

Loop

0

Break

Interrupt

(BI)

Clear to

Send

Bit 4

Bit 5

Bit 4

Bit 5

Bit 12

Bit 13

(CTS)

0

Reserved

Stick

Transmitter

Holding

Data

Set

Parity

Register

(THRE)

Ready

(DSR)

6

7

Data Bit 6

Data Bit 7

Data Bit 6

Data Bit 7

0

FIFOs

Enabled

(Note 2)

RCVR

Trigger

(LSB)

Set

0

Transmitter

Empty

Ring

Indicator

(RI)

Bit 6

Bit 7

Bit 6

Bit 7

Bit 14

Bit 15

Break

(TEMT)

FIFOs

Enabled

(Note 2)

RCVR

Trigger

(MSB)

Divisor

Latch

Error in

RCVR

FIFO

Data

Carrier

Detect

(DCD)

Access Bit

(DLAB)

(Note 2)

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

Note 2: These bits are always 0 in the NS16450 Mode.

Note 3: This bit no longer has a pin associated with it.

65

6.0 Serial Ports (Continued)

TABLE 6-3. PC87332 UART Reset Configuration

Register or Signal

Interrupt Enable

Interrupt Identification

FIFO Control

Reset Control

Master Reset (MR)

Master Reset

Reset State

0000 0000 (Note 1)

0000 0001

Master Reset

0000 0000

Line Control

Master Reset

0000 0000

MODEM Control

Line Status

Master Reset

0000 0000

Master Reset

0110 0000

MODEM Status

SOUT

Master Reset

XXXX 0000 (Note 2)

High

Master Reset

INTR (RCVR Errors)

INTR (RCVR Data Ready)

INTR (THRE)

Read LSR/MR

Read RBR/MR

Read IIR/Write THR/MR

Read MSR/MR

Master Reset

Low/TRI-STATE

Low/Low/TRI-STATE

Low/TRI-STATE

Low

INTR (Modem Status Changes)

Interrupt Enable Bit

RTS

Master Reset

High

DTR

Master Reset

High

e

RCVR FIFO

MR or (FCR1

MR or (FCR2

1 and FCR0

1) or Change in FCR0

All Bits Low

XMIT FIFO

Note 1: Boldface bits are permanently low.

Note 2: Bits 7–4 are driven by the input signals.

6.3 PROGRAMMABLE BAUD RATE GENERATOR

TABLE 6-4. PC87332 UART Divisors,

Baud Rates and Clock Frequencies

The PC87332 contains two independently programmable

Baud rate Generators. The 24 MHz crystal oscillator fre-

quency input is divided by 13, resulting in a frequency of

1.8462 MHz. This is sent to each Baud rate Generator and

divided by the divisor of the associated UART. The output

24 MHz Input Divided to 1.8462 MHz

Decimal Divisor

for 16 x Clock

Percent

Baud Rate

Error (Note)

c

frequency of the Baud rate Generator (BOUT1,2) is 16

the baud rate.

50

75

2304

1536

1047

857

768

384

192

96

0.1

e

c

(frequency input) (baud rate 16)

Ý

divisor

110

The output of each Baud rate Generator drives the transmit-

ter and receiver sections of the associated serial channel.

Two 8-bit latches per channel store the divisor in a 16-bit

binary format. These Divisor Latches must be loaded during

initialization to ensure proper operation of the Baud rate

Generator. Upon loading either of the Divisor Latches, a

16-bit Baud Counter is loaded. Table 6-4 provides decimal

divisors to use with crystal frequencies of 24 MHz. The os-

cillator input to the chip should always be 24 MHz to ensure

that the Floppy Disk Controller timing is accurate and that

the UART divisors are compatible with existing software.

Using a divisor of zero is not recommended.

134.5

150

0.4

0.5

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

57600

115200

64

58

48

32

24

16

12

6

3

2

1

Note: The percent error for all baud rates, except where indicated other-

wise, is 0.2%.

66

6.0 Serial Ports (Continued)

When a break occurs only one character is loaded

into the FIFO. To Restart after a break is received,

the SIN pin must be 1 for at least one half bit time.

6.4 LINE STATUS REGISTER (LSR)

This 8-bit register provides status information to the CPU

concerning data transfers. Table 6-2 shows the contents of

the Line Status Register. Details on each bit follow:

Note: Bits

1 through 4 are the error conditions that produce a

Receiver Line Status interrupt whenever any of the corre-

sponding conditions are detected and the interrupt is en-

abled.

Bit 0 This bit is the receiver Data Ready (DR) indicator. It

is set to 1 whenever a complete incoming character

has been received and transferred into the Receiver

Buffer Register or the FIFO. It is reset to 0 by read-

ing the data in the Receiver Buffer Register or the

FIFO.

Bit 5 This bit is the Transmitter Holding Register Empty

(THRE) indicator. It indicates that the UART is ready

to accept a new character for transmission. In addi-

tion, it causes the UART to issue an interrupt to the

CPU when the Transmit Holding Register Empty In-

terrupt enable is set high. The THRE bit is set to 1

when a character is transferred from the Transmitter

Holding Register into the Transmitter Shift Register.

The bit is reset to 0 whenever the CPU loads the

Transmitter Holding Register. In the FIFO mode it is

set when the XMIT FIFO is empty; it is cleared when

at least 1 byte is written to the XMIT FIFO.

Bit 1 This bit is the Overrun Error (OE) indicator. It indi-

cates that data in the Receiver Buffer Register was

not read by the CPU before the next character was

transferred into the Receiver Buffer Register, there-

by destroying the previous character. The OE indica-

tor is set to 1 upon detection of an overrun condition,

and reset whenever the CPU reads the contents of

the Line Status Register. If the FIFO mode data con-

tinues to fill the FIFO beyond the trigger level, an

Overrun error will occur only after the FIFO is com-

pletely full and the next character has been received

in the shift register. OE is indicated to the CPU as

soon as it happens. The character in the shift regis-

ter is overwritten, but it is not transferred to the

FIFO.

Bit 6 This bit is the Transmitter Empty (TEMT) indicator. It

is set to 1 whenever the Transmitter Holding Regis-

ter (THR) and the Transmitter Shift Register (TSR)

are both empty. It is reset to 0 if either the THR or

TSR contains a data character. In the FIFO mode

this bit is set to 1 whenever the transmitter FIFO and

the shift register are both empty.

Bit 2 This bit is the Parity Error (PE) indicator. It indicates

that the received data character does not have the

correct parity, as selected by the even parity select

bit. The PE bit is set to 1 upon detection of a parity

error and is reset to 0 whenever the CPU reads the

contents of the Line Status Register. In the FIFO

mode this error is associated with the particular

character that it applies to in the FIFO. This error is

revealed to the CPU when its associated character is

at the top of the FIFO.

Bit 7 In the NS16450 Mode this is 0. In the FIFO Mode

this bit is set when there is at least one parity error,

framing error or break indication in the FIFO. It is

cleared when the CPU reads the LSR, if there are no

subsequent errors in the FIFO.

Note: The Line Status Register is intended for read operations

only. Writing to this register is not recommended as this

operation is only used for factory testing. In the FIFO mode

the software must load a data byte in the Rx FIFO via the

Loopback Mode in order to write to LSR2–LSR4. LSR0 and

LSR7 can’t be written to in the FIFO Mode.

Bit 3 This bit is the Framing Error (FE) indicator. It indi-

cates that the received character did not have a val-

id Stop bit. It is set to 1 whenever the Stop bit follow-

ing the last data bit or parity bit is a 0 (Spacing level).

The FE indicator is reset whenever the CPU reads

the contents of the Line Status Register. In the FIFO

mode this error is associated with the particular

character that it applies to in the FIFO. This error is

revealed to the CPU when its associated character is

at the top of the FIFO. The UART will try to resyn-

chronize after a framing error by assuming that the

error was due to the next start bit. It samples this

‘‘start’’ bit twice and then takes in the bits following it

as the rest of the frame.

6.5 FIFO CONTROL REGISTER (FCR)

This is a write-only register at the same location as the IIR

(the IIR is a read-only register). This register is used to en-

able the FIFOs, clear the FIFOs and to set the RCVR FIFO

trigger level.

Bit 0

Writing a 1 to FCR0 enables both the XMIT and

RCVR FIFOs. Resetting FCR0 clears all bytes in

both FIFOs. When changing from FIFO Mode to

NS16450 Mode and vice versa, data is automati-

cally cleared from the FIFOs. This bit must al-

ready be 1 when other FCR bits are written to or

they will not be programmed.

Bit 1

Bit 2

Bit 3

Writing 1 to FCR1 clears all bytes in the RCVR

FIFO and resets its counter logic to 0. The shift

register is not cleared. The 1 that is written to this

bit position is self-clearing.

Bit 4 This bit is the Break Interrupt (BI) indicator. It is set

to 1 whenever the received data input is held in the

Spacing (0) state for longer than a full word trans-

a

mission time (i.e., the total time of Start bit

data

a

Stop bits). The BI indicator is reset

Writing 1 to FCR2 clears all bytes in the XMIT

FIFO and resets its counter logic to 0. The shift

register is not cleared. The 1 that is written to this

bit position is self-clearing.

a

bits

Parity

whenever the CPU reads the contents of the Line

Status Register. In the FIFO mode this error is asso-

ciated with the particular character that it applies to

in the FIFO. This error is revealed to the CPU when

its associated character is at the top of the FIFO.

Writing to FCR3 does not change UART opera-

tions.

Bits 4, 5 FCR4 to FCR5 are reserved for future use.

67

6.0 Serial Ports (Continued)

Bits 6, 7 The combination of FCR6 and FCR7 is used to

designate the interrupt trigger level (see Figure

6.2). When the number of bytes in the RCVR FIFO

equals the designated interrupt trigger level, a Re-

ceived Data Available Interrupt is activated. This

interrupt must be enabled by setting the Interrupt

Enable Register (IER) bit 0.

When the CPU accesses the IIR, the UART freezes all inter-

rupts and indicates to the CPU which pending interrupt has

the highest priority. While the CPU accesses this interrupt

routine, the UART records new interrupts, but does not

change its current indication until the current access is com-

plete. Table 6-2 shows the contents of the IIR. Details on

each bit follow:

Bit 0

This bit can be used in an interrupt environment to

indicate whether an interrupt condition is pending.

When it is 0, an interrupt is pending and the IIR

contents may be used as a pointer to the appropri-

ate interrupt service routine. When it is 1, no inter-

rupt is pending. See Table 6-5.

FCR Bits

RCVR FIFO

Trigger Level (Bytes)

7

0

1

6

0

1

0

1

01

04

08

14

Bits 1, 2 These two bits of the IIR are used to identify the

highest priority interrupt pending as indicated in

Table 6-5.

FIGURE 6-2. Receiver FIFO Trigger Level

Bit 3

In the 16450 mode this bit is 0. In the FIFO mode it

is set along with bit 2 when a time-out interrupt is

pending. See Table 6-5.

6.6 INTERRUPT IDENTIFICATION REGISTER (IIR)

In order to provide minimum software overhead during data

character transfers, the UART prioritizes interrupts into four

levels and records these in the Interrupt Identification Reg-

ister. The four levels of interrupt conditions in order of priori-

ty are Receiver Line Status; Received Data Ready; Trans-

mitter Holding Register Empty; and MODEM Status.

Bits 4, 5 These bits of the IIR are always 0.

e

Bits 6, 7 These two bits are set when FCR0

Mode enabled.)

1. (FIFO

TABLE 6-5. PC87332 Interrupt Control Functions

Interrupt Identification

Register

Interrupt Set and Reset Functions

Bit 3

(FIFO Mode Bit 2

Only)

Priority

Level

Bit 1

Bit 0

Interrupt Type

Interrupt Source

Interrupt Reset Control

0

1

0

1

0

Ð

None

Ð

Highest Receiver Line Status

Overrun Error, Parity Error,

Framing Error or Break

Interrupt

Reading the Line

Status Register

0

1

0

Second Received Data Available Receiver Data Available

Read Receiver Buffer

Second Character

(FIFO Time-Out

mode Indication

only)

No Characters have been

removed from or input to the

RCVR FIFO during the last 4

char. times and there is at least

1 char. in it during this time.

Reading the Receiver

Buffer Register

0

1

0

Third Transmitter Holding

Register Empty

Transmitter Holding

Register Empty

Reading the IIR Register

(if Source of Interrupt) or

Writing the Transmitter

Holding Register

Fourth MODEM Status

Clear to Send or Data Set

Ready or Ring Indicator

or Data Carrier Detect

Reading the MODEM

Status Register

68

6.0 Serial Ports (Continued)

6.7 INTERRUPT ENABLE REGISTER (IER)

DTR, RTS, OUT1, IRQ ENABLE bits in MCR are

internally connected to DSR, CTS, RI and DCD in

MSR, respectively. The MODEM Control output

pins are forced to their high (inactive) states. In the

Loopback Mode, data that is transmitted is imme-

diately received. This feature allows the processor

to verify the transmit-and-received-data paths of

the serial port.

This register enables the five types of UART interrupts.

Each interrupt can individually activate the appropriate inter

rupt (IRQ3 or IRQ4) output signal. It is possible to totally

disable the interrupt system by resetting bits 0 through 3 of

the Interrupt Enable Register (IER). Similarly, setting bits of

this register to 1, enables the selected interrupt(s). Disabling

an interrupt prevents it from being indicated as active in the

IIR and from activating the interrupt output signal. All other

system functions operate in their normal manner, including

the setting of the Line Status and MODEM Status Registers.

Table 6-2 shows the contents of the IER. Details on each bit

follow. See MODEM Control Register bit 3 for more informa-

tion on enabling the interrupt pin.

In the Loopback Mode, the receiver and transmit-

ter interrupts are fully operational. The MODEM

Status Interrupts are also operational, but the in-

terrupts’ sources are the lower four bits of MCR

instead of the four MODEM control inputs. Writing

a 1 to any of these 4 MCR bits will cause an inter-

rupt. In Loopback Mode the interrupts are still con-

trolled by the Interrupt Enable Register. The IRQ3

and IRQ4 pins will be at TRI-STATE in the Loop-

back Mode.

Bit 0

When set to 1 this bit enables the Received Data

Available Interrupt and Timeout Interrupt in the

FIFO Mode.

Bit 1

Bit 2

Bit 3

This bit enables the Transmitter Holding Register

Empty Interrupt when set to 1.

Bits 5–7 These bits are permanently set to 0.

This bit enables the Receiver Line Status Inter-

rupt when set to logic 1.

6.9 MODEM STATUS REGISTER (MSR)

This register provides the current state of the control lines

from the MODEM (or peripheral device) to the CPU. In addi-

tion to this current-state information, four bits of the

MODEM Status Register provide change information. These

bits are set to a logic 1 whenever a control input from the

MODEM changes state. They are reset to logic 0 whenever

the CPU reads the MODEM Status Register. Table 6-2

shows the contents of the MSR. Details on each bit follow.

This bit enables the MODEM Status Interrupt

when set to logic 1.

Bits 4–7 These four bits are always logic 0.

6.8 MODEM CONTROL REGISTER (MCR)

This register controls the interface with the MODEM or data

set (or a peripheral device emulating a MODEM). The con-

tents of the MODEM Control Register (MCR) are indicated

in Table 6-2 and are described as follows:

Bit 0 This bit is the Delta Clear to Send (DCTS) indicator.

It indicates that the CTS input to the chip has

changed state since the last time it was read by the

CPU.

Bit 0

This bit controls the Data Terminal Ready (DTR)

output. When it is set to 1, the DTR output is

forced to a logic 0. When it is reset to 0, the DTR

output is forced to 1. In Local Loopback Mode,

this bit controls bit 5 of the MODEM Status Regis-

ter.

Bit 1 This bit is the Delta Data Set Ready (DDSR) indica-

tor. It indicates that the DSR input to the chip has

changed state since the last time it was read by the

CPU.

Note: The DTR and RTS output of the UART may be applied

to an EIA inverting line driver (such as the DS1488) to

obtain the proper polarity input at the MODEM or data

set.

Bit 2 This bit is the Trailing Edge of Ring Indicator (TERI)

detector. It indicates that the RI input to the chip has

changed from a low to a high state.

Bit 1

This bit controls the Request to Send (RTS) out-

put. Its effect on the RTS output is identical to that

described above for bit 0. In Local Loopback

Mode, this bit controls bit 4 of the MODEM Status

Register.

Bit 3 This bit is the Delta Data Carrier Detect (DDCD) in-

dicator. It indicates that the DCD input to the chip

has changed state.

Note: Whenever bit 0, 1, 2 or 3 is set to logic 1, a MODEM Status

Interrupt is generated.

Bit 4 This bit is the complement of the Clear to Send

(CTS) input. If bit 4 (loopback) of the MCR is set to

1, this bit is equivalent to RTS in the MCR.

Bit 2

Bit 3

Bit 4

This bit is the OUT1 bit. It does not have an output

pin associated with it. It can be written to and read

by the CPU. In Local Loopback Mode, this bit con-

trols bit 6 of the MODEM Status Register.

Bit 5 This bit is the complement of the Data Set Ready

(DSR) input. If bit 4 of the MCR is set to 1, this bit is

equivalent to DTR in the MCR.

This bit enables the interrupt when set. No exter-

nal pin is associated with this bit other than IRQ3,

4. In Local Loopback Mode, this bit controls bit 7

of the MODEM Status Register.

Bit 6 This bit is the complement of the Ring Indicator (RI)

input. If bit 4 of the MCR is set to 1, this bit is equiva-

lent to OUT1 in the MCR.

This bit provides a Local Loopback feature for di-

agnostic testing of the UART. When it is set to 1,

the following changes take place: the transmitter

Serial Output (SOUT) is set to the Marking (1)

state; the receiver Serial Input (SIN) is disconnect-

ed; the output of the Transmitter Shift Register is

‘‘looped back’’ (connected) to the Receiver Shift

Register; the four MODEM Control inputs (DSR,

CTS, RI and DCD) are disconnected; and the

Bit 7 This bit is the complement of the Data Carrier De-

tect (DCD) input. If bit 4 of the MCR is set to 1, this

bit is equivalent to IRQ ENABLE in the MCR.

6.10 SCRATCHPAD REGISTER (SCR)

This 8-bit Read/Write Register does not control the UART

in any way. It is intended as a scratchpad register to be used

by the programmer to hold data temporarily.

69

7.0 Parallel Port

TABLE 7-3. SPP Data Register Read and Write Modes

7.1 INTRODUCTION

PTR7 CTR5 RD WR

Result

This parallel interface is designed to provide all of the sig-

nals and registers needed to communicate through a stan-

dard parallel printer port as found in the IBM PC-XT, PC-AT,

PS/2 and Centronics systems. This parallel port supports

three standard modes of operation: SPP, EPP, ECP. The

Standard Parallel Port (SPP) is a software based protocol

with performance of up to 150 kbps.

0

X

1

0

1

Data Written to PD0–7

Data Read from the Output

Latch

1

0

1

0

1

0

1

Data Written to PD0–7

Data Written is Latched

The Enhanced Parallel Port (EPP) is a hardware protocol

which offers up to 2 Mbps.

Data Read from the Output

Latch

The Extended Capabilities Port (ECP) is also a hardware

protocol with up to 2 Mbps transfer rate. In addition, the

ECP has FIFO’s for receive and transmit, and DMA support,

to reduce the CPU overhead. The ECP mode 0 is in fact

compatible with the SPP mode. The ECP specification de-

fines the AC/DC parameters of the signals to allow fast

communication without termination problems.

1

0

1

Data Read from PD0–7

7.2 DATA REGISTER (DTR)

All the above standards are incorporated into the 1284 IEEE

specifications.

The address decoding of the registers utilizing A0 and A1 is

shown in Table 7-1. Table 7-3 shows the Reset states of

Parallel port registers and pin signals. These registers are

shown in Section 7.2 to Section 7.4.

TL/C/11930–12

TABLE 7-1. Parallel Interface Register Addresses

This is a bidirectional data port that transfers 8-bit data. The

direction is determined by the Power and Test Configuration

Register (PTR) bit 7 and the CTR5 bits. When PTR7 is high,

the CTR5 bit will determine the data direction in conjunction

with the Read and Write strobes. When PTR7 bit is low, the

parallel port operates in the output mode only. The reset

value of this register is 0. See Table 7-3.

A1

0

A0

0

Address

Register

Data

Access

Read/Write

Read

0

1

2

3

0

1

Status

1

0

Control

Read/Write

1

TRI-STATE

7.3 STATUS REGISTER (STR)

Special circuitry provides protection against damage that

might be caused when the printer is powered but the

PC87332 is not.

There are two Standard Parallel Port (SPP) modes of opera-

tion (Compatible and Extended; see Table 7-2), two En-

hanced Parallel Port (EPP) modes of operation and one Ex-

tended Capabilities Port (ECP) mode to complete a full IEEE

1284 parallel port.

TL/C/11930–13

TABLE 7-2. Standard Parallel Port Modes Selection

This register provides status for the TIMEOUT, ERROR,

SLCT, PE, ACK, and BUSY signals for a connected printer.

It is a read only register. Writing to it is an invalid operation

that has no effect.

Port Function

Compatible

Extended

PTR7

0

1

Bit 0 When in EPP mode, this is the timeout status bit.

When this bit is 0, no timeout.

In Compatible mode a write operation causes the data to be

presented on pins PD0–7. A read operation in this mode

causes the Data Register to present the last data written to

it by the CPU. See Table 7-3.

When this bit is 1, timeout occurred on EPP cycle

(minimum 10 msec). It is cleared to 0 after STR is

read, i.e., consecutive reads (after the first read) al-

ways return 0. It is also cleared to 0 when EPP is

enabled (bit 0 of PCR is changed from 0 to 1).

In the Extended mode a write operation to the data register

causes the data to be latched. If the Data Port Direction bit

(Control Register (CTR) bit 5) is 0, the latched data is pre-

sented to the pins and a read operation from this register

allows the CPU to read the last data it wrote to the port. If

CTR5 is 1, the data is only latched and a read from this

register causes the port to present the data on pins PD0–7.

See Table 7-2.

When not in EPP mode, this bit is 1.

Bit 1 Reserved; this bit is always 1.

Bit 2 In the compatible mode (PTR7 bit is 0), or in ECP and

e

EPP mode with bit 4 of PCR

one.

0, this bit is always

In the Extended Mode (PTR7 bit is 1), or in ECP and

e

EPP with bit 4 of PCR

bit.

1, this bit is the IRQ Status

70

7.0 Parallel Port (Continued)

In the Extended mode, if CTR4

e

1, then this bit is

Compatible mode:

latched low when the ACK signal makes a transition

from low to high.

e

when bit 4

0 IRQx is floated

1 IRQx follows ACK transitions

Reading this bit sets it to a 1.

Extended mode:

e

Bit 3 This bit represents the current state of the printer

error signal (ERROR). The printer sets this bit low

when there is a printer error. This bit follows the state

of the ERR pin.

when bit 4

0 IRQx is floated

1 IRQx becomes active on ACK trail-

ing edge

EPP mode:

when bit 4

e

Bit 4 This bit represents the current state of the printer

select signal (SLCT). The printer sets this bit high

when it is selected. This bit follows the state of the

SLCT pin.

0 IRQx is floated

1 IRQx is pulsed when ACK is acti-

vated, or an EPP timeout occurs

Bit 5

This bit determines the parallel port direction when

bit 7 of PTR is 1. The default condition results in

the parallel port being in the output mode. This is a

Read/Write bit in EPP mode. In SPP mode it is a

write only bit; a read from it will return 1. See

Table 7-3 for further details.

Bit 5 This bit represents the current state of the printer

paper end signal (PE). The printer sets this bit high

when it detects the end of the paper. This bit follows

the state of the PE pin.

Bit 6 This bit represents the current state of the printer

acknowledge signal (ACK). The printer pulses this

signal low after it has received a character and is

ready to receive another one. This bit follows the

state of the ACK pin.

Bits 6, 7 Reserved. These bits are always 1.

Normally when the Control Register is read, the bit values

are provided by the internal output data latch. These bit

values can be superseded by the logic level of the STB,

AFD, INIT, and SLIN pins if these pins are forced high or low

by an external voltage. In order to force these pins high or

low the corresponding bits should be set to their inactive

Bit 7 This bit represents the current state of the printer

busy signal (BUSY). The printer sets this bit low when

it is busy and cannot accept another character. This

bit is the inverse of the (BUSY/WAIT) pin.

e

0, INIT 1). See Table

state (e.g., AFD

7-4.

STB

SLIN

7.4 CONTROL REGISTER (CTR)

TABLE 7-4. Parallel Port Reset States

Signal

SLIN

INIT

Reset Control

State after Reset

MR

TRI-STATE

Zero

AFD

TRI-STATE

TL/C/11930–14

STB

This register provides all output signals to control the print-

er. Except for bit 5, it is a read and write register.

IRQ5,7

7.5 ENHANCED PARALLEL PORT OPERATION

Bit 0

This bit (STB) directly controls the data strobe sig-

nal to the printer via the STB pin. This bit is the

inverse of the STB pin.

EPP mode provides for greater throughput, and more com-

plexity, than the Compatible or Extended modes by support-

ing faster transfer times and a mechanism that allows the

host to address peripheral device registers directly. Faster

transfers are achieved by automatically generating the ad-

dress and data strobes. EPP is compatible with both Com-

patible and Extended mode parallel-port devices. It consists

of eight (0–7) single-byte registers. (See Table 7-5.)

Bit 1

This bit (AFD) directly controls the automatic feed

XT signal to the printer via the AFD pin. Setting this

bit high causes the printer to automatically feed

after each line is printed. This bit is the inverse of

the AFD pin.

Bit 2

This bit (INIT) directly controls the signal to initial-

ize the printer via the INIT pin. Setting this bit to

low initializes the printer. This bit follows the INIT

pin.

There are two EPP modes:

EPP rev. 1.7 is supported when bit 0 of PCR is 1, and bit 1 of

PCR is 0.

Note: This bit must be set to 1 before enabling the EPP or ECP

modes via bits 0 or 2 of the PCR register.

EPP rev. 1.9 (IEEE 1284) is supported when bit 0 of PCR is

1, and bit 1 of PCR is 1.

Bit 3

Bit 4

This bit directly controls the select-in (SLIN) signal

to the printer via the SLIN pin. Setting this bit high

selects the printer. It is the inverse of the SLIN pin.

EPP is supported for a parallel port whose base address is

278h or 378h, but not for a parallel port whose base ad-

dress is 3BCh (there are no EPP registers at 3BFh). There

are four EPP transfer operations: address write, address

read, data write and data read. An EPP transfer operation is

composed of a host read or write cycle (from or to an EPP

register) and an EPP read or write cycle (from a peripheral

device to an EPP register, or from an EPP register to a

peripheral device).

This bit controls the interrupt generated by the

ACK signal. Its function changes slightly depend-

ing on the parallel port mode selected. In ECP

mode this bit should be set to 0. In the following

description, IRQx indicates either IRQ5 or IRQ7

(based upon PTR3):

71

7.0 Parallel Port (Continued)

TABLE 7-5. EPP Register Addresses

Access Description

A2 A1 A0 Address

Register

0

1

0

1

0

1

2

Data (DTR)

R/W

A write to this register sets the state of the eight data pins on the 25-pin

D-shell connector.

Status (STR)

Control (CTR)

R

A read from this register presents the system micro-processor with the real-

time status of five pins on the 25-pin D-shell connector, and the IRQ.

R/W

A write operation to this register sets the state of four pins on the 25-pin

D-shell connector, and controls both the parallel port interrupt enable and

direction.

0

1

3

Address

R/W

A write operation to this register initiates an EPP device/register selection

operation.

1

0

1

4

5

Data Port 0

Data Port 1

R/W

Accesses to this port initiate device read or write operations with bits 0–7.

This port is only accessed to transfer bits 8 to 15 of a 16-bit read or write to

data port 0.

1

0

1

6

7

Data Port 2

Data Port 3

R/W

This port is only accessed to transfer bits 16 to 23 of a 32-bit read or write to

data port 0.

This port is only accessed to transfer bits 24 to 31 of a 32-bit read or write to

data port 0.

The software must write zero to bits 0, 1 and 3 of the CTR

register, before accessing the EPP registers, since the pins

controlled by these bits are controlled by hardware during

EPP access. Once these bits are written with zero, the soft-

ware may issue multiple EPP access cycles. The software

must set bit 7 of the PTR register to 1, if bit 5 of CTR is to

control direction.

3. If WAIT is low during the host write cycle, IOCHRDY

goes low.

When WAIT goes high, the EPP pulls IOCHRDY high.

4. When IOCHRDY goes high it causes WR to go high. If

WAIT is high during the host write cycle then the EPP

does not pull IOCHRDY to low.

5. When WR goes high it causes the EPP to pull WRITE

and ASTRB to high.

To meet the EPP 1.9 specifications, the software should

change direction (bit 5 of CTR) only when bit 7 of STR is 1

(i.e., change direction at EPP Idle Phase, as defined in the

IEEE 1284 document).

Only when WRITE and ASTRB are high can the EPP

change PD0–7.

When bit 7 of PTR is 0, EPP cycles to the external device

are generated by invoking read or write cycles to the EPP.

When bit 7 of PTR is 1:

1. Reading an EPP register during forward direction (bit 5 of

CTR is 0) is allowed only in EPP 1.7. It returns the regis-

ter latched value (not the PD0–7 pins’ value), and does

not generate an EPP read cycle.

2. Writing to an EPP register during backward direction (bit

5 of CTR is 1) updates the register data, and does not

generate an EPP write cycle.

EPP 1.7 Address Write

The following procedure selects a peripheral device or reg-

ister. See also Figure 7-1.

1. The host writes a byte to the EPP address register. WR

goes low to latch D0–7 into the address register. The

latch drives the address register onto PD0–7 and the

EPP pulls WRITE low.

TL/C/11930–15

2. The EPP pulls ASTRB low to indicate that data has been

sent.

FIGURE 7-1. EPP 1.7 Address Write

72

7.0 Parallel Port (Continued)

EPP 1.7 Address Read

2. The EPP first pulls WRITE low, and then pulls ASTRB low

to indicate that data has been sent.

The following procedure reads from the address register.


型号：	PC87332
厂家：	National Semiconductor
描述：	PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac PC87332VLJ （ 3.3V / 5V ）和PC87332VLJ - 5 （ 5V ）（ SuperI / OTM III高级绿色）软盘控制器，双UART ， IEEE1284并行端口，而且IDE Interfac 控制器 PC
文件：	总98页 (文件大小：882K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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