LCP152SD [ETC]
PROGRAMMABLE TRANSIENT VOLTAGE SUPPRESSOR FOR SLIC PROTECTION ; 可编程瞬态电压抑制器SLIC保护\n
| 型号： | LCP152SD |
| 厂家： | 
ETC |
| 描述： | PROGRAMMABLE TRANSIENT VOLTAGE SUPPRESSOR FOR SLIC PROTECTION
|
| 文件： | 总9页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
LCP1521S/LCP152DEE
PROGRAMMABLE TRANSIENT VOLTAGE
SUPPRESSOR FOR SLIC PROTECTION
PRELIMINAY DATASHEET
A.S.D.™
FEATURES
■
Dual programmable transient suppressor
■
Wide negative firing voltage range:
VMGL = -150 V max.
■
■
■
■
■
Low dynamic switching voltages: VFP and VDGL
Low gate triggering current: IGT = 5 mA max
Peak pulse current: IPP = 30 A (10/1000 µs)
Holding current: IH = 150 mA min
QFN 3x3
LCP152DEE
Low space consuming package
SO-8
LCP1521S
DESCRIPTION
These devices have been especially designed to
protect new high voltage, as well as classical
SLICs, against transient overvoltages.
FUNCTIONAL DIAGRAM (LCP1521S)
Positive overvoltages are clamped by 2 diodes.
Negative surges are suppressed by 2 thyristors,
their breakdown voltage being referenced to -VBAT
through the gate.
TIP
GATE
NC
1
TIP
These components present a very low gate
triggering current (IGT) in order to reduce the cur-
rent consumption on printed circuit board during
the firing phase.
GND
GND
RING
A particular attention has been given to the internal
wire bonding. The Kelvin method configuration en-
sures reliable protection, reducing the overvoltage
introduced by the parasitic inductances of the wiring,
especially for very fast transients.
RING
FUNCTIONAL DIAGRAM (LCP152DEE)
BENEFITS
Trisils are not subject to ageing and provide a fail
safe mode in short circuit for a better protection.
Trisils are used to help equipment to meet various
standards such as UL1950, IEC950 / CSA C22.2,
UL1459 and FCC part68. Trisils have UL94 V0
resin approved (Trisils are UL497B approved (file:
E136224)).
TIP
GATE
RING
TIP
GND
NC
RING
TM: ASD is a trademark of STMicroelectronics
January 2003 - Ed: 1A
1/9
LCP1521S/LCP152DEE
IN COMPLIANCES WITH THE FOLLOWING STANDARDS
Peak Surge
Voltage
Required
peak current
(A)
Minimum serial
resistor to meet
standard (Ω)
Current
Waveform
STANDARD
Voltage
(V)
Waveform
GR-1089 Core
First level
2500
1000
2/10µs
10/1000µs
500
100
2/10µs
10/1000µs
10
24
GR-1089 Core
Second level
5000
2/10µs
500
2/10µs
2/10µs
5/310µs
20
GR-1089 Core
Intra-building
1500
2/10µs
100
0
6000
1500
10/700µs
1/60 ns
150
37.5
110
0
ITU-T-K20/K21
ITU-T-K20
(IEC61000-4-2)
8000
15000
ESD contact discharge
ESD air discharge
0
0
4000
2000
10/700µs
1.2/50µs
100
50
5/310µs
60
10
VDE0433
VDE0878
4000
2000
100
50
1/20µs
0
0
4000
4000
10/700µs
1.2/50µs
100
100
5/310µs
8/20µs
60
0
IEC61000-4-5
FCC Part 68, lightning
surge type A
1500
800
10/160µs
10/560µs
200
100
10/160µs
10/560µs
22.5
15
FCC Part 68, lightning
surge type B
1000
9/720µs
25
5/320µs
0
THERMAL RESISTANCE
Symbol
Parameter
Value
Unit
Rth (j-a)
Junction to ambient
SO-8
QFN 3x3
130
170
°C/W
ELECTRICAL CHARACTERISTICS (Tamb = 25°C)
Symbol
IGT
Parameter
I
Gate triggering current
IH
Holding current
IRM
Reverse leakage current LINE / GND
Reverse leakage current GATE / LINE
Reverse voltage LINE / GND
Gate triggering voltage
IRG
VRM
VGT
VF
VR
VRM
VF
V
IRM
IR
Forward drop voltage LINE / GND
Peak forward voltage LINE / GND
VFP
IH
VDGL Dynamic switching voltage GATE / LINE
VGATE GATE / GND voltage
IPP
VRG
C
Reverse voltage GATE / LINE
Capacitance LINE / GND
2/9
LCP1521S/LCP152DEE
ABSOLUTE RATINGS (Tamb = 25°C, unless otherwise specified).
Symbol
Parameter
Peak pulse current (see note1)
Value
Unit
IPP
10/1000µs
8/20µs
10/560µs
5/310µs
10/160µs
1/20µs
30
100
35
40
50
100
170
A
2/10µs
ITSM
Non repetitive surge peak on-state
current
(50Hz sinusoidal)
t = 10ms
t = 1s
10
3
A
IGSM
Maximum gate current
(50Hz sinusoidal)
t = 10ms
2
A
V
VMLG
VMGL
Maximum voltage LINE/GND
Maximum voltage GATE/LINE
-40°C < Tamb < +85°C
-40°C < Tamb < +85°C
-150
-150
Tstg
Tj
Storage temperature range
Maximum junction temperature
- 55 to + 150
150
°C
°C
TL
Maximum lead temperature for soldering during 10s
260
Repetitive peak pulse current
% I
PP
100
tr: rise time (µs)
tp: pulse duration (µs)
ex: Pulse waveform 10/1000µs
50
0
tr = 10µs tp = 1000µs
t
t
t
r
p
1- PARAMETERS RELATED TO THE DIODE LINE / GND (Tamb = 25°C)
Symbol
Test conditions
Max
Unit
V
VF
IF = 5A
t = 500µs
RS = 10Ω
RS = 10Ω
RS = 62Ω
2
VFP
(note 1)
10/700µs
1.2/50µs
2/10µs
1.5kV
1.5kV
2.5kV
5
9
30
V
Note 1: see test circuit for V ; R is the protection resistor located on the line card.
FP
S
3/9
LCP1521S/LCP152DEE
2 - PARAMETERS RELATED TO THE PROTECTION THYRISTOR (Tamb = 25°C unless otherwise specified)
Symbol
IGT
Test conditions
Min
0.1
Max
Unit
mA
mA
V
VGND / LINE = -48V
5
IH
VGATE = -48V (note 2)
at IGT
150
VGT
IRG
2.5
VRG = -150V
Tc=25°C
Tc=85°C
5
50
µA
VRG = -150V
VDGL
VGATE = -48V (note 3)
10/700µs
1.2/50µs
2/10µs
1.5kV
1.5kV
2.5kV
RS = 10Ω
RS = 10Ω
RS = 62Ω
IPP = 30A
IPP = 30A
IPP = 38A
7
10
25
V
Note 2: see functional holding current (I ) test circuit
H
Note 3: see test circuit for V
DGL
The oscillations with a time duration lower than 50ns are not taken into account
3 - PARAMETERS RELATED TO DIODE AND PROTECTION THYRISTOR (Tamb = 25°C, unless other-
wise specified)
Symbol
Test conditions
Typ.
Max.
Unit
IRM
VGATE / LINE = -1V VRM = -150V
Tc=25°C
Tc=85°C
5
50
µA
VGATE / LINE = -1V VRM = -150V
C
VR = 50V bias, VRMS = 1V, F = 1MHz
VR = 2V bias, VRMS = 1V, F = 1MHz
15
35
pF
4/9
LCP1521S/LCP152DEE
FUNCTIONAL HOLDING CURRENT (IH) TEST CIRCUIT : GO-NO GO TEST
R
Surge generator
V
= - 100V
BAT
D.U.T
This is a GO-NO GO test which allows to confirm the holding current (IH) level in a functional test circuit.
TEST PROCEDURE :
- Adjust the current level at the IH value by short circuiting the D.U.T.
- Fire the D.U.T. with a surge current : IPP = 10A, 10/1000µs.
- The D.U.T. will come back to the off-state within a duration of 50ms max.
TEST CIRCUIT FOR VFP AND VDGL PARAMETERS
R
(VP is defined in unload condition)
4
TIP
L
R
2
RING
R
3
R
V
P
C
C
2
1
1
G ND
Pulse (µs)
Vp
C1
(µF)
20
C2
(nF)
200
33
L
R1
(Ω)
50
R2
(Ω)
15
13
0
R3
(Ω)
25
25
3
R4
(Ω)
25
25
3
IPP
Rs
(Ω)
10
10
62
tr
10
1.2
2
tp
700
50
(V)
(µH)
0
(A)
30
30
38
1500
1500
2500
1
0
76
10
10
0
1.1
1.3
5/9
LCP1521S/LCP152DEE
TECHNICAL INFORMATION
Fig. A1: LCP152 concept behavior.
Rs1
L 1
TIP
V Tip
ID1
IG
T1
Th1
D1
Gate
-Vbat
GND
GND
L 2
C
Rs2
VRing
RING
Figure A1 shows the classical protection circuit using the LCP152 crowbar concept. This topology
has been developed to protect the new high voltage SLIC’s. It allows to program the negative firing
threshold while the positive clamping value is fixed at GND.
When a negative surge occurs on one wire (L1 for example) a current IG flows through the base of the tran-
sistor T1 and then injects a current in the gate of the thyristor Th1. Th1 fires and all the surge current flows
through the ground. After the surge when the current flowing through Th1 becomes less negative than the
holding current IH, then Th1 switches off.
When a positive surge occurs on one wire (L1 for example) the diode D1 conducts and the surge current
flows through the ground.
Fig. A2: Example of PCB layout based on LCP152 protection.
GND
To
To
SLIC side
line side
In order to minimize the remaining voltage across the SLIC inputs during the surge, the TIP and RING pins
of the LCP152 are doubled (Pins 1 and 8 for TIP / Pins 4 and 5 for RING).
This fact allows the board designer to connect the tracks like in figure A2. With such a PCB design, the ex-
tra voltages caused by track stray inductance remain located on the line side of the LCP and do not affects
the SLIC side.
The capacitor C is used to speed up the crowbar structure firing during the fast surge edges.
This allows to minimize the dynamical breakover voltage at the SLIC Tip and Ring inputs during fast
strikes. Note that this capacitor is generally present around the SLIC - Vbat pin.
So to be efficient it has to be as close as possible from the LCP152 Gate pin and from the reference
ground track (or plan) (see Fig. A2). The optimized value for C is 220nF.
6/9
LCP1521S/LCP152DEE
The series resitors Rs1 and Rs2 designed in figure A1 represent the fuse resistors or the PTC which are man-
datory to withstand the power contact or the power induction tests imposed by the various country standards.
Taking into account this fact the actual lightning surge current flowing through the LCP is equal to:
I surge = V surge / (Rg + Rs)
With
V surge = peak surge voltage imposed by the standard.
Rg = series resistor of the surge generator
Rs = series resistor of the line card (e.g. PTC)
e.g. For a line card with 30Ω of series resistors which has to be qualified under GR1089 Core 1000V
10/1000µs surge, the actual current through the LCP152 is equal to:
I surge = 1000 / (10 + 30) = 25A
The LCP152 is particularly optimized for the new telecom applications such as the fiber in the loop, the
WLL, the remote central office. In this case, the operating voltages are smaller than in the classical system.
This makes the high voltage SLICs particularly suitable. The schematics of figure A3 gives the most fre-
quent topology used for these applications.
Fig. A3: Protection of high voltage SLIC.
-Vbat
Rs (*)
TIP
Gate
220nF
TIP
GND
GND
GND
Line
SLIC
RING
Rs (*)
RING
LCP152
Line card
Rs (*) = PTC or Resitor fuse
7/9
LCP1521S/LCP152DEE
Fig. 1: Surge peak current versus overload dura-
tion.
Fig. 2: Relative variation of holding current versus
junction temperature
IH ( Tj ) / IH ( Tj=25°C )
1.3
1.2
1.1
1
TO BE DEFINED
0.9
0.8
Tj ( °C )
0.7
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
PACKAGE MECHANICAL DATA
QFN 3x3 (6 Leads)
DIMENSIONS
REF.
Millimetres
Inches
Min. Typ. Max. Min. Typ. Max.
A
A1
A2
A3
b
0.80
0
1
0.031
0
0.040
0.002
0.030
0.05
0.65
0.75 0.026
20
3
0.787
0.33
2.90
1.92
2.90
1.11
0.43 0.013
0.017
D
3.10 0.114 0.118 0.122
2.12 0.076 0.083
0.114 0.118 0.122
D2
E
3
3.10
E2
e
1.31 0.044
0.051
0.018
0.005
12°
0.95
0.24
0.037
0.009
L
0.20
0.45 0.008
L1
L2
K
0.13
0.20
0°
0.008
<
12°
0°
8/9
LCP1521S/LCP152DEE
DIMENSIONS
PACKAGE MECHANICAL DATA
SO-8 (Plastic)
REF.
Millimetres
Inches
Min. Typ. Max. Min. Typ. Max.
L
A
a1
a2
a3
b
1.75
0.069
0.010
0.065
0.033
0.019
0.010
0.020
c1
C
0.1
0.25 0.004
1.65
a3
A
a2
0.65
0.35
0.19
0.85 0.025
0.48 0.014
0.25 0.007
b
1
a1
e
b
E
e3
b1
C
D
M
0.25 0.50 0.50 0.010
45° (typ)
c1
D
5
8
4.8
5.8
5.0 0.189
6.2 0.228
0.197
0.244
F
E
1
4
e
1.27
3.81
0.050
0.150
e3
F
3.8
0.4
4.0 0.15
1.27 0.016
0.6
0.157
0.050
0.024
L
M
S
8° (max)
Order code
Marking
CP152S
CP152S
CP15
Package
SO-8
Weight
Base qty
Delivery mode
Tube
LCP1521S
0.08 g
0.08 g
100
2500
3000
LCP1521SRL
SO-8
Tape & Reel
Tape & Reel
LCP152DEERL
QFN 3x3
0.022 g
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of
use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroelectronics - Printed in Italy - All rights reserved.
STMicroelectronics GROUP OF COMPANIES
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9/9
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