L6917DTR [ETC]
Analog IC ; 模拟IC\n
| 型号： | L6917DTR |
| 厂家： | 
ETC |
| 描述： | Analog IC
|
| 文件： | 总27页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6917
5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER
■
2 PHASE OPERATION WITH
SYNCRHONOUS RECTIFIER CONTROL
■ ULTRA FAST LOAD TRANSIENT RESPONSE
■
INTEGRATED HIGH CURRENT GATE
DRIVERS: UP TO 2A GATE CURRENT
SO-28
■
TTL-COMPATIBLE 5 BIT PROGRAMMABLE
ORDERING NUMBERS: L6917D
OUTPUT COMPLIANT WITH VRM 9.0
L6917DTR (Tape & Reel)
■
0.8% INTERNAL REFERENCE ACCURACY
■
10% ACTIVE CURRENT SHARING
ACCURACY
DESCRIPTION
The device is a power supply controller specifically
designed to provide a high performance DC/DC con-
version for high current microprocessors.
The device implements a dual-phase step-down con-
troller with a 180° phase-shift between each phase.
■ DIGITAL 2048 STEP SOFT-START
■
OVERVOLTAGE PROTECTION
■
OVERCURRENT PROTECTION REALIZED
USING THE LOWER MOSFET’S R
OR A
dsON
SENSE RESISTOR
A precise 5-bit digital to analog converter (DAC) al-
lows adjusting the output voltage from 1.100V to
1.850V with 25mV binary steps.
■
■
300 kHz INTERNAL OSCILLATOR
OSCILLATOR EXTERNALLY ADJUSTABLE
UP TO 1MHz
■ POWER GOOD OUTPUT AND INHIBIT
The high precision internal reference assures the se-
lected output voltage to be within ±0.8%. The high
peak current gate drive affords to have fast switching
to the external power mos providing low switching
losses.
FUNCTION
■
REMOTE SENSE BUFFER
■ PACKAGE: SO-28
APPLICATIONS
■ POWER SUPPLY FOR SERVER AND
The device assures a fast protection against load
over current and load over/under voltage. An internal
crowbar is provided turning on the low side mosfet if
an over-voltage is detected. In case of over-current
or under voltage, the system works in HICCUP mode.
WORKSTATION
■
POWER SUPPLY FOR HIGH CURRENT
MICROPROCESSORS
■
DISTRIBUTED POWER SUPPLY
BLOCK DIAGRAM
ROSC /INH
SG ND
VCCDR
BOOT1
PGO OD
UGATE1
PHASE1
HS
2
PHASE
OSCILLATOR
PWM1
-
+
CH 1 OVER
CU RR ENT
LGATE1
ISEN1
LS
DIGITAL
SO FT STA RT
VCC
VCCDR
CURRENT
READING
LO GIC
AND
PROTECTIONS
PGNDS1
PGND
TOTAL
CURR ENT
+
VID4
VID3
AVG
CU RRENT
PGNDS2
CURRENT
READING
VID2
VID1
< >
DAC
CH 2 OVER
CURR ENT
ISEN2
VID0
CH1 OVER
CU RR ENT
LGATE2
CH
CU RR ENT
2 OVER
LS
10k
+
-
10k
10k
IFB
FBG
FBR
PHASE2
UGATE2
BOOT2
PWM2
ERROR
AMPLIFIER
REMOTE
BUFFER
HS
10k
Vcc
VSEN
FB
COMP
Vc c
October 2001
1/27
L6917
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
15
Unit
V
Vcc, V
To PGND
CCDR
V
-V
Boot Voltage
15
V
BOOT PHASE
V
V
-V
15
V
UGATE1 PHASE1
-V
UGATE2 PHASE2
LGATE1, PHASE1, LGATE2, PHASE2 to PGND
All other pins to PGND
-0.3 to Vcc+0.3
-0.3 to 7
V
V
THERMAL DATA
Symbol
Parameter
Value
60
Unit
R
Thermal Resistance Junction to Ambient
Maximum junction temperature
Storage temperature range
C/W
°
th j-amb
T
150
C
°
max
T
-40 to 150
-25 to 125
2
C
°
storage
T
j
Junction Temperature Range
°C
P
Max power dissipation at T
= 25°C
W
MAX
amb
PIN CONNECTION
LGATE1
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PGND
LGATE2
PHASE2
UGATE2
BOOT2
PGOOD
VID4
VCCDR
PHASE1
UGATE1
BOOT1
VCC
2
3
4
5
6
GND
7
COMP
FB
8
VID3
9
VID2
VSEN
FBR
10
11
12
13
14
VID1
VID0
FBG
OSC/ INH/ FAULT
ISEN2
ISEN1
PGNDS1
PGNDS2
SO28
2/27
L6917
ELECTRICAL CHARACTERISTICS
(V = 12V, T
= 25°C unless otherwise specified)
CC
amb
Symbol
Vcc SUPPLY CURRENT
Vcc supply current
Parameter
Test Condition
Min
Typ
Max
Unit
I
HGATEx and LGATExopen
6
8
10
mA
CC
V
=V
CCDR
=12V
BOOT
I
V
supply current
LGATEx open; V =12V
CCDR
2
3
1
4
mA
mA
CCDR
CCDR
I
Boot supply current
HGATEx open; PHASEx to PGND
0.5
1.5
BOOTx
V
=V
CC
=12V
BOOT
POWER-ON
Turn-On V threshold
V
V
Rising; V =5V
CCDR
7.8
6.5
4.2
9
10.2
8.5
V
V
V
CC
CC
Turn-Off V threshold
Falling; V =5V
CCDR
7.5
4.4
CC
CC
Turn-On V
Threshold
V
V
Rising
4.6
CCDR
CCDR
=12V
CC
Turn-Off V
Threshold
V
V
Falling
=12V
4.0
4.2
4.4
V
CCDR
CCDR
CC
OSCILLATOR AND INHIBIT
f
Initial Accuracy
OSC = OPEN
OSC = OPEN; Tj=0°C to 125°C
278
270
300
500
322
330
kHz
kHz
OSC
f
Total Accuracy
R
T
to GND=74kΩ
450
550
0.9
kHz
OSC,Ros
c
INH
Inhibit threshold
I
=5mA
SINK
0.8
80
0.85
85
2
V
%
V
d
Maximum duty cycle
Ramp Amplitude
OSC = OPEN
MAX
∆Vosc
1.8
2.2
0.8
REFERENCE AND DAC
Output Voltage
Accuracy
VID0, VID1, VID2, VID3, VID4
-0.8
-
%
see Table1; Tamb=0 to 70 ;
°
°
FBR = V ; FBG = GND
OUT
I
VID pull-up Current
VID pull-up Voltage
VIDx = GND
4
5
-
6
A
µ
DAC
VIDx = OPEN
3.1
3.4
V
ERROR AMPLIFIER
DC Gain
80
15
dB
SR
Slew-Rate
COMP=10pF
V/µs
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER)
DC Gain
1
V/V
dB
CMRR Common Mode Rejection Ratio
40
Input Offset
FBR=1.100V to1.850V;
FBG=GND
-12
12
mV
3/27
L6917
ELECTRICAL CHARACTERISTICS
(continued)(V = 12V, T
= 25°C unless otherwise specified)
CC
amb
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
SR
Slew Rate
VSEN=10pF
15
V/µs
DIFFERENTIAL CURRENT SENSING
I
I
,
Bias Current
Iload=0
45
50
50
55
µA
µA
ISEN1
ISEN2
I
Bias Current
45
80
55
90
PGNDSx
I
I
,
Bias Current at
Over Current Threshold
Positive
Negative
85
37.5
µA
µA
ISEN1
ISEN2
I
Active Droop Current
Iload<0%
Iload=100%
0
50
1
52.5
µA
µA
FB
47.5
GATE DRIVERS
t
High Side
Rise Time
V
C
-V =10V;
BOOTx PHASEx
15
30
ns
RISE
HGATE
to PHASEx=3.3nF
HGATEx
I
High Side
Source Current
V
V
-V =10V
BOOTx PHASEx
2
2
A
Ω
HGATEx
R
High Side
Sink Resistance
-V =12V;
BOOTx PHASEx
1.5
2.5
55
HGATEx
t
Low Side
Rise Time
V
C
=10V;
CCDR
30
ns
RISE
LGATE
to PGNDx=5.6nF
LGATEx
I
Low Side
Source Current
V
V
=10V
1.8
1.1
A
LGATEx
CCDR
R
Low Side
=12V
CCDR
0.7
1.5
Ω
LGATEx
Sink Resistance
PROTECTIONS
PGOOD Upper Threshold
V
V
V
V
Rising
Falling
Rising
Falling
109
84
112
88
115
92
%
%
V
SEN
SEN
SEN
SEN
(V
SEN
/DACOUT)
PGOOD Lower Threshold
(V /DACOUT)
SEN
OVP
Over Voltage Threshold
(V
2.0
76
2.1
80
2.2
84
)
SEN
UVP
Under Voltage Trip
(V /DACOUT)
%
SEN
V
PGOOD Voltage Low
I
= -4mA
PGOOD
0.3
0.4
5.0
0.5
V
V
PGOOD
FAULT Fault Condition
After OVP or 3 HICCUP cycles
4.75
5.25
4/27
L6917
Table 1. VID Settings
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Output Voltage (V)
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
OUTPUT OFF
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
5/27
L6917
PIN FUNCTION
N
1
2
3
Name
LGATE1 Channel 1 low side gate driver output.
Description
VCCDR Mosfet driver supply. It can be varied from 5V to 12V Bus.
PHASE1 This pin is connected to the source of the upper mosfet and provides the return path for the high
side driver of channel 1.
4
5
UGATE1 Channel 1 high side gate driver output.
BOOT1 Channel 1 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper
mosfet. Connect through a capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs.
boot).
6
7
8
VCC
GND
Device supply voltage. The operative supply voltage is 12V.
All the internal references are referred to this pin. Connect it to the PCB signal ground.
COMP This pin is connected to the error amplifier output and is used to compensate the control
feedback loop.
9
FB
This pin is connected to the error amplifier inverting input and is used to compensate the voltage
control feedback loop.
A current proportional to the sum of the current sensed in both channel is sourced from this pin
(50µA at full load, 70µA at the Over Current threshold). Connecting a resistor between this pin
and VSEN pin allows programming the droop effect.
10
11
VSEN
Connected to the output voltage it is able to manage Over & Under-voltage conditions and the
PGOOD signal. It is internally connected with the output of the Remote Sense Buffer forRemote
Sense of the regulated voltage.
If no Remote Sense is implemented, connect it directly to the regulated voltage in order to
manage OVP, UVP and PGOOD.
FBR
FBG
Remote sense buffer non-inverting input. It has to be connected to the positive side of the load to
perform a remote sense.
If no remote sense is implemented, connect directly to the output voltage (in this case connect
also the VSEN pin directly to the output regulated voltage).
12
13
Remote sense buffer inverting input. It has to be connected to the negative side of the load to
perform a remote sense.
Pull-down to ground if no remote sense is implemented.
ISEN1 Channel 1 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet Rds This pin has to be connected to the low-side mosfet drain or
ON.
to the sense resistor through a resistor Rg in order to program the positive current limit at 140%
as follow:
35µA Rg
IMAX_POS1 = --------------------------
Rsense
Where 35 A is the current offset information relative to the Over Current condition (offset at OC
µ
threshold minus offset at zero load).
In the same way the negative current limit threshold results to be set at –50% as follow:
–12.5µA Rg
I MAX_NEG1 = ----------------------------------
Rsense
Where –12.5µA is the current offset information relative to the Negative Over Current condition
(offset at Negative OC threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS1 net in order to couple in common mode any picked-up noise.
14
PGNDS1 Channel 1 Power Ground sense pin. The net connecting the pin to the sense point (Through a
resistor R ) must be routed as close as possible to the ISEN1 net in order to couple in common
g
mode any picked-up noise.
6/27
L6917
PIN FUNCTION
(continued)
Name
PGNDS2 Channel 2 Power Ground sense pin. The net connecting the pin to the sense (Through a resistor
N
Description
15
R ) point must be routed as close as possible to the ISEN2 net in order to couple in common
g
mode any picked-up noise.
16
ISEN2 Channel 2 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet Rds
This pin has to be connected to the low-side mosfet drain or
ON.
to the sense resistor through a resistor Rg in order to program the positive current limit at 140%
as follow:
35µA Rg
IMAX_POS2 = --------------------------
Rsense
Where 35 A is the current offset information relative to the Over Current condition (offset at OC
µ
threshold minus offset at zero load).
In the same way the negative current limit threshold results to be set at –50% as follow
–12.5µA Rg
I MAX_NEG2 = ----------------------------------
Rsense
Where –12.5µA is the current offset information relative to the Negative Over Current condition
(offset at Negative OC threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS2 net in order to couple in common mode any picked-up noise.
17
OSC/INH Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the
FAULT external frequency is increased according to the equation:
14.82 106
f S = 300KHz + -----------------------------
R
OSC(KΩ)
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to
the equation:
12.91 107
f S = 300KHz + -----------------------------
R
OSC(KΩ)
If the pin is not connected, the switching frequency is 300KHz.
Forcing the pin to a voltage lower than 0.8V, the device stop operation and enter the inhibit state.
The pin is forced high when an over voltage is detected and after three hiccup cycles. This
condition is latched; to recover it is necessary turn off and on VCC.
18-22
23
VID4-0 Voltage IDentification pins. These input are internally pulled-up and TTL compatible. They are
used to program the output voltage as specified in Table 1 and to set the power good thresholds.
Connect to GND to program a ‘0’ while leave floating to program a ‘1’.
PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above
specified thresholds.
If not used may be left floating.
24
BOOT2 Channel 2 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper
mosfet. Connect through a capacitor to the PHASE2 pin and through a diode to Vcc (cathode vs.
boot).
25
26
UGATE2 Channel 2 high side gate driver output.
PHASE2 This pin is connected to the source of the upper mosfet and provides the return path for the high
side driver of channel 2.
27
28
LGATE2 Channel 2 low side gate driver output.
PGND Power ground pin. This pin is common to both sections and it must be connected through the
closest path to the low side mosfets source pins in order to reduce the noise injection into the
device.
7/27
L6917
Device Description
The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections
for a high performance multiphase step-down DC-DC converter optimized for microprocessor power supply. It
is designed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg
phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing
also the size and the losses. The output voltage of the converter can be precisely regulated, programming the
VID pins, from 1.100V to 1.850V with 25mV binary steps, with a maximum tolerance of ±0.8% over temperature
and line voltage variations. The device provides an average current-mode control with fast transient response.
It includes a 300kHz free-running oscillator externally adjustable up to 1MHz. The error amplifier features a 15Vµ/s
slew rate that permits high converter bandwidth for fast transient performances. Current information is read
across the lower mosfets rDSON or across a sense resistor in fully differential mode. The current information
corrects the PWM output in order to equalize the average current carried by each phase. Current sharing be-
tween the two phases is then limited at ±10% over static and dynamic conditions. The device protects against
over-current, with an OC threshold for each phase, entering in HICCUP mode. After three hiccup cycles, the
condition is latched and the FAULT pin is driven high. The device performs also an under voltage protection that
causes a hiccup cycle when detected, and an over voltage protection that disable immediately the device turning
ON the lower driver and driving high the FAULT pin.
The device is available in SO28 package.
Oscillator
The switching frequency is internally fixed to 300kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
oscillator is typically 25µA (F
= 300KHz) and may be varied using an external resistor (R ) connected be-
OSC
SW
tween OSC pin and GND or Vcc. Since the OSC pin is maintained at fixed voltage (typ). 1.235V, the frequency
µ
is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 12KHz/ A.
In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting
ROSC to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relation-
ships:
6
1.237
+ ------------------------------
kHz
----------- =
14.82 10
=
S
+ ------------------------------
R
vs. GND: f
300kHz
12
300kHz
OSC
OSC
( Ω)
µ
A
R
K
R
(KΩ)
OSC
OSC
7
12 – 1.237
+ ------------------------------ 12----------- =
(KΩ) µA
kHz
12.918 10
=
– ------------------------------- -
(KΩ)
R
vs. 12V: f
300kHz
300kHz
S
R
R
OSC
OSC
Note that forcing a 25µA current into this pin, the device stops switching because no current is delivered to the
oscillator.
Figure 1. R
vs. Switching Frequency
OSC
7000
1000
900
800
700
600
500
400
300
200
100
0
6000
5000
4000
3000
2000
1000
0
0
100
200
300
300 400 500 600 700 800 900 1000
Frequency(KHz)
Frequency (KHz)
8/27
L6917
Digital to Analog Converter
The built-in digital to analog converter allows the adjustment of the output voltage from 1.100V to 1.850V with
25mV steps as shown in the previous table 1. The internal reference is trimmed to ensure the precision of 0.8%
and a zero temperature coefficient around 70°C. The internal reference voltage for the regulation is pro-
grammed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is
realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code
drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an
amplifier obtaining the V
voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are
PROG
provided (realized with a 5µA current generator up to 3.3V max); in this way, to program a logic ”1” it is enough
to leave the pin floating, while to program a logic ”0” it is enough to short the pin to GND.
The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the over-
voltage protection (OVP) thresholds.
Soft Start and INHIBIT
At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in
2048 clock periods as shown in figure 2.
Before soft start, the lower power MOS are turned ON after that V
reaches 2V (independently by Vcc value)
CCDR
to discharge the output capacitor and to protect the load from high side mosfet failures. Once soft start begins,
the reference is increased; when it reaches the bottom of the oscillator triangular waveform (1V typ) also the
upper MOS begins to switch and the output voltage starts to increase with closed loop regulation. At the end of
the digital soft start, the Power Good comparator is enabled and the PGOOD signal is then driven high (See fig.
2). The Negative Current Limit comparators and Under Voltage comparator are enabled when the reference
voltage reaches 0.8V.
The Soft-Start will not take place, if both Vcc and VCCDR pins are not above their own turn-on thresholds. Dur-
ing normal operation, if any under-voltage is detected on one of the two supplies the device shuts down.
Forcing the OSC/INH/FAULT pin to a voltage lower than 0.8V the device enter in INHIBIT mode: all the power
mosfets are turned off until this condition is removed. When this pin is freed, the OSC/INH/FAULT pin reaches
the band-gap voltage and the soft start begins.
Figure 2. Soft Start
VIN=VCCDR
Turn ON threshold
2V
VLGATEx
t
t
t
t
VOUT
PGOOD
2048 Clock Cycles
Timing Diagram
Acquisition:
CH1 = PGOOD; CH2 = V ; CH4 = LGATEx
OUT
9/27
L6917
Driver Section
The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the
RDSON), maintaining fast switching transition.
The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers for
the low-side mosfets use VCCDR pin for supply and PGND pin for return. A minimum voltage of 4.6V at VCCDR
pin is required to start operations of the device.
The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction
time maintaining good efficiency and saving the use of Schottky diodes. The dead time is reduced to few nano-
seconds assuring that high-side and low-side mosfets are never switched on simultaneously: when the high-
side mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side mosfet
gate drive is applied with 30ns delay. When the low-side mosfet turns off, the voltage at LGATEx pin is sensed.
When it drops below 1V, the high-side mosfet gate drive is applied with a delay of 30ns.
If the current flowing in the inductor is negative, the source of high-side mosfet will never drop. To allow the turn-
ing on of the low-side mosfet even in this case, a watchdog controller is enabled: after 240ns, the low side mos-
fet is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the
system to regulate even if the current is negative.
The BOOTx and VCCDR pins are separated from IC’s power supply (VCC pin) as well as signal ground (SGND
pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The separated supply
for the different drivers gives high flexibility in mosfet choice, allowing the use of logic-level mosfet. Several com-
bination of supply can be chosen to optimize performance and efficiency of the application. Power conversion
is also flexible, 5V or 12V bus can be chosen freely.
Placement of the power mosfets is critical: long and narrow trace length from UGATEx and LGATEx pins to the
mosfets’ gates may cause high amount of ringing due to the resonance between inductance of the trace and
the gate capacitance of the mosfet. A gate resistance of a few ohms can help in reducing ringing and power
dissipation of the controller without compromising system efficiency.
The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF capac-
itive load has been used. For the upper drivers, the source current is 1.9A while the sink current is 1.5A with
V
-V
= 12V; similarly, for the lower drivers, the source current is 2.4A while the sink current is 2A with
BOOT PHASE
VCCDR = 12V.
Figure 3. Drivers peak current: High Side (left) and Low Side (right)
CH3 = HGATE1; CH4 = HGATE2
CH3 = LGATE1; CH4 = LGATE2
10/27
L6917
Current Reading and Over Current
The current flowing trough each phase is read using the voltage drop across the low side mosfets r
or
DSON
across a sense resistor (R ) and internally converted into a current. The transconductance ratio is issued
SENSE
by the external resistor Rg placed outside the chip between ISENx and PGNDSx pins toward the reading points.
The full differential current reading rejects noise and allows to place sensing element in different locations with-
out affecting the measurement’s accuracy. The current reading circuitry reads the current during the time in
which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx
at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two
pins at the same voltage sinking from the ISENx pin the necessary current.
The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and
negative current. This circuit reproduces the current flowing through the sensing element using a high speed
Track & Hold transconductance amplifier. In particular, it reads the current during the second half of the OFF
time reducing noise injection into the device due to the mosfet turn-on (See fig. 4).
Figure 4.
ILS1
LGATEX
Rg
ILS2
ISENX
IISENx
Total current
information
Rg
PGNDSX
50µA
Track & Hold
This circuit sources a constant 50µA current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at
the same voltage. Referring to figure 4, the current that flows in the ISENx pin is then given by the following
equation:
R
I
SENSE PHASE
=
µ
+ ---------------------------------------------- =
µ
+
50 A I
INFOx
I
50 A
ISENx
R
g
Where R
is an external sense resistor or the r , on of the low side mosfet and Rg is the transconduc-
dson
SENSE
tance resistor used between ISENx and PGNDSx pins toward the reading points; I
is the current carried
PHASE
by each phase and, in particular, the current measured in the middle of the oscillator period
The current information reproduced internally is represented by the second term of the previous equation as
follow:
R
I
SENSE PHASE
I
= ----------------------------------------------
INFOx
R
g
Since the current is read in differential mode, also negative current information is kept; this allow the device to
check for dangerous returning current between the two phases assuring the complete equalization between the
phase’s currents.
From the current information of each phase, information about the total current delivered (I = I
+ I
)
FB
INFO1
INFO2
and the average current for each phase (I
= (I
+ I
)/2 ) is taken. I
is then compared to I
INFOX AVG
AVG
INFO1
INFO2
to give the correction to the PWM output in order to equalize the current carried by the two phases.
11/27
L6917
Figure 5. HICCUP Mode (left) and OCP threshold and Current information (right)
IFB
µ
µ
2x35 A=70
A
2x25µA=50µA
IOUT
IINFOx
µ
35
A
µ
25
A
IOUT
-12.5µA
Hiccup Mode:
CH1 = FAULT; CH2 = V ; CH3 = I ; CH4 = I
L2
OUT
L1
The over current threshold for each phase is set when I
= 35µA. Since the over current detection gives
INFOx
origin to Hiccup cycles (and the output voltage goes down to zero, with information losses for the microproces-
sor) the over current threshold must be greater than the nominal current.
Placing the OC threshold at +40% gives a margin to sustain the heavy load transient issued by the processor.
As a consequence, the transconductance resistor Rg has to be designed in order to have current information of
µ
FB
µ
35 A at 140% of the nominal load, corresponding to 25 A at nominal load. Considering the feedback current
(I ), this will be equal to 50µA at nominal load and 70µA at over current threshold as shown in figure 5.
Since the device is able to read negative current, negative current limit is also provided and it is set when I
INFOx
µ
= -12.5 A , corresponding to -50% of the full nominal current. No current is sunk from the FB pin in this condition.
According to the above relationship, the positive limiting current (I ) for each phase, which has to be
LIM_POS
placed at one half of the total delivered maximum current and the limiting negative current (I
), results:
LIM_NEG
R
SENSE
I
35µA Rg
–12.5µA Rg
LIM
I
= ---------------------------
I
= -----------------------------------
Rg = -------------------------------------
LIM_POS
LIM_NEG
R
R
35µA
SENSE
SENSE
When over current is detected, all mosfets are turned OFF, the device waits for 2048 clock cycles and another
soft-start is implemented. Over Current is always active, also during soft-start. After three Over Current event,
the condition is latched and the device stops working; Vcc turn OFF and ON is required to restart device oper-
ation.
µ
reaches 35 A. The full load value is only a convention to work with con-
Over current is set anyway when I
INFOx
venient values for I . Since the OPC intervention threshold is fixed, to modify the percentage with respect to
FB
the load value, it can be simply considered that, for example, to have on OCP threshold of 170%, this will cor-
respond to I
= 35µA (I = 70µA). The full load current will then correspond to I
= 20.5µA (I = 41µA).
INFOx FB
INFOx
FB
Over current is managed as an under voltage: after a combination of three of then, the device latches the con-
dition and the FAULT pin is driven high.
The full differential path helps the designer to place sensing element where wanted. Transconductance Rg re-
sistors must be placed as close as possible to ISENx and PGNDSx pins in order to reject noise from the device.
Keeping the traces parallel and guarded by a power plane results in common mode coupling for any picked-up
noise.
12/27
L6917
Current Sharing
Active current sharing is implemented using the information from transconductance differential amplifier in an
average current mode control scheme. A current reference equal to the average of the read current (I ) is
AVG
internally built; the error between the read current and this reference is converted to a voltage with a proper gain
and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at COMP pin.
The current sharing control is a high bandwidth control allowing current sharing even during load transients.
The current sharing error is affected by the choose of external components; choose precise Rg resistor (±1%
is necessary) to sense the current. The current sharing error is internally dominated by the voltage offset of
transconductance differential amplifier; considering a voltage offset equal to 2mV across the sense resistor, the
current reading error is given by the following equation:
∆
I
2mV
-------------------- = --------------------------------------- -
READ
I
R
I
SENSE MAX
MAX
∆
Where
I
is the difference between one phase current and the ideal current (I
/2).
MAX
READ
For Rsense=4mΩ and Imax=40A the current sharing error is equal to 2.5%, neglecting errors due to Rg and
Rsense mismatches.
Figures 6 and 7 show the current sharing error obtained at 0A and 30A using a sense resistor or the low side
mosfet’s R
as sensing element. The static error obtained using the R
is due to the tolerance of this
dsON
dsON
parameter (up to 30%).
Figure 6. Current Sharing Error using R
as sensing element at 0A (left) and 30A (right).
dsON
CH1 = PHASE1; CH2 = PHASE2; CH3 = I ; CH4 = I
L2
L1
13/27
L6917
Figure 7. Current Sharing Error using R
as sensing element at 0A (left) and 30A (right)..
SENSE
CH1 = PHASE1; CH2 = PHASE2; CH3 = I ; CH4 = I
L2
L1
Integrated Droop Function
The device uses a droop function to satisfy the requirements of high performance microprocessors, reducing
the size and the cost of the output capacitor.
This method ”recovers” part of the drop due to the output capacitor ESR in the load transient, introducing a de-
pendence of the output voltage on the load current
As shown in figure 8, the ESR drop is present in any case, but using the droop function the total deviation of the
output voltage is minimized. In practice the droop function introduces a static error (Vdroop in figure 8) propor-
tional to the output current. Since the device has an average current mode regulation, the information about the
total current delivered is used to implement the Droop Function. This current (equal to the sum of both I
)
INFOx
is sourced from the FB pin. Connecting a resistor between this pin and Vout, the total current information flows
only in this resistor because the compensation network between FB and COMP has always a capacitor in series
(See fig. 9). The voltage regulated is then equal to:
V
= V - R · I
ID FB FB
OUT
Since I depends on the current information about the two phases, the output characteristic vs. load current is
FB
given by:
R
SENSE
---------------------- I
V
= VID – R
FB
OUT
OUT
Rg
Figure 8. Output transient response without (a) and with (b) the droop function
ESR DROP
ESR DROP
VMAX
VDROOP
VNOM
VMIN
(a)
(b)
14/27
L6917
Figure 9. Active Droop Function Circuit
RFB
To VOUT
FB
COMP
IFB
VPROG
µ
µ
) and 70 A at the OC threshold,
FB INFO1 INFO2
The feedback current is equal to 50 A at nominal full load (I = I
+ I
so the maximum output voltage deviation is equal to:
∆V = +R · 70µA
∆V
= +R · 70µA
FB
FULL_POSITIVE_LOAD
FB
POSITIVE_OC_THRESHOLD
Droop function is provided only for positive load; if negative load is applied, and then I
< 0, no current is
INFOx
sunk from the FB pin. The device regulates at the voltage programmed by the VID.
Output Voltage Protection and Power Good
The output voltage is monitored by pin VSEN. If it is not within +12/-10% (typ.) of the programmed value, the
powergood output is forced low. Power good is an open drain output and it is enabled only after the soft start is
finished (2048 clock cycles after start-up).
The device provides over voltage protection; when the voltage sensed by the V
pin reaches 2.1V (typ.), the
SEN
controller permanently switches on both the low-side mosfets and switches off both the high-side mosfets in or-
der to protect the CPU. The OSC/INH/FAULT pin is driven high (5V) and power supply (Vcc) turn off and on is
required to restart operations. The over Voltage percentage is set by the ratio between the OVP threshold (set
at 2.1V) and the reference programmed by VID.
2.1V
---------------------------------------------------------------------------- - 100
=
OVP[%]
(
)
Reference Voltage VID
Under voltage protection is also provided. If the output voltage drops below the 85% of the reference voltage for
more than one clock period the device turns off all mosfets and waits for 2048 clock cycles before another soft-
start. An Under Voltage event is then managed as an Over Current event; after a combination of three of them,
the device latches the condition and the FAULT is driven high.
Both Over Voltage and Under Voltage are active also during soft start (Under Voltage after than Vout reaches
0.8V). The reference voltage used to determine the UV thresholds is nowthe increasing voltage driven by the
2048 soft start digital counter.
Remote Voltage Sense
A remote sense buffer is integrated into the device to allow output voltage remote sense implementation without
any additional external components. In this way, the output voltage programmed is regulated between the re-
mote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM
module. The low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR is for
the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin
15/27
L6917
with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded by a power plane
results in common mode coupling for any picked-up noise.
If remote sense is not required, the output voltage is sensed by the VSEN pin connecting it directly to the output
voltage. In this case the FBG and FBR pins must be connected anyway to the regulated voltage.
Input Capacitor
The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFETS. Con-
sidering the dual phase topology, the input rms current is highly reduced because of the peak current is one half
if compared with a single-phase solution.
Input capacitor must have a low ESR to minimize the losses. The rms value of this ripple is:
I
OUT
= ------------
D
1 – D
( )
I
rms
2
Where D is the duty cycle. The equation reaches its maximum value width D=0.5. The losses in worst case are:
2
rms
P = ESR I
Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible
to reduce switching noise above all during load transient. A symmetrical power path will help to improve tran-
sient response. Input coil may be used taking from this point the supply for the controller VCC and VCCDRV,
designing a ’star connection’.
IC’s power supplies filter capacitor must be placed as close as possible to VCC and VCCDRV pins; for the VCC
pins a typical value is of 1µF and must be used connected between VCC and SGND pins. For better noise fil-
tering a series resistor of a few tenth ohm is suggested since the device typically works with the same power
supply used for the power conversion (noisy because of the switching mosfet).
Capacitor on VCCDRV pin filter the low-side drivers power supply toward the PGND pin; 1µF capacitor is rec-
ommended.
The 12V input power bus can be used to supply the bootstrap capacitor alone or together with a 5.1V zener
diode in series and a 1µF capacitor for filtering. A gate-source voltage of 7V is so ready to switch on the high-
side mosfets with a good compromise of efficiency and controller power dissipation. Alternatively a linear regu-
lator can be used to produce the supply for high-side and low-side power mosfet drivers. This can help to opti-
mize the choose of switching frequency, controller power dissipation and overall efficiency.
Output Capacitor
Since the microprocessors require a current variation beyond 50A doing load transients, with a slope in the
range of tenth A/µs, the output capacitor is a basic component for the fast response of the power supply.
Dual phase topology reduces the amount of output capacitance needed because of faster load transient re-
sponse (switching frequency is doubled at the load connections). Current ripple cancellation due to the 180°
phase shift between the two phases also reduces requirements on the output ESR to sustain a specified voltage
ripple.
When a load transient is applied to the converter’s output, for first few microseconds the current to the load is
supplied by the output capacitors. The controller recognizes immediately the load transient and increases the
duty cycle, but the current slope is limited by the inductor value.
The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):
∆V
= ∆I
· ESR
OUT
OUT
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
16/27
L6917
voltage drop due to the output capacitor discharge is given by the following equation:
2
∆
I
L
OUT
∆
= --------------------------------------------------------------------------------------------
V
OUT
(
–
V
)
OUT
2 C
V
D
OUT
INMIN
MAX
Where D
is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load
MAX
transient and the lower is the output voltage static ripple.
Inductor design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
∆
the ripple current IL between 20% and 30% of the maximum output current. The inductance value can be cal-
culated with this relationship:
V
– V
V
OUT OUT
IN
= ------------------------------ ---------------
L
fs ∆I
V
IN
L
Where f is the switching frequency, V is the input voltage and V is the output voltage.
OUT
S
IN
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. The response time is the time required by the inductor to change its current
from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by
the output capacitors. Minimizing the response time can minimize the output capacitance required.
The response time to a load transient is different for the application or the removal of the load: if during the ap-
plication of the load the inductor is charged by a voltage equal to the difference between the input and the output
voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-
imate response time for DI load transient in case of enough fast compensation network response:
∆
∆
I
L
I
L
V
= ------------------------------
= ---------------
t
t
removal
application
–
V
V
IN
OUT
OUT
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response time after removal of the load with the minimum output voltage programmed and the max-
imum input voltage available.
Figure 10. Inductor ripple current vs V
out
9
8
7
6
5
4
3
2
1
0
µ
L=1.5 H, Vin=12V
L=2µH,
Vin=12V
L=3µH,
Vin=12V
L=1.5µH,
Vin=5V
L=2µH,
Vin=5V
L=3µH, Vin=5V
0.5
1.5
2.5
3.5
Output Voltage [V]
17/27
L6917
Figure 11. Control Loop Scheme
IFB
RF
ZF
CF
VOUT
Av
-ZF/RFB
RFB
VCOMP
REF
IOUT
IFB
Ac
Rs/Rg
-ZF
L
VOUT
PWM
GLOOPI
IN
d•V
d
Cout
ESR
1/ V
∆ osc
VCOMP
Rout
Average Current Mode Compensation Network Design
The average current mode control loop is reported in figure 11. The current information I sourced by the FB
FB
pin flows into R implementing the dependence of the output voltage from the read current.
FB
Two different loops are present and precisely a current loop internal to a voltage loop. The current gain (Ac) and
voltage gain (Av) present in the above figure are defined by the following relationships:
+
1
s ESR C
OUT
V
OUT
( ) = --------------- = { } =
-----------------------------------------------------------------------------------------------------------------------------
Av s
....
V
IN
2
d
L
L
-- +
+ ----------------------- +
S
C
s
ESR C
1
OUT
OUT
2
2 R
OUT
I
V
1 + s ESR C
OUT
IN
OUT
= ------------ =
= --------------- -----------------------------------------------------------------------------------------------------------------------------
Ac(s)
{....}
R
L
d
2
L
OUT
-- +
+ ----------------------- +
S
C
s
ESR C
1
OUT
OUT
2
2 R
OUT
The current loop gain may now be expressed by the following equation:
Ac s Rs V IN 1 + s ESR COUT
Z
s
F( )
Z F (s )
( )
Rs
G
s
LOOPI ( ) = ----------------------------------------------- = –-------------- ------------------------------------------------------------------------------------------------------------------------------ ------ -----------------
Rg Vosc
ROUT
L
Rg Vosc
∆
S2 COUT -- + s ESR COUT + ---------------------- + 1
∆
L
2
2
ROUT
Where ∆Vosc has a typical value of 2V and Z (s) is the impedance of the series R -C . The current loop gain
F
F
F
is designed to obtain a high DC gain to minimize static error and cross the 0dB axes with a constant -20dB/dec
slope with a crossover frequency ω . Neglecting the effect of Z (s), the transfer function has one zero and two
TI
F
poles. Both the poles are fixed once the output filter is designed and also the zero (ω
=1/R
C
) is fixed
OUT
OUT OUT
by the maximum current deliverable by the converter. To obtain the desired shape an R -C series network is
F
F
considered for the Z (s) implementation. A zero at ω =1/R C is then introduced together with an integrator.
F
F
F F
This integrator minimizes the static error while placing the zero in correspondence with the L-C resonance a
simple -20dB/dec shape of the gain is assured (See Figure 12).
18/27
L6917
Figure 12. Current loop Gain (left) and Voltage loop Gain (right)
dB
dB
Ro Rg
Rs RFB
GLOOPI
ZF
Ac
ωTV
ωTI
ωOUT
ωESR ωTI
ω
ωOUT
ωLC
ωF
ω
The R C network may be designed considering the desired crossover frequency ω as follow:
F
F
TI
■ Assuming that ω = ω , and that Z =R if ω>ω , it can be observed that:
F
LC
F
F
F
V
R
R
ω
LC
IN
F
S
------------------------------------------- ----------
(ω ω ) =
G
=
LOOPI
LC
∆
ω
O
Ro Vosc Rg
■
Given the cross-over frequencyω , it results:
TI
L C
ω
TI
OUT
-------------------------------------
ω
ω
TI
2
Rg Ro ∆Vosc
Rg Ro ∆Vosc
2
Rg ∆Vosc
L
2 ω
o
= ------- ------------------------------- -------------------- = ------- ------------------------------- ------------------------------------ - = ------- ------------------ ----------------
R
F
Rs
Vin
Rs
Vin
Ro C
Rs
Vin
OUT
TI
ω
LC
■ Since ω =ω
:
LC
F
L
--
2
C
OUT
C
= ---------------------------
F
R
F
ω
,
TI
Since the device works in current mode and then the control loop acts to control the current, the highest is
the fastest is the device to react after a load transient. The placement of this singularity must consider the worst
case for the load and precisely the maximum output current (minimum output resistance R ).
OUT
The voltage loop gain may be expressed by the following relationship:
1
------------------
∆Vosc
+
V
V
Z (s )
F
OUT
COMP
= ------------------- ------------------- = – ------------------------------- ---------------
Av(s)
G
(s)
LOOPV
V
V
1
G
R
FB
COMP
OUT
LOOPI
Assuming that G I>>1 and after substitution and simplification the final expression for GLOOPV is given by:
LOOP
+
1
s ESR C
R
Rg
OUT
1
OUT
---------------------------------------------------- ---------------------------- -------------------
G
(s) = {... } =
LOOPV
1 + s R
C
Rs R
FB
s
OUT
OUT
+ --------
1
ω
TI
Where the additional pole placed at the current loop ω must be inserted to consider that the current loop gain
TI
is not always G >>1. The LC resonance disappears thanks to the average current mode control and the
LOOPI
system is automatically stable if ESR is small enough.
Since all the above modeling are valid at frequencies much lower than the switching frequency, the highest is
this, the highest may be the converter’s loop bandwidth (both current and voltage). In this way the converter is
able to fast react after a load transient following, with the current delivered by the inductors, the current required
by the load minimizing the number of the output capacitor required.
The average current mode compensation network is then designed as follow:
19/27
L6917
■
ω
TV
Given the voltage loop bandwidth
, the current loop bandwidth wTI is extracted from the following:
Rs R
ω
Rs R
Ro C
Rs R
FB
FB
ESR
F B
OUT
=
----------------------- -------------- =
----------------------- -------------------------------- - =
ω
-------------------------
TV
ω
ω
ω
TI
TV
T V
Ro Rg
ω
Ro Rg ESR C
ESR Rg
O
OUT
■ Once the current loop bandwidth is defined, the R C network may be designed as shown previously.
F
F
Demo Board Description
The L6917 demo board shows the operation of the device in a dual phase application. This evaluation board
allows voltage adjustability (1.100V - 1.850V) through the switches S0-S4 and high output current capability.
The 12V input rail supplies both the device and the high-side drain for the power conversion.
2
The board has been layed out with the possibility to use up to two D PACK mosfets for the low side switch in
order to give maximum flexibility in the mosfet’s choice.
The four layers demo board’s copper thickness is of 70µm in order to minimize conduction losses considering
the high current that the circuit is able to deliver.
Figure 13 shows the demo board’s schematic circuit.
Figure 13. Demo Board Schematic
Vin
DZ1
JP1
JP2
GNDin
C9,C10 C11..C13
R10
R16
VCCDR
VC C
2
6
C6
L1
D4
C8
C7
D3
C5
L2
BOOT1
BOOT2
5
4
24
25
UGATE1
UGATE2
C4
Q2
Q4
C3
R15
R14
PH ASE1
LGATE1
ISEN1
PH ASE2
LGATE2
ISEN2
3
26
27
16
VoutCORE
GNDCORE
R18
R13
R17
R12
R19
C14,
Q1
1
Q3
C24
R20
D2
D1
Q1a
13
Q3a
R3
R6
R5
U1
L6917
PGNDS1
PGNDS2
PGND
14
15
R1
R4
28
S4
S3
S2
VID4
VID3
VID2
22
PGOOD
VSEN
23
10
PGOOD
21
20
19
18
17
S1
S0
JP3
R7
VID10
FB
9
OSC / INH
JP4
JP5
R8
C2
R2
C1
R9
7
SGND
COMP
8
11
12
FBR
FBG
FBG
FBR
20/27
L6917
Efficiency
Figure 14 shows the demo board measured efficiency versus load current for different values of input voltage
and mosfet configurations.
Measures were done at Vin=5V and Vin=12V with low side mosfet composed by a single STB90NF03L (30V,
Ω
Ω
5.6m typ @ Vgs=10V) or a couple of STB70NF03L (30V, 8m typ @ Vgs=10V) to reduce equivalent R
When 5V input is considered, the 12V bus supplies the IC and the mosfet’ drivers.
.
dsON
Figure 14. Efficiency
95
90
85
80
75
70
Vin = 12V; LS=STB90NF03L
65
Vin = 12V; LS=2xSTB70NF03L
60
Vin = 5V; LS=2xSTB70NF03L
55
Vin = 5V; LS=STB90NF03L
50
45
0
10
20
30
40
50
Output Current [A]
PCB and Components Layouts
Figure 15. PCB and Components Layouts
Component Side
Internal PGND Plane
21/27
L6917
Figure 16. PCB and Components Layouts
Internal SGND Plane
Solder Side
Design Example.
■
Output Voltage (nominal) 1.700V
■
Output Current (nominal) 45A
■
Static tolerance
+100mV; -50mV
Considering the high slope for the load transient, a high switching frequency has to be used. In addition to fast
reaction, this helps in reducing output and input capacitor. Inductance value is also reduced.
A switching frequency of 300kHz for each phase is then considered allowing large bandwidth for the compen-
sation network.
■ Current Reading Network and Over Current:
Since the maximum output current is 45A, the over current threshold has to be set at 140% of the
maximum nominal current, the over-current threshold has then to be set at 31.5A. Considering to sense
the output current across the low-side mosfet RdsON, STB90NF03L has 6.5mΩ max at 25° that
becomes 9.1mΩ considering the temperature variation (+40%); the resulting transconductance resistor
Rg has to be:
I
RdsON
31.5 9.1m
= -------------------------------------- - = ------------------------------ =
MAX
Ω
8.2k (R3 to R6)
Rg
Droop function Design:
µ
µ
35
35
■
Considering a voltage drop of 100mV at full load, the feedback resistor RFB has to be
100mV
= ------------------- =
R
2kΩ (R7)
FB
µ
50 A
voltage drop at OCP threshold results in 140mV.
22/27
L6917
■
■
Inductor design:
Each phase has to deliver up to 22.5A; considering a current ripple of 5A (<25%), the resulting
inductance value is:
Vin – Vout
L = ----------------------------- ----------- = --------------------- ------- -------------------- = 1µH (L1, L2)
∆I Fsw 12 300000
d
12 – 1.7 1.7
1
5
Output Capacitor:
Six PANASONIC SP-CAP EEFUE0D27 (270µF, 15mΩmax) has been used implementing a resulting
Ω
Ω
ESR of 2.5m resulting in a voltage drop of 45A*2.5m =112.5mV after a load transient.
■ Compensation Network:
A voltage loop bandwidth of 40kHz is considered to let the device fast react after load transient.
Rs R
7.8m 2k
------------------------------
2.5m 8.2k
F B
-------------------------
f
= 20kHz=> f = f
= 20k
= 15.2kHz
TV
TI
TV
ESR Rg
The R C network results:
F
F
∆
µ
1
2
Rg Vosc L
8.2k
7.8m 12
2
------- ------------------ --
------------- ----- ------ 2
=
ω
=
TI
π
= Ω
8.2k (R8)
R
15.2k
F
Rs
Vin
2
L
1 µ
------------------------
2 1.62m
8.2k
-----------------------
2 C
OUT
C
= --------------------------- = ----------------------------- = 3.4nF (C2)
F
R
F
■
VID settings:
Considering the 100mV voltage drop programmed by the feedback resistor and the static tolerance, the
VID are set for 1.775V (00011 code) in order to have a ±25mV of margin in the regulation.
Part List
R1
10k
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 1206
SMD 1206
Radial 10x10.5
SMD 7343
R2, R9, R20
R3, R4, R5, R6
R7
Not Mounted
8.2k
2k
1%
1%
R8
10k
82Ω
R10
R12 to R15
C2
0
Ω
4.7n
100n
1µ
C3, C4
C5, C6, C7
C8, C9, C10
C11, C12, C13
C19 to C24
L1, L2
Ceramic
10
Ceramic
µ
100µ / 20V
OSCON 20SA100M
PANASONIC SP-CAP
270 / 2V
µ
1µ
77121 Core – 7 Turns or
TO50-52B Core – 6 Turns
U1
L6917
STMicroelectronics
STMicroelectronics
SO28
2
Q1, Q3
STB90NF03L
D PACK
2
Q2, Q4
STB70NF03L
STMicroelectronics
D PACK
D1, D2
D3, D4
STPS340U
1N4148
STMicroelectronics
STMicroelectronics
SMB
SOT23
23/27
L6917
Application Idea: 12V input 3.3V / 5V 40A output
Figure 17 shows the device in a high current server power supply application.
Adding an external resistor divider after the remote sense buffer gives the possibility to increase the regulated
voltage. Considering for example a divider by two (two equal resistors) the DAC range is doubled from 2.200V
to 3.700V with 50mV binary steps. It is then possible to regulate the 3.3V and 2.5V rails from the 12V available
from the AC/DC converter. The 5V rail can be obtained modifying the external divider. The regulator assures all
the advantages of the dual phase conversion (especially in the 5V conversion where the duty cycle is near the
50% and practically no ripple is present in the input capacitors) and a 300kHz free-running frequency that re-
duces components size. Output current ranges from 35A up to 50A.
Figure 17. Server power supply schematic
Vin
GNDin
C9,C10 C11..C13
R10
R16
V CCD R
V CC
2
6
C6
L1
D4
C8
C7
D3
C5
L2
BOOT
1
BOOT 2
5
4
24
25
UGATE1
UGA TE2
C4
D1
Q2
Q4
C3
D2
R14
R15
P
HASE1
P HASE2
3
26
27
16
VoutCORE
GNDCORE
R18
R13
R17
R12
R19
R20
C14,
C24
LGATE1
ISE N1
LGA TE2
Q1
1
Q3
D6
D5
IS EN
2
13
R3
R6
R5
U1
L6917
P GNDS1
P
P
GNDS2
GND
14
15
28
R1
R4
S4
S3
S2
S1
S0
22
21
20
19
18
17
P
V
GOO
SE N
D
23
10
PGOOD
V ID4
V ID32
V ID1
V ID0
R7
FB
9
O SC
/ INH
R8
C2
R2
C1
R9
7
SG ND
COMP
8
11
12
FB
R
FBG
FBG
FBR
Part List
R1
10k
8.2k
820
10k
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
R3, R4, R5, R6
1%
1%
R7
R8
R10
82
Ω
R12 to R16
R17, R18
R19, R20
C2
0Ω
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 1206
SMD 1206
SMD 1026
0
Ω
330Ω
4.7n
100n
1µ
C3, C4
C5, C6, C7
C8
Ceramic
Ceramic
Ceramic
10µ
C9 to C13
47µ
24/27
L6917
Part List
C14, C15
L1, L2
1500µ / 6.3V
Radial
SO28
4
µ
77121 Core – 10T (30A Out) or
77848 Core – 11T (45A Out)
U1
L6917
STMicroelectronics
STMicroelectronics
2
Q1, Q3
STB90NF03L
D PACK
2
Q2, Q4
STB70NF03L
STMicroelectronics
D PACK
D1, D2
D3, D4
STPS340U
1N4148
STMicroelectronics
STMicroelectronics
SMB
SOT23
Figure 18.
vout
1.700
1.698
1.696
1.694
1.692
1.690
1.688
1.686
1.684
-40
-20
0
20
40
60
80
100
120
140
Temperature [C]
Output Voltage vs. Temperature
49
48
47
46
45
44
43
42
41
-40
-20
0
20
40
60
80
100
120
140
Temperature [C]
PGNDS Bias Current vs. Temperature
25/27
L6917
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
A
a1
b
2.65
0.3
0.104
0.012
0.019
0.013
0.1
0.004
0.35
0.23
0.49 0.014
0.32 0.009
b1
C
c1
D
E
0.5
0.020
45° (typ.)
17.7
10
18.1 0.697
10.65 0.394
0.713
0.419
e
1.27
0.050
0.65
e3
F
16.51
7.4
0.4
7.6
0.291
0.299
0.050
L
1.27 0.016
SO28
S
8 ° (max.)
26/27
L6917
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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