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L6918ADTR [STMICROELECTRONICS]

5 BIT PROGRAMMABLE MULTIPHASE CONTROLLER; 5位可编程多相控制器
L6918ADTR
型号： L6918ADTR
厂家： ST    ST
描述：

5 BIT PROGRAMMABLE MULTIPHASE CONTROLLER
5位可编程多相控制器

控制器
文件： 总35页 (文件大小：761K)
中文：  中文翻译
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L6918 L6918A  
5 BIT PROGRAMMABLE MULTIPHASE CONTROLLER  
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■
■
■
■
■
■
■
OUTPUT CURRENT IN EXCESS OF 100A  
ULTRA FAST LOAD TRANSIENT RESPONSE  
REMOTE SENSE BUFFER  
INTEGRATED 2A GATE DRIVERS  
5 BIT VID VOLTAGE POSITIONING, VRM 9.0  
0.6% INTERNAL REFERENCE ACCURACY  
DIGITAL 2048 STEP SOFT-START  
OVP & OCP PROTECTIONS  
SO28  
ORDERING NUMBERS: L6918D, L6918AD  
L6918DTR, L6918ADTR  
DESCRIPTION  
L6918A is a master device that it has to be combined  
with the L6918,slave, realizing a 4-phases topology,  
interleaved. The device kit is specifically designed to  
provide a high performance/high density DC/DC con-  
version for high current microprocessors and distrib-  
uted power. Each device implements a dual-phase  
step-down controller with a 180° phase-shift between  
each phase.  
Rdson or Rsense CURRENT SENSING  
1200KHz EFFECTIVE SWITCHING  
FREQUENCY, EXTERNALLY ADJUSTABLE  
■
■
POWER GOOD OUTPUT AND INHIBIT  
PACKAGE: SO28  
A precise 5-bit DAC allows adjusting the output volt-  
age from 1.100V to 1.850V with 25mV binary steps.  
The high peak current gate drives affords to have  
high system switching frequency, typically of  
1200KHz, and higher by external adjustement.  
The device kit assure a fast protection against OVP,  
UVP and OCP. An internal crowbar, by turning on the  
low side mosfets, eliminates the need of external pro-  
tection. In case of over-current, the system works in  
Constant Current mode.  
APPLICATIONS  
■
■
■
HIGH DENSITY DC-DC FOR SERVERS AND  
WORKSTATIONS  
SUPPLY FOR HIGH CURRENT  
MICROPROCESSORS  
DISTRIBUTED POWER  
PIN CONNECTIONS  
LGATE1  
1
PGND  
LGATE1  
VCCDR  
PHASE1  
UGATE1  
BOOT1  
VCC  
PGND  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCCDR  
2
LGATE2  
PHASE2  
UGATE2  
BOOT2  
PGOOD  
VID4  
LGATE2  
2
PHASE1  
3
PHASE2  
3
UGATE1  
4
UGATE2  
4
BOOT1  
5
BOOT2  
5
VCC  
6
PGOOD  
6
SGND  
7
SGND  
COMP  
FB  
VPROG_IN  
SYNC_IN  
SLAVE_OK  
SYNC / ADJ  
SYNC_OUT  
OSC / INH / FAULT  
ISEN2  
7
COMP  
8
VID3  
8
FB  
9
VID2  
9
VPROG_OUT  
10  
VSEN  
VID1  
10  
11  
12  
13  
14  
SYNC_OUT  
11  
FBR  
VID0  
SLAVE_OK  
12  
FBG  
OSC / INH / FAULT  
ISEN2  
ISEN1  
13  
ISEN1  
PGNDS1  
PGNDS2  
PGNDS2  
PGNDS1  
14  
October 2002  
1/35  
L6918 L6918A  
L6918A (MASTER) DEVICE BLOCK DIAGRAM  
SYNC_ OUT  
ROSC / INH  
SGND  
VCCDR  
BOOT1  
HS  
UGATE1  
PHAS E1  
SYNCH.  
CIRCUITRY  
SLAVE_OK  
PWM1  
CH1  
OCP  
LS  
LGATE1  
ISEN1  
VCC  
VCC DR  
PGOOD  
TO TAL  
CUR RENT  
CURRENT  
READING  
PGNDS1  
PGND  
PGNDS2  
CURRENT  
READING  
CH2 OCP  
CH1 OCP  
ISEN2  
DIGITAL  
SOFT-STAR T  
LS  
LGATE2  
CH2  
OCP  
IFB  
PHAS E2  
UGATE2  
BOOT2  
VID4  
VID3  
VID2  
VID1  
VID0  
PWM2  
HS  
DAC  
Vc c  
ERROR  
AMPLIFIER  
VSEN  
FB  
COMP  
Vcc  
L6918 (SLAVE) DEVICE BLOCK DIAGRAM  
SLAVE / ADJ  
SYNC_OUT  
ROSC / INH  
SGND  
VCCDR  
BOOT1  
SYNC_IN  
HS  
LS  
UGATE1  
PHAS E1  
SYNCH.  
CIRCUITRY  
PWM1  
SLAVE_OK  
PGOOD  
CH1  
OCP  
LGATE1  
ISEN1  
VCC  
VCC DR  
TO TAL  
CUR RENT  
CURRENT  
READING  
PGNDS1  
PGND  
PGNDS2  
CURRENT  
READING  
CH2 OCP  
CH1 OCP  
ISEN2  
VPROG_IN  
LS  
LGATE2  
CH2  
OCP  
10k  
10 k  
10 k  
IFB  
FBG  
FBR  
PHAS E2  
UGATE2  
BOOT2  
PWM2  
HS  
REMOTE  
BUFFER  
10k  
Vc c  
ERROR  
AMPLIFIER  
VVSSEENN  
FB  
COMP  
Vcc  
2/35  
L6918 L6918A  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
15  
Unit  
V
Vcc, V  
To PGND  
CCDR  
V
-V  
Boot Voltage  
15  
V
BOOT PHASE  
V
V
-V  
15  
V
UGATE1 PHASE1  
-V  
UGATE2 PHASE2  
LGATE1, PHASE1, LGATE2, PHASE2 to PGND  
VID0 to VID4  
-0.3 to Vcc+0.3  
-0.3 to 5  
-0.3 to 7  
26  
V
V
V
V
All other pins to PGND  
V
Sustainable Peak Voltage t<20nS @ 600kHz  
PHASEx  
THERMAL DATA  
Symbol  
Parameter  
Value  
60  
Unit  
R
Thermal Resistance Junction to Ambient  
Maximum junction temperature  
Storage temperature range  
°
C / W  
th j-amb  
T
max  
150  
°
°
°
C
C
C
T
-40 to 150  
0 to 125  
2
storage  
T
j
Junction Temperature Range  
P
MAX  
°
W
Max power dissipation at Tamb=25 C  
L6918A (MASTER) PIN FUNCTION  
N.  
1
Name  
LGATE1  
VCCDR  
PHASE1  
Description  
Channel 1 low side gate driver output.  
LS Mosfet driver supply. 5V or 12V buses can be used.  
2
3
This pin is connected to the Source of the upper mosfet and provides the return path for the  
high side driver of channel 1.  
4
5
UGATE1  
BOOT1  
Channel 1 high side gate driver output.  
Channel 1 bootstrap capacitor pin. This pin supplies the high side driver. Connect through a  
capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs. boot).  
6
7
8
VCC  
GND  
Device supply voltage. The operative supply voltage is 12V.  
All the internal references are referred to this pin. Connect it to the PCB signal ground.  
COMP  
This pin is connected to the error amplifier output and is used to compensate the control  
feedback loop.  
9
FB  
This pin is connected to the error amplifier inverting input and is used to compensate the  
voltage control feedback loop.  
A current proportional to the sum of the current sensed in both channel is sourced from this pin  
µ
µ
(50 A at full load, 70 A at the Over Current threshold). Connecting a resistor R between  
FB  
this pin and VSEN pin allows programming the droop effect.  
10  
11  
12  
VPROG_OUT Reference voltage output used for voltage regulation.  
This pin must be connected together with the slave device VPROG_IN pin.  
Filter to SGND with 1nF capacitor (a total 30nF distributed capacitance is allowed).  
SYNC_OUT Synchronization output signal. From this pin exits a square - 50% duty cycle - 5Vpp –90 deg  
phase shifted wave clock signal that the Slave device PLL locks to.  
Connect this pin to the Slave SYNC_IN pin.  
SLAVE_OK  
Open-drain input/output used for start-up and to manage protections as shown in the timing  
diagram. Internally pulled-up. Connect together with other IC’s SLAVE_OK pin. Filter with 1nF  
capacitor vs. SGND.  
3/35  
L6918 L6918A  
L6918A (MASTER) PIN FUNCTION (continued)  
N.  
Name  
Description  
13  
ISEN1  
Channel 1 current sense pin. The output current may be sensed across a sense resistor or  
across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain  
or to the sense resistor through a resistor Rg in order to program the current intervention for  
each phase at 140% as follow:  
35µA Rg  
IOCPx = --------------------------  
Rsense  
Where 35µA is the current offset information relative to the Over Current condition (offset at  
OC threshold minus offset at zero load).The net connecting the pin to the sense point must be  
routed as close as possible to the PGNDS1 net in order to couple in common mode any  
picked-up noise.  
14  
15  
PGNDS1  
PGNDS2  
Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be routed as  
close as possible to the ISEN1 net in order to couple in common mode any picked-up noise.  
Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be  
routed as close as possible to the ISEN2 net in order to couple in common mode any picked-  
up noise.  
16  
ISEN2  
Channel 2 current sense pin. The output current may be sensed across a sense resistor or  
across the low-side mosfet Rds  
This pin has to be connected to the low-side mosfet drain  
ON.  
or to the sense resistor through a resistor Rg in order to program the current intervention for  
each phase at 140% as follow:  
35µA Rg  
I OCPx = --------------------------  
Rsense  
µ
Where 35 A is the current offset information relative to the Over Current condition (offset at  
OC threshold minus offset at zero load).  
The net connecting the pin to the sense point must be routed as close as possible to the  
PGNDS2 net in order to couple in common mode any picked-up noise.  
17  
OSC/INH  
FAULT  
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the  
external frequency is increased according to the equation:  
14.82 106  
f S = 300KHz + -----------------------------  
R
OSC(KΩ)  
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according  
to the equation:  
12.91 107  
f S = 300KHz + -----------------------------  
R
OSC(KΩ)  
If the pin is not connected, the switching frequency is 300KHz.  
Forcing the pin to a voltage lower than 0.8V, the device stop operation and enter the inhibit  
state; all mosfets are turned OFF.  
18  
to  
22  
VID0-4  
Voltage Identification pins. These input are internally pulled-up and TTL compatible. They are  
used to program the output voltage as specified in Table 1 and to set the over voltage and  
power good thresholds.  
Connect to GND to program a ‘0’ while leave floating to program a ‘1’.  
23  
24  
PGOOD  
BOOT2  
This pin is an open collector output and is pulled low if the output voltage is not within the  
above specified thresholds. It must be connected with the Slave’s PGOOD pin.  
If not used may be left floating.  
Channel 2 bootstrap capacitor pin. This pin supplies the high side driver. Connect through a  
capacitor to the PHASE2 pin and through a diode to Vcc (cathode vs. boot).  
25  
26  
UGATE2  
PHASE2  
Channel 2 high side gate driver output.  
This pin is connected to the source of the upper mosfet and provides the return path for the  
high side driver of channel 2.  
27  
28  
LGATE2  
PGND  
Channel 2 low side gate driver output.  
Power ground pin. This pin is common to both sections and it must be connected through the closest  
path to the low side mosfets source pins in order to reduce the noise injection into the device.  
4/35  
L6918 L6918A  
L6918 (SLAVE) PIN FUNCTION  
N.  
1
Name  
LGATE1  
VCCDR  
PHASE1  
Description  
Channel 1 low side gate driver output.  
LS Mosfet driver supply. 5V or 12V buses can be used.  
2
3
This pin is connected to the Source of the upper mosfet and provides the return path for the  
high side driver of channel 1.  
4
5
UGATE1  
BOOT1  
Channel 1 high side gate driver output.  
Channel 1 bootstrap capacitor pin. This pin supplies the high side driver. Connect through a  
capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs. boot).  
6
7
8
VCC  
GND  
Device supply voltage. The operative supply voltage is 12V.  
All the internal references are referred to this pin. Connect it to the PCB signal ground.  
COMP  
This pin is connected to the error amplifier output and is used to compensate the control  
feedback loop.  
9
FB  
This pin is connected to the error amplifier inverting input and is used to compensate the  
voltage control feedback loop.  
A current proportional to the sum of the current sensed in both channel is sourced from this pin  
µ
µ
(50 A at full load, 70 A at the Over Current threshold). Connecting a resistor R between this  
FB  
pin and VSEN pin allows programming the droop effect.  
10  
11  
VSEN  
FBR  
Connected to the output voltage it is able to manage Over & Under-voltage conditions and the  
PGOOD signal. It is internally connected with the output of the Remote Sense Buffer for  
Remote Sense of the regulated voltage.  
If no Remote Sense is implemented, connect it directly to the regulated voltage in order to  
manage OVP, UVP and PGOOD.  
Remote sense buffer non-inverting input. It has to be connected to the positive side of the load  
to perform a remote sense.  
If no remote sense is implemented, connect directly to the output voltage (in this case connect  
also the VSEN pin directly to the output regulated voltage).  
12  
13  
FBG  
Remote sense buffer inverting input. It has to be connected to the negative side of the load to  
perform a remote sense.  
Pull-down to ground if no remote sense is implemented.  
ISEN1  
Channel 1 current sense pin. The output current may be sensed across a sense resistor or  
across the low-side mosfet Rds  
This pin has to be connected to the low-side mosfet drain or  
ON.  
to the sense resistor through a resistor Rg in order to program the current intervention for each  
phase at 140% as follow:  
35µA Rg  
IOCPx = --------------------------  
Rsense  
µ
Where 35 A is the current offset information relative to the Over Current condition (offset at  
OC threshold minus offset at zero load).  
The net connecting the pin to the sense point must be routed as close as possible to the  
PGNDS1 net in order to couple in common mode any picked-up noise.  
14  
15  
PGNDS1  
PGNDS2  
Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be  
routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up  
noise.  
Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be  
routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up  
noise.  
5/35  
L6918 L6918A  
L6918 (SLAVE) PIN FUNCTION (continued)  
N.  
Name  
Description  
16  
ISEN2  
Channel 2 current sense pin. The output current may be sensed across a sense resistor or  
across the low-side mosfet Rds  
This pin has to be connected to the low-side mosfet drain or  
ON.  
to the sense resistor through a resistor Rg in order to program the current intervention for each  
phase at 140% as follow:  
35µA Rg  
IOCPx = --------------------------  
Rsense  
µ
Where 35 A is the current offset information relative to the Over Current condition (offset at  
OC threshold minus offset at zero load).  
The net connecting the pin to the sense point must be routed as close as possible to the  
PGNDS2 net in order to couple in common mode any picked-up noise.  
17  
OSC/INH  
FAULT  
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the  
external frequency is increased according to the equation:  
14.82 106  
f S = 300KHz + -----------------------------  
R
OSC(KΩ)  
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according  
to the equation:  
12.91 107  
f S = 300KHz + -----------------------------  
R
OSC(KΩ)  
If the pin is not connected, the switching frequency is 300KHz.  
Forcing the pin to a voltage lower than 0.8V, the device stops operation and enters the inhibit  
state; all mosfets are turned OFF.  
The pin is forced high when an over voltage is detected. This condition is latched; to recover it  
is necessary turn off and on VCC.  
18  
19  
SYNC_OUT Output synchronization signal.  
°
A 60 phase shift signal exits when the device works as a Slave  
while no signal exits when the device works as an adjustable.  
SYNC / ADJ Slave or Adjustable operation.  
Connecting this pin to GND the device becomes an adjustable two-phase controller using an  
external reference for its regulation. No soft start is implemented in this condition, so it must be  
performed with external circuitry. The device switches using its internal oscillator according to  
the frequency set by R  
.
OSC  
Leaving this pin floating, the device works as a Slave two-phase controller. It uses the  
reference sourced from the master device and an internal PLL locks the synchronization signal  
sourced from the master device.  
20  
SLAVE_OK Open-drain output used for start-up and to manage protections as shown in the timing diagram. Internally  
pulled-up. Connect together with other IC’s SLAVE_OK pin. Filter with 1nF capacitor vs. SGND.  
21  
22  
SYNC_IN  
Synchronization input signal locked during the slave operation. Connect to the master SYNC_OUT pin.  
VPROG_IN Reference voltage input used for voltage regulation.  
This pin must be connected together with the other’s slave (if present) to the VPROG_OUT pin  
of the master device.  
Filter to SGND with 1nF capacitor (a total 30nF distributed capacitance is allowed).  
If the device works as an Adjustable (SYNC/ADJ to GND), this is the reference used for the regulation.  
23  
PGOOD  
This pin is an open collector output and is pulled low if the output voltage is not within the  
above specified thresholds. It must be connected with the master’s PGOOD pin.  
If not used may be left floating.  
6/35  
L6918 L6918A  
L6918 (SLAVE) PIN FUNCTION (continued)  
N.  
Name  
Description  
24  
BOOT2  
Channel 2 bootstrap capacitor pin. This pin supplies the high side driver. Connect through a  
capacitor to the PHASE2 pin and through a diode to Vcc (cathode vs. boot).  
25  
26  
UGATE2  
PHASE2  
Channel 2 high side gate driver output.  
This pin is connected to the Source of the upper mosfet and provides the return path for the  
high side driver of channel 2.  
27  
28  
LGATE2  
PGND  
Channel 2 low side gate driver output.  
Power ground pin. This pin is common to both sections and it must be connected through the closest  
path to the low side mosfets source pins in order to reduce the noise injection into the device.  
ELECTRICAL CHARACTERISTCS  
(Vcc=12V±10%, TJ=0°C to 70°C unless otherwise specified)  
Symbol  
Vcc SUPPLY CURRENT  
Vcc supply current  
Parameter  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
I
HGATEx and LGATEx open  
7.5  
10  
12.5  
mA  
CC  
V
CCDR  
=V  
=12V  
BOOT  
I
V
supply current  
LGATEx open; V =12V  
CCDR  
2
3
1
4
mA  
mA  
CCDR  
CCDR  
I
Boot supply current  
HGATEx open; PHASEx to  
PGND  
0.5  
1.5  
BOOTx  
V
CC  
=V  
=12V  
BOOT  
POWER-ON  
Turn-On V threshold  
V
V
V
V
Rising; V  
Falling; V  
=5V  
7.8  
6.5  
4.2  
4.0  
9
10.2  
8.5  
4.6  
4.4  
V
V
V
V
CC  
CC  
CCDR  
Turn-Off V threshold  
=5V  
7.5  
4.4  
4.2  
CC  
CC  
CCDR  
Turn-On V  
Turn-Off V  
Threshold  
Threshold  
Rising; V =12V  
CC  
CCDR  
CCDR  
CCDR  
CCDR  
Falling; V =12V  
CC  
OSCILLATOR AND INHIBIT  
f
Initial Accuracy  
OSC = OPEN  
OSC = OPEN; Tj=0 C to 125 C  
278  
270  
300  
322  
330  
kHz  
kHz  
OSC  
°
°
f
Total Accuracy  
Ω
450  
500  
2
550  
kHz  
V
R to GND=74k  
OSC,Rosc  
T
∆
Vosc  
Ramp Amplitude  
Maximum duty cycle  
Inhibit threshold  
d
MAX  
OSC = OPEN  
45  
50  
-
%
INH  
I
=5mA  
0.8  
0.85  
0.9  
V
SINK  
REFERENCE AND DAC only for L6918A (MASTER)  
V
Reference Voltage  
Accuracy  
VID0 to VID4 see Table1  
-0.6  
-
0.6  
%
PROG_OUT  
I
VID pull-up Current  
VID pull-up Voltage  
VIDx = GND  
4
5
-
6
µ
A
DAC  
VIDx = OPEN  
3.1  
3.4  
V
ERROR AMPLIFIER  
DC Gain  
80  
15  
dB  
SR  
Slew-Rate  
Offset  
COMP=10pF  
µ
V/ S  
-7  
7
mV  
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER) only for L6918 (SLAVE)  
DC Gain  
1
V/V  
dB  
CMRR  
Common Mode Rejection Ratio  
Input Offset  
40  
FBR=1.100V to1.850V;  
FBG=GND  
-12  
45  
12  
55  
mV  
DIFFERENTIAL CURRENT SENSING  
Bias Current  
I
,
I
= 0%  
LOAD  
50  
µ
A
ISEN1  
I
ISEN2  
7/35  
L6918 L6918A  
ELECTRICAL CHARACTERISTCS (continued)  
(Vcc=12V±10%, TJ=0°C to 70°C unless otherwise specified)  
Symbol  
Parameter  
Bias Current  
Test Condition  
Min.  
45  
Typ.  
50  
Max.  
55  
Unit  
I
µ
µ
A
A
PGNDSx  
I
,
Bias Current at  
80  
85  
90  
ISEN1  
Over Current Threshold  
I
ISEN2  
I
Active Droop Current  
I
I
= 0  
0
1
µ
µ
A
A
FB  
LOAD  
= 100%  
47.5  
50  
52.5  
LOAD  
GATE DRIVERS  
t
High Side  
Rise Time  
V
C
-V  
=10V;  
15  
30  
nS  
RISE HGATE  
BOOTx PHASEx  
to PHASEx=3.3nF  
HGATEx  
I
High Side  
Source Current  
V
V
V
-V  
=10V  
2
2
A
Ω
HGATEx  
BOOTx PHASEx  
R
High Side  
Sink Resistance  
-V  
BOOTx PHASEx  
=12V;  
1.5  
0.7  
2.5  
55  
HGATEx  
t
Low Side  
Rise Time  
=10V;  
CCDR  
30  
nS  
RISE LGATE  
C
to PGNDx=5.6nF  
LGATEx  
I
Low Side  
Source Current  
V
=10V  
1.8  
1.1  
A
LGATEx  
CCDR  
CCDR  
R
Low Side  
V
=12V  
1.5  
Ω
LGATEx  
Sink Resistance  
PROTECTIONS  
PGOOD  
PGOOD  
OVP  
Upper Threshold  
(V / VPROG_IN)  
V
V
V
V
Rising  
Falling  
Rising  
Falling  
109  
87  
112  
90  
115  
93  
%
%
%
%
V
SEN  
SEN  
SEN  
SEN  
SEN  
Lower Threshold  
(V / VPROG_IN)  
SEN  
Over Voltage Threshold  
(V / VPROG_IN)  
114  
55  
117  
60  
120  
65  
SEN  
UVP  
Under Voltage Trip  
(V / VPROG_IN)  
SEN  
V
PGOOD Voltage Low  
I
= -4mA  
0.3  
0.4  
0.5  
PGOOD  
PGOOD  
Table 1. VID Settings (only for L6918A)  
Output  
Output  
Voltage (V)  
VID4  
VID3  
VID2  
VID1  
VID0  
VID4  
VID3  
VID2  
VID1  
VID0  
Voltage (V)  
1.850  
1.825  
1.800  
1.775  
1.750  
1.725  
1.700  
1.675  
1.650  
1.625  
1.600  
1.575  
1.550  
1.525  
1.500  
1.475  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.450  
1.425  
1.400  
1.375  
1.350  
1.325  
1.300  
1.275  
1.250  
1.225  
1.200  
1.175  
1.150  
1.125  
1.100  
Shutdown  
8/35  
L6918 L6918A  
FOUR PHASE REFERENCE SCHEMATICS  
Vin  
GNDin  
CIN  
VCCDR  
2
VCC  
6
BOOT1  
5
BOOT2  
24  
25  
UGATE1  
UGATE2  
HS1  
LS1  
4
HS2  
LS2  
L1  
L2  
PHASE1  
LGATE1  
ISEN1  
PHASE2  
LGATE2  
ISEN2  
3
26  
27  
16  
CPU  
1
COUT  
13  
Rg  
Rg  
Rg  
PGNDS2  
PGND  
PGNDS1  
14  
15  
28  
L6918A  
Rg  
22 Master  
VID4  
VID3  
VID2  
VID1  
VID0  
S4  
S3  
S2  
S1  
S0  
PGOOD  
23  
PGOOD  
21  
20  
19  
18  
17  
RFB  
FB  
OSC / INH  
9
8
RF  
CF  
SGND  
7
COMP  
10  
VPROG_OUT  
11  
12  
SLAVE OK  
VPROG_IN  
22  
SLAVE_OK  
8
21  
20  
OSC / INH  
COMP  
17  
CF  
RF  
R2  
SGND  
7
9
FB  
To Slave’s  
PGOOD  
PGOOD  
RF  
23  
18  
VSEN  
FBR  
10  
11  
12  
SYNC_OUT  
FBG  
19  
14  
SYNC/ADJ  
Rg  
28  
15  
PGND  
Rg  
Rg  
L6918  
PGNDS1  
Rg  
PGNDS2  
Slave  
13  
1
16  
27  
26  
ISEN1  
ISEN2  
LS3  
HS3  
LS4  
HS4  
LGATE1  
PHASE1  
LGATE2  
PHASE2  
3
L3  
L4  
4
5
25  
24  
UGATE1  
BOOT1  
UGATE2  
BOOT2  
2
6
VCCDR  
VCC  
9/35  
L6918 L6918A  
DEVICES DESCRIPTION  
The devices are integrated circuit realized in BCD technology. They provide, in kit, a complete control logic and  
protections sets for a high performance four-phases step-down DC-DC converter optimized for microprocessors  
supply and High Density DC-DC converters. They are designed to drive N-Channel mosfets in an interleaved  
four-phase synchronous-rectified buck topology. Each controller provides a 180 deg phase shift between its two  
phases and a 90deg phase-shifted synchronization signal is passed from the master to the slave controller that  
locks the signal through a PLL. The resulting four-phases converter synchronized together results in a 90 deg  
phase shift on each phase, allowing a consistent reduction of the input capacitors ripple current, minimizing also  
the size and the power losses. The output voltage of the converter can be precisely regulated, programming the  
master's VID pins, from 1.100V to 1.850V with 25mV binary steps. The reference for the regulation is passed  
from the master device to the slave device through apposite pin likewise the synchronization signal. Each device  
provides an average current-mode control with fast transient response. They include a 300kHz free-running os-  
cillator externally adjustable up to 600kHz, realized in order to multiply by 4 times the equivalent system fre-  
quency. The error amplifier features a 15MHz gain-bandwidth product and 10V/  
converter bandwidth for fast transient performances. Current information is read in all the devices across the  
lower mosfets R or across a sense resistor in fully differential mode. The current information corrects the  
µ
s slew rate that permits high  
DSON  
PWM output in order to equalize the average current carried the two phases of each device. Current sharing  
between the two phases of each device is then limited at ±10% over static and dynamic conditions. Current  
sharing between devices is assured by the droop function. The device protects against over-current, with an  
OCP threshold for each phase, entering in constant current mode. Since the current is read across the low side  
mosfets, the constant current keeps constant the bottom of the inductors current triangular waveform. When an  
under voltage is detected the Slave device latches. The Slave device also perform an over voltage protection  
that disable immediately both devices turning ON the lower driver and driving high the FAULT pin. Over Load  
condition are transmitted from the Slave device(s) to the master through the SLAVE_OK line.  
MASTER - SLAVE INTERACTIONS  
Figure 1. Four Phase connection with L6918 family  
VID 9.0  
SYNC_OUT  
VPROG_OUT  
SLAVE_OK  
PGOOD  
SYNC_IN  
VPROG_IN  
SLAVE_OK  
PGOOD  
OSC  
OSC  
SYNC_OUT  
Master and slave devices are connected together in order to realize four-phase high performance step-down  
DC/DC converter. Four-phase converter is implemented using L6918A master and one L6918 slave devices as  
shown in figure 1.  
A communication bus is implemented among all the controllers involved in the regulation. This bus consists in  
the following lines:  
– Reference (VPROG_IN / VPROG_OUT pins): Unidirectional line.  
The devices share the reference for the regulation. The reference is programmed through the master  
device VID pins. It exits from the master through the VPROG_OUT pin and enters the slave device  
through the VPROG_IN pin(s). Filter externally with at least 1nF capacitor.  
10/35  
L6918 L6918A  
– Clock Signal (SYNC_IN / SYNC_OUT pins): Unidirectional line.  
A synchronization signal exits from the Master device through the SYNC_OUT pin with 90 deg phase-  
shift and enters the Slave device through the SYNC_IN pin. The Slave device locks that signal  
through an internal PLL for its regulation. An auxiliary synchronization signal exits from the Slave  
through the SYNC_OUT.  
– SLAVE_OK Bus (SLAVE_OK pins): Bi-directional line.  
While the supply voltages are increasing, this line is hold to GND by all the devices. The Slave device  
sets this line free (internally 5V pulled-up) when it is ready for the Soft-Start. After that this line is  
freed, the Master device starts the Soft Start (for further details about Soft-Start, see the relevant sec-  
tion).  
During normal operation, the line is pulled low by the Slave device if an Over / Under voltage is de-  
tected (See relevant section).  
– PGOOD pins:  
PGOOD pins are connected together and pulled-up. During Soft-Start, the master device hold down  
this line while during normal regulation the slave device de-assert the line if PGOOD has been lost.  
Connections between the devices are shown in figure 1.  
OSCILLATOR  
The devices have been designed in order to operate on each phase at the same switching frequency of the in-  
ternal oscillator. So, input and output resulting frequencies are four times bigger.  
The oscillator is present in all the devices. Since the Master oscillator sets the main frequency for the regulation,  
the Slave oscillator gives an offset to the Slave's PLL. In this way the PLL is able to lock the synchronization  
signal that enters from its SYNC_IN pin; it is able to recover up to ±15% offset in the synchronization signal fre-  
quency. It is then necessary to program the switching frequency for all the devices involved in the multi-phase  
conversion as follow.  
The switching frequency is internally fixed to 300kHz. The internal oscillator generates the triangular waveform  
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the  
oscillator is typically 25  
µ
A (Fsw = 300KHz) and may be varied using an external resistor (R  
) connected be-  
OSC  
tween OSC pin and GND or Vcc. Since the OSC pin is maintained at fixed voltage (typ. 1.235V), the frequency  
µ
is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 12KHz/ A.  
In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting  
ROSC to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relation-  
ships:  
14.82 106  
ROSC(KΩ)  
1.237  
OSC(KΩ)  
KHz  
µA  
fS = 300kHz + ----------------------------- 12----------- = 300KHz + -----------------------------  
R
vs. GND:  
OSC  
R
12.918 107  
ROSC(KΩ)  
12 – 1.237  
KHz  
µA  
R
vs. 12V:  
f S = 300kHz + ----------------------------- 12----------- = 300KHz – -------------------------------  
OSC  
R
OSC(KΩ)  
µ
Note that forcing a 25 A current into this pin, the device stops switching because no current is delivered to the  
oscillator.  
Figure 2 shows the frequency variation vs. the oscillator resistor ROSC considering the above reported relation-  
ships.  
11/35  
L6918 L6918A  
Figure 2. R  
vs. Switching Frequency  
OSC  
7000  
1000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
6000  
5000  
4000  
3000  
2000  
1000  
0
0
100  
200  
300  
300  
400  
500  
600  
Frequency (KHz)  
Frequency (KHz)  
DIGITAL TO ANALOG CONVERTER (ONLY FOR MASTER DEVICE L6918A)  
The built-in digital to analog converter allows the adjustment of the output voltage from 1.100V to 1.850V with  
25mV as shown in the previous table 1. The internal reference is trimmed to ensure the precision of ±0.6% and  
a zero temperature coefficient around the 70° C. The internal reference voltage for the regulation is programmed  
by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realized by  
means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a mul-  
tiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier ob-  
taining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided for  
the VID pins (realized with a 5 A current generator); in this way, to program a logic "1" it is enough to leave the  
µ
pin floating, while to program a logic "0" it is enough to short the pin to GND.  
The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the Over/  
Under voltage protection (OVP/UVP) thresholds.  
The reference for the regulation is generated into the master device and delivered to the slave device through  
the VPROG_OUT / VPROG_IN pins.  
Programming the "11111" VID code, the device enters the NOCPU state: both devices keeps all mosfets OFF  
and the condition is latched. Cycle the power supply to restart operation. Moreover, in this condition, the OVP  
protection is still active into the slave device with a 0.8V threshold.  
SOFT START AND INHIBIT  
At start-up a ramp is generated from the master device increasing its loop reference from 0V to the final value  
programmed by VID in 2048 clock periods. The same reference is present on the VPROG_OUT pin, producing  
an increasing loop reference also into the slave device. In this way all the devices involved in the multi-phase  
conversion start together with the same increasing reference (See Figure 3).  
Before soft start, the lower power MOS are turned ON after that VCCDR reaches 2V (independently by Vcc val-  
ue) to discharge the output capacitor and to protect the load from high side mosfet failures. Once soft start be-  
gins, the reference is increased and also the upper MOS begins to switch: the output voltage starts to increase  
with closed loop regulation. At the end of the digital soft start, the Power Good comparator is enabled and the  
PGOOD signal is then driven high (See fig. 3). The Under Voltage comparator is enabled when the reference  
voltage reaches 0.8V.  
The Soft-Start will not take place, if both VCC and VCCDR pins are not above their own turn-on thresholds. The  
soft-start takes place, and the Master device starts to increase the reference, only if the SLAVE_OK bus is at  
high level. The Slave device keeps this line shorted to GND until it is ready for the start-up while the master  
keeps this line free before soft-start; anyway, this line is shorted to GND if VCC and VCCDR are not above the  
turn-ON threshold. During normal operation, if any under-voltage is detected on one of the two supplies, the  
devices are shutdown.  
12/35  
L6918 L6918A  
Figure 3. Soft Start  
VCC  
SLAVE_OK  
VPROG_OUT  
LS  
PGOOD  
SYNC_OUT  
CH1=PGOOD; CH2=LGATEx; CH3=VPROG_OUT; CH4=SLAVE_OK  
Forcing the master OSC/INH/FAULT pin to a voltage lower than 0.8V, the devices enter in INHIBIT mode: all  
the power mosfets are turned off until this condition is removed. When this pin is freed, the OSC/INH/FAULT  
pin reaches the band-gap voltage and the soft start begin as previously explained.  
In INHIBIT mode the Slave device still have both OVP and UVP protection active referring the thresholds to the  
incoming reference present at the VPROG_IN pin if this one is greater than 0.8V. Otherwise (VPROG_IN <  
0.8V) UVP is disabled and the OVP threshold is fixed at 0.8V.  
DRIVER SECTION  
The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the  
RDSON), maintaining fast switching transition.  
The drivers for the high-side mosfets use BOOT pins for supply and PHASE pins for return. The drivers for the  
low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 5V at VCCDRV  
pin is required to start operations of the device. The controller embodies a sophisticated anti-shoot-through sys-  
tem to minimize low side body diode conduction time so maintaining good efficiency saving the use of Schottky  
diodes. The conduction time is reduced to few nanoseconds assuring that high-side and low-side mosfets are  
never switched on simultaneously: when the high-side mosfet turns off, the voltage on its source begins to fall;  
when the voltage reaches 2V, the low-side mosfet gate drive is applied with 30ns delay. When the low-side mos-  
fet turns off, the voltage at LGATE pin is sensed. When it drops below 1V, the high-side mosfet gate drive is  
applied with a delay of 30ns. If the current flowing in the inductor is negative, the source of high-side mosfet will  
never drop. To allow the turning on of the low-side mosfet even in this case, a watchdog controller is enabled:  
if the source of the high-side mosfet don't drop for more than 240ns, the low side mosfet is switched on so al-  
lowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if  
the current is negative.  
The BOOT and VCCDRV pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND  
pin) and power ground (PGND pin) in order to maximize the switching noise immunity.  
The peak current is shown for both the upper and the lower driver of the two phases in figure 4.A 10nF capacitive  
load has been used.  
For the upper drivers, the source current is 1.9A while the sink current is 1.5A with V  
-V  
= 12V; sim-  
BOOT PHASE  
ilarly, for the lower drivers, the source current is 2.4A while the sink current is 2A with V  
= 12V.  
CCDR  
13/35  
L6918 L6918A  
Figure 4. Drivers peak current: High Side (left) and Low Side (right)  
CH3 = HGATE1; CH4 = HGATE2  
CH3 = LGATE1; CH4 = LGATE2  
CURRENT READING AND OVER CURRENT  
Each device involved in the four phase conversion has its own current reading circuitry and over current protec-  
tion. As a results, the OCP network design for each device must be performed fort half of the maximum output  
current.  
The current flowing trough each phase is read using the voltage drop across the low side mosfets R  
or  
DSON  
across a sense resistor (R ) and internally converted into a current. The transconductance ratio is issued  
SENSE  
by the external resistor Rg placed outside the chip between ISENx and PGNDSx pins toward the reading points.  
The full differential current reading rejects noise and allows to place sensing element in different locations with-  
out affecting the measurement's accuracy. The current reading circuitry reads the current during the time in  
which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx  
at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two  
pins at the same voltage sinking from the ISENx pin the necessary current (Needed if low-side mosfet R  
sense is implemented to avoid absolute maximum rating overcome on ISENx pin).  
dsON  
The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and  
negative current. This circuit reproduces the current flowing through the sensing element using a high speed  
Track & Hold Tran conductance amplifier. In particular, it reads the current during the second half of the OFF  
time reducing noise injection into the device due to the high side mosfet turn-on (See fig. 5). Track time must  
be at least 200ns to make proper reading of the delivered current.  
µ
This circuit sources a constant 50 A current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at  
the same voltage. Referring to figure 5, the current that flows in the ISENx pin is then given by the following  
equation:  
RSENSE IPHASE  
IISENx  
50µA --------------------------------------------- 50µA  
I
+
INFOx  
=
+
=
Rg  
Where R  
is an external sense resistor or the R  
of the low side mosfet and Rg is the transconductance  
dsON  
SENSE  
resistor used between ISENx and PGNDSx pins toward the reading points; I  
phase.  
is the current carried by each  
PHASE  
The current information reproduced internally is represented by the second term of the previous equation as  
follow:  
14/35  
L6918 L6918A  
RSENSE IPHASE  
IINFOx = ---------------------------------------------  
Rg  
Since the current is read in differential mode, also negative current information is kept; this allow the device to  
check for dangerous returning current between the two phases assuring the complete equalization between the  
phase's currents.  
Figure 5. Current reading timing (left) and circuit (right)  
ILS1  
LGATEX  
Rg  
ILS2  
ISENX  
E
S
IISENx  
A
Total  
current  
information  
PH  
I
Rg  
PGNDSX  
µ
50 A  
Track & Hold  
From the current information for each phase, information about the total current delivered ( I =II  
+I  
)
FB NFO1 INFO2  
and the average current for each phase ( I  
=(I  
+I  
)/2 ) is taken. I  
is then compared to I  
to  
AVG  
AVG INFO1 INFO2  
INFOX  
give the correction to the PWM output in order to equalize the current carried by the two phases.  
µ
The transconductance resistor Rg can be designed in order to have current information of 25 A per phase at  
µ
= 35 A). Accord-  
full nominal load; the over current intervention threshold is set at 140% of the nominal (II  
NFOx  
ing to the above relationship, the over current threshold (I  
half of the total delivered maximum current, results:  
) for each phase, which has to be placed at one  
OCPx  
35µA Rg  
IOCPx RSENSE  
I OCPx = --------------------------  
Rg = -----------------------------------------  
35µA  
RSENSE  
µ
>35 A):  
INFOx  
An over current is detected when the current flowing into the sense element is greater than IOCP (I  
the device enters in Quasi-Constant-Current operation. The low-side mosfets stays ON until IINFO becomes  
µ
lower than 35 A skipping clock cycles. The high side mosfets can be turned ON with a T  
imposed by the  
ON  
control loop at the next available clock cycle and the device works in the usual way until another OCP event is  
detected.  
The device limits the bottom of the inductor current triangular waveform. So the average current delivered can  
slightly increase also in Over Current condition since the current ripple increases. In fact, the ON time increases  
due to the OFF time rise because of the current has to reach the I  
bottom. The worst-case condition is when  
OCP  
the duty cycle reaches its maximum value (d=50% internally limited). When this happens, the device works in  
Constant Current and the output voltage decrease as the load increase. Crossing the UVP threshold causes the  
Slave device to pull down the SLAVE_OK line. All mosfets are turned off and all the devices involved in the reg-  
ulation stop working. Cycle the power supply to restart operation.  
Figure 6 shows the constant current working condition  
15/35  
L6918 L6918A  
Figure 6. Constant Current operation  
Vout  
Ipeak  
IMAX  
Droop effect  
UVP  
IOCPx  
TonMAX  
TonMAX  
2·IOCPx  
Iout  
IMAX,TO  
µ
(IFB=70  
A
µ
(IFB=50 A)  
It can be observed that the peak current (Ipeak) is greater than the 140% but it can be determined as follow:  
V
IN – Voutmin  
V
IN – VoutMIN  
--------------------------------------  
0.5 T  
-------------------------------------  
Ipeak = IOCPx  
+
TonMAX= IOCPx  
+
L
L
Where Vout  
is the minimum output voltage (UVP threshold).  
MIN  
The device works in Constant-Current, and the output voltage decreases as the load increase, until the output  
voltage reaches the under-voltage threshold (Vout ). When this threshold is crossed, all mosfets are turned  
MIN  
off, the FAULT pin is driven high and the device stops working. Cycle the power supply to restart operation. The  
maximum average current during the Constant-Current behavior results:  
Ipeak – IOCPx  
IMAX,TOT = 2 IMAX= 2  
I
OCPx + -------------------------------------  
2
In this particular situation, the switching frequency results reduced.  
The ON time is the maximum allowed (T ) while the OFF time depends on the application:  
onMAX  
Ipeak – IOCPx  
1
f = ------------------------------------------  
TonMAX + TOFF  
-------------------------------------  
T OFF = L  
VOUT  
µ
reaches 35 A. The full load value is only a convention to work with con-  
Over current is set anyway when I  
INFOx  
venient values for I . Since the OCP intervention threshold is fixed, to modify the percentage with respect to  
FB  
the load value, it can be simply considered that, for example, to have on OCP threshold of 170%, this will cor-  
µ
µ
µ µ  
= 20.5 A (I = 41 A).  
INFOx FB  
respond to I  
= 35 A (I = 70 A). The full load current will then correspond to I  
INFOx  
FB  
INTEGRATED DROOP FUNCTION  
The devices use the droop function to satisfy the requirements of high performance microprocessors, reducing  
the size and the cost of the output capacitor.  
This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a de-  
pendence of the output voltage on the load current  
As shown in figure 7, the ESR drop is present in any case, but using the droop function the total deviation of the  
output voltage is minimized. In practice the droop function introduces a static error proportional to the output  
current that can be represented by an equivalent output resistance R  
. Since the device has an average cur-  
OUT  
rent mode regulation, the information about the total current delivered is used to implement the Droop Function.  
This current (equal to the sum of both I ) is sourced from the FB pin. Connecting a resistor between this pin  
INFOx  
and Vout, the total current information flows only in this resistor because the compensation network between  
16/35  
L6918 L6918A  
FB and COMP has always a capacitor in series (See fig. 8). The voltage regulated by each device is then equal  
to:  
RSENSE  
---------------------  
VOUT = VID – RFB IFB = VID – RFB  
I OUT  
Rg  
Where I  
is the output current of each device (equal to the total load current I  
divided by the number of  
LOAD  
OUT  
devices N)  
Since I depends on the current information about the two phases of each device, the output characteristic vs.  
FB  
load current is given by:  
RSENSE  
RSENSE I LOAD  
VOUT = VID – RFB IOUT = VID – RFB --------------------- I OUT = VID – RFB --------------------- ---------------  
Rg  
Rg  
2
Where R  
is the equivalent output resistance due to the droop function and I  
is still the output current of  
OUT  
OUT  
each device (that is the total current delivered to the load I  
divided by 2.  
LOAD  
Figure 7. Output transient response without (a) and with (b) the droop function  
ESR DROP  
ESR DROP  
VMAX  
VDROOP  
VNOM  
VMIN  
(a)  
(b)  
Figure 8. Active Droop Function Circuit  
VDROOP  
To VOUT  
RFB  
COMP  
FB  
Total Current Info (IINFO1+I  
)
INFO2  
Ref  
µ
µ
) and 70 A at the OCP interven-  
INFO2  
The feedback current is equal to 50 A at nominal full load (I = I  
+ I  
FB  
INFO1  
tion threshold, so the maximum output voltage deviation is equal to:  
∆VFULL_POSITIVE_LOAD = +RFB 50µA  
∆VOL_INTERVENTION = +RFB 70µA  
17/35  
L6918 L6918A  
Droop function is provided only for positive load; if negative load is applied, and then IINFOx<0, no current is  
sunk from the FB pin. The device regulates at the voltage programmed by the VID.  
OUTPUT VOLTAGE MONITORING AND PROTECTION: POWER GOOD  
The output voltage is monitored by the Slave device through the pin VSEN. If it is not within +12/-10% (typ.) of  
the programmed value, the PGOOD output is forced low. PGOOD is always active in the Slave device, also dur-  
ing soft-start. PGOOD in the Master device has the only masking function during soft-start. Since the master  
has not the output voltage sense, it keeps the PGOOD to GND during soft-start and after this step it is freed.  
The Slave device provides Over-Voltage protection: when the voltage sensed by VSEN reaches 117% (typ.) of  
the reference voltage present at the VPROG_IN pin, the Slave device stops switching keeping the LS mosfets  
ON. The FAULT pin is driven high (5V) and the SLAVE_OK line is pulled low. The master device then stops  
switching keeping the LS mosfets ON, too. Since the condition is latched, power supply (Vcc) turn off and on is  
required to restart operations.  
Under voltage protection is also provided and still detected by the Slave device. If the output voltage drops be-  
low the 60% (typ.) of the reference voltage present at the VPROG_IN pin for more than one clock period, the  
Slave device stops switching turning OFF all mosfets and pulling down the SLAVE_OK line: the Master device  
stops switching with LS mosfets ON. The OSC/INH/FAULT is not driven high in this case.  
Both Over Voltage and Under Voltage are active also during soft start (Under Voltage after than Vout reaches  
0.8V). During soft-start the reference voltage used to determine the UV threshold is the increasing voltage driv-  
en by the 2048 soft start digital counter. Moreover, OVP is always active, even during INHIBIT (see relevant  
section).  
Over / Under Voltage behavior are shown in Figure 9.  
Figure 9. OVP and UVP latch  
SLAVE_OK  
SLAVE_OK  
OSC  
OSC  
L6918  
L6918A  
LS  
LS  
L6918A  
L6918  
UNDER VOLTAGE LATCH  
OVER VOLTAGE LATCH  
REMOTE VOLTAGE SENSE  
A remote sense buffer is integrated into the device to allow output voltage remote sense implementation without  
any additional external components. In this way, the output voltage programmed is regulated between the re-  
mote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM  
module.  
The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR is for the  
regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin with  
unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded by a power plane re-  
sults in common mode coupling for any picked-up noise.  
If remote sense is not required, the output voltage is sensed by the VSEN pin connecting it directly to the output  
voltage. In this case the FBG and FBR pins must be connected anyway to the regulated voltage  
18/35  
L6918 L6918A  
INPUT CAPACITOR  
The input capacitor is designed considering mainly the input rms current that depends on the duty cycle as re-  
ported in figure. Considering the four phase topology, the input rms current is highly reduced comparing with  
single or dual phase operation.  
It can be observed that the input rms value is one half of the dual-phase equivalent input current in the worst-  
case condition that happens for D=1/8, 3/8,5/8 and 7/8.  
The power dissipated by the input capacitance is then equal to:  
2
PRMS = ESR (IRMS  
)
Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the  
high rms value needed by the CPU power supply application and also to minimize components cost, the input  
capacitance is realized by more than one physical capacitor. The equivalent rms current is simply the sum of  
the single capacitor's rms current.  
Figure 10. Input rms Current vs. Duty Cycle.  
Single Phase  
0.50  
Dual Phase  
0.25  
4 Phase  
0.25  
0.50  
0.75  
)
Duty Cycle (V OUT/VIN  
OUTPUT CAPACITOR  
Since the microprocessors require a current variation beyond 100A doing load transients, with a slope in the  
µ
range of tenth A/ s, the output capacitor is a basic component for the fast response of the power supply.  
Dual phase topology reduces the amount of output capacitance needed because of faster load transient re-  
sponse (switching frequency is doubled at the load connections). Current ripple cancellation due to the 180°  
phase shift between the two phases also reduces requirements on the output ESR to sustain a specified voltage  
ripple.  
When a load transient is applied to the converter's output, for first few microseconds the current to the load is  
supplied by the output capacitors. The controller recognizes immediately the load transient and increases the  
duty cycle, but the current slope is limited by the inductor value.  
The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the  
ESL):  
∆VOUT = ∆IOUT ESR  
19/35  
L6918 L6918A  
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The  
voltage drop due to the output capacitor discharge is given by the following equation:  
∆i2OUT  
∆VOUT = ------------------------------------------------------------------------------------------  
2 COUT (VINmin MAX – VOUT  
L
D
)
Where D  
is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load  
MAX  
transient and the lower is the output voltage static ripple.  
INDUCTOR DESIGN  
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost  
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain  
∆
the ripple current I between 20% and 30% of the maximum output current. The inductance value can be cal-  
L
culated with this relationship:  
V
IN – VOUT V OUT  
L = ----------------------------- --------------  
fSW ∆IL VIN  
Where f  
is the switching frequency, V is the input voltage and V  
is the output voltage.  
OUT  
SW  
IN  
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter  
response time to a load transient. The response time is the time required by the inductor to change its current  
from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by  
the output capacitors. Minimizing the response time can minimize the output capacitance required.  
The response time to a load transient is different for the application or the removal of the load: if during the ap-  
plication of the load the inductor is charged by a voltage equal to the difference between the input and the output  
voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-  
imate response time for DI load transient in case of enough fast compensation network response:  
L ∆I  
t application = -----------------------------  
IN – VOUT  
L ∆I  
t removal = --------------  
VOUT  
V
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst  
case is the response time after removal of the load with the minimum output voltage programmed and the max-  
imum input voltage available.  
Figure 11. Inductor ripple current vs. Vout  
9
L=1.5µH, Vin=12V  
8
L=2µH,  
Vin=12V  
7
6
L=3µH,  
Vin=12V  
5
4
L=1.5µH,  
Vin=5V  
3
L=2µH,  
Vin=5V  
2
L=3µH, Vin=5V  
1
0
0.5  
1.5  
Output Voltage [V]  
Figure 12 – Inductor ripple current vs. Vout  
2.5  
3.5  
20/35  
L6918 L6918A  
MAIN CONTROL LOOP  
The four phases control loop is composed by two dual phases devices that are independent each other. So, the  
compensation network and the control loop stability of each device don't depend on the other except for the fact  
that the other converter represents a load for this one.  
The L6918/A control loop is composed by the Current Sharing control loop and the Average Current Mode con-  
trol loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its  
regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Current  
Mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 12 reports the  
block diagram of the main control loop  
Figure 12. Main Control Loop Diagram  
L
1
+
PWM1  
1/5  
IINFO2  
CURRENT  
SHARING  
DUTY CYCLE  
CORRECTION  
IINFO1  
1/5  
L
2
+
PWM2  
CO  
RO  
ERROR  
AMPLIFIER  
REFERENCE  
PROGRAMMED  
BY VID  
+
-
4/5  
COMP  
FB  
ZF(S)  
RFB  
D02IN1392  
CURRENT SHARING (CS) CONTROL LOOP  
The devices are configured to work in a four synchronized phase application. Since the application is composed  
by two-phase devices that share reference and synchronization signals, the current sharing between the phases  
is realized in two different steps:  
1. Sharing between the phases of the same device;  
2. Sharing between devices.  
The Current Sharing between phases of the same device uses the internal current information to correct the  
PWM signal in order to equalize the current. Active current sharing is implemented using the information from  
Tran conductance differential amplifier in an average current mode control scheme. A current reference equal  
to the average of the read current (I ) is internally built; the error between the read current and this reference  
AVG  
is converted to a voltage with a proper gain and it is used to adjust the duty cycle whose dominant value is set  
by the error amplifier at COMP pin (See fig. 13).  
The current sharing control is a high bandwidth control allowing current sharing even during load transients.  
The current sharing error is affected by the choice of external components; choose precise Rg resistor (±1% is  
necessary) to sense the current. The current sharing error is internally dominated by the voltage mismatch of  
Tran conductance differential amplifier between phases; considering a voltage mismatch equal to 2mV across  
the sense resistor, the current reading error is given by the following equation:  
∆IREAD  
------------------- = --------------------------------------  
IMAX RSENSE IMAX  
2mV  
Where  
∆
I
is the difference between one phase current and the ideal current (I  
).  
MAX/2  
READ  
Ω
For Rsense=4m and Imax=40A the current sharing error is equal to 2.5%, neglecting errors due to Rg and  
Rsense mismatches.  
21/35  
L6918 L6918A  
Figure 13. Current Sharing Control Loop.  
L
1
+
PWM1  
IINFO2  
CURRENT  
SHARING  
DUTY CYCLE  
CORRECTION  
1/5  
1/5  
IINFO1  
+
PWM2  
L
2
VOUT  
COMP  
D02IN1393  
The current sharing between devices uses the droop function. Each device can be modeled with its Thevenin  
equivalent circuit (that is an ideal voltage source equal to the programmed voltage by VIDs and its related output  
resistance R  
), while the whole converter is modeled by the same ideal voltage source and an equivalent  
OUT  
output resistance R  
=R  
/2;  
DROOP OUT  
Considering this modelization reported in figure 14, it can be seen that the recirculating current between devices  
depends on the accuracy of the regulation.  
The accuracy of the voltage source is given by the offset of the master error amplifier Vos (6mV typ) and de-  
pends on the ratio between this offset and the output voltage variation with load (R  
,I  
). The mismatch  
OUT OUT  
between the regulated voltages causes a converter to source a current that is sunk by the other one. The accu-  
racy related to droop resistance depends on precision of feedback current of the device I , sense resistors  
FB  
R , Transconductance resistors Rg and feedback resistors R  
SENSE  
.
FB  
The current sharing error (CSE) results:  
2
2
2
2
∆I  
∆ I FB  
∆ R FB  
∆ R SENSE  
∆ R g  
4
2 R g  
2
1
Vos  
1
2
1
2
2
2
------O----U----T--  
-- -------------------------------  
2 ROUT IOUT  
-- -----------  
-- --------------  
-- -------------------------  
-- ----------  
+
CSE =  
≡
+
+
+
IOUT  
IFB  
RFB  
RSENSE  
µ
µ
Considering the external resistors tolerance of 1%, the typical current feedback accuracy of 2.5 A/50 A (5%),  
Ω
4 phases operation, Error Amplifier offset Vos=6mV, droop resistance R  
=1.5m (R  
=2,R  
OUT  
) and  
DROOP  
DROOP  
I
=60A (I  
LOAD  
=I  
/2), it results:  
OUT LOAD  
2
2
1
0.006V  
1 2.5µA  
-- ----------------  
2 50µA  
1
--  
2
2
2
2
2
4
2
2
-- ---------------------------------  
--  
--  
CSE =  
+
+
(0.01) + (0.01) + (0.01) = 0.062(6.2%)  
2 1.5mΩ 60A  
Figure 14. Equivalent Circuit for current sharing error calculation  
Recirculating Current  
ROUT  
RDROOP  
IOUT  
ILOAD  
ILOAD  
ROUT  
IOUT  
VPROG  
VID  
VOUT  
RLOAD  
VOUT  
RLOAD  
L6918  
22/35  
L6918 L6918A  
AVERAGE CURRENT MODE (ACM) CONTROL LOOP  
The average current mode control loop is reported in figure 15. The current information I sourced by the FB  
FB  
pin flows into R implementing the dependence of the output voltage from the read current.  
FB  
The ACM control loop gain results (obtained opening the loop after the COMP pin):  
PWM ZF(s) (RDROOP + ZP(s))  
G
LOOP(s) = – -------------------------------------------------------------------------------------------------------------------  
ZF(s)  
(ZP(s) + ZL(s)) -------------- + 1 + ----------- RFB  
A(s) A(s)  
1
where:  
R DROOP  
Rsense  
----------------------  
Rg  
=
R FB  
–
is the equivalent output resistance determined by the droop function;  
– Z (s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied  
P
load Ro;  
– Z (s) is the compensation network impedance;  
F
– Z (s) is the parallel of the two inductor impedance;  
L
– A(s) is the error amplifier gain;  
V IN  
-- ------------------  
4
5
PWM =  
∆
osc  
–
is the ACM PWM transfer function where V  
is the oscillator ramp amplitude  
∆VOSC  
and has a typical value of 2V  
Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, the control loop  
gain results:  
V IN  
LOOP(s) = –-- ------------------ ------------------------------------ ------- + --------------  
∆VOSC ZP(s) + ZL(s) Rg RFB  
Z F (s )  
Z P (s )  
4
5
Rs  
G
With further simplifications, it results:  
V IN  
Z F (s ) Ro + RDROOP  
1 + s Co (RDROOP//Ro + ESR)  
4
5
G
LOOP(s) = –-- ------------------ -------------- ------------------------------------- ----------------------------------------------------------------------------------------------------------------------------------  
∆VOSC RFB  
RL  
RL  
L
L
s2 Co -- + s --------------- + Co ESR + Co  
+ 1  
Ro + ------  
------  
2
2
2
2 Ro  
Considering now that in the application of interest it can be assumed that Ro>>R ; ESR<<Ro and  
L
R <<Ro, it results:  
DROOP  
V IN  
-- ------------------ -------------- ----------------------------------------------------------------------------------------------------------------------------------  
LOOP(s) = –  
Z F (s )  
1 + s Co (RDROOP + ESR)  
4
5
G
∆VOSC RFB  
RL  
s2 Co -- + s --------------- + Co ESR + Co ------ + 1  
2 Ro  
L
L
2
2
The ACM control loop gain is designed to obtain a high DC gain to minimize static error and cross the 0dB axes  
ω
with a constant -20dB/dec slope with the desired crossover frequency T. Neglecting the effect of Z (s), the  
F
transfer function has one zero and two poles. Both the poles are fixed once the output filter is designed and the  
zero is fixed by ESR and the Droop resistance.  
To obtain the desired shape an R -C series network is considered for the Z (s) implementation.  
F
F
F
ω
A zero at =1/R C is then introduced together with an integrator. This integrator minimizes the static error  
f
F F  
23/35  
L6918 L6918A  
while placing the zero in correspondence with the L-C resonance a simple -20dB/dec shape of the gain is as-  
sured (See Figure 15). In fact, considering the usual value for the output filter, the LC resonance results to be  
at frequency lower than the above reported zero.  
Figure 15. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right).  
dB  
IFB  
ZF  
CF  
RF  
GLOOP  
RFB  
VCOMP  
K
REF  
ZF(s)  
L/2  
VOUT  
PWM  
•
ω
d VIN  
Cout  
ESR  
ωLC  
ωZ  
ωT  
V IN  
K = -- --------------- ----------  
∆Vosc R FB  
Rout  
4
5
1
dB  
ω
ω
ω
as  
T
Compensation network can be simply designed placing  
desired obtaining:  
=
Z
and imposing the cross-over frequency  
LC  
L
2
--  
Co  
RFB ∆V  
------------------------O-----S---C-- --  
5
4
L
-------------------------------------------------------  
RF  
=
ω T  
CF = -------------------  
VIN  
2 (RDROOP + ESR)  
R F  
In a four phase operation (since the four phase converter is realized by two dual phase converters in parallel  
that shares current using droop), also the other sub-system in parallel must be considered. In particular, in the  
above reported relationships, it must be considered with Co and ESR the total output capacitance and equiva-  
lent ESR while the output impedance Zo of the other sub-system must be considered in parallel to the output  
capacitance Co and to the load Ro.  
The output impedance of the other sub-system in parallel results:  
V IN  
ZL(s) + -- ------------------ ---------------------- Z F (s )  
∆VOSC Rg  
Zo(s) = -----------------------------------------------------------------------------------------------  
V IN Z F (s )  
-- ------------------ --------------  
4
Rsense  
5
4
5
1 +  
∆VOSC RFB  
Considering Zo in parallel to Ro, it can be verified that the R and C design relationships are still valid.  
F
F
LAYOUT GUIDELINES  
Since the device manages control functions and high-current drivers, layout is one of the most important things  
to consider when designing such high current applications.  
A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radi-  
ation and a proper connection between signal and power ground can optimize the performance of the control  
loops.  
Integrated power drivers reduce components count and interconnections between control functions and drivers,  
reducing the board space.  
Here below are listed the main points to focus on when starting a new layout and rules are suggested for a cor-  
rect implementation.  
24/35  
L6918 L6918A  
Power Connections.  
These are the connections where switching and continuous current flows from the input supply towards the load.  
The first priority when placing components has to be reserved to this power section, minimizing the length of  
each connection as much as possible.  
To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane  
and anyway realized by wide and thick copper traces. The critical components, i.e. the power transistors, must  
be located as close as possible, together and to the controller. Considering that the "electrical" components re-  
ported in figure are composed by more than one "physical" component, a ground plane or "star" grounding con-  
nection is suggested to minimize effects due to multiple connections.  
Fig. 16a shows the details of the power connections involved and the current loops. The input capacitance  
(CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order  
to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are required.  
Figure 16. Power connections and related connections layout guidelines (same for both phases).  
VIN  
HS  
LS  
Rgate  
HGATEx  
PHASEx  
L
COUT  
D
Rgate  
LOAD  
CIN  
LGATEx  
PGNDx  
a. PCB power and ground planes areas  
VIN  
BOOTx  
PHASEx  
VCC  
CBOOTx  
HS  
LS  
L
+VCC  
COUT  
D
LOAD  
CIN  
SGND  
CVCC  
b. PCB small signal components placement  
Power Connections Related.  
Fig.16b shows some small signal components placement, and how and where to mix signal and power ground planes.  
The distance from drivers and mosfet gates should be reduced as much as possible. Propagation delay times as  
well as for the voltage spikes generated by the distributed inductance along the copper traces are so minimized.  
In fact, the further the mosfet is from the device, the longer is the interconnecting gate trace and as a consequence,  
the higher are the voltage spikes corresponding to the gate PWM rising and falling signals. Even if these spikes  
are clamped by inherent internal diodes, propagation delays, noise and potential causes of instabilities are intro-  
duced jeopardizing good system behavior. One important consequence is that the switching losses for the high  
side mosfet are significantly increased.  
For this reason, it is suggested to have the device oriented with the driver side towards the mosfets and the GATEx  
and PHASEx traces walking together toward the high side mosfet in order to minimize distance (see fig 17). In  
addition, since the PHASEx pin is the return path for the high side driver, this pin must be connected directly to  
the High Side mosfet Source pin to have a proper driving for this mosfet. For the LS mosfets, the return path is the  
PGND pin: it can be connected directly to the power ground plane (if implemented) or in the same way to the LS  
mosfets Source pin. GATEx and PHASEx connections (and also PGND when no power ground plane is imple-  
mented) must also be designed to handle current peaks in excess of 2A (30 mils wide is suggested).  
25/35  
L6918 L6918A  
Figure 17. Device orientation (left) and sense nets routing (right).  
To LS mosfet  
(or sense resistor)  
Towards HS mosfet  
(30 mils wide)  
Towards LS mosfet  
(30 mils wide)  
To LS mosfet  
Towards HS mosfet  
(or sense resistor)  
(30 mils wide)  
To regulated output  
Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the system  
efficiency.  
The placement of other components is also important:  
– The bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to min-  
imize the loop that is created.  
– Decoupling capacitor from Vcc and SGND placed as close as possible to the involved pins.  
– Decoupling capacitor from VCCDR and PGND placed as close as possible to those pins. This capac-  
itor sustains the peak currents requested by the low-side mosfet drivers.  
– Refer to SGND all the sensible components such as frequency set-up resistor (when present) and  
also the optional resistor from FB to GND used to give the positive droop effect.  
– Connect SGND to PGND on the load side (output capacitor) to avoid undesirable load regulation ef-  
fect and to ensure the right precision to the regulation when the remote sense buffer is not used.  
– An additional 100nF ceramic capacitor is suggested to place near HS mosfet drain. This helps in re-  
ducing noise.  
– PHASE pin spikes. Since the HS mosfet switches in hard mode, heavy voltage spikes can be ob-  
served on the PHASE pins. If these voltage spikes overcome the max breakdown voltage of the pin,  
the device can absorb energy and it can cause damages. The voltage spikes must be limited by prop-  
er layout, the use of gate resistors, Schottky diodes in parallel to the low side mosfets and/or snubber  
network on the low side mosfets, to a value lower than 26V, for 20nSec, at Fosc of 600kHz max.  
Current Sense Connectio ns.  
– Remote Buffer: The input connections for this component must be routed as parallel nets from the  
FBG/FBR pins to the load in order to compensate losses along the output power traces and also to  
avoid the pick-up of any common mode noise. Connecting these pins in points far from the load will  
cause a non-optimum load regulation, increasing output tolerance.  
– Current Reading: The Rg resistor has to be placed as close as possible to the ISENx and PGNDSx  
pins in order to limit the noise injection into the device. The PCB traces connecting these resistors to  
the reading point must be routed as parallel traces in order to avoid the pick-up of any common mode  
noise. It's also important to avoid any offset in the measurement and to get a better precision, to con-  
nect the traces as close as possible to the sensing elements, dedicated current sense resistor or low  
side mosfet R  
.
dsON  
– Moreover, when using the low side mosfet R  
as current sense element, the ISENx pin is practi-  
dsON  
cally connected to the PHASEx pin. DO NOT CONNECT THE PINS TOGETHER AND THEN TO  
THE HS SOURCE! The device won't work properly because of the noise generated by the return of  
the high side driver. In this case route two separate nets: connect the PHASEx pin to the HS Source  
(route together with HGATEx) with a wide net (30 mils) and the ISENx pin to the LS Drain (route to-  
gether with PGNDSx). Moreover, the PGNDSx pin is always connected, through the Rg resistor, to  
the PGND: DO NOT CONNECT DIRECTLY TO THE PGND! In this case the device won't work prop-  
erly. Route anyway to the LS mosfet source (together with ISENx net).  
Right and wrong connections are reported in Figure 18.  
Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter  
26/35  
L6918 L6918A  
Figure 18. PCB layout connections for sense nets.  
NOT CORRECT  
CORRECT  
ToLS Drain  
and Source  
VIA to GND plane  
To HS Gate  
and Source  
To PHASE  
connection  
Wrong (left) and correct (right) connections for the current reading sensing nets.  
Interconnections between devices.  
Master and Slave devices share reference and other signals for the regulation. To avoid noise injection into de-  
vices, it is recommended to route these nets carefully.  
– VPROG_IN / VPROG_OUT: This is the reference for the regulation. It must be routed far away from  
any noisy trace and guarded by ground traces in order to avoid noise injection into the device. It can  
be filtered with a 30nF maximum of distributed capacitance vs. signal ground.  
– SLAVE_OK: This signal is used by the devices for the start-up synchronization and also to commu-  
nicate UVP from Slave to Master device. It must be filtered by 1nF capacitor near the pin of each de-  
vice to avoid the noise to cause false protection's trigger.  
Demo Board Description  
The L6918 demo board shows the operation of the device in a four phases application. This evaluation board al-  
lows output voltage adjustability (1.100V - 1.850V) through the switches S0-S4 and high output current capability.  
2
The board has been laid out with the possibility to use up to two D PACK mosfets for the low side switch in order  
to give maximum flexibility in the mosfet choice.  
µ
The four layers demo board's copper thickness is of 70 m in order to minimize conduction losses considering  
the high current that the circuit is able to deliver.  
Demo board schematic circuit is reported in Figure 19.  
Several jumpers allow setting different configurations for the device: JP3, JP4 and JP5 allow configuring the  
remote buffer as desired. Simply shorting JP4 and JP5 the remote buffer is enabled and it senses the output  
voltage on-board; to implement a real remote sense, leave these jumpers open and connect the FBG and FBR  
connectors on the demo board to the remote load. To avoid using the remote buffer, simply short all the jumpers  
JP3, JP4 and JP5. Local sense through the R7 is used for the regulation.  
The input can be configured in different ways using the jumpers JP1, JP2 and JP6; these jumpers control also  
the mosfet driver supply voltage. Anyway, power conversion starts from V and the device is supplied from V  
IN  
CC  
(See Figure 20).  
27/35  
L6918 L6918A  
Figure 19. Demo Board Schematic  
Vin  
JP6  
DZ1  
JP1  
JP2  
R16  
GNDin  
C9,C10;  
C33,C34  
C11,C13,C51;  
C46,C47,C52  
R30  
VCCDR  
VCC  
Vcc  
2
6
C29  
L3  
D10  
Q6  
C32  
D9  
C31  
GNDcc  
C28  
L4  
BOOT1  
BOOT2  
5
4
24  
25  
UGATE1  
PHASE1  
LGATE1  
ISEN1  
UGATE2  
C27  
Q8  
C26  
R34  
R35  
PHASE2  
LGATE2  
ISEN2  
VoutCOR  
3
26  
27  
16  
R38  
R33  
R39  
R32  
R19  
R20  
Q5  
1
Q7  
C14..C23,  
C35..C44  
GNDCORE  
13  
Q5a  
Q7a  
R24  
R25  
R27  
R26  
PGNDS2  
PGND  
PGNDS1  
14  
15  
28  
R21 C24  
L6918A  
Master  
VID4  
VID3  
VID2  
VID1  
VID0  
S4  
S3  
S2  
S1  
S0  
PGOOD  
22  
21  
20  
19  
18  
17  
23  
PGOOD  
R22  
C30  
C53  
JP3  
R28  
FB  
OSC / INH  
9
JP4  
JP5  
R37  
To L6918A  
Pin 6  
R29  
C25  
R23  
C48  
R31  
SGND  
7
COMP  
8
11  
10  
12  
VPROG_OUT  
SLAVE_OK  
C50  
C12  
C45  
FBR  
FBG  
C49  
VPROG_IN  
SLAVE_OK  
22  
21  
20  
OSC  
/
INH  
8
COMP  
17  
7
C2  
R8  
R36  
To L6918  
Pin 6  
R2  
C1  
R7  
R9  
SGND  
9
FB  
C24  
R11  
To Slave’s  
PGOOD  
PGOOD  
23  
18  
VSEN  
FBR  
10  
11  
12  
SYNC_OUT  
SL/ADJ  
FBG  
19  
14  
SYNC/ADJ  
28  
15  
PGND  
PGNDS2  
R4  
R3  
R5  
R6  
L6918  
PGNDS1  
Slave  
Q1a  
13  
1
16  
27  
26  
Q3a  
ISEN1  
ISEN2  
D5  
D6  
R12  
R13  
R18  
Q1  
Q2  
Q3  
LGATE1  
PHASE1  
LGATE2  
PHASE2  
R17  
3
L1  
C5  
L2  
C6  
R15  
R14  
C7  
C4  
4
5
25  
24  
Q4  
C3  
UGATE1  
BOOT1  
UGATE2  
BOOT2  
D4  
D3  
C8  
2
6
VCCDR  
VCC  
R10  
28/35  
L6918 L6918A  
Figure 20. Power supply configuration  
To Vcc pin  
Vin  
To HS Drains (Power Input)  
To BOOTx (HS Driver Supply)  
JP6  
DZ1  
JP1  
GNDin  
JP2  
Vcc  
To VCCDR pin (LS Driver Supply)  
GNDcc  
Two main configurations can be distinguished: Single Supply (V = V = 12V) and Double Supply (V = 12V  
CC  
IN  
CC  
V
IN  
= 5V or different).  
– Single Supply: In this case JP6 has to be completely shorted. The device is supplied with the same rail  
that is used for the conversion. With an additional zener diode DZ1 a lower voltage can be derived to  
supply the mosfets driver if Logic level mosfet are used. In this case JP1 must be left open so that the  
HS driver is supplied with V -V  
through BOOTx and JP2 must be shorted to the left to use V or to  
IN DZ1  
IN  
the right to use V -V  
to supply the LS driver through VCCDR pin. Otherwise, JP1 must be shorted  
IN DZ1  
and JP2 can be freely shorted in one of the two positions.  
– Double Supply: In this case V supply directly the controller (12V) while VIN supplies the HS drains  
CC  
for the power conversion. This last one can start indifferently from the 5V bus (Typ.) or from other buses  
allowing maximum flexibility in the power conversion. Supply for the mosfet driver can be programmed  
through the jumpers JP1, JP2 and JP6 as previously illustrated. JP6 selects now V or V depending  
CC  
IN  
on the requirements.  
Some examples are reported in the following Figures 21 and 22.  
Figure 21. Jumpers configuration: Double Supply  
Vcc = 12V  
Vin = 5V  
HS Drains = 5V  
HS Supply = 5V  
JP6  
DZ1  
GNDin  
JP2  
JP1  
Vcc = 12V  
GNDcc  
VCCDR (LS Supply) = 5V  
(a) VCC = 12V; VBOOTx = VCCDR = VIN = 5V  
Vcc = 12V  
Vin = 5V  
GNDin  
HS Drains = 5V  
HS Supply = 12V  
JP6  
DZ1  
JP2  
JP1  
Vcc = 12V  
GNDcc  
VCCDR (LS Supply) = 12V  
(b) VCC = VBOOTx = VCCDR = 12V; VIN = 5V  
29/35  
L6918 L6918A  
Figure 22. Jumpers configuration: Single Supply  
Vcc = 12V  
Vin = 12V  
HS Drains = 12V  
HS Supply = 5.2V  
JP6  
DZ1 6.8V  
JP1  
GNDin  
JP2  
Vcc = Open  
GNDcc  
VCCDR (LS Supply) = 12V  
(a) VCC = VIN = VCCDR = 12V; VBOOTx = 5.2V  
Vcc = 12V  
Vin = 12V  
GNDin  
HS Drains = 12V  
HS Supply = 12V  
JP6  
DZ1  
JP2  
JP1  
Vcc = Open  
GNDcc  
VCCDR (LS Supply) = 12V  
(b) VCC = V = VBOOTx = VCCDR = 12V  
IN  
PCB AND COMPONENT LAYOUT  
Figure 23. PCB and Components Layouts (Dimensions: 10.8mm x 14.5mm)  
Internal PGND Plane  
Component Side  
Internal SGND Plane  
Solder Side  
30/35  
L6918 L6918A  
CPU Power Supply: 12VIN; 1.45VOUT; 110ADC  
Considering the high slope for the load transient, a high switching frequency has to be used. In addition to fast  
reaction, this helps in reducing output and input capacitor. Inductance value is also reduced.  
A switching frequency of 200kHz for each phase is then considered allowing large bandwidth for the compen-  
sation network. Considering the high output current, power conversion will start from the 12V bus.  
– Current Reading Network and Over Current:  
Since the maximum output current is I  
= 110A, the over current threshold has been set to 110A  
MAX  
(27.5A x 4) in the worst case (max mosfet temperature). Since the device limits the valley of the trian-  
gular ripple across the inductors, the current ripple must be considered too. Considering the inductor  
core saturation, a current ripple of 10A has to be considered so that the OCP threshold in worst case  
becomes OCPx = 22A (27.5A-5A). Considering to sense the output current across the low-side mosfets  
Ω
), each STB90NF03L has 6.5m max at 25°C that  
RdsON (two in parallel to reduce equivalent R  
dsON  
Ω
becomes 9.1m at 100°C considering the temperature variation; the resulting transconductance resis-  
tor Rg has to be:  
R
dsON  
4.5m  
-------------  
-----------------  
=
=
=
Ω
2.7k  
Rg  
I
22  
(R3 to R6; R24 to R27)  
OCPx  
µ
µ
35  
35  
– Droop function Design:  
Considering a voltage drop of 85mV at full load, the feedback resistor R has to be:  
FB  
85mV  
= ---------------- =  
Ω
(R7)  
R
1.2k  
FB  
µ
70 A  
– Inductor design:  
Transient response performance needs a compromise in the inductor choice value: the biggest the in-  
ductor, the highest the efficient but the worse the transient response and vice versa. Considering then  
µ
an inductor value of 1 H, the current ripple becomes:  
–
L
–
Vin Vout  
d
Fsw  
12 1.4 1.4  
1
∆ = ---------------------------- ----------- = -------------------- ------- ------------ =  
I
6.2A (L1, L2)  
µ
1
12 200k  
– Output Capacitor:  
Ten Rubycon MBZ (3300 F / 6.3V / 12m max ESR) has been used implementing a resulting ESR of  
µ
Ω
Ω
Ω
1.2m resulting in an ESR voltage drop of 52A*1.2m = 62mV after a 52A load transient.  
– Compensation Network:  
A voltage loop bandwidth of 20kHz is considered to let the device fast react after load transient.  
The R C network results:  
F
F
RFB ∆VOS  
5
4
L
1.2K 2 5  
1µ  
RF = ------------------------------ -- ω T ------------------------------------------------------- = -------------------- -- 20k 2Π ---------------------------------------------------------- = 3.9kΩ  
(R8)  
VIN  
2 (RDROOP + ESR)  
12  
4
4.5m  
2
------------- 1k + 1.2m  
2.7  
µ
1
2
L
2
--  
------  
µ
Co  
6 3300  
= ------------------- = ---------------------------------------- =  
C
22nF (C2)  
F
R
3.9k  
F
Further adjustments can be done on the work bench to fit the requirements and to compensate layout parasitic  
components.  
31/35  
L6918 L6918A  
Part List  
Resistors  
R2, R9, R20, R23, R31, R42  
Not Mounted  
2.7K  
SMD 0805  
SMD 0805  
R3, R4, R5, R6  
R24, R25, R26, R27  
1%  
1%  
R7, R28  
1.2K  
510  
0
SMD 0805  
SMD 0805  
SMD 0805  
R11, R22  
R12 to R19  
R32, R33, R34, R35, R38, R39  
R8, R29  
3.9K  
82  
SMD 0805  
SMD 0805  
SMD 0805  
SMD 0805  
R10, R30  
R21  
10K  
1M  
R36, R37  
1%  
Capacitors  
C1, C48  
Not Mounted  
47n  
SMD 0805  
SMD 0805  
SMD 0805  
SMD 0805  
SMD 0805  
SMD 1206  
SMD 1206  
Radial 23x10.5  
C2, C25  
C24, C30  
100n  
C3, C4, C26, C27  
C5, C6, C7, C28, C29, C32  
C8, C31  
100n  
1µ  
10µ  
C9, C10, C33, C34  
10µ or 22µ / 16V  
1800µ / 16V  
TDK Multilayer Ceramic  
Rubycon MBZ  
C11, C13, C46, C47,  
C51, C52  
C12, C45, C49, C50  
C53  
1n  
SMD 0805  
1n  
SMD 0805  
C14, C16, C18, C20, C22  
C35, C37, C39, C41, C43  
3300µ /6.3V  
Rubycon MBZ  
Radial 23x10.5  
Diodes  
D3, D4, D9, D10  
DZ1  
1N4148  
SOT23  
Not Mounted  
MINIMELF  
Mosfets  
Q1, Q1A, Q3, Q3A,  
Q5, Q5A, Q7, Q7A  
STB90NF03L  
STB90NF03L  
STMicroelectronics  
STMicroelectronics  
D2PACK  
D2PACK  
Q2, Q4, Q6, Q8  
Inductors  
L1, L2, L3, L4  
Controllers  
U2  
1µ  
77121 Core / 5 Turns 2 x 1.5 mm  
STMicroelectronics  
L6918  
SO28  
32/35  
L6918 L6918A  
STATIC PERFORMANCES  
Figure 24 shows the demo board measured efficiency versus load current in steady state conditions without air-  
flow at ambient temperature.  
Figure 24. System Efficiency  
90  
85  
80  
75  
70  
65  
60  
55  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100 110  
Output Current [A]  
Figure 25 shows the mosfets temperature versus output current in steady state condition without any air-flow  
or heat sink. It can be observed that the mosfets are under 100°C in any conditions. Load regulation is also re-  
ported from 10A to 110A.  
Figure 25. Mosfet Temperature and Load Regulation.  
110  
1.470  
100  
High-Side MOS  
1.450  
1.430  
1.410  
1.390  
1.370  
1.350  
90  
80  
70  
60  
50  
40  
30  
Low-Side MOS  
0
10 20 30 40 50 60 70 80 90 100 110  
0
10 20 30 40 50 60 70 80 90 100 110  
Output Current [A]  
Output Current [A]  
DYNAMIC PERFORMANCES  
Figure 26 shows the system response to a load transient from 0A to 110A. The output voltage is contained in  
the ±50mV range. Additional output capacitors can help in reducing the initial voltage spike mainly due to the  
ESR.  
Figure 26. 110A Load Transient Response.  
33/35  
L6918 L6918A  
mm  
inch  
DIM.  
OUTLINE AND  
MECHANICAL DATA  
MIN. TYP. MAX. MIN. TYP. MAX.  
A
a1  
b
2.65  
0.3  
0.104  
0.012  
0.019  
0.013  
0.1  
0.004  
0.35  
0.23  
0.49 0.014  
0.32 0.009  
b1  
C
0.5  
0.020  
c1  
D
45° (typ.)  
17.7  
10  
18.1 0.697  
10.65 0.394  
0.713  
0.419  
E
e
1.27  
0.050  
0.65  
e3  
F
16.51  
7.4  
0.4  
7.6  
0.291  
0.299  
0.050  
L
1.27 0.016  
SO28  
S
8 ° (max.)  
34/35  
L6918 L6918A  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics  
© 2002 STMicroelectronics - All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco -  
Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.  
http://www.st.com  
35/35  

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