HFBR-5701LP_技术文档

Agilent HFBR-5701L/LP

Small Form Factor Pluggable

Optical Transceiver for

Gigabit Ethernet (1.25 GBd) and

Fibre Channel (1.0625 GBd)

Data Sheet

Applications

• Switch to switch interface

• Switched backplane applications

• File server interface

• iSCSI applications

Description

Features

Related Products

The HFBR-5701L optical transceiver

is compliant with the specifications

set forth in the IEEE802.3

• IEEE 802.3 Gigabit Ethernet (1.25

GBd) 1000BASE-SX compliant

• HFBR-5710L: 1.25 GBd Ethernet

(1000BASE-SX) SFP

Fibre Channel (100-M5-SN-I, 100-

•

(1000BASE-SX), Fibre Channel

(100-M5-SN-I, 100-M6-SN-I), and the

Small Form-Factor Pluggable (SFP)

Multi-Source Agreement (MSA). Its

primary application is servicing

Gigabit Ethernet and Fibre Channel

links between optical networking

equipment. It offers previously

unavailable system cost, upgrade,

and reliability benefits by virtue of

being hot-pluggable. Further, it

incorporates the latest 3.3 VDC

compatible transceiver technology

including an 850 nm VCSEL

• HFBR-5720L: 2.125 GBd Fibre

Channel (200-M5-SN-I, 200-M6-SN-I)

Multi-Mode SFP

M6-SN-I) compliant

• Small Form Factor Pluggable (SFP)

Multi-Source Agreement (MSA)

compliant

• HFBR-5730L: 1.0625 GBd Fibre

Channel (100-M5-SN-I, 100-M6-SN-I)

Multi-Mode SFP

• Manufactured in an ISO 9001

compliant facility

• HDMP-1687: Quad Channel SerDes

IC 1.25 GBd Ethernet

• Hot-pluggable

• Optional extended de-latch for

high density applications as shown

in Figure 10

– HFBR-5701LP bail-wire pull

de-latch

• HDMP-1646A: Single Channel

SerDes IC for 1.25 GBd Ethernet and

1.0625 GBd Fibre Channel

– HFBR-5701L standard de-latch

transmitter as well as a convenient

LC-Duplex optical interface.

• +3.3 V DC power supply

• Industry leading EMI performance

for high port density

• 850 nm Vertical Cavity Surface

Emitting Laser (VCSEL)

• Eye safety certified:

– US 21 CFR(J)

– EN 60825-1 (+All)

• LC-Duplex fiber connector

compliant

• Fiber compatibility:

– 2 to 550 meters with 50/125 µm

fiber

– 2 to 275 meters with 62.5/125 µm

fiber

OPTICAL INTERFACE

RECEIVER

ELECTRICAL INTERFACE

RD+ (RECEIVE DATA)

RD– (RECEIVE DATA)

LOSS OF SIGNAL

AMPLIFICATION

& QUANTIZATION

INCOMING OPTICAL SIGNAL

PHOTODETECTOR

TRANSMITTER

VCSEL

TX_DISABLE

LASER

DRIVER &

SAFETY

TD+ (TRANSMIT DATA)

TD– (TRANSMIT DATA)

TX_FAULT

OUTGOING OPTICAL SIGNAL

CIRCUITRY

MOD-DEF2

MOD-DEF1

MOD-DEF0

EEPROM

Figure 1. HFBR-5701L block diagram.

Overview

Factor port regardless of whether

the host equipment is operating

or not. The module is simply

inserted, electrical-interface first,

under finger-pressure. Controlled

hot-plugging is ensured by

3-stage pin sequencing at the

electrical interface. This printed

circuit board card-edge connector

is depicted in Figure 2.

As the HFBR-5701L is inserted,

first contact is made by the

housing ground shield,

The HFBR-5701L offers maxi-

mum flexibility to designers,

manufacturers, and operators of

Gigabit Ethernet networking

equipment. A pluggable architec-

ture allows the module to be

installed into MSA standard SFP

ports at any time – even with the

host equipment operating and

online. This facilitates the rapid

configuration of equipment to

precisely the user’s needs –

reducing inventory costs and

network downtime. Compared

with traditional transceivers, the

size of the Small Form Factor

package enables higher port

densities.

discharging any potentially

component-damaging static

electricity. Ground pins engage

next and are followed by Tx and

Rx power supplies. Finally, signal

lines are connected. Pin functions

and sequencing are listed in

Table 2.

3 2 1

ENGAGEMENT

SEQUENCE

20

19

18

17

16

15

14

13

12

11

V

T

1

2

V

T

EE

TD–

TD+

TX FAULT

3

TX DISABLE

MOD-DEF(2)

MOD-DEF(1)

MOD-DEF(0)

RATE SELECT

LOS

V

T

4

EE

CC

Module Diagrams

T

5

Figure 1 illustrates the major

functional components of the

HFBR-5701L. The external

configuration of the module is

depicted in Figure 7. Figure 8

depicts the panel and host board

footprints.

R

6

R

7

EE

RD+

RD–

8

9

V

R

EE

V

R

10

V

EE

Installation

The HFBR-5701L can be installed

in or removed from any MSA-

compliant Pluggable Small Form

TOP OF BOARD

BOTTOM OF BOARD

(AS VIEWED THROUGH TOP OF BOARD)

Figure 2. Pin description of the SFP electrical interface.

2

Before extracting the module, the

black plastic tab beneath the

optical port must be depressed,

releasing the latch mechanism.

The transceiver can then be

operation. In the event of a fault

(e.g., eye safety circuit activated),

cycling this control signal resets

the module as depicted in Figure 6.

Loss of Signal

The Loss Of Signal (LOS) output

indicates an unusable optical

input power level. A high LOS

output signal indicates a loss of

signal while a low LOS output

signal indicates normal operation.

The Loss Of Signal thresholds are

set to indicate a definite optical

fault has occurred (e.g.,

pulled out of the port manually by Eye Safety Circuit

gripping the side of the LC ports.

The HFBR-5701L provides Class

1 eye safety by design and has

been tested for compliance with

the requirements listed in

Table 1. The eye safety circuit

continuously monitors optical

output power levels and will

disable the transmitter and assert

a TX_FAULT signal upon

detecting an unsafe condition.

Such unsafe conditions can be

created by inputs from the host

board (Vcc fluxuation,

For easier fingertip delatching in

high port density applications, an

optional extended tab is offered

as shown in Figure 10.

disconnected or broken fiber

connection to receiver, failed

transmitter, etc.).

Serial Identification (EEPROM)

The HFBR-5701L features an

EEPROM for Serial ID. It

Functional I/O

The HFBR-5701L accepts

industry standard differential

signals such as LVPECL and CML

within the scope of the SFP MSA.

To simplify board requirements,

transmitter bias resistors and

coupling capacitors are

incorporated into the transceiver

module. The module is “ac-

coupled” and internally

contains the product data stored

for retrieval by host equipment.

This data is accessed via the 2-

wire serial EEPROM protocol of

the ATMEL AT24C01A or similar

in compliance with the industry

standard SFP Multi-Source

Agreement. Contents of the

HFBR-5701L serial ID memory

are displayed in Table 9.

unbalanced code) or faults within

the module.

Receiver Section

The receiver section includes the

Receiver Optical Subassembly

(ROSA) and amplification/

terminated.

quantization circuitry. The ROSA,

containing a PIN photodiode and

custom trans-impedance

Transmitter Section

Figure 4 illustrates a recom-

mended interface circuit to link

the HFBR-5701L to the

supporting Physical Layer

integrated circuits.

The transmitter section includes

the Transmitter Optical Sub-

assembly (TOSA) and laser driver

circuitry. The TOSA, containing

an 850 nm VCSEL (Vertical

Cavity Surface Emitting Laser)

light source, is located at the

optical interface and mates with

the LC optical connector. The

TOSA is driven by a custom IC,

which converts differential logic

signals into an analog laser diode

drive current. This Tx driver

circuit regulates the optical

power at a constant level

preamplifier, is located at the

optical interface and mates with

the LC optical connector. The

ROSA is mated to a custom IC

that provides post-amplification

and quantization. Also included is

a Loss Of Signal (LOS) detection

circuit.

Timing diagrams for the MSA

compliant control signals

implemented in this module are

depicted in Figure 6.

1 µH

V

T

CC

0.1 µF

provided the data pattern is DC

balanced (8B10B code for

example).

1 µH

3.3 V

V

R

CC

Tx Disable

10 µF

0.1 µF

10 µF

The HFBR-5701L accepts a

transmit disable control signal

input which shuts down the

transmitter. A high signal

SFP MODULE

HOST BOARD

implements this function while a

low signal allows normal laser

Figure 3. MSA required power supply filter.

3

Required Host Board Components

Electrostatic Discharge (ESD)

The metal housing and shielded

design of the HFBR-5701L

minimize the EMI challenge

facing the host equipment

designer.

The MSA power supply noise

rejection filter is required on the

host PCB to meet data sheet

performance. The MSA filter

incorporates an inductor which

should be rated 400 mADC and

1 Ω series resistance or better. It

should not be replaced with a

ferrite. The required filter is

illustrated in Figure 3.

There are two design cases in

which immunity to ESD damage

is important.

The first case is during handling

of the transceiver prior to

Flammability

insertion into the transceiver

port. To protect the transceiver,

it’s important to use normal ESD

handling precautions. These

precautions include using

The HFBR-5701L transceiver is

made of metal and high strength,

heat resistant, chemically

resistant, and UL 94V-0 flame

retardant plastic.

The MSA also specifies that 4.7 K

to 10 KΩ pull-up resistors for

TX_FAULT, LOS, and

MOD_DEF0,1,2 are required on

the host PCB.

grounded wrist straps, work

benches, and floor mats in ESD

controlled areas. The ESD

sensitivity of the HFBR-5701L is

compatible with typical industry

production environments.

Caution

There are no user serviceable

parts nor any maintenance

required for the HFBR-5701L. All

adjustments are made at the

factory before shipment to our

customers. Tampering with,

modifying, misusing or improp-

erly handling the HFBR-5701L

will void the product warranty. It

may also result in improper

operation of the HFBR-5701L

circuitry, and possible overstress

of the laser source. Device

degradation or Product failure

may result. Connection of the

HFBR-5701L to a non-Gigabit

Ethernet-compliant optical

source, operating above the

recommended absolute maximum

conditions or operating the

Application Support

Evaluation Kit

The second case to consider is

static discharges to the exterior

of the host equipment chassis

after installation. To the extent

that the optical interface is

exposed to the outside of the host

equipment chassis, it may be

subject to system-level ESD

requirements.

To assist in the transceiver

evaluation process, Agilent offers

a 1.25 Gbd Gigabit Ethernet

evaluation board which facilitates

testing of the HFBR-5701L. It can

be obtained through the Agilent

Field Organization by referencing

Agilent part number HFBR-0571.

Immunity

Reference Designs

The ESD performance of the

HFBR-5701L exceeds typical

industry standards.

A Reference Design including the

HFBR-5701L and the HDMP-

1687 GigaBit Quad SerDes is

available. It may be obtained

through the Agilent Field Sales

organization.

Equipment hosting HFBR-5701L

modules will be subjected to

radio-frequency electromagnetic

fields in some environments. The

transceiver has good immunity to

such fields due to its shielded

design.

HFBR-5701L in a manner

inconsistent with its design and

function may result in hazardous

radiation exposure and may be

considered an act of modifying or

manufacturing a laser product.

The person(s) performing such

an act is required by law to re-

certify and re-identify the laser

product under the provisions of

U.S. 21 CFR (Subchapter J).

Regulatory Compliance

See Table 1 for transceiver

Regulatory Compliance. Certi-

fication level is dependent on the

overall configuration of the host

equipment. The transceiver

performance is offered as a figure

of merit to assist the designer.

Electromagnetic Interference (EMI)

Equipment incorporating Gigabit

Ethernet transceivers is typically

required to meet the require-

ments of the FCC in the United

States, CENELEC EN55022

(CISPR 22) in Europe, and VCCI

in Japan.

4

1 µH

V

T,R

CC

HOUSING

GROUND

10 µF

0.1 µF

AGILENT

HFBR-5701L

V

T

CC

*RES

TX_DISABLE

*RES

0.1

µF

GP04

TX_FAULT

50 Ω

TD+

VREFR

SO1+

SO1–

C

R

LASER DRIVER

& EYE SAFETY

CIRCUITRY

TX[0:9]

C

50 Ω

TD–

VEET

TBC

SYNC

LOOP

EWRAP

AGILENT

HDMP-1687

V

R

CC

10

µF

0.1

µF

MAC

ASIC

RX[0:9]

RD+

50 Ω

SYN1

SI1+

SI1–

C

RBC

RC1(0:1)

RCM0

R

AMPLIFICATION

&

RX_RATE

RD–

RFCT

QUANTIZATION

REF_RATE

RX_LOS

V

T,R

CC

*RES

RX_LOS

GPIO(X)

GP14

MOD_DEF2

MOD_DEF1

MOD_DEF0

EEPROM

REFCLK

125 MHz

VEER

NOTE: * 4.7 k < RES < 10 kΩ

Figure 4. Typical application configuration.

Table 1. Regulatory Compliance

Feature

Test Method

Performance

Class 2 (> +2000 Volts)

Electrostatic Discharge (ESD) JEDEC/EIA

to the Electrical Pins

JESD22-A114-A

Electrostatic Discharge (ESD) Variation of IEC 6100-4-2

to the Duplex LC Receptacle

Typically withstands at least 25 kV without

damage when the duplex LC connector

receptacle is contacted by a Human Body

Model probe

Electromagnetic Interference

(EMI)

FCC Class B

CENELEC EN55022 Class B

(CISPR 22A) VCCI Class 1

Applications with high SFP port counts are

expected to be compliant; however, margins are

dependent on customer board and chassis design.

Immunity

Variation of IEC 61000-4-3

Typically shows a negligible effect from a

10 V/m field swept from 80 to 1000 MHz applied

to the transceiver without a chassis enclosure.

[1]

Eye Safety

US FDA CDRH AEL Class 1

EN(IEC)60825-1,2, EN60950

Class 1

CDRH certification #9720151-13

TUV file #E9971083.07

Component Recognition

Underwriters Laboratories and

Canadian Standards Associa-

tion Joint Component Recognition

for Information Technology

Equipment Including Electrical

Business Equipment

UL File #E173874

Note:

1. Changes to IEC 60825-1,2 are currently anticipated to allow higher eye-safe Optical Output Power levels. Agilent may choose to take advantage of these

in future revisions to this part.

5

Table 2. Pin Description

Pin Name Function/Description

Engagement Order

(insertion)

Notes

1

2

3

4

5

6

7

8

9

VeeT

Transmitter Ground

1

3

1

3

1

2

1

3

1

TX Fault

Transmitter Fault Indication

1

2

3

TX Disable Transmitter Disable - Module disables on high or open

MOD-DEF2 Module Definition 2 - Two wire serial ID interface

MOD-DEF1 Module Definition 1 - Two wire serial ID interface

MOD-DEF0 Module Definition 0 - Grounded in module

Rate Select Not Connected

LOS

Loss of Signal

4

VeeR

Receiver Ground

10 VeeR

11 VeeR

12 RD-

Receiver Ground

Inverse Received Data Out

Received Data Out

5

13 RD+

14 VeeR

15 VccR

16 VccT

17 VeeT

18 TD+

19 TD-

Receiver Ground

Receiver Power - 3.3 V ±5%

Transmitter Power - 3.3 V ±5%

Transmitter Ground

Transmitter Data In

Inverse Transmitter Data In

Transmitter Ground

6

7

20 VeeT

Notes:

1. TX Fault is an open collector/drain output which should be pulled up externally with a 4.7K – 10 KΩ resistor on the host board to a supply < VccT+0.3 V

or VccR+0.3 V. When high, this output indicates a laser fault of some kind. Low indicates normal operation. In the low state, the output will be pulled to

< 0.8 V.

2. TX disable input is used to shut down the laser output per the state table below. It is pulled up within the module with a 4.7-10 K resistor.

Low (0 – 0.8 V):

Transmitter on

Between (0.8 V and 2.0 V): Undefined

High (2.0 – 3.465 V):

Open:

Transmitter Disabled

3. Mod-Def 0,1,2. These are the module definition pins. They should be pulled up with a 4.7-10 KΩ resistor on the host board to a supply less than

VccT +0.3 V or VccR+0.3 V.

Mod-Def 0 is grounded by the module to indicate that the module is present

Mod-Def 1 is clock line of two wire serial interface for optional serial ID

Mod-Def 2 is data line of two wire serial interface for optional serial ID

4. LOS (Loss of Signal) is an open collector/drain output which should be pulled up externally with a 4.7 K – 10 KΩ resistor on the host board to a supply

< VccT,R+0.3 V. When high, this output indicates the received optical power is below the worst case receiver sensitivity (as defined by the standard in

use). Low indicates normal operatio0n. In the low state, the output will be pulled to < 0.8 V.

5. RD-/+: These are the differential receiver outputs. They are AC coupled 100 Ω differential lines which should be terminated with 100 Ω differential at the

user SERDES. The AC coupling is done inside the module and is thus not required on the host board. The voltage swing on these lines must be between

370 and 2000 mV differential (185 – 1000 mV single ended) according to the MSA. Typically it will be 1500mv differential.

6. VccR and VccT are the receiver and transmitter power supplies. They are defined as 3.135 – 3.465 V at the SFP connector pin. The in-rush current will

typically be no more than 30 mA above steady state supply current after 500 nanoseconds.

7. TD-/+: These are the differential transmitter inputs. They are AC coupled differential lines with 100 Ω differential termination inside the module. The AC

coupling is done inside the module and is thus not required on the host board. The inputs will accept differential swings of 500 – 2400 mV (250 – 1200 mV

single ended). However, the applicable recommended differential voltage swing is found in Table 5.

6

Table 3. Absolute Maximum Ratings

Parameter

Symbol

Minimum

Maximum

Unit

Notes

Ambient Storage Temperature

(Non-Operating)

Ts

–40

+100

°C

1

Case Temperature

T

–40

5

+85

95

°C

%

1

C

Relative Humidity

RH

Supply Voltage

V

–0.5

3.6

V

CCT,R

Voltage at any Input Pin

Sense Output Current – LOS, TX Fault

Sense Output Current – MOD_DEF2

V

CC

V

IH

ID

150

5

mA

Notes:

1. Absolute Maximum Ratings are those values beyond which damage to the device may occur if these limits are exceeded. See Reliability Data Sheet for

specific reliability performance.

2. Between Absolute Maximum Ratings and the Recommended Operating Conditions functional performance is not intended, device reliability is not

implied, and damage to the device may occur.

Table 4. Recommended Operating Conditions

Parameter

Symbol

Minimum

Typical

25

Maximum

70

Unit

°C

Notes

1, 2

1

Case Temperature

Supply Voltage

Data Rate

T

0

C

V

CC

3.135

3.3

3.465

V

1.25

Gb/s

1, 3

1, 4

Data Rate

1.0625

Notes:

1. Recommended Operating Conditions are those within which functional performance within data sheet characteristics is intended.

2. Refer to the Reliability Data Sheet for specific reliability performance predictions.

3. IEEE802.3 Gigabit Ethernet.

4. ANSIX3.230 (FC-PI).

7

Table 5. Transceiver Electrical Characteristics (T = 0°C to 70°C, V

= 3.3 V ±5%)

C

CCT,R

Parameter

Symbol

Minimum

Typical

160

Maximum

220

Unit

mA

Notes

Module Supply Current

Power Dissipation

I

CC

P

DISS

530

765

mW

Power Supply Noise

Rejection (peak-peak)

PSNR

100

mV

1

2

3

PP

Data Input:

Transmitter Differential

Input Voltage (TD +/–)

V

I

500

370

1660

2000

mV

Data Output:

Receiver Differential

Output Voltage (RD +/–)

V

O

1500

220

mV

ps

Receive Data Rise & Fall

Times

T

rf

Sense Outputs:

Transmit Fault

[TX_FAULT,

Loss of Signal (LOS),

MOD_DEF2]

V

2.0

0

V

OH

CC

V

OL

0.8

Control Inputs:

Transmitter Disable

[TX_DISABLE,

MOD_DEF1,2]

V

2.0

0

V

IH

CC

0.8

IL

Notes:

1. Measured at the input of therequired MSA Filter on host board.

2. Internally AC coupled and terminated to 100 Ohm differential load.

3. Internally AC coupled, but requires a 100 Ohm differential termination at or internal to Serializer/Deserializer.

8

Table 6. Transmitter Optical Characteristic(sT = 0°C to 70°C, V

= 3.3 V± 5%)

C

CCT,R

Parameter

Symbol

Minimum

Typical

Maximum

Unit

Notes

Output Optical Power (Average)

Optical Extinction Ratio

Pout

ER

–9.5

–6.5

14.5

850

0

dBm

dB

1, 2, 3

1

9

Center Wavelength

λ

830

860

nm

1

C

Spectral Width – rms

σ

0.85

260

nm

Optical Rise/Fall Time (1.25 GBd)

Optical Rise/Fall Time (1.0625 GBd)

Relative Intensity Noise, maximum

T

150

ps

rise/fall

300

ps

1,4

1

RIN

TJ

–117

dB/Hz

Total Jitter

(TP1 to TP2 Contribution 1.25 GBd)

227

ps

UI

ps

UI

1

4

0.284

252

(TP1 to TP2 Contribution 1.0625 GBd)

0.267

Deterministic Jitter

(TP1 to TP2 Contribution 1.0625 GBd)

DJ

85

ps

4

1

4

0.09

–35

UI

Pout TX_DISABLE Asserted

Optical Modulation Amplitude

P

OFF

dBm

µW

OMA

156

Notes:

1. IEEE 802.3.

2. Max. Pout is the lesser of 0 dBm or Maximum allowable per Eye Safety Standard.

3. 50/125 µm fiber with NA = 0.2, 62.5/125 µm fiber with NA = 0.275.

4. ANSIX3.230 (FC-PI).

NORMALIZED TIME (UNIT INTERVAL)

0

0.22 0.375

0.625 0.78

1.0

1.30

130

100

80

1.00

0.80

50

0.50

20

0

0.20

0

–20

–0.20

0

22 37.5

62.5 78

100

NORMALIZED TIME (% OF UNIT INTERVAL)

Figure 5a. Gigabit Ethernet transmitter eye mask diagram.

Figure 5b. Typical HFBR-5701L eye mask diagram.

9

Table 7. Receiver Optical Characteristics (T = 0°C to 70°C, V

= 3.3 V ± 5%)

C

CCT,R

Parameter

Symbol

PR

Minimum

Typical

Maximum

Unit

dBm

Notes

Optical Input Power

–17

0

1

Receiver Sensitivity

(Optical Input Power)

PRMIN

–21

–17

Stressed Receiver Sensitivity

1.25 GBd (GBE)

–12.5

–13.5

–11.74

–12.59

266

dBm

ps

1, 2

1, 3

2, 4

3, 4

1

Stressed Receiver Sensitivity

1.0625 GBd (FC-PI)

Total Jitter

TJ

DJ

(TP3 to TP4 Contribution 1.25 GBd)

Total Jitter

0.332

205

UI

1

ps

4

(TP3 to TP4 Contribution 1.0625 GBd)

Deterministic Jitter

0.218

113

UI

4

ps

4

(TP3 to TP4 Contribution 1.0625 GBd)

Return Loss

0.12

UI

4

–12

dB

1

LOS De-Asserted

P

–17

dBm

dB

1

D

LOS Asserted

P

A

–31

31

1

LOS Hysterisis

P - P

D

3

1

A

Optical Modulation Amplitude

OMA

µW

4

Notes:

1. IEEE 802.3.

2. 62.5/125 µm fiber.

3. 50/125 µm fiber.

4. ANSIX3.230 (FC-PI).

Table 8. Transceiver Timing Characteristics (T = 0°C to 70°C, V

= 3.3 V ±5%)

C

CCT,R

Parameter

Symbol

t_off

Minimum

Typical

Maximum

Unit

Notes

Tx Disable Assert Time

Tx Disable Negate Time

10

1

µs

1

2

3

t_on

ms

Time to initialize, including

reset of Tx_Fault

t_init

300

Tx Fault Assert Time

Tx Disable to Reset

LOS Assert Time

t_fault

100

µs

kHz

4

5

6

7

t_reset

10

t_loss_on

t_loss_off

f_serial_clock

100

LOS Deassert Time

Serial ID Clock Rate

Notes:

1. Time from rising edge of Tx Disable to when the optical output falls below 10% of nominal.

2. Time from falling edge of Tx Disable to when the modulated optical output rises above 90% of nominal.

3. From power on or negation of Tx Fault using Tx Disable.

4. Time from fault to Tx fault on.

5. Time Tx Disable must be held high to reset Tx_fault.

6. Time from LOS state to Rx LOS assert.

7. Time from non-LOS state to RX LOS deassert.

10

V

> 3.15 V

V

> 3.15 V

CC

TX_FAULT

TX_DISABLE

TRANSMITTED SIGNAL

t_init

t-init: TX DISABLE NEGATED

t-init: TX DISABLE ASSERTED

V

> 3.15 V

TX_FAULT

TX_DISABLE

CC

TX_FAULT

TX_DISABLE

TRANSMITTED SIGNAL

t_off

t_on

t_init

INSERTION

t-init: TX DISABLE NEGATED, MODULE HOT PLUGGED

t-off & t-on: TX DISABLE ASSERTED THEN NEGATED

OCCURANCE OF FAULT

TX_FAULT

TX_DISABLE

TRANSMITTED SIGNAL

t_reset

TRANSMITTED SIGNAL

t_fault

* SFP SHALL CLEAR TX_FAULT IN

t_init IF THE FAILURE IS TRANSIENT

t_init*

t-fault: TX FAULT ASSERTED, TX SIGNAL NOT RECOVERED

t-reset: TX DISABLE ASSERTED THEN NEGATED, TX SIGNAL RECOVERED

OCCURANCE OF FAULT

OPTICAL SIGNAL

TX_FAULT

TX_DISABLE

OCCURANCE OF LOSS

LOS

TRANSMITTED SIGNAL

t_fault2

t_reset

t_loss_on

t_loss_off

* SFP SHALL CLEAR Tx_FAULT IN

t_init*

t_init IF THE FAILURE IS TRANSIENT

t-fault2: TX DISABLE ASSERTED THEN NEGATED,

TX SIGNAL NOT RECOVERED

t-loss-on & t-loss-off

NOTE: t_fault2 timing is typically 1.7 to 2 ms.

Figure 6. Transceiver timing diagrams (Module installed except where noted).

11

Table 9. EEPROM Serial ID Memory Contents

Address

0

Hex

03

04

07

00

01

20

40

0C

00

01

0C

00

37

1B

00

41

47

49

4C

45

4E

54

20

ASCII

Address

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Hex

20

00

30

D3

48

46

42

52

2D

35

37

30

31

4C

20

00

Note 3

ASCII

Address

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

Hex ASCII Address

Hex

ASCII

00

96

Note 4

1

1A

97

2

00

98

3

00

99

4

Note 1

Note 2

00

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

5

6

7

8

H

F

B

R

-

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

5

7

0

1

L

A

G

I

L

E

N

T

00

Note 3

Notes:

1. These addresses are reserved for serial number information and will vary from module to module.

2. These addresses are reserved for date code information and may vary from lot to lot.

3. Byte Addresses 63 and 95 are Check Sums which may vary from module to module.

4. These fields are reserved for future use by Agilent Technologies.

12

AGILENT HFBR-5701L

850 nm LASER PROD

21CFR(J) CLASS 1

COUNTRY OF ORIGIN YYWW

TX

RX

TUV

UL

XXXXXX

13.40 ± 0.1

(0.53 ± 0.004)

13.75 ± 0.1

(0.54 ± 0.004)

56.40 ± 0.2

(2.22 ± 0.01)

SEE DETAIL 1

TCASE REFERENCE POINT

AREA

FOR

13.0 ± 0.1

PROCESS

PLUG

(0.51 ± 0.004)

14.8

(0.58)

MAX. UNCOMPRESSED

14.20 ± 0.1

(0.56 ± 0.004)

DETAIL 1

SCALE 2x

FRONT EDGE OF SFP

TRANSCEIVER CAGE

6.25 ± 0.05

(0.25 ± 0.002)

0.7

(0.03)

MAX. UNCOMPRESSED

8.50 ± 0.1

(0.33 ± 0.004)

11.80 ± 0.2

(0.46 ± 0.008)

TX

RX

DIMENSIONS ARE IN MILLIMETERS (INCHES)

Figure 7. Module drawing.

13

X

Y

34.5

3x 10

7.2

2.5

7.1

10x 1.05 ± 0.01

0.1 S X A S

0.85 ± 0.05

0.1 S X Y

16.25

MIN. PITCH

B

1

2.5

A

1

PCB

EDGE

3.68

5.68

20

PIN 1

8.58

11.08

14.25

8.48

2x 1.7

11.93

16.25

REF.

9.6

4.8

11

10

SEE DETAIL 1

9x 0.95 ± 0.05

11x 2.0

3

0.1 L X A S

11x 2.0

5

26.8

2

3x 10

41.3

42.3

5

20x 0.5 ± 0.03

0.06 S A S B S

3.2

0.9

NOTES:

1. PADS AND VIAS ARE CHASSIS GROUND.

2. THROUGH HOLES, PLATING OPTIONAL.

20

11

PIN 1

10.53

10.93

11.93

9.6

0.8

TYP.

3. HATCHED AREA DENOTES COMPONENT AND

TRACE KEEPOUT (EXCEPT CHASSIS GROUND).

10

4. AREA DENOTES COMPONENT KEEPOUT

(TRACES ALLOWED).

4

2 ± 0.05 TYP.

0.06 L A S B S

2x 1.55 ± 0.05

0.1 L A S B S

DIMENSIONS IN MILLIMETERS

DETAIL 1

Figure 8. SFP host board mechanical layout.

14

1.7 ± 0.9

(0.07 ± 0.04)

3.5 ± 0.3

(0.14 ± 0.01)

41.73 ± 0.5

(1.64 ± 0.02)

PCB

BEZEL

AREA

FOR

PROCESS

PLUG

15

(0.59)

MAX.

CAGE ASSEMBLY

15.25 ± 0.1

(0.60 ± 0.004)

11

(0.43)

REF.

10.4 ± 0.1

(0.41 ± 0.004)

9.8

MAX.

(0.39)

10

(0.39)

TO PCB

REF

1.5

REF.

(0.06)

BELOW PCB

16.25 ± 0.1

(0.64 ± 0.004)

MIN. PITCH

0.4 ± 0.1

(0.02 ± 0.004)

BELOW PCB

MSA-SPECIFIED BEZEL

DIMENSIONS ARE IN MILLIMETERS (INCHES).

Figure 9. Assembly drawing.

15

www.agilent.com/semiconductors

For product information and a complete list of

distributors, please go to our web site.

For technical assistance call:

Americas/Canada: +1 (800) 235-0312 or

(408) 654-8675

Europe: +49 (0) 6441 92460

China: 10800 650 0017

Hong Kong: (+65) 6271 2451

India, Australia, New Zealand: (+65) 6271 2394

Japan: (+81 3) 3335-8152(Domestic/Interna-

tional), or 0120-61-1280(Domestic Only)

Korea: (+65) 6271 2194

Malaysia, Singapore: (+65) 6271 2054

Taiwan: (+65) 6271 2654

Data subject to change.

Obsoletes 5988-2954EN

July 16, 2002

5988-7281EN


型号：	HFBR-5701LP
厂家：	ETC
描述：	1.25/1.0625 GBd MMF Pluggable (SFP) Transceiver for GbE and Fibre Channel: Bail-wire delatch 1.25 / 1.0625 GBd的MMF可插拔（SFP）收发器千兆以太网和光纤通道：保释线锁上\n 光纤以太网
文件：	总16页 (文件大小：252K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HFBR-5701LP [ETC]

相关型号：

HFBR-5710L

HFBR-5710LP

HFBR-5720AL

HFBR-5720ALP

HFBR-5720L

HFBR-5720L

HFBR-5720LP

HFBR-5720LP

HFBR-5730L

HFBR-5730LP

HFBR-5760AL

HFBR-5760ALP