HFBR-5720AL_技术文档

Agilent HFBR-5720AL/5720ALP

Fibre Channel 2.125/1.0625 GBd 850 nm

Small Form Pluggable Low Voltage (3.3 V)

Extended Temperature and Extended

Operating Voltage (V ±10%, Temperature

CC

–20 to 85°C) Optical Transceiver

Data Sheet

Features

• 2.97 V to 3.63 V operating voltage range

• –20°C to +85°C operating temperature range

• Compliant with 2.125 GBd Fibre

Channel FC-PI standard

• FC-PI 200-M5-SN-I for 50/125 µm

multimode cables

• FC-PI 200-M6-SN-I for 62.5/125 µm

multimode cables

Applications

• Compliant with 1.0625 GBd VCSEL

operation for both 50/125 and 62.5/125 µm

multimode cables

• Industry standard Small Form Pluggable

(SFP) package

Description

The HFBR-5720AL/ALP optical

transceiver from Agilent

Technologies offers maximum

flexibility to Fibre Channel

• Mass storage system I/O

• Computer system I/O

• High speed peripheral interface

• High speed switching systems

• Host adapter I/O

• LC-Duplex connector optical interface

designers, manufacturers, and

system integrators to implement a

range of solutions for multimode

Fibre Channel applications. In order

to provide a wide range of system

level performance, without the need

for a data rate select input, this

product is fully compliant with all

equipment meeting the Fibre

Channel FC-PI 200-M5-SN-I and

200-M6-SN-I 2.125 GBd

specifications, and is compatible

with the Fibre Channel FC-PI 100-

M5-SN-I and FC-PI 100-M6-SN-I,

FC-PH2 100-M5-SN-I, and the

FC-PH2 100-M6-SN-I 1.0625 GBd

specifications.

• Link lengths at 2.125 GBd:

0.5 to 300 m – 50/125 µm MMF

0.5 to 150 m – 62.5/125 µm MMF

• Link lengths at 1.0625 GBd:

0.5 to 500 m – 50/125 µm MMF

0.5 to 300 m – 62.5/125 µm MMF

• Reliable 850 nm Vertical Cavity Surface

Emitting Laser (VCSEL) source technology

• Laser AEL Class 1 (eye safe) per:

US 21 CFR (J)

EN-60825-1 (+A11+A2)

• RAID cabinets

Related Products

• HFBR-5602: 850 nm 5 V Gigabit Inter-

face Converter (GBIC) for Fibre

Channel FC-PH-2

• HFBR-53D3: 850 nm 5 V 1 x 9 laser

transceiver for Fibre Channel FC-PH-2

• HFBR-5910E: 850 nm 3.3 V SFF laser

transceiver for Fibre Channel FC-PH-2

• HDMP-2630/2631: 2.125/1.0625 Gbps

TRx family of SerDes IC

• Single 3.3 V power supply operation

• De-latch options:

– HFBR-5720AL standard de-latch

– HFBR-5720ALP bail-wire pull de-latch

Module Package

Installation

Ground, (2) Power, and then (3)

Signal pins, making contact with

the host board surface mount

connector in that order. This

printed circuit board card-edge

connector is depicted in Figure 2.

The transceiver meets the Small

Form Pluggable (SFP) industry

standard package utilizing an

integral LC-Duplex optical

interface connector. The hot-

pluggable capability of the SFP

package allows the module to be

installed at any time – even with

the host system operating and on-

line. This allows for system

configuration changes or

maintenance without system

down time. The HFBR-5720AL/

ALP uses a reliable 850 nm

VCSEL source and requires a 3.3

V DC power supply for optimal

design.

The HFBR-5720AL/ALP can be

installed in or removed from any

MultiSource Agreement (MSA)-

compliant Small Form Pluggable

port regardless of whether the

host equipment is operating or

not. The module is simply

inserted, electrical interface first,

under finger pressure. Controlled

hot-plugging is ensured by design

and by 3-stage pin sequencing at

the electrical interface. The

module housing makes initial

contact with the host board EMI

shield mitigating potential

Serial Identification (EEPROM)

The HFBR-5720AL/ALP complies

with an industry standard MSA

that defines the serial

identification protocol. This

protocol uses the 2-wire serial

CMOS E2PROM protocol of the

ATMEL AT24C01A or equivalent.

The contents of the HFBR-

5720AL/ALP serial ID memory

are defined in Table 10 as

damage due to Electro-Static

Discharge (ESD). The 3-stage pin

contact sequencing involves (1)

specified in the SFP MSA.

Module Diagrams

Figure 1 illustrates the major

functional components of the

HFBR-5720AL/ALP. The

connection diagram of the

module is shown in Figure 2.

Figure 7 depicts the external

configuration and dimensions of

the module.

HFBR-5720AL BLOCK DIAGRAM

RECEIVER

ELECTRICAL INTERFACE

RD+ (RECEIVE DATA)

RD– (RECEIVE DATA)

LOSS OF SIGNAL

AMPLIFICATION

& QUANTIZATION

LIGHT FROM FIBER

OPTICAL INTERFACE

LIGHT TO FIBER

PHOTO-DETECTOR

TRANSMITTER

VCSEL

Tx_DISABLE

LASER

DRIVER &

SAFETY

TD+ (TRANSMIT DATA)

TD– (TRANSMIT DATA)

Tx_FAULT

CIRCUITRY

MOD-DEF2

MOD-DEF1

MOD-DEF0

EEPROM

Figure 1. Transceiver functional diagram.

2

20

19

18

17

16

15

14

13

12

11

V

T

1

2

V

T

EE

TD–

TD+

TxFAULT

3

Tx DISABLE

MOD-DEF(2)

MOD-DEF(1)

MOD-DEF(0)

RATE SELECT

LOS

V

4

EE

CC

T

5

R

6

R

7

EE

RD+

RD–

8

9

V

R

EE

V

R

10

V

EE

TOP OF BOARD

BOTTOM OF BOARD

(AS VIEWED THROUGH TOP OF BOARD)

Figure 2. Connection diagram of module printed circuit board.

Transmitter Section

The transmitter section includes

the transmitter optical

the module as depicted in

Figure 6. The Tx Disable control

should be actuated upon

Receiver Section

The receiver section includes the

receiver optical subassembly

(ROSA) and amplification/

quantization circuitry. The ROSA,

containing a PIN photodiode and

custom transimpedance

preamplifier, is located at the

optical interface and mates with

the LC optical connector. The

ROSA is mated to a custom IC

that provides post-amplification

and quantization. This circuit also

includes a loss of signal (LOS)

detection circuit which provides

an open collector logic high

output in the absence of a usable

input optical signal level.

subassembly (TOSA) and laser

driver circuitry. The TOSA,

containing an 850 nm VCSEL

(Vertical Cavity Surface Emitting

Laser) light source, is located at

the optical interface and mates

with the LC optical connector.

The TOSA is driven by a custom

silicon IC, which converts

differential logic signals into an

analog laser diode drive current.

This Tx driver circuit regulates

the optical power at a constant

level provided the data pattern is

valid 8B/10B balanced code.

initialization of the module.

Tx Fault

The HFBR-5720AL/ALP module

features a transmit fault control

signal output which when high

indicates a laser transmit fault

has occurred and when low

indicates normal laser operation.

A transmitter fault condition can

be caused by deviations from the

recommended module operating

conditions or by violation of eye

safety conditions. A fault is

cleared by cycling the Tx Disable

control input.

Tx Disable

Loss of Signal

The HFBR-5720AL/ALP accepts a

transmit disable control signal

input which shuts down the

transmitter. A high signal

implements this function while a

low signal allows normal laser

operation. In the event of a fault

(e.g., eye safety circuit activated),

cycling this control signal resets

Eye Safety Circuit

The Loss of Signal (LOS) output

indicates that the optical input

signal to the receiver does not

meet the minimum detectable

level for Fibre Channel compliant

signals. When LOS is high it

indicates loss of signal. When

LOS is low it indicates normal

operation. The Loss of Signal

For an optical transmitter device

to be eye-safe in the event of a

single fault failure, the

transmitter will either maintain

normal eye-safe operation or be

disabled. In the event of an eye

safety fault, the VCSEL will be

disabled.

3

thresholds are set to indicate a

definite optical fault has occurred

(e.g., disconnected or broken

fiber connection to receiver,

failed transmitter).

Application Support

Evaluation Kit

Electrostatic Discharge (ESD)

There are two conditions in which

immunity to ESD damage is

important. Table 1 documents

our immunity to both of these

conditions. The first condition is

during handling of the transceiver

prior to insertion into the

transceiver port. To protect the

transceiver, it is important to use

normal ESD handling

precautions. These precautions

include using grounded wrist

straps, work benches, and floor

mats in ESD controlled areas.

The ESD sensitivity of the HFBR-

5720AL/ALP is compatible with

typical industry production

environments. The second

condition is static discharges to

the exterior of the host

To help you in your preliminary

transceiver evaluation, Agilent

offers a 2.125 GBd Fibre Channel

evaluation board. This board will

allow testing of the fiber-optic

VCSEL transceiver. Please

contact your local field sales

representative for availability and

ordering details.

Functional Data I/O

Agilent’s HFBR-5720AL/ALP

fiber-optic transceiver is designed

to accept industry standard

differential signals. In order to

reduce the number of passive

components required on the

customer’s board, Agilent has

included the functionality of the

transmitter bias resistors and

coupling capacitors within the

fiber optic module. The

transceiver is compatible with an

“AC-coupled” configuration and is

internally terminated. Figure 1

depicts the functional diagram of

the HFBR-5720AL/ALP.

Reference Designs

Reference designs for the HFBR-

5720AL/ALP fiber-optic

transceiver and the HDMP-2630/

2631 physical layer IC are

available to assist the equipment

designer. Figure 4 depicts a

typical application configuration,

while Figure 5 depicts the MSA

power supply filter circuit design.

All artwork is available at the

Agilent Website. Please contact

your local field sales engineer for

more information regarding

application tools.

equipment chassis after

installation. To the extent that the

duplex LC optical interface is

exposed to the outside of the host

equipment chassis, it may be

subject to system-level ESD

requirements. The ESD

performance of the HFBR-

5720AL/ALP exceeds typical

industry standards.

Caution should be taken for the

proper interconnection between

the supporting Physical Layer

integrated circuits and the HFBR-

5720AL/ALP. Figure 4 illustrates

the recommended interface

circuit.

Regulatory Compliance

See Table 1 for transceiver

Regulatory Compliance

performance. The overall

equipment design will determine

the certification level. The

transceiver performance is

offered as a figure of merit to

assist the designer.

Several MSA compliant control

data signals are implemented in

the module and are depicted in

Figure 6.

1.3

1.0

0.8

0.5

0.2

0

–0.2

0

x1

0.4

0.6 1-x1 1.0

NORMALIZED TIME

Figure 3. Transmitter eye mask diagram and typical transmitter eye.

4

Immunity

Flammability

Ordering Information

Equipment hosting the HFBR-

5720AL/ALP modules will be

subjected to radio-frequency

electro-magnetic fields in some

environments. These transceivers

have good immunity to such

fields due to their shielded

design.

The HFBR-5720AL/ALP VCSEL

transceiver housing is made of

metal and high strength, heat

resistant, chemically resistant,

and UL 94V-0 flame retardant

plastic.

Please contact your local field

sales engineer or one of the

Agilent Technologies franchised

distributors for ordering

information. For additional

technical information associated

with this product, including the

MSA, please visit Agilent

Technologies Semiconductor

Products Website at

www.agilent.com/view/fiber

Use the Quick Search feature to

search for this part number.

Agilent Technologies

Semiconductor Products

Customer Response Center is

also available to assist you at

1-800-235-0312.

Caution

There are no user serviceable

parts nor any maintenance

required for the HFBR-5720AL/

ALP. Tampering with or

modifying the performance of the

HFBR-5720AL/ALP will result in

voided product warranty. It may

also result in improper operation

of the HFBR-5720AL/ALP

circuitry, and possible overstress

of the laser source. Device

degradation or product failure

may result. Connection of the

HFBR-5720AL/ALP to a non-

approved optical source,

operating above the recommend-

ed absolute maximum conditions

or operating the HFBR-5720AL/

ALP in a manner inconsistent

with its design and function may

result in hazardous radiation

exposure and may be considered

an act of modifying or

Electromagnetic Interference (EMI)

Most equipment designs utilizing

these high-speed transceivers

from Agilent Technologies will be

required to meet the

requirements of FCC in the

United States, CENELEC

EN55022 (CISPR 22) in Europe

and VCCI in Japan.

The metal housing and shielded

design of the HFBR-5720AL/ALP

minimize the EMI challenge

facing the host equipment

designer. These transceivers

provide superior EMI

performance. This greatly assists

the designer in the management

of the overall system EMI

perfornmance.

Eye Safety

These 850 nm VCSEL-based

transceivers provide Class 1 eye

safety by design. Agilent

Technologies has tested the

transceiver design for compliance

with the requirements listed in

Table 1 under normal operating

conditions and under a single

fault condition.

manufacturing a laser product.

The person(s) performing such

an act is required by law to re-

certify and re-identify the laser

product under the provisions of

U.S. 21 CFR (Subchapter J) and

the TUV.

5

Table 1. Regulatory Compliance

Feature

Test Method

Performance

Electrostatic Discharge (ESD)

to the Electrical Pins

MIL-STD-883C Method 3015.4

Class 2 (>2000 Volts)

Electrostatic Discharge (ESD)

to the Duplex LC Receptacle

Variation of IEC 61000-4-2

Typically withstand at least 25 kV without

damage when the duplex LC connector

receptacle is contacted by a Human Body

Model probe.

Electromagnetic Interference

(EMI)

FCC Class B

CENELEC EN55022 Class B

(CISPR 22A)

System margins are dependent on customer

board and chassis design.

VCCI Class 1

Immunity

Variation of IEC 61000-4-3

Typically shows a negligible effect from a

10 V/m field swept from 80 to 1000 MHz

applied to the transceiver without a chassis

enclosure.

Eye Safety

US FDA CDRH AEL Class 1

CDRH File # 9720151-16 (HFBR-5720AL)

CDRH File # Pending (HFBR-5720ALP)

EN 60950 Class 1

EN (IEC) 60825-1:1994+A11+A2

EN (IEC) 60825-2:1994+A1

TUV File # E2171216.01 (HFBR-5720AL)

Note 1

TUV File # Pending

(HFBR-5720ALP)

Component Recognition

Underwriters Laboratories and

UL file # E173874

Canadian Standards Association

Joint Component Recognition for

Information Technology Equipment

Including Electrical Business Equipment

Note:

1. Units manufactured prior to August 1, 2001 were certified to the previous TUV standard EN60825-1:1994+A11.

6

1 µH

3.3 V

10 µF

0.1 µF

3.3 V

V

,T

CC

HFBR-5720AL/ALP

0.1 µF

4.7 K to 10 K

Tx_DISABLE

Tx_FAULT

GP04

Tx_FAULT

0.01 µF

TD+

50 Ω

VREFR

SO+

SO–

LASER DRIVER

& SAFETY

100

TX[0:9]

TD–

CIRCUITRY

TX GND

TBC

0.01 µF

EWRAP

V

,R

CC

4.7 K to 10 K

HDMP-2630/31

0.1

µF

PROTOCOL

IC

10 µF

RX[0:9]

0.01 µF

RD+

50 Ω

SI+

SI–

RBC

100

AMPLIFICATION

&

Rx_RATE

RD–

REFCLK

QUANTIZATION

0.01 µF

Rx_LOS

RX GND

Rx_LOS

MOD_DEF2

MOD_DEF1

MOD_DEF0

GPIO(X)

GP14

EEPROM

REFCLK

4.7 K to 4.7 K to

4.7 K to

10 K

106.25 MHz

3.3 V

Figure 4. Recommended application configuration.

1 µH

V

T

CC

0.1 µF

1 µH

3.3 V

V

R

CC

10 µF

0.1 µF

10 µF

SFP MODULE

HOST BOARD

NOTE: INDUCTORS MUST HAVE LESS THAN 1 Ω SERIES RESISTANCE PER MSA.

Figure 5. MSA required power supply filter.

7

Table 2. Pin Description

1

Name

Function/Description

MSA Notes

V T

ee

Transmitter Ground

2

Tx Fault

Transmitter Fault Indication – High Indicates a Fault

Transmitter Disable – Module Disables on High or Open

Module Definition 2 – Two Wire Serial ID Interface

Module Definition 1 – Two Wire Serial ID Interface

Module Definition 0 – Grounded in Module

Not Connected

Note 1

Note 2

Note 3

3

Tx Disable

MOD-DEF2

MOD-DEF1

MOD-DEF0

Rate Select

LOS

4

5

6

7

8

Loss of Signal – High Indicates Loss of Signal

Receiver Ground

Note 4

9

V

ee

V

ee

V

ee

R

10

11

12

13

14

15

16

17

18

19

20

Notes:

Receiver Ground

RD–

RD+

Inverse Received Data Out

Received Data Out

Note 5

V

R

Receiver Ground

ee

CC

R

T

Receiver Power – 3.3 V +/– 10%

Transmitter Power – 3.3 V +/– 10%

Transmitter Ground

Note 6

T

ee

TD+

TD–

Transmitter Data In

Note 7

Inverse Transmitter Data In

Transmitter Ground

V T

ee

1. Tx Fault is an open collector/drain output which should be pulled up externally with a 4.7 K – 10 KΩ resistor on the host board to a supply

< V T+0.3 V or V R+0.3 V. When high, this output indicates a laser fault of some kind. Low indicates normal operation. In the low state, the

CC

output will be pulled to < 0.8 V.

2. Tx disable input is used to shut down the laser output per the state table below. It is pulled up within the module with a 4.7 K – 10 KΩ resistor.

Low (0 – 0.8 V):

Between (0.8 V and 2.0 V):

High (2.0 – 3.63 V):

Open:

Transmitter On

Undefined

Transmitter Disabled

3. Mod-Def 0,1,2. are the module definition pins. They should be pulled up with a 4.7 K – 10 KΩ resistor on the host board to a supply less than

V

T+0.3 V or V R+0.3 V.

CC

Mod-Def 0 is grounded by the module to indicate that the module is present

Mod-Def 1 is clock line of two wire serial interface for optional serial ID

Mod-Def 2 is data line of two wire serial interface for optional serial ID

4. LOS (Loss of Signal) is an open collector/drain output which should be pulled up externally with a 4.7 K – 10 KΩ resistor on the host board to a

supply < V T, R+0.3 V. When high, this output indicates the received optical power is below the worst case receiver sensitivity (as defined by

CC

the standard in use). Low indicates normal operation. In the low state, the output will be pulled to < 0.8 V.

5. RD–/+: These are the differential receiver outputs. They are AC coupled 100 Ω differential lines which should be terminated with 100 Ω

differential at the user SERDES. The AC coupling is done inside the module and is thus not required on the host board. The voltage swing on

these lines will be between 400 and 2000 mV differential (200 – 1000 mV single ended) when properly terminated.

6. V R and V T are the receiver and transmitter power supplies. They are defined as 2.97 – 3.63 V at the SFP connector pin. The maximum supply

CC

current is 200 mA and the associated in-rush current will typically be no more than 30 mA above steady state after 500 nanoseconds.

7. TD–/+: These are the differential transmitter inputs. They are AC coupled differential lines with 100 Ω differential termination inside the module.

The AC coupling is done inside the module and is thus not required on the host board. The inputs will accept differential swings of 400 – 2400 mV

(200 – 1200 mV single ended), though it is recommended that values between 500 and 1200 mV differential (250 – 600 mV single ended) be used

for best EMI performance. These levels are compatible with CML and LVPECL voltage swings.

8

Table 3. Absolute Maximum Ratings

Parameter

Symbol

Minimum

–40

Typical

Maximum

Unit

°C

%

Notes

Storage Temperature

Case Temperature

Relative Humidity

Module Supply Voltage

Data/Control Input Voltage

Sense Output Current – LOS, Tx Fault

MOD-DEF 2

T

100

85

Note 1

Note 1, 2

Note 1

S

C

–40

RH

5

95

V

T,R

–0.5

4.0

V

CC

V

CC

+0.3

V

I

150

5.0

mA

D

Notes:

1. Absolute Maximum Ratings are those values beyond which damage to the device may occur if these limits are exceeded for other than a short

period of time. See Reliability Data Sheet for specific reliability performance.

2. Between Absolute Maximum Ratings and the Recommended Operating Conditions functional performance is not intended, device reliability is

not implied, and damage to the device may occur over an extended period of time.

Table 4. Recommended Operating Conditions

Parameter

Symbol

Minimum

–20

Typical

Maximum

85

Unit

°C

Notes

Note 1

Case Temperature

Module Supply Voltage

Data Rate

T

C

V

CC

T,R

2.97

3.3

3.63

V

1.0625

2.125

Gb/s

Note:

1. Recommended Operating Conditions are those values outside of which functional performance is not intended, device reliability is not implied,

and damage to the device may occur over an extended period of time. See Reliability Data Sheet for specific reliability performance.

Table 5. Transceiver Electrical Characteristics (T = –20°C to 85°C, V T,R = 3.3 V ± 10%)

C

CC

Parameter

Symbol

Minimum

Typical

Maximum

Unit

Notes

AC Electrical Characteristics

Power Supply Noise

PSNR

100

mV

Note 1

Rejection (peak-to-peak)

DC Electrical Characteristics

Module Supply Current

Power Dissipation

I

150

495

200

726

mA

CC

P

mW

DISS

Sense Outputs:

Transmit Fault

(TX_FAULT),

Loss of Signal (LOS),

MOD-DEF 2

V

2.0

V

T, R+0.3

T,R

V

Note 2

Note 3

OH

CC

0.8

OL

Control Inputs:

Transmitter Disable

(TX_DISABLE)

MOD-DEF 1,2

V

2.0

0

V

CC

V

IH

0.8

IL

Notes:

1. MSA filter is required on host board 10 Hz to 2 MHz.

2. LVTTL, external 4.7 – 10 KΩ pull-up resistor required.

3. LVTTL, external 4.7 – 10 KΩ resistor required for MOD-DEF 1 and MOD-DEF 2.

9

Table 6. Transmitter and Receiver Electrical Characteristics (T = –20°C to 85°C, V T,R = 3.3 V ± 10%)

C

CC

Parameter

Symbol

Minimum

Typical

Maximum

Unit

Notes

Data Input:

Transmitter Differential

Input Voltage (TD +/–)

V

400

2400

2000

mV

Note 1

1

Data Output:

Receiver Differential

V

O

400

700

mV

Note 2

Output Voltage (RD +/–)

Contributed Deterministic

Jitter (Receiver) 2.125 Gb/s

DJ

RJ

Trf

0.1

47

UI

ps

Note 3, 6

Note 4, 6

Note 5

Contributed Deterministic

Jitter (Receiver) 1.0625 Gb/s

0.12

113

UI

ps

Contributed Random

Jitter (Receiver) 2.125 Gb/s

0.162

76

UI

ps

Contributed Random

Jitter (Receiver) 1.0625 Gb/s

0.098

92

UI

ps

Receive Data Rise and

Fall Times (Receiver)

250

ps

Notes:

1. Internally AC coupled and terminated (100 Ohm differential). These levels are compatible with CML and LVPECL voltage swings.

2. Internally AC coupled with an external 100 Ohm differential load termination.

3. Contributed DJ is measured on an oscilloscope in average mode with 50% threshold and K28.5 pattern.

–12

4. Contributed RJ is calculated for 1 x 10 BER by multiplying the RMS jitter (measured on a single rise or fall edge) from the oscilloscope by 14.

Per the FC-PI standard (Table 13 – MM Jitter Output, note 1), the actual contributed RJ is allowed to increase above its limit if the actual

contributed DJ decreases below its limits, as long as the component output DJ and TJ remain within their specified FC-PI maximum limits with

the worst case specified component jitter input.

5. 20%–80% Rise and Fall times measured with a 500 MHz signal utilizing a 1010 data pattern.

6. In a network link, each component‘s output jitter equals each component‘s input jitter combined with each component‘s contributed jitter.

Contributed DJ adds in a linear fashion and contributed RJ adds in a RMS fashion. In the Fibre Channel FC-PI Rev 11 specification ”6.3.3 MM

Jitter Budget“ section, there is a table specifying the input and output DJ and TJ for the receiver at each data rate. In that table, RJ is found from

TJ - DJ where the Rx input jitter is noted as Gamma R and the Rx output jitter is noted as Delta R. Our component contributed jitter is such that, if

the maximum specified input jitter is present, and is combined with our maximum contributed jitter, then we meet the specified maximum output

jitter in the FC-PI MM jitter specification table.

10

Table 7. Transmitter Optical Characteristics (T = –20°C to 85°C, V T,R = 3.3 V ± 10%)

C

CC

Parameter

Symbol

Minimum

Typical

–6.3

Maximum

Unit

Notes

Output Optical Power

(Average)

Pout

–10

–1.5

dBm

50/125 um,

NA = 0.2

Pout

–10

–6.2

–1.5

dBm

62.5/125 um,

NA = 0.275

Optical Extinction Ratio

ER

9

dB

Optical Modulation

Amplitude (Peak-to-Peak)

2.125 Gb/s

OMA

196

156

830

392

µW

FC-PI Std

Note 1

Optical Modulation

Amplitude (Peak-to-Peak)

1.0625 Gb/s

OMA

350

µW

FC-PI Std

Note 2

Center Wavelength

Spectral Width – rms

Optical Rise/Fall Time

λ

860

0.85

150

nm

ps

FC-PI Std

C

σ

T

20% – 80%,

FC-PI Std

rise/fall

RIN (OMA), maximum

RIN

DJ

–117

dB/Hz

FC-PI Std

Note 3, 5

12

Contributed Deterministic

Jitter (Transmitter) 2.125 Gb/s

0.12

56

UI

ps

Contributed Deterministic

Jitter (Transmitter) 1.0625 Gb/s

DJ

RJ

0.09

85

UI

ps

Note 3, 5

Note 4, 5

Contributed Random

Jitter (Transmitter) 2.125 Gb/s

0.134

63

UI

ps

Contributed Random

Jitter (Transmitter) 1.0625 Gb/s

0.177

167

UI

ps

Pout TX_DISABLE Asserted

P

OFF

–35

dBm

Notes:

1. An OMA of 196 is approximately equal to an average power of –9 dBm assuming an Extinction Ratio of 9 dB.

2. An OMA of 156 is approximately equal to an average power of –10 dBm assuming an Extinction Ratio of 9 dB.

3. Contributed DJ is measured on an oscilloscope in average mode with 50% threshold and K28.5 pattern.

–12

4. Contributed RJ is calculated for 1 x 10 BER by multiplying the RMS jitter (measured on a single rise or fall edge) from the oscilloscope by 14.

Per the FC-PI standard (Table 13 – MM Jitter Output, note 1), the actual contributed RJ is allowed to increase above its limit if the actual

contributed DJ decreases below its limits, as long as the component output DJ and TJ remain within their specified FC-PI maximum limits with

the worst case specified component jitter input.

5. In a network link, each component‘s output jitter equals each component‘s input jitter combined with each component‘s contributed jitter.

Contributed DJ adds in a linear fashion and contributed RJ adds in a RMS fashion. In the Fibre Channel FC-PI Rev 11 specification ”6.3.3 MM

Jitter Budget“ section, there is a table specifying the input and output DJ and TJ for the receiver at each data rate. In that table, RJ is found from

TJ - DJ where the Rx input jitter is noted as Gamma R and the Rx output jitter is noted as Delta R. Our component contributed jitter is such that, if

the maximum specified input jitter is present, and is combined with our maximum contributed jitter, then we meet the specified maximum output

jitter in the FC-PI MM jitter specification table.

11

Table 8. Receiver Optical Characteristics (T = –20°C to 85°C, V T,R = 3.3 V ± 10%)

C

Symbol

CC

Parameter

Minimum

Typical

Maximum

Unit

dBm

µW

Notes

Optical Power

0

FC-PI Std

Min. Optical Modulation

Amplitude (Peak-to-Peak) 2.125 Gb/s

OMA

49

31

16

18

FC-PI Std

Note 1

Min. Optical Modulation

Amplitude (Peak-to-Peak) 1.0625 Gb/s

OMA

µW

FC-PI Std

Note 2

Stressed Receiver

Sensitivity (OMA)

2.125 Gb/s

96

25

23

µW

50 µm fiber,

FC-PI Std

62.5 µm fiber,

FC-PI Std

Note 3

109

Stressed Receiver

Sensitivity (OMA)

1.0625 Gb/s

55

67

15

20

µW

50 µm fiber,

FC-PI Std

62.5 µm fiber,

FC-PI Std

Note 4

Return Loss

12

dB

FC-PI Std

Note 5

Loss of Signal – Assert

Loss of Signal – De-Assert

Loss of Signal Hysteresis

Notes:

P

–31

–17.5

–17.0

5

dBm

dB

A

Note 5

D

P –P

D

0.5

2.3

A

1. An OMA of 49 µW is approximately equal to an average power of –15 dBm, and the OMA typical of 16 µW is approximately equal to an average

power of –20 dBm, assuming an Extinction Ratio of 9 dB. Sensitivity measurements are made at eye center with a BER = 10E–12.

2. An OMA of 31 is approximately equal to an average power of –17 dBm assuming an Extinction Ratio of 9 dB.

3. 2.125 Gb/s Stressed receiver vertical eye closure penalty (ISI) min. is 1.26 dB for 50 µm fiber and 2.03 dB for 62.5 µm fiber. Stressed receiver DCD

component min. (at TX) is 40 ps.

4. 1.0625 Gb/s Stressed receiver vertical eye closure penalty (ISI) min. is 0.96 dB for 50 µm fiber and 2.18 dB for 62.5 µm fiber. Stressed receiver

DCD component min. (at TX) is 80 ps.

5. These average power values are specified with an Extinction Ratio of 9 dB. The loss of Signal circuitry responds to OMA (peak to peak) power,

not to average power.

Table 9. Transceiver Timing Characteristics (T = –20°C to 85°C, V T,R = 3.3 V ± 10%)

C

CC

Parameter

Symbol

t_off

Minimum

Maximum

Unit

µs

Notes

Note 1

Note 2

Note 3

Tx Disable Assert Time

Tx Disable Negate Time

10

1

t_on

ms

Time to Initialize,

t_init

300

Including Reset of Tx_Fault

Tx Fault Assert Time

Tx Disable to Reset

LOS Assert Time

LOS Deassert Time

Serial ID Clock Rate

Notes:

t_fault

100

µs

Note 4

Note 5

Note 6

Note 7

t_reset

10

µs

t_loss_on

t_loss_off

100

µs

f-serial-clock

kHz

1. Time from rising edge of Tx Disable to when the optical output falls below 10% of nominal.

2. Time from falling edge of Tx Disable to when the modulated optical output rises above 90% of nominal.

3. From power on or negation of Tx Fault using Tx Disable.

4. Time from fault to Tx fault on.

5. Time Tx Disable must be held high to reset Tx_Fault.

6. Time from LOS transition to Rx LOS assert per Figure 6.

7. Time from non-LOS transition to Rx LOS deassert per Figure 6.

12

V

> 2.97 V

V

> 2.97 V

CC

Tx_FAULT

Tx_DISABLE

TRANSMITTED SIGNAL

t_init

t-init: TX DISABLE NEGATED

t-init: TX DISABLE ASSERTED

V

> 2.97 V

Tx_FAULT

Tx_DISABLE

CC

Tx_FAULT

Tx_DISABLE

TRANSMITTED SIGNAL

t_off

t_on

t_init

INSERTION

t-init: TX DISABLE NEGATED, MODULE HOT PLUGGED

t-off & t-on: TX DISABLE ASSERTED THEN NEGATED

OCCURANCE OF FAULT

Tx_FAULT

HFBR-5720L fig 6b

Tx_FAULT

Tx_DISABLE

TRANSMITTED SIGNAL

t_fault

t_reset

t_init*

t-fault: TX FAULT ASSERTED, TX SIGNAL NOT RECOVERED

t-reset: TX DISABLE ASSERTED THEN NEGATED, TX SIGNAL RECOVERED

OCCURANCE OF FAULT

Tx_FAULT

Tx_DISABLE

OCCURANCE

OF LOSS

OPTICAL SIGNAL

LOS

TRANSMITTED SIGNAL

t_fault

t_reset

* SFP SHALL CLEAR Tx_FAULT IN

t_init IF THE FAILURE IS TRANSIENT

t_loss_on

t_loss_off

t_init*

t-fault: TX DISABLE ASSERTED THEN NEGATED,

TX SIGNAL NOT RECOVERED

t-loss-on & t-loss-off

Figure 6. Transceiver timing diagrams (module installed except where noted).

13

Table 10. EEPROM Serial ID Memory Contents

Address Hex

ASCII

Address Hex

ASCII

H

F

B

R

–

5

7

2

0

A

L

Address

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

Hex

ASCII

Address Hex

96

97

98

99

ASCII

0

03

04

07

00

20

40

0C

05

01

15

00

1E

0F

00

41

47

49

4C

45

4E

54

20

00

30

D3

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

48

46

42

52

2D

35

37

32

30

41

4C

20

00

Note 3

00

1A

00

Note 1

Note 2

00

1

2

3

4

5

6

7

8

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

A

G

I

L

E

N

T

00

Note 3

Notes:

1. Address 61–83 specify a unique identifier.

2. Address 84–91 specify the date code.

3. Addresses 63 and 95 are check sums. Address 63 is the check sum for bytes 0–62 and address 95 is the check sum for bytes 64–94.

14

AGILENT HFBR-5720AL

850 nm LASER PROD

21CFR(J) CLASS 1

COUNTRY OF ORIGIN YYWW

XXXXXX

13.4 ± 0.1

(0.53 ± 0.004)

13.75 ± 0.1

(0.54 ± 0.004)

2.60

(0.10)

55.2 ± 0.2

(2.17 ± 0.01)

6.25 ± 0.05

(0.25 ± 0.002)

FRONT EDGE OF SFP

TRANSCEIVER CAGE

0.7

(0.03)

MAX. UNCOMPRESSED

12.7 ± 0.2

(0.50 ± 0.008)

8.5 ± 0.1

(0.33 ± 0.004)

TX

RX

AREA

FOR

PROCESS

PLUG

13.0 ± 0.1

(0.51 ± 0.004)

14.8

(0.58)

MAX. UNCOMPRESSED

14.04 ± 0.1

(0.55 ± 0.004)

DIMENSIONS ARE IN MILLIMETERS (INCHES)

Figure 7a. Module drawing.

15

X

Y

34.5

10

3x

7.2

7.1

10x 1.05 ± 0.01

0.1 L X A S

2.5

0.85 ± 0.05

0.1 S X Y

16.25

MIN. PITCH

1

2.5

B

A

1

PCB

EDGE

3.68

5.68

20

PIN 1

8.58

11.08

14.25

8.48

2x 1.7

11.93

16.25

REF.

9.6

4.8

11

10

SEE DETAIL 1

9x 0.95 ± 0.05

2.0

11x

0.1 L X A S

11x 2.0

5

26.8

2

10

3x

3

41.3

42.3

5

3.2

20x 0.5 ± 0.03

0.9

0.06 L A S B S

LEGEND

20

11

PIN 1

10.53

11.93

10.93

1. PADS AND VIAS ARE CHASSIS GROUND

2. THROUGH HOLES, PLATING OPTIONAL

9.6

0.8

TYP.

10

3. HATCHED AREA DENOTES COMPONENT

AND TRACE KEEPOUT (EXCEPT

CHASSIS GROUND)

4

4. AREA DENOTES COMPONENT

KEEPOUT (TRACES ALLOWED)

2 ± 0.005 TYP.

0.06 L A S B S

2x 1.55 ± 0.05

0.1 L A S B S

DETAIL 1

DIMENSIONS ARE IN MILLIMETERS

Figure 7b. SFP host board mechanical layout.

16

1.7 ± 0.9

(0.07 ± 0.04)

3.5 ± 0.3

(0.14 ± 0.01)

41.73 ± 0.5

(1.64 ± 0.02)

PCB

BEZEL

AREA

FOR

PROCESS

PLUG

15

(0.59)

MAX.

CAGE ASSEMBLY

15.25 ± 0.1

(0.60 ± 0.004)

12.4

(0.49)

REF.

10.4 ± 0.1

(0.41 ± 0.004)

9.8

MAX.

(0.39)

10

(0.39)

TO PCB

REF

1.15

(0.05)

BELOW PCB

REF.

16.25 ± 0.1

(0.64 ± 0.004)

MIN. PITCH

0.4 ± 0.1

(0.02 ± 0.004)

BELOW PCB

MSA-SPECIFIED BEZEL

DIMENSIONS ARE IN MILLIMETERS (INCHES).

Figure 7c. Assembly drawing.

17

www.agilent.com/semiconductors

For product information and a complete list of

distributors, please go to our web site.

For technical assistance call:

Americas/Canada: +1 (800) 235-0312 or

(408) 654-8675

Europe: +49 (0) 6441 92460

China: 10800 650 0017

Hong Kong: (+65) 6271 2451

India, Australia, New Zealand: (+65) 6271 2394

Japan: (+81 3) 3335-8152(Domestic/Interna-

tional), or 0120-61-1280(Domestic Only)

Korea: (+65) 6271 2194

Malaysia, Singapore: (+65) 6271 2054

Taiwan: (+65) 6271 2654

Data subject to change.

Obsolete 5988-6974EN

August 30, 2002

5988-7491EN


型号：	HFBR-5720AL
厂家：	ETC
描述：	2.125/1.0625 GBd MMF SFP Transceiver for Fibre Channel: Ext Temp & Voltage. Standard delatch 2.125 / 1.0625 GBd的MMF SFP收发器光纤通道：外部温度和电压。标准锁上光纤
文件：	总18页 (文件大小：273K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HFBR-5720AL [ETC]

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