FST16292MTDX [ETC]
Bus Exchanger ; 总线交换器\n
ETC 
July 1997
Revised November 2000
FST16292
12-Bit to 24-Bit Multiplexer/Demultiplexer Bus Switch
General Description
Features
The Fairchild Switch FST16292 provides twelve 2:1 high-
speed CMOS TTL-compatible multiplexer/demultiplexer
bus switches. The low on resistance of the switch allows
inputs to be connected to outputs without adding propaga-
tion delay or generating additional ground bounce noise.
■ 4Ω switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low lCC
.
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
■ Internal 500Ω pull-down resistor on A2 Port.
The select pin connects the A Port to the selected B Port
output. The A2 Ports are not externally connected, thus
have a 500Ω pull-down resistor to ground.
Ordering Code:
Order Number
FST16292MEA
FST16292MTD
Package Number
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD56
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
Truth Table
Pin Descriptions
A1
A2
S
L
Function
Pin Name
Description
Data-select input
Bus A
B1
B2
B2
B1
A
A
1 = B1, A2 = B2
1 = B2, A2 = B1
S
A1
H
B1, B2
Bus B
© 2000 Fairchild Semiconductor Corporation
DS500104
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5V to +7.0V
−50mA
DC Switch Voltage (VS)
Power Supply Operating (VCC
Input Voltage (VIN
Output Voltage (VOUT
)
4.0V to 5.5V
0V to 5.5V
0V to 5.5V
DC Input Voltage (VIN) (Note 2)
DC Input Diode Current (lIK) VIN < 0V
DC Output (IOUT) Sink Current
)
)
128mA
Input Rise and Fall Time (tr, tf)
Switch Control Input
DC VCC/GND Current (ICC/IGND
)
+/− 100mA
0ns/V to 5ns/V
0ns/V to DC
Storage Temperature Range (TSTG
)
−65°C to +150 °C
Switch I/O
Free Air Operating Temperature (TA)
−40 °C to +85 °C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
DC Electrical Characteristics
T
A = −40 °C to +85 °C
VCC
(V)
Symbol
Parameter
Units
Conditions
Min
Typ
Max
(Note 3)
VIK
Clamp Diode Voltage
4.5
4.0–5.5
4.0–5.5
5.5
−1.2
V
V
IIN = −18mA
VIH
VIL
II
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
2.0
0.8
±1.0
10
±1.0
7
V
µA
µA
µA
Ω
0≤ VIN ≤ 5.5V
IN = 5.5V
0 ≤A, B ≤ VCC
0
V
IOZ
OFF-STATE Leakage Current
Switch On Resistance
(Note 4)
5.5
RON
4.5
4
4
V
V
V
V
V
IN = 0V, IIN = 64mA
4.5
7
Ω
IN = 0V, IIN = 30mA
4.5
8
12
20
3
Ω
IN = 2.4V, IIN = 15mA
IN = 2.4V, IIN = 15mA
IN = VCC or GND, IOUT = 0
4.0
14
Ω
ICC
Quiescent Supply Current
Increase in ICC per Input
5.5
µA
mA
∆ ICC
5.5
2.5
One input at 3.4V
Other inputs at VCC or GND
Note 3: Typical values are at VCC = 5.0V and TA =+25°C
Note 4: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
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2
AC Electrical Characteristics
TA = −40 °C to +85 °C,
C
L = 50pF, RU = RD = 500Ω
Figure
No.
Symbol
Parameter
Units
Conditions
V
CC = 4.5 – 5.5V
VCC = 4.0V
Min
Max
Min
Max
t
PHL, tPLH
Prop Delay Bus to Bus (Note 5)
Prop Delay S to A1
0.25
0.25
7.4
ns
ns
VI = OPEN
Figures
1, 2
tPHL, tPLH
PZL, tPZH
1.5
7.0
VI = OPEN
Figures
1, 2
t
Output Enable Time
S to B1 or B2
VI = 7V for tPZL
Figures
1, 2
1.0
1.0
6.7
7.5
7.0
7.8
ns
ns
VI = OPEN for tPZH
VI = 7V for tPLZ
tPLZ, tPHZ
Output Disable Time
S to B1 or B2
Figures
1, 2
VI = OPEN for tPHZ
Note 5: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 6)
Symbol
Parameter
Control Pin Input Capacitance
Input/Output Capacitance
Typ
3
Max
Units
pF
Conditions
CC = 5.0V
CIN
V
V
CI/O
10
pF
CC = 5.0V, S0 =GND
Note 6: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50 Ω source terminated in 50 Ω
Note: CL includes load and stray capacitance
Note: Input PRR = 1.0 MHz, tW = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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5
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