FST16862MTDX [ETC]
BUS SWITCH|CMOS|TSSOP|48PIN|PLASTIC ; BUS开关| CMOS | TSSOP封装| 48PIN |塑料
| 型号： | FST16862MTDX |
| 厂家： | 
ETC |
| 描述： | BUS SWITCH|CMOS|TSSOP|48PIN|PLASTIC
|
| 文件： | 总6页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2001
Revised February 2002
FST16862
20-Bit Bus Switch
General Description
Features
I 4Ω switch connection between two ports.
The Fairchild Switch FST16862 provides 20-bits of high-
speed CMOS TTL-compatible bus switching. The low On
Resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
I Minimal propagation delay through the switch.
I Low lCC
.
I Zero bounce in flow-through mode.
I Control inputs compatible with TTL level.
The device is organized as a 20-bit bus switch. When OEX
is LOW, the switch is ON and Port A is connected to Port B.
When OEX is HIGH,
a high impedance state exists
between the A and B Ports.
Ordering Code:
Package
Order Number
Package Description
Number
FST16862QSP MQA48A 48-Lead Quarter Size Very Small Outline Package (QVSOP), JEDEC MO-154, 0.150" Wide
(Preliminary)
FST16862MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
© 2002 Fairchild Semiconductor Corporation
DS500702
www.fairchildsemi.com
Connection Diagram
Truth Table
Inputs
Inputs/Outputs
OEx
L
A, B
A = B
Z
H
Pin Descriptions
Pin Name
Description
OEx
A
Bus Switch Enables
Bus A
B
Bus B
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
)
0.5V to +7.0V
−0.5V to +7.0V
−0.5V to +7.0V
−50 mA
DC Switch Voltage (VS) (Note 2)
DC Input Voltage (VIN) (Note 3)
DC Input Diode Current (lIK) VIN < 0V
DC Output (IOUT) Current
Power Supply Operating (VCC)
4.0V to 5.5V
0V to 5.5V
0V to 5.5V
Input Voltage (VIN
)
Output Voltage (VOUT
)
128 mA
Input Rise and Fall Time (tr, tf)
Switch Control Input
DC VCC/GND Current (ICC/IGND
)
100 mA
0 ns/V to 5 ns/V
0 ns/V to DC
Storage Temperature Range (TSTG
)
−65°C to +150 °C
Switch I/O
Free Air Operating Temperature (TA)
-40 °C to +85 °C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: VS is the voltage observed/applied at either the A or B Ports across
the switch.
Note 3: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 4: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
TA = −40 °C to +85 °C
VCC
(V)
Symbol
Parameter
Units
Conditions
Min
Typ
Max
(Note 5)
VIK
Clamp Diode Voltage
4.5
4.0 - 5.5
4.0 - 5.5
5.5
−1.2
V
V
IIN = −18 mA
VIH
VIL
II
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
2.0
0.8
1.0
1.0
1.0
7
V
µA
µA
µA
Ω
0 ≤ VIN ≤ 5.5V
0
VIN = 5.5V
IOZ
OFF-STATE Leakage Current
Switch On Resistance
(Note 6)
5.5
0 ≤ A, B ≤ VCC
RON
4.5
4
4
VIN = 0V, IIN = 64 mA
VIN = 0V, IIN = 30 mA
VIN = 2.4V, IIN = 15 mA
VIN = 2.4V, IIN = 15 mA
VIN = VCC or GND, IOUT = 0
One Input at 3.4V
4.5
7
Ω
4.5
7
12
20
3
Ω
4.0
11
Ω
ICC
Quiescent Supply Current
Increase in ICC per Input
(Note 7)
5.5
µA
mA
∆ ICC
5.5
2.5
Other Inputs at VCC or GND
Note 5: Typical values are at VCC = 5.0V and TA = +25°C
Note 6: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Note 7: Per TTL driven input, control pins only.
3
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AC Electrical Characteristics
TA = −40 °C to +85 °C,
CL = 50pF, RU = RD = 500Ω
Figure
Number
Symbol
Parameter
Units
Conditions
VCC = 4.5 – 5.5V
VCC = 4.0V
Min Max
Min
Max
t
PHL, tPLH
Propagation Delay Bus-to-Bus
(Note 8)
0.25
0.25
ns
ns
VI = OPEN
Figures
1, 2
tPZH, tPZL
Output Enable Time
1.0
1.0
5.0
6.0
5.3
VI = 7V for tPZL
Figures
1, 2
VI = OPEN for tPZH
VI = 7V for tPLZ
tPHZ, tPLZ
Output Disable Time
6.3
ns
Figures
1, 2
VI = OPEN for tPHZ
Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 9)
Symbol
CIN
CI/O
Parameter
Typ
Max
Units
Conditions
VCC = 5.0V, VIN = 0V
VCC, OE = 5.0V, VIN = 0V
Control Pin Input Capacitance
3
pF
Input/Output Capacitance “OFF State”
6
pF
Note 9: TA = +25°C, f = 1 Mhz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50Ω source terminated in 50Ω
Note: CL includes load and stray capacitance
Note: Input PRR = 1.0 MHz, tW = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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4
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Quarter Size Very Small Outline Package (QVSOP), JEDEC MO-154, 0.150" Wide
Package Number MQA48A
(Preliminary)
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384(FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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www.fairchildsemi.com
6
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