FST162861MTDX [ETC]
Bus Switch ; 总线开关\n
ETC 
March 2000
Revised July 2000
FST162861
20-Bit Bus Switch with 25Ω Series Resistors in Outputs
General Description
Features
The Fairchild Switch FST162861 provides 20-Bits of high-
speed CMOS TTL-compatible bus switching. The low on
resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
■ 25Ω switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low lCC
.
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
The device is organized as a 10-bit or 20-Bit bus switch.
When OE1 is LOW, the switch is ON and Port 1A is con-
nected to Port 1B. When OE2 is LOW, Port 2A is connected
to Port 2B. When OEX is HIGH, a high impedance state
exists between the A and B ports. The FST162861 has an
equivalent 25Ω series resistors to reduce signal-reflection
noise, eliminating the need for external terminating resis-
tors.
Ordering Code:
Order Number Package Number
Package Description
FST162861MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
Truth Table
Inputs
Inputs/Outputs
Pin Descriptions
OE1
OE2
1A, 1B
2A, 2B
Pin Name
Description
L
L
L
H
L
1A = 1B
2A = 2B
1A = 1B
Z
2A = 2B
Z
OE1, OE2
1A, 2A
Bus Switch Enables
Bus A
H
H
Z
Z
H
1B, 2B
Bus B
© 2000 Fairchild Semiconductor Corporation
DS500319
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5V to +7.0V
−50mA
DC Switch Voltage (VS) (Note 2)
DC Input Voltage (VIN) (Note 3)
DC Input Diode Current (lIK) VIN < 0V
DC Output (IOUT) Current
Power Supply Operating (VCC
Input Voltage (VIN
Output Voltage (VOUT
)
4.0V to 5.5V
0V to 5.5V
0V to 5.5V
)
)
128mA
Input Rise and Fall Time (tr, tf)
Switch Control Input
DC VCC/GND Current (ICC/IGND
)
±100mA
0nS/V to 5nS/V
0nS/V to DC
Storage Temperature Range (TSTG
)
−65°C to +150 °C
Switch I/O
Free Air Operating Temperature (TA)
-40 °C to +85 °C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: VS is the voltage observed/applied at either the A or B Port across
the switch.
Note 3: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 4: Unused control inputs must be held high or low. They may not float.
DC Electrical Characteristics
T
A = −40 °C to +85 °C
VCC
(V)
Symbol
Parameter
Units
Conditions
Min
Typ
Max
(Note 5)
VIK
Clamp Diode Voltage
4.5
4.0–5.5
4.0–5.5
5.5
−1.2
V
V
IIN = −18mA
VIH
VIL
II
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
2.0
0.8
±1.0
±1.0
±1.0
38
V
µA
µA
µA
Ω
0 ≤ VIN ≤ 5.5V
IN = 5.5V
0 ≤ A, B ≤ VCC
0
V
IOZ
OFF-STATE Leakage Current
Switch ON Resistance
(Note 6)
5.5
RON
4.5
20
20
20
20
26
27
28
30
V
V
V
V
V
IN = 0V, IIN = 64mA
4.5
40
Ω
IN = 0V, IIN = 30mA
4.5
48
Ω
IN = 2.4V, IIN = 15mA
IN = 2.4V, IIN = 15mA
IN = VCC or GND, IOUT = 0
4.0
48
Ω
ICC
Quiescent Supply Current
Increase in ICC per Input
5.5
3
µA
mA
∆ ICC
5.5
2.5
One input at 3.4V
Other inputs at VCC or GND
Note 5: Typical values are at VCC = 5.0V and TA = +25°C
Note 6: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
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2
AC Electrical Characteristics
T
A = −40 °C to +85 °C,
C
L = 50 pF, RU = RD = 500Ω
Figure
No.
Symbol
Parameter
Units
Conditions
V
CC = 4.5 – 5.5V CC = 4.0V
V
Min
Max
Min
Max
t
PHL,tPLH
Prop Delay Bus to Bus (Note 7)
Output Enable Time
1.25
1.25
ns
ns
ns
VI = OPEN
Figures
1, 2
tPZH, tPZL
1.0
1.0
5.3
6.0
5.5
6.3
VI = 7V for tPZL
Figures
1, 2
VI = OPEN for tPZH
VI = 7V for tPLZ
tPHZ, tPLZ
Output Disable Time
Figures
1, 2
VI = OPEN for tPHZ
Note 7: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 8)
Symbol
CIN
CI/O
Parameter
Typ
Max
Units
Conditions
Control Pin Input Capacitance
3.5
pF
V
CC = 5.0V, VIN = 0V
Input/Output Capacitance “OFF State”
6.0
pF
VCC, OE = 5.0V, VIN = 0V
Note 8: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50Ω source terminated in 50Ω
Note: CL includes load and stray capacitance
Note: Input PRR = 1.0 MHz, tW = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384(FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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4
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