DP83924A [ETC]
;
| 型号： | DP83924A |
| 厂家： | 
ETC |
| 描述： |
|
| 文件： | 总30页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
October 1997
DP83924A Quad 10 Mb/s Ethernet Transceiver
General Description
Features
The Quad 10 Mb/s Ethernet Transceiver is a 4-Port ■ 100 pin package
Encoder/Decoder (ENDEC) that includes all the circuitry
■ 10BASE-T and AUI interfaces
■ 4 ports TP interface with TRI-STATE control
required to interface four Ethernet Media Access Control-
lers (MACs) to 10BASE-T. This device is ideally suited for
switch hub applications where 8, 16, 24, or 32 ports are
commonly used.
■ Single Full AUI and TP Interface on port 1 supports 50
meter drops
■ Automatic or manual selection of twisted pair or Attach-
The DP83924A has three dedicated 10BASE-T ports.
There is an additional port that is selectable for either
10BASE-T or for an Attachment Unit Interface (AUI). In
10BASE-T mode, any port can be configured to be Half or
Full Duplex. (Continued)
ment Unit Interfaces on port 1
■ Direct Interface to NRZ Compatible controllers
■ MII-Like Management Interface (Continued)
System Diagram
RTX REQ
Reference
TXU+
TXE
Transmit
Pre-empha-
sis/TX Logic
Manchester
Encoder and
Data Ctl.
Transmit
Control
Interface
Transmit
Filter
Output
Driver
TXD
TXC
TXU-
Oscillator
Prescaler
X1
TX+
TX-
Transmit
AUI Driver
Link
Generator
MDC
Manage-
ment Con-
trol Interface
Configura-
tion Reg-
isters
AUI Collision
MDIO
+
-
CD+
CD-
TP LBK
AUI LBK
LED_CLK
LED_DATA
LED Control
Interface
Link
Detector
Heartbeat
Jabber Timer
TP
Rcv
Common
RXI+
RXI-
RX+
Analog/PLL
for Wave
Shapers
+
Collision
MUX
Smart
Squelch
Decoder
-
AUI Rcv
+
COL
Phase
Lock Loop
Decoder
CRS
RXD
RXC
Receive
Control
Interface
MUX
-
RX-
ENDEC-Transceiver
Block (replicated 4
times)
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1997 National Semiconductor Corporation
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General Description (Continued)
Features (Continued)
The various modes on the transceivers can be configured ■ Serial management interface for configuration and mon-
and controlled via the MII management interface. This
management interface makes inter-operability with other
manufacturers MAC units relatively easy. If no manage-
ment interface is desired, some of the critical operating
modes of the transceiver can be set via strapping options
(latching configuration information during reset). The
ENDEC section of the transceiver also supplies a simple
Non-Return-to-Zero (NRZ) interface to transmit and
receive data to/from standard 10 Mb/s MACs.
itoring of ENDEC/Transceiver operation
■ Twisted Pair Transceiver Module
– On-chip filters for transmit outputs
– Adjustable Equalization and Amplitude
– Low Power Driver
– Heartbeat and Jabber Timers
– Link Disable and Smart Receive Squelch
– Polarity detection and correction
– Jabber Enable/Disable
The transceivers include on-chip filtered transmit outputs,
which reduce emissions and eliminate the need for exter-
nal filter modules.
■ ENDEC Module (one per port)
– Low Power Class AB Attachment Unit Interface (AUI)
Driver for one port
– Enhanced Supply Rejection
– Enhanced Jitter Performance
– Diagnostic ENDEC Loopback
– Squelch on Collision and Receive Pair
■ Serial LED interface for LINK, POLARITY, ACTIVITY,
and ERROR
■ JTAG Boundary Scan per IEEE 1149.1
2
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Table of Contents
1.0
2.0
Pin Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.0
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Register Map and Descriptions . . . . . . . . . . . . . 15
Application Information . . . . . . . . . . . . . . . . . . . . . . . 17
1.1
1.2
Pin Connection Diagram . . . . . . . . . . . . . . . . . . . . 4
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.0
Interface Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
5.2
Magnetics Specifications . . . . . . . . . . . . . . . . . . 17
Layout Considerations . . . . . . . . . . . . . . . . . . . . 17
2.1
2.2
2.3
Management Interface . . . . . . . . . . . . . . . . . . . . . . 8
LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.0
Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.0
AC and DC Electrical Specifications . . . . . . . . . . . . . 18
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.0
Detailed Functional Description . . . . . . . . . . . . . . . . . 12
3.1
3.2
3.3
Twisted Pair Functional Description . . . . . . . . . . 12
ENDEC Module . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Additional Features . . . . . . . . . . . . . . . . . . . . . . . 13
3
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1.0 Pin Information
1.1 Pin Connection Diagram
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
NC
NC
NC
NC
TDI
TMS
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TXE[3]
TXD[3]
RXC[4]
COL[4]
CRS[4]
RXD[4]
TXE[4]
TXD[4]
RESET
FDX[4]
FDX[3]
FDX[2]
FDX[1]
RTX
TRST
GND_DIG
VDD_DIG
LED_CLK
LED_DATA
LINK_1
LINK_2
GND_2
DP83924A
Quad 10Mb/s
Ethernet
Transceiver
100-Pin PQFP
(TOP VIEW)
LINK_3 / INT
LPBK / MDC
LINK_4 / MDIO
X1
GND_CLK
VDD_CLK
NC
REQ
GND_WS_1
VDD_WS_1
NC
NC
Order Number DP83924AVCE
NS Package Number VCE100A
4
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1.0 Pin Information (Continued)
1.2 Pin Description
Table 1. NRZ CONTROLLER INTERFACE and MANAGEMENT INTERFACE: These pins provide the interface
signalling between the Media Access Controller and the transceiver. (30 Pins)
Symbol
TXC
Pin #
Type
Description
77
O
Transmit Clock: This pin outputs a 10 MHz output clock signal synchronized to the
transmit data (one pin for all ports).
TXD[4]
TXD[3]
TXD[2]
TXD[1]
40
46
56
71
I
I
Transmit Data: The serial TXD contains the transmit serial data output stream.
TXE[4]
TXE[3]
TXE[2]
TXE[1]
41
47
57
72
Transmit Enable: This active high input indicates the presence of valid data on the TXD
pins.
CRS[4]
CRS[3]
CRS{2]
CRS[1]
43
52
59
74
O, pull-up Carrier Sense: Active high output indicates that valid data has been detected on the
O, pull-up receive inputs.
O, pull-up
O, pull-up
CRS[3:1] are dual purpose pins. When RESET is active, the value on these pins are
sampled to determine the transceiver address for the mgmt interface. These pins have
internal pull-ups, a 2.7 kΩ pull down resistor is required to program a logic ‘0’.
COL[4]
COL[3]
COL[2]
COL[1]
44
54
60
75
O, pull-up Collision: This active high output is asserted when a collision condition has been de-
O, pull-up tected. It is also asserted for 1µs at the end of a packet to indicate the SQE test function.
O, pull-up
O, pull-up
COL[4:1] are dual purpose pins. When RESET is active, these pins are sampled and
selects the operating mode for the device. To select the non-default mode(s), a 2.7 kΩ
pull down resistor(s) is required. The strappable functions are:
COL[4]; selects the number of receive clocks after carrier sense deassertion (5 RXCs
or continuous RXCs). Default is 5 RXCs.
COL[3]; enables or disables the receive filter. Default is to disable the receive filter.
COL[2]; selects the full duplex operating mode (normal or enhanced). Default is normal
full duplex mode.
COL[1]; selects the LED operating mode (normal or enhanced). Default is normal LED
mode.
RXC[4]
RXC[3]
RXC[2]
RXC[1]
45
55
61
76
O
O
I
Receive Clock: This 10 MHz signal is generated by the transceiver, and is the recov-
ered clock from the decoded network data stream.
The number of RXCs after the deassertion of CRS is programmable via the Global Con-
figuration Register, GATERXC bit, D0. The options are for 5 RXCs or continuous RXCs.
RXD[4]
RXD[3]
RXD[2]
RXD[1]
42
51
58
73
Receive Data: Provides the decoded receive serial data. Data is valid on the rising
edge of RXC.
MDC
93
94
92
Management Data Clock: When “normal” full duplex mode is selected (strap option,
COL[2]=1), this clock signal (0-2.5 MHz) is the clock for transferring data across the
management interface.
LPBK
LoopBack: When “enhanced” full duplex mode is selected (strap option, COL[2]=0),
then this pin is an active high input to configure all ports into diagnostic loopback mode.
MDIO
I/O
Management Data I/O: When “normal” full duplex mode is selected (strap option,
COL[2]=1), this Bidirectional signal transfers data on the management interface be-
tween the controller and the transceiver.
LINK_4
Link Lost Status Port 4: When “enhanced” full duplex mode is selected, (strap option,
COL[2]=0), this pin outputs the link lost status for port 4. If link is lost, this output is high.
INT
OD
Interrupt: When “normal” full duplex mode is selected (strap option, COL[2]=1), this
output pin is driven low when an interrupt condition is detected within the Quad Trans-
ceiver. An interrupt can occur when, link status changes or, LED status changes. This
is an open-drain output. And requires an external pull-up resistor.
LINK_3
Link Lost Status Port 3: When “enhanced” full duplex mode is selected, (strap option,
COL[2]=0), this pin outputs the link lost status for port 3. If link is lost, this output is high.
LINK_2
LINK_1
90
89
O
Link Lost Status Ports 1,2: These pins indicate the link lost status for ports 1 and 2,
when “enhanced” full duplex mode is selected.
5
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1.0 Pin Information (Continued)
Table 2. NETWORK INTERFACES: Attachment Unit, Twisted Pair Interface (24 Pins)
Symbol
RXI4+
RXI4-
Pins
Type
Description
29
30
I
Twisted Pair Receive Input: This differential input pair receives the incoming data from
the twisted pair medium via an isolation transformer.
RXI3+
RXI3-
19
20
RXI2+
RXI2-
17
18
RXI1+
RXI1-
7
8
TXU4+
TXU4-
25
26
O
UTP Transmit Outputs: This pair of drivers provide pre-emphasized and filtered differ-
ential output for UTP (100Ω cable). These drivers maintain the same common mode
voltage during data transmission and idle mode.
TXU3+
TXU3-
23
24
TXU2+
TXU2-
13
14
TXU1+
TXU1-
11
12
REQ
33
I
I
Equalization Resistor: An external resistor connects to ground to adjust the equaliza-
tion on the twisted pair transmit outputs.
RTX
34
Transmit Amplitude Resistor: An external resistor connects to ground to adjust the
amplitude of the differential transmit outputs to the unshielded twisted pair cable.
Attachment Unit Interface
RX+
RX-
5
6
I
Port 1 Full AUI Receive Input: In AUI mode this differential input pair receives the in-
coming data from the AUI medium via an isolation transformer.
TX+
TX-
1
2
O
Port 1 Full AUI Transmit Output: In AUI mode this differential pair sends encoded data
from the AUI transceiver. These outputs are source followers and require 270 Ohm pull
down resistors.
CD+ CD-
34
I
Port 1 Full AUI Collision Detect: In AUI mode, this differential input pair receives the
collision detect signals from the AUI medium via an isolation transformer.
Table 3. LED & GENERAL CONFIGURATION Pins (8 Pins)
Symbol
Pins
Type
Description
LED_DATA
88
O
LED serial data output: This output should be connected to the input of the 1st serial
shift register.
LED_CLK
X1
87
95
O
I
LED Clock: This is the clock for the serial shift registers.
External Oscillator Input: This signal is used to provide clocking signals for the inter-
nal ENDEC. A 20 MHz oscillator module should be used to drive this pin.
RESET
39
I
I
Reset: Active low input resets the transceiver, and starts the initialization of the device.
This pin has a noise filter on it’s input, which requires that the reset pulse must be great-
er than 30 TXC’s.
FDX[4:1]
38
Full Duplex: This pin is sampled during reset. They control the full duplex (or half du-
-35
plex) configuration of each port.
6
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1.0 Pin Information (Continued)
Table 4. SCAN TEST Pins (5 Pins)
Description
Symbol
TCK
Pins
Type
79
I
Test Clock: This signal is used during boundary scan to clock data in and out of the
device.
TDI
82
78
83
84
I
Test Input: The signal contains serial data that is shifted into the device by the TAP
controller. An internal pullup is provided if not used.
TDO
TMS
TRST
O,Z Test Output: The signal can be set to TRI-STATE and contains serial data that is shift-
ed out of the device by the TAP controller.
I
I
Test Mode Select: This selects the operation mode of the TAP controller. An internal
pullup is provided if not used.
Test Reset: When this signal is asserted low, it forces the TAP (Test Access Port) con-
troller into a logic reset state. An internal pullup is provided. This pin should be pulled
low during normal operation.
Table 5. POWER AND GROUND Pins (33 Pins)
Table 6. Pin Type Description
Description
Symbol
Pins Type
Description
Pin Type
NC
NC
NC
NC
NC
NC
NC
NC
48
49
50
80
81
98
99
100
NA No Connect
I
Input Buffer
O
Output Buffer (driven at all times)
Bi-directional Buffer
I/O
O, Z
OD
Output Buffer with High Impedance Capability
Open Drain-Like Output. Either driven Low or
to a High Impedance State
VDD_TPI_4
VDD_TPI_3
VDD_TPI_2
VDD_TPI_1
27
21
15
9
P
Power for TPI Ports 1-4
Ground for TPI Ports 1-4
GND_TPI_4
GND_TPI_3
GND_TPI_2
GND_TPI_1
28
22
16
10
G
VDD_PLL_2
VDD_PLL_1
67
63
P
Power for PLL Circuitry
Ground for PLL Circuitry
GND_PLL_4
GND_PLL_3
GND_PLL_2
GND_PLL_1
66
65
64
62
G
VDD_WSPLL_1 68
P
G
P
Power for Wave Shaper and
PLL Circuitry
GND_WSPLL_1 69
Ground for Wave Shaper
and PLL Circuitry
VDD_WS_1
GND_WS_1
31
32
Power for Wave Shaper Cir-
cuitry
G
Ground for Wave Shaper
Circuitry
VDD_DIG
GND_DIG
GND_CLK
VDD_CLK
86
85
96
97
P
G
G
P
Power for Core Logic
Ground for Core Logic
Ground for Clock Circuitry
Power for Clock Circuitry
Ground for NRZ Circuitry
GND_2
GND_1
91
53
G
VDD_1
70
P
Power for NRZ Circuitry
7
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2.0 Interface Descriptions
During a read operation, the first 14 bits are driven onto
MDIO by the host, then the bus is released, allowing the
DP83924A to drive the requested data onto MDIO.
Interface Overview
The Quad Transceiver’s interfaces can be categorized into
the following groups of signals:
The serial lines do not require any preamble on these pins,
however if it is provided it is ignored so long as the 0110 or
0101 pattern is not present. If a continuous MDC is not
supplied, then at the end of each command (read or write),
2 additional MDCs are required in order to allow the inter-
nal state machine to transition back to it’s idle state. Refer
to Figure 1.
1. Management Interface - Allows host to read status and
set operating modes.
2. Media Access Control Interface - Straight forward NRZ
interface to Ethernet MACs.
3. LED Interface - Serial LED interface to off chip shift reg-
isters.
4. Network Interfaces - Integrated 10BASE-T and AUI.
5. Clock - Allows connection of an external clock module.
2.2 MAC Interface
This interface connects the ENDEC/Transceiver to an
Ethernet MAC controller. This interface consists of a serial
data transmit interface and a serial receive interface. The
interface clocks data out (on receive) or in (on transmit) on
the rising edge of the clock. Refer to Figure 2. All signals
are active high with rising edge sampling.The recovered
clock (RXC) is selectable for 5 RXCs after the deassertion
of carrier sense (CRS) or for continuous RXCs after the
deassertion of CRS. This is programmable through the
serial MII or through the COL[4] strapping option.
2.1 Management Interface
This interface is a simple serial interface that is modeled
after the MII standard serial interface, though it does not
adhere to the MII standard completely (the protocol is fol-
lowed, but the register space is not). The interface signals
consist of a clock and data line for transfer of data to and
from the registers.
In a multiple Quad Transceiver system, it is necessary to
distinguish between the devices in order to access the cor-
rect registers for configuration and status information. This
is accomplished by assigning each Quad Transceiver a
unique transceiver address. The lower 3 bits of the trans-
ceiver address, T[2:0], is latched in during reset based on
the logic state of CRS[3:1]. The upper 2 bits of the trans-
ceiver address, T[4:3], must be zero. Therefore, 32 ports
can be supported with a single MII bus.
2.3 LED Interface
The LED interface consists of two modes. The first option,
normal LED mode, requires an external 8-bit shift register.
During every LED update cycle, 8-bits are shifted out to the
external shift registers. This allows two status LEDs per
port. One LED indicates activity (Tx or Rx) and the second
indicates port status (per Table 6). The LEDs attached to
the shift register will be on, if the associated port has tx or
rx activity. The status LEDs will blink at different rates
depending on the associated ports status.
The register address field indicates which register within
the DP83924A that is to be accessed (read or write).
During a write operation, all 32 bits are driven onto MDIO
by the host, indicating which transceiver and register the
data is to be written.
1
3
4
6
7
9
10
12 13
15 16
31 32 33 34
2
5
8
11
14
17
MDC
Z
T4
T2
T1 T0
A4 A3 A2 A1 A0
register address
0
0
0
MDIO
T3
1
1
D15
D0
turn
prefix
read
transceiver address
data
around
Register Read
T4
T2
T1 T0
A4 A3 A2 A1 A0
register address
0
1
0
prefix
1
MDIO
T3
1
0
D15
D0
turn
write
transceiver address
data
around
Register Write
Note 1: The management interface addressing includes a 5 bit field for the Transceiver Address, T[4:0], and a 5 bit field for the register
address, A[4:0]. The MII assumes the transceiver address applies to a single port, but in this implementation a single address
refers to a single IC. The transceiver address is set by 3 external pins, CRS[3:1]. T[4:3] must be zero to address the transceiver.
Thus up to 32 10BASE-T ports can be addressed from a single interface (8 addr x 4 ports/addr).
Note 2: Two MDCs (clocks 33, 34) are required after each read or write in order to allow the internal state machine to transition back to
it’s IDLE state.
Figure 1. Serial Management Interface Timing Diagram (read/write)
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2.0 Interface Descriptions (Continued)
5 Clocks
Transmit Interface SIgnals
TXC
Setup
TXE
Hold
TXD
COL
Receive Interface SIgnals
RXC
Setup
CRS
Hold
RXD
Figure 2. NRZ Interface Timing Diagram
LED_CLK
LED_DATA
Note: act.n - Transmit or Receive
activity for Port n
act.1 act.2 act.3 act.4 stat.1 stat.2 stat.3stat.4
stat.n - Port n status
Signal is active low (LED on)
Figure 3. Normal LED Mode Timing Diagram
If a port experiences both Bad Polarity and Link Lost, then used to support two LEDs. One is a bi-color LED (decode
the LEDs will go to the fast blink state (i.e. Link Lost). Port of the FDX and LinkCoded bits) to indicate LINK status.
activity and status are shifted out serially, with port 1 The second LED indicates activity (Tx or Rx). The Tx and
shifted out first. The LED update rate is every 50 ms. The Rx bits are not intended to be used as separate LEDs for
LED clock rate is 1 MHz. All port activity is extended to 50 transmit and receive activity. Refer to the User Information
ms to make it visible. Data is valid on the rising edge of document regarding this mode. As with the first LED
LED_CLK and is active low (LED on). Refer to Figure 3.
option, port 1 status is shifted out first. Refer to Figure 4.
Table 7. Normal LED Mode
Table 8. Enhanced LED Mode - Bit Decode
LED Condition
Status Indication
Good Status
FDX
LinkCoded
LED Status
Comments
Off
0
0
OFF
Link Fail, Full
Duplex
On - Solid
Error’d Status
Link Lost
0
1
1
1
0
1
ON
ON
Good Link, Full
Duplex
Fast Blink (400 ms)
Slow Blink (1600 ms)
Bad Polarity
Good Link, Half
Duplex
The second option, enhanced LED mode, serially shifts a
16-bit stream out of the Quad Transceiver. This option out-
puts per port data for Rx, Tx, Full Duplex (FDX), and Link-
Coded status. These four bits per port are intended to be
OFF
Link Fail, Half
Duplex
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2.0 Interface Descriptions (Continued)
LED_CLK
Link
coded
FDX
Link
coded
Link
coded
Link
coded
Tx.2 Tx.3 Tx.4 Rx.1 Rx2 Rx.3 Rx.4
Tx.1
FDX
FDX
FDX
LED_DATA
Port.1
Port.2
Port.3
Port.4
Figure 4. Enhanced Mode LED Timing Diagram
To select the desired LED mode, the COL [1] pin has a mistaken for a valid signal. This smart squelch circuitry
strapping feature. If COL[1] is a logic ‘0’ during reset, then (which is described in detail under the Functional Descrip-
“enhanced” LED mode is enabled. If COL[1] is a logic ‘1’ tion) employs a combination of amplitude and timing mea-
during reset, then “normal” LED mode is enabled.
surements to determine the validity of data on the twisted
pair inputs. Only after these conditions have been satisfied
will Carrier Sense (CRS) be generated to indicate that valid
data is present.
2.4 Network Interface
2.4.1 Twisted Pair Interface
The Quad 10 Mb/s Transceiver provides two buffered and
filtered 10BASE-T transmit outputs (for each port) that are
connected to the output isolation transformer via two
impedance matching resistor/capacitor networks. See
Figure 5. The twisted pair receiver implements an intelli-
gent receive squelch on the RXI+ differential inputs to
ensure that impulse noise on the receive inputs will not be
2.4.2 Attachment Unit Interface
A single port (port 1) on the transceiver has a separate
(non- multiplexed) AUI interface. This interface is a full
802.3 standard AUI interface capable of driving the full 50m
cable. The schematic for connecting this interface to the
AUI connector is shown in Figure 6.
1000 pF
1:2
10Ω
TX+
200pF
1000 pF
TD+
TD-
RD+
RD-
TX-
RXI+
RXI-
10Ω
RJ45
T1
1:1
REQ
RTX
R5
49.9Ω
Common Mode
Chokes may be
required.
R6
49.9Ω
+5V
R3
R4
C1
0.01µF
All values are typical and are + 1%
Figure 5. Twisted Pair Interface Schematic Diagram
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2.0 Interface Descriptions (Continued)
+12V
AUI
1:1
+12V
CD+
CD-
RX+
RX-
CD+
CD-
RX+
RX-
TX+
TX-
TX+
TX-
GND
T2
R1
R2
R3
R4
DB15
39.2Ω 39.2Ω
39.2Ω 39.2Ω
C1
0.01µF
C2
0.01µF
Figure 6. Full AUI Interface Schematic
If the standard 78Ω transceiver cable is used, the receive 2.4.3 Oscillator Clock
differential input must be externally terminated with two
When using an oscillator, additional output drive may be
necessary if the oscillator must also drive other compo-
nents. The X1 pin is a simple TTL compatible input. See
Figure 7.
39Ω resistors connected in series. In thin Ethernet applica-
tions, these resistors are optional. To prevent noise from
falsely triggering the decoder, a squelch circuit at the input
rejects signals with levels less than -175 mV. Signals more
negative than -300 mV are decoded.
To Internal Circuit
Oscillator
20 MHz, 0.01%
40-60% Duty Cycle
Drive ≥ 2 TTL Loads
X1
VCC
Oscillator
Figure 7. External Oscillator Connection Diagram
11
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3.0 Detailed Functional Description
This product utilizes the standard 10BASE-T and AUI inter- due to noise on the network. The COL signal remains for
face core building blocks which are replicated on this the duration of the collision.
device, one per port. The basic function of these blocks are
Approximately 1 sec after the transmission of each packet a
described in the following sections. Also described are the
signal called the Signal Quality Error (SQE) consisting of
common digital blocks. Refer to the “System Diagram” on
typically 10 cycles of a 10 MHz signal is generated by the
page 1.
transceiver. This 10 MHz signal, also called the Heartbeat,
assures the continued functioning of the collision circuitry.
The SQE signal is passed on to the MAC via the COL sig-
nal and is represented as a pulse.
3.1 Twisted Pair Functional Description
3.1.1 Smart Squelch
The Smart Squelch is responsible for determining when
valid data is present on the differential receive inputs
(RXI±). The Twisted Pair Transceiver (TPT) implements an
intelligent receive squelch on the RXI± differential inputs to
ensure that impulse noise on the receive inputs will not be
mistaken for a valid signal.
3.1.3 Link Detector/Generator
The link generator is a timer circuit that generates a link
pulse as defined by the 10BASE-T specification that will be
sent by the transmitter section. The pulse which is 100ns
wide is transmitted on the transmit output, every 16ms, in
the absence of transmit data. The pulse is used to check
the integrity of the connection to the remote MAU.
The squelch circuitry employs a combination of amplitude
and timing measurements to determine the validity of data
on the twisted pair inputs. The operation of the smart
squelch is shown in Figure 8.
The link detection circuit checks for valid pulses from the
remote MAU and if valid link pulses are not received the
link detector will disable the twisted pair transmitter,
receiver and collision detection functions.
>200ns
<150ns <150ns
3.1.4 Jabber
The Jabber function disables the transmitter if it attempts to
transmit a much longer than legal sized packet. The jabber
timer monitors the transmitter and disables the transmis-
sion if the transmitter is active for greater than 20-30ms.
The transmitter is then disabled for the entire time that the
ENDEC module's internal transmit is asserted. The trans-
mitter signal has to be deasserted for approximately 400-
600 ms (the unjab time) before the Jabber re-enables the
transmit outputs.
VSQ+
VSQ+
(reduced)
VSQ+
(reduced)
VSQ+
start of packet
end of packet
There is also a jabber disable bit in each of the port con-
trol/status registers which when activated, disables the jab-
ber function.
Figure 8. Twisted Pair Squelch Operation Diagram
The signal at the start of packet is checked by the smart
squelch and any pulses not exceeding the squelch level
3.1.5 Transmit Driver
(either positive or negative, depending upon polarity) will The transmit driver function utilizes the internal filters to
be rejected. Once this first squelch level is overcome cor- provide a properly matched and wave shaped output which
rectly the opposite squelch level must then be exceeded directly drives the isolation transformer/choke.
within 150ns. Finally, the signal must exceed the original
squelch level within an additional 150ns to ensure that the
3.1.6 Transmit Filter
There is no need for external filters on the twisted pair
transmit interface because the filters are integrated. Only
an isolation transformer and impedance matching resistors
are needed for the transmit twisted pair interface (see
Figure 5). The transmit filter ensures that all the harmonics
in the transmit signal are attenuated by at least 27dB. The
transmit signal requires a 1:2 (1 on the chip side and 2 on
the cable side) isolation transformer.
input waveform will not be rejected. The checking proce-
dure results in the loss of typically three bits at the begin-
ning of each packet.
Only after all these conditions have been satisfied will a
control signal be generated to indicate to the remainder of
the circuitry that valid data is present. At this time, the
smart squelch circuitry is reset.
Valid data is considered to be present until squelch level
has not been generated for a time longer than 150ns, indi-
cating End of Packet. Once good data has been detected
the squelch levels are reduced to minimize the effect of
noise causing premature End of Packet detection.
3.2 ENDEC Module
The ENDEC consists of two major blocks:
— The Manchester encoder accepts NRZ data from the
controller, encodes the data to Manchester, and trans-
mits it differentially to the transceiver, through the differ-
ential transmit driver.
3.1.2 Collision Detect
A collision is detected on the twisted pair cable when the
receive and transmit channels are active simultaneously. If
the ENDEC is receiving when a collision is detected (AUI
only) it is reported to the MAC block immediately (through
the COL signal). If, however, the ENDEC is transmitting
when a collision is detected the collision is not reported
until seven bits have been received while in the collision
state. This prevents a collision being reported incorrectly
— The Manchester decoder receives Manchester data
from the transceiver, converts it to NRZ data and recov-
ers clock pulses and sends them to the controller.
3.2.1 Manchester Encoder and Differential Driver
The encoder begins operation when the Transmit Enable
input (TXE) goes high and converts the clock and NRZ
data to Manchester data for the transceiver. For the dura-
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3.0 Detailed Functional Description (Continued)
tion of TXE remaining high, the Transmit Data (TXD) is 3.3.2 AUI/TP AutoSwitching - Port 1
encoded for the transmit-driver pair (TX±). TXD must be
The AUI/TP autoswitching lets the transceiver auto-switch
valid on the rising edge of Transmit Clock (TXC). Transmis-
sion ends when TXE goes low. The last transition is always
positive; it occurs at the center of the bit cell if the last bit is
a one, or at the end of the bit cell if the last bit is a zero.
between the AUI and TP outputs. At power up, the
autoswitch function is enabled (AUTOSW bit = 1). When
the auto-switch function is enabled, it allows the transceiver
to automatically switch between TP and AUI outputs. If
there is an absence of link pulses, the transceiver will
switch to AUI mode. Similarly, when the transceiver starts
detecting link pulses it will switch to TP mode. The switch-
ing from one mode to the next is only done after the current
packet has been transmitted or received. If the twisted pair
output is jabbering and it gets into the link fail state, then
the switch to AUI mode is made only after the jabbering
has stopped (this includes the time it takes to unjab). Also,
if TP mode is selected, transmit packet data will only be
driven by the twisted pair outputs and the AUI transmit out-
puts will remain idle. Similar behavior applies when AUI
mode is selected. In TPI mode, the twisted pair drivers will
continue to send link pulses, however, no packet data will
be transmitted. It must also be noted that when switching
from TP to AUI mode, it might take a few msec to com-
pletely power-up the AUI before it becomes fully opera-
tional. Switching in the opposite direction (AUI to TP) does
not have this power-up time, since the TP section is
already powered (the twisted pair transmit section still
sends link pulses in AUI mode).
3.2.2 Manchester Decoder
The decoder consists of a differential receiver and a PLL to
separate the Manchester encoded data stream into inter-
nal clock signals and data. Once the input exceeds the
squelch requirements, Carrier Sense (CRS) is asserted off
the first edge presented to the decoder. Once the decoder
has locked onto the incoming data stream, it provides data
(RXD) and clock (RXC) to the MAC.
The decoder detects the end of a frame when no more
mid-bit transitions are detected. Within one and a half bit
times after the last bit, carrier sense is de-asserted.
Receive clock stays active for at least five more bit times
after CRS goes low, to guarantee the receive timings of the
controller.
The GATERXC bit, D0, in the Global Control and Status
Register, controls the receive clock (RXC) gated function.
This allows the selection between 5 RXCs after the deas-
sertion of carrier sense (CRS) or continuous RXCs after
the deassertion of CRS. The GATERXC function which is
programmable through the serial management interface is
also available via a strap option. The default mode is to
enable 5 RXCs after the deassertion of CRS. If a 2.7 k
resistor is connected to the COL[4] pin (and the device
reset), then the continuous RXCs mode is enabled. If the
GATERXC mode is configured through the strap option, a
register write via the serial management interface to the
GATERXC control bit in the Global Control Register will be
ignored (this bit only). A read of this register will always
show the default value for this bit (5 RXCs) even though
continuous RXCs may have been programmed through the
strap option. All other bits are read/write as normal.
3.3.3 Full Duplex Mode
The full duplex mode is supported by the transceiver being
able to simultaneously transmit and receive without assert-
ing collision. The ENDEC has been implemented such that
it can encode and decode simultaneously and also be
robust enough to reject crosstalk noise with both transmit
and receive channels enabled.
The full duplex feature has two modes of operation. The
first option (normal FDX mode), allows full duplex configu-
ration of the ports only after a reset (through the FDX[4:1]
pins). The FDX[4:1] pins are sampled during reset to deter-
mine which ports to configure into full duplex mode.
Changing the logic state on the FDX[4:1] pins will not take
affect until a reset is performed. A logic ‘0’ enables full
duplex and a logic ’1’ enables simplex mode. In addition,
the full duplex capability of a port can also be changed
dynamically by writing the FDX bit (D12) of the Port Control
Register via the Mgmt Interface.
3.2.3 Collision Translator
When in AUI Mode and the external Ethernet transceiver
detects a collision, it generates a 10 MHz signal to the dif-
ferential collision inputs (CD ±) of the Quad Transceiver.
When these inputs are detected active, the transceiver
asserts COL which signals the MAC controller to back off
its current transmission and reschedule another one.
The second option (enhanced FDX mode), allows chang-
ing the full duplex configuration of each port dynamically
through the FDX[4:1] pins. As soon as the logic state on
the FDX[4:1] pins are changed, the corresponding ports full
duplex mode will be enabled or disabled.
The differential collision inputs are terminated the same
way as the differential receive inputs. The squelch circuitry
is the same, rejecting pulses with levels less than -175 mV.
3.3 Additional Features
3.3.1 Transceiver Loopback
In order to select the desired full duplex mode, the COL[2]
pin has a strapping feature. The default is normal full
duplex mode. If enhanced full duplex mode is desired, then
a 2.7k pull-down resistor is required on the COL[2] pin.
During reset, the COL[2] pin is sampled to determine the
correct full duplex mode configuration.
When diagnostic loopback is programmed (in twisted pair
mode), the transceiver redirects its transmitted data back
into its receive path. The transmit driver and receive input
circuitry are disabled in diagnostic loopback mode, hence,
the transceiver is isolated from the network cable. This
allows for diagnostic testing of the data path all the way up
to the transceiver without transmitting or being interrupted
by the media. This test can be performed regardless of the
link status (i.e. a twisted pair cable does not have to be
connected to perform transceiver loopback).
Regardless of the full duplex mode, the logic state of the
FDX[4:1] pins are sampled during reset to determine a
port’s initial configuration for full duplex capability.
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3.0 Detailed Functional Description (Continued)
CRS
RXC1
RXC2
2
3
4
5
1
RXD
Note 1: Continuous receive clock mode. In this mode, when CRS is deasserted, at least 5 RXCs are generated. RXC will go to idle until the RXC can be
switched to an internal free running 10 MHz signal. Conversely, when CRS is asserted, RXC will go to idle. It remains idle until the decoder is able to lock
onto the incoming data stream and generate the recovered clock.
Note 2: 5 Receive clock mode. In this mode, when CRS deasserts, at least 5 RXCs are generated before RXC goes to idle. RXC will remain in idle until the
next received packet.
Figure 9. Receive Clock Timing - 5 RXC Mode vs Continuous RXC Mode
3.3.4 JTAG Boundary Scan
of the knee in a 5M waveform). If resistors are used to
change the differential output voltage, then it is recom-
mended that the same value resistor be used for both pins
and both pins are either pulled-up or pulled-down. All IEEE
transmitter electrical characteristics should be verified after
adding resistors to REQ and RTX. Based on device charac-
terization, it is recommended that 47 kΩ pull down resistors
be used for both REQ and RTX in order to meet the IEEE
802.3 differential output voltage specification.
The DP83924A supports JTAG Boundary Scan per IEEE
1149.1 via test clock (TCK), test data input (TDI), test data
output (TDI), test mode select (TMS), and test reset
(TRST).
3.3.5 Strapping Options
Table 9 shows the various strapping options and the asso-
ciated pins used to configure the device at power-up.
These pins are sampled during reset. These pins have
internal pull-ups, if the default modes are desired, no exter-
nal resistors are required. A 2.7 kΩ pull down resistor(s)
are required to select non-default modes. If some type of
control logic is used to select the non-default modes,
instead of pull down resistors, then the level on the strap-
ping pins must be maintained for approximately 10 clocks
after the RESET signal deasserts.
RTX
REQ
3.3.6 REQ and RTX
These pins can change the twisted pair differential output
voltage amplitude. By adding pull-up resistors, the differen-
tial output voltage will increase. And adding pull down
resistors, the differential output voltage will decrease. RTX
controls the amplitude of the output waveform and REQ
controls the waveform equalization (pre-emphasis, location
Figure 10. 5M Waveform Differential Output Voltage
Table 9. Strapping Option Description
Default ‘1’ ‘0’
Continuous Selects the # of RXCs after CRS deassertion
Pin Name
COL[4]
Function
Comments
Gate RXC
5 RXCs
COL[3]
Rx Filter Select
Disabled
Enabled
Enables/disables the Rx filter. Suggest en-
able
COL[2]
Full Duplex Mode Select
LED Mode Select
Normal
Normal
Address
None
Enhanced Selects normal or enhanced full duplex mode
Enhanced Selects normal or enhanced LED mode
COL[1]
CRS[3:1]
FDX[4:1]
Transceiver Address Select
Per Port Full Duplex Select
Address
Sets the tcvr’s address for MII access
Full Duplex Selects full or half duplex configuration per
port (no internal pull-ups)
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4.0 Register Descriptions
4.1 Register Map and Descriptions
The following is an overall register map for the transceiver/ENDEC. There are two groups of registers. The first group pro-
vides individual port control which configures and reports status for functions applicable on a port basis. The second
group provides global control which enables configuration of operations that are common to all the ports.
Table 10. DP83924A Register Map Accessible via the Management Interface
Register Address
Name
Description
Access
R/W
R/W
R/W
R/W
R
00H
Port 1 Control/Status
Port 2 Control/Status
Port 3 Control/Status
Port 4 Control/Status
Reserved
Configuration setting and Operational Status for Port 1.
Configuration setting and Operational Status for Port 2.
Configuration setting and Operational Status for Port 3.
Configuration setting and Operational Status for Port 4.
reserved
01H
02H
03H
04H - 07H
08H
Global Control and status Provides global reset and interrupt configuration capabilities. R/W
09H - 1EH
1FH
Reserved
reserved
R
Test Control
Controls test functions for manufacturing test of the device.
User MUST NOT access this register.
R/W
Table 11. Port N Control/Status Register, addr = 00h - 03h (port 1 to port 4)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1
D0
RST LPBK resv FDX JABE resv resv LNKDIS ERR resv resv resv resv POLST LNK ST JAB ST
This register controls the various operating modes available for the transceiver and ENDEC functions. There is one reg-
ister per ENDEC/Transceiver on this device.
Reset
Bit (Default)
Value
Name
Description
Type
RST
D15
0
0
0
Software Reset/Enable: If this bit is set, then this port’s transceivers and ENDEC
modules are reset back to their idle state. If this bit is reset, then normal operation is
expected.
R/W
LPBK D14
Loopback Transceiver: If this bit is set, then this port’s 10base-T transceiver will loop R/W
data from near the network interface pins back to the MAC, to test the operation of the
transceiver. If this bit is reset, loopback is disabled.
resv
FDX
D13
D12
Reserved: Must be written with ‘0’.
R/W
strap Full Duplex Operation: If this bit is set, then the ports full duplex capability is enabled. R/W
If this bit is reset, then half-duplex is enabled.
JABE D11
1
Jabber Enable: If this bit is set, then the ports jabber function is enabled. If this bit is R/W
reset, then the jabber feature is disabled.
resv D10-9
LNKDIS D8
0
0
Reserved: Must be written with ‘0’.
R
Link Disable: If this bit is set, this port’s link detection circuitry will be disabled. If this R/W
bit is reset, then normal link operation is enabled.
ERR
D7
0
LED Error: If this bit is set, this port’s status LED will go solid. If this bit is reset, normal R/W
LED operation is resumed.
resv
D6-3
0
1
Reserved: Must be written with ‘0’.
R
R
POL ST D2
Polarity Status: This bit is set when bad polarity has been detected. Status bit, read-
only.
LNK ST D1
JAB ST D0
1
0
Link Status: This bit is set when the port is in the link-fail state. Status bit, read-only.
R
R
Jabber Status: This bit is set when the port is in the jabber condition. Status bit, read-
only.
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4.0 Register Descriptions (Continued)
Table 12. Global Control/Mask Register, addr = 08h
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D15 D14
D13
D12
D1
D0
resv resv LNKJABINT AUTOSW TPIAUI HBEN ENPOLSW resv resv resv resv resv resv KLED LJINTMASK GATERXC
This register controls the various operating modes available for the transceiver and ENDEC functions. This register will
affect the operation of ALL ports of the DP83924A.
Reset
Bit (Default)
Value
Name
Description
Reserved: Must be written with ‘0’.
Type
resv
D15-14
0
0
R
R
LNKJABINT D13
Link Jabber Interrupt Status: This bit is set when an interrupt occurs due to a
link status change or a jabber condition on any port. This bit is cleared on a reg-
ister read (the interrupt is also cleared).
AUTOSW
TPIAUI
D12
D11
1
1
Auto Switching: If this bit is set, automatic selection of TPI or AUI on port 1 is R/W
enabled. If this bit is reset, port 1 configuration is determined by the TPIAUI bit.
TPI Select: If this bit is set, then port 1 is placed into TP mode. If this bit is reset, R/W
then port 1 is configured for AUI mode.
This bit is ignored if the AUTOSW bit is set.
HBEN
D10
D9
1
1
Hearbeat Enable: If this bit is set, then heartbeat is enabled. If this bit is reset, it R/W
is disabled for all ports.
ENPOLSW
Enable Polarity Switching: If this bit is set, then auto polarity detection and cor- R/W
rection is enabled for all ports. If this bit is reset, it is disabled.
resv
D[8:3]
D2
0
0
Reserved: Must be written with ‘0’.
R
KLED
Enhanced LED Mode: If this bit is set, “enhanced” LED mode is selected. If this R/W
bit is reset, “normal” LED mode is selected.
LJINTMASK D1
0
1
Link Jabber Interrupt Mask: If this bit is set, an interrupt will NOT be generated R/W
on a link-fail or jabber condition experienced on any port. If this bit is reset, inter-
rupt generation is enabled.
GATERXC
D0
RXC Gated: If this bit is set, five RXC clocks are forced after CRS is deasserted. R/W
If this bit is reset, then RXC clocks are continuous after CRS deasserts.
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5.0 Application Information
1:1
1
16
5.1 Magnetics Specifications
Rx
Tx
This section describes the required magnetics to be used
with the Quad Transceiver. The external filter/transformer
used in conventional twisted pair ports is now replaced by
a transformer. By integrating the transmit filter, the trans-
former is the only magnetics required. In this configuration,
a transformer with 1:2 turn ratio on the transmit path and a
1:1 turn ratio on the receive path is required. The system
designer must determine if a choke is required. Careful lay-
out may eliminate the need.
2
3
15
14
4
13
12
1:2
1:2
IC SIDE
NETWORK SIDE
5
Tx
Rx
The following is a list of suppliers that may provide mag-
netic components with the electrical specifications listed in
Table 13. This is not an exclusive list, and National Semi-
conductor makes no warranty as to the suitability of any of
the magnetics. It is the responsibility of the user to verify
the performance of any magnetics prior to production use.
6
7
11
10
8
9
1:1
BEL FUSE
HALO Electronics
PCA
Figure 11. Typical Dual Transformer Pinout
PULSE Engineering
VALOR Electronics
— Each trace of a differential pair (i.e. TX+, TX-) between
the DP83924A and the transformer module should be as
follows:
Table 13. Transformer Electrical Specifications
Rx + pair trace lengths should be matched. The width
should be 8 mils min, with a trace-to-trace spacing of 8
mils min.
Parameter
Pins
Value
Open Circuit In- 3-4, 5-6
ductance (OCL)
50 µH (min)
Tx + pair trace lengths should be matched. The width
should be 15 mils min, with a trace-to-trace spacing of 15
mils min (if the total trace length between the DP83924A
and the RJ45 connector is less than 1.5”, then 8 mil
spacing and width can be used).
1-2, 7-8, 9-10, 11- 200 µH (min)
12, 13-14, 15-16.
Inter-winding Ca- 1-2 to 15-16,
12 pF (max)
0.3 µH (max)
0.35Ω (max)
pacitance (Cww
)
3-4 to 13-14
5-6 to 11-12
7-8 to 9-10
The Tx and Rx spacing should be 15 mils min.
— The source termination (R,C) must be placed as close to
the device as possible.
Leakage Induc- 1-2, short 15-16
tance (LL)
3-4, short 13-14
5-6, short 11-12
7-8, short 9-10
— 100Ω traces between the transformer module and the
RJ45 connector.
Analog Power and Ground Circuit
DC Resistance 3-4, 5-6
(DCR)
Recommended Low Pass Filter for the Internal PLL and
WSPLL Circuitry to eliminate any power supply injected
noise. This applies to both the PLL and WS supply pins.
This should improve jitter performance. Refer to Figure 10
and Figure 11.
1-2, 7-8, 9-10, 15- 0.5Ω (max)
16.
11-12, 13-14
1.0Ω (max)
High Potential
1-2 to 15-16
3-4 to 13-14
5-6 to 11-12
7-8 to 9-10
2000 Vrms for 1
min.
Bypass for all other supplies should use a 0.01 µF capacitor.
Additional bypass for the VDD_TPI supplies should use a
1.0 µF capacitor.
5.2 Layout Considerations
Power Plane
DP83924A
10Ω
— Minimize signal traces which traverse across multiple is-
lands to reduce reflections and impedance mismatches.
Therefore, the ground should extend from the
WSPLL_VCC
PLL_VCC
DP83924A to under the magnetics (transformer).
0.1 µF
22 µF
VCC
— Use a single power plane.
Ground Plane
— Use a single ground plane, similar to the Power Plane.
DP83924A Placement and Routing
GND
— The DP83924A should be placed as close as possible to
the external transformer module/RJ45 connector.
Figure 12. WSPLL and PLL VCC Circuit Diagram
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17
6.0 AC and DC Electrical Specifications
Absolute Maximum Ratings
Recommended Operating Conditions
Supply Voltage (VCC
)
-0.5V to + 7.0V Supply voltage (VCC
)
-0.5V to VCC + 0.5V Ambient Temperature
-0.5V to VCC + 0.5V
5 Volts + 5%
DC Input Voltage (VIN)
0°C to 70°C
DC Output Voltage (VOUT
)
Storage Temperature Range (TSTG
)
-65°C to + 150°C
Note: Absolute maximum ratings are those values beyond
which the safety of the device cannot be guaranteed. They
are not meant to imply that the device should be operated
at these limits.
Power Dissipation (PD)
1.6W
Lead Temperature (TL)
(Soldering, 10 sec.)
260°C
ESD Rating
1.5 kV
(RZAP = 1.5k, CZAP = 120 pF)
DC Specifications TA = 0˚C to 70˚C, VCC = 5V + 5%.
Symbol
Parameter
Conditions
Min
Max
Units
DIGITAL PINS (LED_CLK,LED_DATA,MDIO,MDC,CRS,RXC,RXD,COL,TXE,TXD,TXC,X1,RESET,LINK, INT,TCK,TDI,TDO,TMS,TRST)
VOH1
VOH2
VOL1
VOL2
VIH
Minimum High Level Output Voltage
Minimum High Level Output Voltage
Maximum Low Level Output Voltage
Maximum Low Level Output Voltage
Minimum High Level Input Voltage
Maximum Low Level Input Voltage
Pull-up Resistor Current (Note 1, 3)
Input Leakage (Note 2)
IOH = -2 mA (Except MDIO and INTz)
IOH = -8 mA (MDIO Only)
3.0
3.0
V
V
IOL = 2 mA (except MDIO and INTz)
IOL = 8 mA (MDIO and INTZ Only)
0.4
0.4
V
V
2.0
V
VIL
0.8
-100
10
V
IIN
VIN = GND, VCC=5V
-250
-10
µA
µA
µA
mA
IIL
VIN = VCC or GND
IOZ
TRI-STATE Output Leakage Current
Average Operating Supply Current
VOUT = VCC or GND
-10
10
ICC
TXU + Transmitting into 50Ω (Note 4)
320
AUI INTERFACE PINS (TX±, RX±, and CD±)
VOD
VDS
Diff. Output Voltage (TX±)
78Ω Termination
± 550
± 1200
mV
mV
Diff. Squelch Threshold (RX± and
CD±)
-160
-300
TWISTED PAIR INTERFACE PINS
VODT TXU + Differential Output Voltage
100Ω Load @RJ45 Connector
4.4
5.6
Vp-p
mV
VSRON1 Receive Threshold Turn-On Voltage
10BASE-T Mode
± 300
± 585
VSROFF Receive Threshold Turn-Off Voltage
± 175
± 300
mV
Note 1: CRS[4:1], COL[4:1], TDI, TMS, TRST
Note 2: MDIO, MDC, TXE[4:1]. TXD[4:1], X1, RESET, TCK
Note 3: Internal pull-up resistor typically 20 kΩ - 50 kΩ
Note 4: This includes the current consumed off chip by the load. Typically, the power dissipated off-chip is about 76 mW/port so the on-chip power being
dissipated will be: [Total power dissipation (5.0v x 320ma)] - [the off-chip power dissipation (4 ports x 76 mW/port)] = 1.3W
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6.0 AC and DC Electrical Specifications (Continued)
AC Switching Specifications TA = 0˚C to 70˚C, VCC = 5V ± 5%
LED Interface Timing
t1
t0
LED_CLK
t2
LED_DATA
t3
Symbol
Parameter
LED Clock Duty Cycle
Min
Max
Units
t0
40
60
%
t1
t2
t3
LED Clock Cycle Time
900
25
1100
ns
ns
ns
LED_Data Valid to LED_Clk
LED_Data Valid from LED_Clk
25
Reset and Strapping Timing
X1
t5
t4
RESETz
Symbol
Parameter
Min
Max
Units
t4
Reset Pulse Width (X1 Must be Active During
RESETz)
30
-
X1 Clks
t5
X1 Duty Cycle
40
60
%
19
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6.0 AC and DC Electrical Specifications (Continued)
Management Interface Timing
t6
t7
MDC
t8
MDIO (INPUT)
t9
MDC
t10
MDIO (OUTPUT)
Symbol
Parameter
Min
Max
Units
t6
MDC Frequency
MDC Duty Cycle
2.5
MHz
t7
t8
40
10
10
60
%
ns
ns
ns
MDIO (Input) Set Up to MDC Rising Edge
MDIO (Input) Hold MDC from Rising Edge
MDC to MDIO (Output) Delay Time
t9
t10
300
20
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6.0 AC and DC Electrical Specifications (Continued)
Twisted Pair Start of Transmit Packet
t18
t17
TXC
t11
t16
t15
TXE
t13
t12
TXD
t14
TXU±
Symbol
Parameter
Min
Max
Units
t11
TXE Setup Time to TXC Rising Edge
20
ns
t12
t13
t14
t15
t16
t17
t18
TXD Setup Time to TXC Rising Edge
TXD Hold Time from TXC Rising Edge
TXU Start-up Delay from TXC Rising Edge
TX Prop Delay (TXC Rising Edge to TXU+)
TXC Low Time (Note 1)
20
5
ns
ns
ns
ns
ns
ns
%
400
350
40
40
40
TXC High Time (Note 1)
TXC Duty Cycle (Note 1)
60
Note 1: This specification is provided for information only and is not tested
21
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6.0 AC and DC Electrical Specifications (Continued)
Twisted Pair Transmit End of Packet
TXC
TXE
,
0 1
Last Bit
t19
TXD
t20
0
0
TXU±
‘0’ Ending Packet
t21
1
1
TXU±
‘1’ Ending Packet
Symbol
Parameter
TXE Hold Time from TXC Rising Edge
Min
Max
Units
t19
t20
t21
5
ns
TXU+ End of Packet Hold Time with “0” Ending Bit
TXU+ End of Packet Hold Time with “1” Ending Bit
225
225
ns
ns
22
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6.0 AC and DC Electrical Specifications (Continued)
Twisted Pair Start of Receive Packet
1st bit decoded
1
0
1
RXI±
t22
t26
CRS
RXC
t23
t24
RXD
t25
Symbol
Parameter
Min
Max
Units
t22
Carrier Sense Turn On Delay (RXI± to CRS)
Decoder Acquisition Time (Note 1)
Receive Data Valid to RXC Rising Edge
Receive Data Invalid From RXC Rising Edge
Receive Data Bit Delay
550
ns
t23
t24
t25
t26
2200
ns
ns
ns
ns
25
25
375
Note 1: This parameter includes TPI smart squelch turn on time plus ENDEC data acquisition time.
23
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6.0 AC and DC Electrical Specifications (Continued)
Twisted Pair End of Receive Packet
IDLE
1
0
1
RXI±
t28
RXC
CRS
t27
Symbol
Parameter
Carrier Sense Turn Off Delay
Number of RXCs after CRS Low (Note 1)
Min
Max
Units
t27
400
ns
t28
5
Bit Times
Note 1: This only applies when the GATERXC bit, D0, in the Global Configuration Register is set.
Link Pulse Timing
t29
t30
TXU±
Symbol
Parameter
Min
Max
Units
t29
Link Integrity Output Pulse Width
Time between Link Output Pulses
80
130
ns
t30
8
24
ms
Heartbeat Specifications
TXE
TXC
COL
t32
t31
Symbol
Parameter
Min
Max
Units
t31
t32
CD Heartbeat Delay
CD Heartbeat Duration
600
1600
ns
500
1500
ns
24
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6.0 AC and DC Electrical Specifications (Continued)
Jabber Specifications
TXE
t33
t34
TX(U)±
COL
Symbol
Parameter
Jabber Activation Time
Jabber Deactivation Time
Min
Max
Units
t33
20
60
ms
t34
250
750
ms
AUI Start of Packet Transmit Timing
TXC
t35
t39
TXE
TXD
TX±
t37
t36
t38
Symbol
Parameter
Min
Max
Units
t35
t36
t37
t38
t39
TXE Setup Time to TXC Rising Edge
TXD Setup Time to TXC Rising Edge
TXD Hold Time from TXC Rising Edge
TX+ Start-up Delay from TXC Rising Edge
TX Prop Delay (TXC Rising Edge to Tx+)
20
ns
20
5
ns
ns
ns
ns
300
300
25
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6.0 AC and DC Electrical Specifications (Continued)
AUI End of Packet Transmit Timing
TXC
,
1
0 1
0
Last Bit
TXD
TXE
t40
t41
0
0
TX±
‘0’ Ending Packet
t42
1
1
TX±
‘1’ Ending Packet
Symbol
Parameter
TXE Hold Time from TXC Rising Edge
Min
Max
Units
t40
5
ns
t41
t42
TX+ End of Packet Hold Time with “0” Ending Bit
TX+ End of Packet Hold Time with “1” Ending Bit
200
200
ns
ns
26
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6.0 AC and DC Electrical Specifications (Continued)
AUI Start of Packet Receive Timing
1st bit
decoded
1
0
1
RX±
t43
CRS
t44
RXC
RXD
t45
t46
Symbol
Parameter
Min
Max
Units
t43
Carrier Sense Turn On Delay (RX± to CRS)
200
ns
t44
t45
t46
Decoder Acquisition Time
2200
ns
ns
ns
Receive Data Valid to RXC Rising Edge
Receive Data Invalid from RXC Rising Edge
25
25
27
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6.0 AC and DC Electrical Specifications (Continued)
AUI End of Packet Receive Timing
1
st bit
decoded
1
1
0
Idle
RX±
t48
RXC
t47
CRS
Symbol
Parameter
Min
Max
Units
t47
Carrier Sense Turn Off Delay
Number of RXCs after CRS Low (Note 1)
400
ns
t48
5
Bit Times
Note 1: This only applies when GATERXC, bit D0, in the Global Configuration Register is set.
Collision Specifications
CD±
t49
t50
COL
Symbol
Parameter
Min
Max
Units
t49
Collision Turn On Delay (CD± to COL)
600
ns
t50
Collision Turn Off Delay (CD± to COL)
900
ns
28
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6.0 AC and DC Electrical Specifications (Continued)
Twisted Pair Interface Load
Network Test Loads
Attachment Unit Interface Load
TX± Output Test Load
TXU+
TXU-
TX+
TX-
50Ω
27 µH
78 W
TX± is after the secondary
side of the transformer.
TXU± is after the secondary
side of the transformer.
AC Timing Test Condition
All measurement taken with the external transformer in place.
Reference
Limits
Input Levels (Digital Pins, tR = tF = 3ns)
0V - 3.0V
Input/Output Reference Levels (Digital Pins)
Differential Input Reference Levels
1.5V
2.0 Vp-p
Differential Input/Output Reference Levels
50% of Differential
29
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7.0 Physical Dimensions inches (millimeters) unless otherwise noted
Molded Plastic Quad Flat Package, JEDEC
Order Number DP83924AVCE
NS Package Number VCE100A
LIFE SUPPORT POLICY
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and whose failure to per-
form, when properly used in accordance with instruc-
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expected to result in a significant injury to the user.
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
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Tel: 1-800-272-9959
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