DP8392C [NSC]
CTI Coaxial Transceiver Interface; CTI同轴收发器接口
| 型号： | DP8392C |
| 厂家： | 
National Semiconductor |
| 描述： | CTI Coaxial Transceiver Interface |
| 文件： | 总12页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1995
DP8392C/DP8392C-1 CTI
Coaxial Transceiver Interface
General Description
Features
Y
Compatible with Ethernet II, IEEE 802.3 10Base5 and
10Base2 (Cheapernet)
The DP8392C Coaxial Transceiver Interface (CTI) is a coax-
ial cable line driver/receiver for Ethernet/Thin Ethernet
(Cheapernet) type local area networks. The CTI is connect-
ed between the coaxial cable and the Data Terminal Equip-
ment (DTE). In Ethernet applications the transceiver is usu-
ally mounted within a dedicated enclosure and is connected
to the DTE via a transceiver cable. In Cheapernet applica-
tions, the CTI is typically located within the DTE and con-
nects to the DTE through isolation transformers only. The
CTI consists of a Receiver, Transmitter, Collision Detector,
and a Jabber Timer. The Transmitter connects directly to a
50 ohm coaxial cable where it is used to drive the coax
when transmitting. During transmission, a jabber timer is ini-
tiated to disable the CTI transmitter in the event of a longer
than legal length data packet. Collision Detection circuitry
monitors the signals on the coax to determine the presence
of colliding packets and signals the DTE in the event of a
collision.
Y
Integrates all transceiver electronics except signal
power isolation
&
Y
Y
Y
Innovative design minimizes external component count
Jabber timer function integrated on chip
Externally selectable CD Heartbeat allows operation
with IEEE 802.3 compatible repeaters
Y
Precision circuitry implements receive mode collision
detection
Y
Y
Squelch circuitry at all inputs rejects noise
Designed for rigorous reliability requirements of
IEEE 802.3
Y
Standard Outline 16-pin DIP uses a special leadframe
that significantly reduces the operating die temperature
Table of Contents
1.0 System Diagram
The CTI is part of a three chip set that implements the com-
plete IEEE 802.3 compatible network node electronics as
shown below. The other two chips are the DP8391 Serial
Network Interface (SNI) and the DP8390 Network Interface
Controller (NIC).
2.0 Block Diagram
3.0 Functional Description
3.1 Receiver Functions
3.2 Transmitter Functions
3.3 Collision Functions
The SNI provides the Manchester encoding and decoding
functions; whereas the NIC handles the Media Access Pro-
tocol and the buffer management tasks. Isolation between
the CTI and the SNI is an IEEE 802.3 requirement that can
be easily satisfied on signal lines using a set of pulse trans-
formers that come in a standard DIP. However, the power
isolation for the CTI is done by DC-to-DC conversion
through a power transformer.
3.4 Jabber Functions
4.0 Typical Applications
5.0 Connection Diagrams
6.0 Pin Descriptions
7.0 Absolute Maximum Ratings
8.0 DP8392C Electrical Characteristics
9.0 DP8392C-1 Electrical Characteristics
10.0 Switching Characteristics
11.0 Timing and Load Diagram
1.0 System Diagram
TL/F/11085–1
IEEE 802.3 Compatible Ethernet/Cheapernet Local Area Network Chip Set
C
1995 National Semiconductor Corporation
TL/F/11085
RRD-B30M115/Printed in U. S. A.
2.0 Block Diagram
TL/F/11085–2
FIGURE 1. DP8392C Block Diagram
3.0 Functional Description
The CTI consists of four main logical blocks:
Receiver then stays off only if within about 1 ms, the DC
level from the low pass filter rises above the DC squelch
threshold. Figure 2 illustrates the Receiver timing.
a) the Receiver - receives data from the coax and sends it
to the DTE
The differential line driver provides ECL compatible signals
to the DTE with typically 3 ns rise and fall times. In its idle
state, its outputs go to differential zero to prevent DC stand-
ing current in the isolation transformer.
b) the Transmitter - accepts data from the DTE and trans-
mits it onto the coax
c) the Collision Detect circuitry - indicates to the DTE any
collision on the coax
3.2 TRANSMITTER FUNCTIONS
d) the Jabber Timer - disables the Transmitter in case of
longer than legal length packets
The Transmitter has a differential input and an open collec-
tor output current driver. The differential input common
mode voltage is established by the CTI and should not be
altered by external circuitry. The transformer coupling of
g
TX will satisfy this condition. The driver meets all IEEE
802.3/Ethernet Specifications for signal levels. Controlled
3.1 RECEIVER FUNCTIONS
The Receiver includes an input buffer, a cable equalizer, a
4-pole Bessel low pass filter, a squelch circuit, and a differ-
ential line driver.
The buffer provides high input impedance and low input ca-
pacitance to minimize loading and reflections on the coax.
g
rise and fall times (25 ns V 5 ns) minimize the higher
harmonic components. The rise and fall times are matched
to minimize jitter. The drive current levels of the DP8392C
meet the tighter recommended limits of IEEE 802.3 and are
set by a built-in bandgap reference and an external 1% re-
sistor. An on chip isolation diode is provided to reduce the
Transmitter’s coax load capacitance. For Ethernet compati-
ble applications, an external isolation diode (see Figure 4 )
may be added to further reduce coax load capacitance. In
Cheapernet compatible applications the external diode is
not required as the coax capacitive loading specifications
are relaxed.
The equalizer is a high pass filter which compensates for
the low pass effect of the cable. The composite result of the
maximum length cable and the equalizer is a flatband re-
sponse at the signal frequencies to minimize jitter.
The 4-pole Bessel low pass filter extracts the average DC
level on the coax, which is used by both the Receiver
squelch and the collision detection circuits.
The Receiver squelch circuit prevents noise on the coax
from falsely triggering the Receiver in the absence of the
signal. At the beginning of the packet, the Receiver turns on
when the DC level from the low pass filter is lower than the
DC squelch threshold. However, at the end of the packet, a
quick Receiver turn off is needed to reject dribble bits. This
is accomplished by an AC timing circuit that reacts to high
level signals of greater than typically 200 ns in duration. The
The Transmitter squelch circuit rejects signals with pulse
widths less than typically 20 ns (negative going), or with
b
levels less than 175 mV. The Transmitter turns off at the
end of the packet if the signal stays higher than 175 mV
b
for more than approximately 300 ns. Figure 3 illustrates the
Transmitter timing.
2
3.0 Functional Description (Continued)
3.3 COLLISION FUNCTIONS
The 10 MHz oscillator generates the signal for the collision
and heartbeat functions. It is also used as the timebase for
all the jabber functions. It does not require any external
components.
The collision circuitry consists of two buffers, two 4-pole
Bessel low pass filters (section 3.1), a comparator, a heart-
beat generator, a 10 MHz oscillator, and a differential line
driver.
The collision differential line driver transfers the 10 MHz sig-
g
Two identical buffers and 4-pole Bessel low pass filters ex-
tract the DC level on the center conductor (data) and the
shield (sense) of the coax. These levels are monitored by
the comparator. If the data level is more negative than the
sense level by at least the collision threshold (Vth), the colli-
sion output is enabled.
nal to the CD pair in the event of collision, jabber, or
heartbeat conditions. This line driver also features zero dif-
ferential idle state.
3.4 JABBER FUNCTIONS
The Jabber Timer monitors the Transmitter and inhibits
transmission if the Transmitter is active for longer than
20 ms (fault). It also enables the collision output for the fault
duration. After the fault is removed, The Jabber Timer waits
for about 500 ms (unjab time) before re-enabling the Trans-
mitter. The transmit input must stay inactive during the unjab
time.
At the end of every transmission, the heartbeat generator
creates a pseudo collision for a short time to ensure that the
collision circuitry is properly functioning. This burst on colli-
sion output occurs typically 1.1 ms after the transmission,
and has a duration of about 1 ms. This function can be dis-
abled externally with the HBE (Heartbeat Enable) pin to al-
low operation with repeaters.
TL/F/11085–3
FIGURE 2. Receiver Timing
TL/F/11085–4
FIGURE 3. Transmitter Timing
3
4.0 Typical Application
TL/F/11085–5
e
Note 1: T1 is a 1:1 pulse transformer, L
100 mH
FIGURE 4
Pulse Engineering (San Diego) Part No. 64103
Valor Electronics (San Diego) Part No.
LT6003 or equivalent
5.0 Connection Diagrams
TL/F/11085–16
Top View
Order Number DP8392CN
See NS Package Number N16E
TL/F/11085–6
Order Number DP8392CV
See NS Package Number V28A
FIGURE 5
4
6.0 Pin Descriptions
28-Pin PLCC
16-Pin DIP
Name
I/O
Description
*
a
b
2
3
1
2
CD
CD
O
Collision Output. Balanced differential line driver outputs from the collision detect
circuitry. The 10 MHz signal from the internal oscillator is transferred to these
outputs in the event of collision, excessive transmission (jabber), or during CD
Heartbeat condition. These outputs are open emitters; pulldown resistors to VEE
are required. When operating into a 78X transmission line, these resistors should
be 500X. In Cheapernet applications, where the 78X drop cable is not used,
higher resistor values (up to 1.5k) may be used to save power.
*
a
b
4
3
6
RX
RX
O
I
Receive Output. Balanced differential line driver outputs from the Receiver. These
outputs also require 500X pulldown resistors.
12
*
a
b
13
14
7
8
TX
TX
Transmit Input. Balanced differential line receiver inputs to the Transmitter. The
common mode voltage for these inputs is determined internally and must not be
externally established. Signals meeting Transmitter squelch requirements are
waveshaped and output at TXO.
15
9
HBE
I
I
I
Heartbeat Enable. This input enables CD Heartbeat when grounded, disables it
when connected to VEE.
a
b
18
19
11
12
RR
RR
External Resistor. A fixed 1k 1% resistor connected between these pins
establishes internal operating currents.
26
14
RXI
Receive Input. Connects directly to the coaxial cable. Signals meeting Receiver
squelch requirements are equalized for inter-symbol distortion, amplified, and
g
outputted at RX
.
28
1
15
16
TXO
CDS
O
I
Transmit Output. Connects either directly (Cheapernet) or via an isolation diode
(Ethernet) to the coaxial cable.
Collision Detect Sense. Ground sense connection for the collision detect circuit.
This pin should be connected separately to the shield to avoid ground drops from
altering the receive mode collision threshold.
16, 17
10
GND
VEE
Positive Supply Pin. A 0.1 mF ceramic decoupling capacitor must be connected
across GND and VEE as close to the device as possible.
5–11
4
5
Negative Supply Pins. In order to make full use of the 3.5W power dissipation
capability of this package, these pins should be connected to a large metal frame
area on the PC board. Doing this will reduce the operating die temperature of the
device thereby increasing the long term reliability.
20–25
13
e
e
e
g
DO
g
g
CI , RX
g
g
DI , TX
g
*IEEE names for CD
6.1 P.C. BOARD LAYOUT
2. The power supply layout to the CTI should be relatively
clean. Usually the CTI’s power is supplied directly by a
DC-DC converter. The power should be routed either
through separate isolated planes, or via thick PCB traces.
The DP8392C package is uniquely designed to ensure that
the device meets the 1 million hour Mean Time Between
Failure (MTBF) requirement of the IEEE 802.3 standard. In
order to fully utilize this heat dissipation design, the three
For the second consideration, the packaged DP8392 must
have a thermal resistance of 40 C–45 C/W to meet the full
0 C–70 C temperature range. The CTI dissipates more
V
EE
pins are to be connected to a copper plane which
should be included in the printed circuit board layout.
§
§
§
§
power when transmitting than while it is idle. In order to do
this the thermal resistance of the device must be 40 C–
There are two basic considerations in designing a PCB for
the DP8392C and C-1 CTI. The first is ensuring that the
layout does not degrade the electrical characteristics of the
DP8392, and enables the end product to meet the IEEE
802.3 specifications. The second consideration is meeting
the thermal requirements to the DP8392.
§
45 C/W. To meet this requirement during transmission, it is
§
recommended that a small printed circuit board plane be
connected to all V pins on the solder side of the PCB.
EE
The size of the trace plane depends on the package used
and the duty cycle of transmissions. For the DIP package
the plane should be connected to pins 4–5, 13, and the size
should be approximately 0.2 square inches for applications
Since the DP8392 is highly integrated the layout is actually
quite simple, and there are just a few guidelines:
1. Ensure that the parasitic capacitance added to the RXI
and TXO pins is minimized. To do this keep these signal
traces short, and remove any power planes under these
signals, and under any components that connect to these
signals. Figure 6 shows the component placement for the
DIP package. The PLCC component placement would be
similar, as shown in Figure 7.
k
where the duty cycle of the transmitter is very low ( 10%).
This would be typical of adapter or motherboard applica-
tions. In applications where the transmitter duty cycle may
be large (repeaters and external transceivers) the total area
2
should be increased to 0.4 in . Figure 6 illustrates a recom-
mended component side layout for these planes.
5
6.0 Pin Descriptions (Continued)
For the PLCC packaged DP8392, it is recommended that a
small printed circuit board V plane be connected to pins
EE
5–11, and a second one be connected to pins 20–25. To
reduce the thermal resistance to the required value, the
2
t
area of the plane on EACH set of pins should be 0.20 in
2
t
for applications with low transmitter duty cycle, and 0.4 in
for high transmit duty cycle applications. Figure 7 illustrates
a recommended component side layout for these planes.
TL/F/11085–14
Layout as viewed from component side
FIGURE 6. Typical Layout Considerations
for DP8392CN
(Not to Scale)
TL/F/11085–15
FIGURE 7. Recommended Layout and Dissipation Planes for DP8392CV (Not to Scale)
6
7.0AbsoluteMaximumRatings(Note 1)
Recommended Operating
Conditions
b
12V
Supply Voltage (V
)
EE
Package Power Rating at 25 C
§
3.5 Watts*
See Section 5
b
g
9v 5%
Supply Voltage (V
)
EE
(PC Board Mounted)
Derate linearly at the rate of 28.6 mW/ C
Ambient Temperature
0 to 70 C
§
§
§
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b
0 to 12V
Input Voltage
b
Storage Temperature
65 to 150 C
§ §
Lead Temp. (Soldering, 10 seconds)
260 C
§
*For actual power dissipation of the device please refer to section 7.0.
e b
e
0 to 70 C (Notes 2 & 3)
§
g
8.0 DP8392C Electrical Characteristics V
g
9V 5%, T
§
EE
A
g
All parameters with respect to CD and RX are measured after the pulse transformer except V
.
OC
Symbol
Parameter
Supply current out of V pinÐnon transmitting
Min
Typ
Max
Units
mA
mA
mA
mA
mA
V
b
b
I
I
I
I
I
85
130
180
EE1
EE2
RXI
EE
b
b
Supply current out of V pinÐtransmitting
EE
125
b
a
25
Receive input bias current (RXI)
2
Transmit output dc current level (TXO)
Transmit output ac current level (TXO)
Collision threshold (Receive mode)
37
41
45
TDC
TAC
g
28
I
TDC
b
b
b
1.58
V
CD
V
OD
V
OC
V
OB
V
TS
1.45
1.53
g
Differential output voltage (RX , CD
g
g
g
1200
)
550
mV
V
b
b
b
2.5
g
Common mode output voltage (RX , CD
g
)
1.5
2.0
g
Diff. output voltage imbalance (RX , CD
g
g
40
)
mV
mV
pF
b
b
b
300
g
Transmitter squelch threshold (TX
Input capacitance (RXI)
)
175
225
C
X
1.2
R
Shunt resistanceÐnon transmitting (RXI)
Shunt resistanceÐtransmitting (TXO)
100
KX
KX
RXI
R
TXO
10
e b
e
All parameters with respect to CD and RX are measured after the pulse transformer except V
g
9V 5%, T
9.0 DP8392C-1 Electrical Characteristics V
g
0 to 70 C (Notes 2 & 3)
§
§
EE
A
g
.
OC
Symbol
Parameter
Supply current out of V pinÐnon transmitting
Min
Typ
Max
Units
mA
mA
mA
mA
mA
V
b
b
I
I
I
I
I
85
130
180
EE1
EE2
RXI
EE
b
b
Supply current out of V pinÐtransmitting
EE
125
b
a
25
Receive input bias current (RXI)
2
Transmit output dc current level (TXO)
Transmit output ac current level (TXO)
Collision threshold (Receive mode)
37
41
45
TDC
TAC
g
28
I
TDC
b
b
b
1.58
V
CD
V
OD
V
OC
V
OB
V
TS
1.45
1.53
g
Differential output voltage (RX , CD
g
g
g
1200
)
550
mV
V
b
b
b
2.5
g
Common mode output voltage (RX , CD
g
)
1.5
2.0
g
Diff. output voltage imbalance (RX , CD
g
g
40
)
mV
mV
pF
b
b
b
275
g
Transmitter squelch threshold (TX
Input capacitance (RXI)
)
175
225
C
X
1.2
R
R
Shunt resistanceÐnon transmitting (RXI)
Shunt resistanceÐtransmitting (TXO)
100
7.5K
KX
KX
RXI
10
TXO
Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: All currents into device pins are positive, all currents out of device pins are negative. All voltages referenced to ground unless otherwise specified.
e
b
e
9V and T 25 C.
A
Note 3: All typicals are given for V
§
EE
7
e b
e
0 to 70 C (Note 3)
§
g
9V 5%, T
10.0 DP8392C Switching Characteristics V
Symbol
§
EE
A
Parameter
Fig
Min
Typ
Max
Units
bits
ns
g
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
Receiver startup delay (RXI to RX
)
8 & 14
8 & 14
8 & 14
8 & 14
13
4
15
4
RON
Rd
g
Receiver propagation delay (RXI to RX
)
50
g
Differential outputs rise time (RX , CD
g
)
ns
Rr
g
Differential outputs fall time (RX , CD
g
)
4
ns
Rf
g
Receiver & cable total jitter
2
ns
RJ
g
Transmitter startup delay (TX to TXO)
9 & 14
9 & 14
9 & 14
9 & 14
1
bits
ns
TST
Td
g
Transmitter propagation delay (TX to TXO)
Transmitter rise time Ð10% to 90% (TXO)
Transmitter fall time Ð90% to 10% (TXO)
25
25
25
0.5
50
ns
Tr
ns
Tf
t and t mismatch
Tr Tf
ns
TM
TS
g
Transmitter skew (TXO)
Transmit turn-on pulse width at V (TX
0.5
ns
g
g
)
)
9 & 14
9 & 14
20
250
7
ns
TON
TOFF
CON
COFF
CD
TS
Transmit turn-off pulse width at V (TX
TS
ns
Collision turn-on delay
Collision turn-off delay
10 & 14
10 & 14
10 & 14
10 & 14
11 & 14
11 & 14
12 & 14
12 & 14
bits
bits
MHz
ns
20
12.5
70
g
Collision frequency (CD
Collision pulse width (CD
)
8.0
35
g
)
CP
g
CD Heartbeat delay (TX to CD
g
)
0.6
0.5
20
1.6
1.5
60
ms
HON
HW
JA
g
CD Heartbeat duration (CD
)
1.0
29
ms
g
Jabber activation delay (TX to TXO and CD
g
)
ms
ms
g
Jabber reset unjab time (TX to TXO and CD
g
)
250
500
750
JR
e b
e
g
9V 5%, T
DP8392C-1 Switching Characteristics V
Symbol
0 to 70 C (Note 3)
§
§
EE
A
Parameter
Fig
Min
Typ
4
Max
5
Units
bits
ns
g
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
Receiver startup delay (RXI to RX
)
8 & 14
8 & 14
8 & 14
8 & 14
13
RON
Rd
g
Receiver propagation delay (RXI to RX
)
15
4
50
7
g
Differential outputs rise time (RX , CD
g
)
ns
Rr
g
Differential outputs fall time (RX , CD
g
)
4
7
ns
Rf
g
Receiver & cable total jitter
2
ns
RJ
g
Transmitter startup delay (TX to TXO)
9 & 14
9 & 14
9 & 14
9 & 14
1
2
bits
ns
TST
Td
g
Transmitter propagation delay (TX to TXO)
Transmitter rise time Ð10% to 90% (TXO)
Transmitter fall time Ð90% to 10% (TXO)
5
25
25
25
0.5
50
30
30
20
20
ns
Tr
ns
Tf
t and t mismatch
Tr Tf
ns
TM
TS
g
Transmitter skew (TXO)
Transmit turn-on pulse width at V (TX
0.5
ns
g
g
)
)
9 & 14
9 & 14
5
20
40
270
13
ns
TON
TOFF
CON
COFF
CD
TS
Transmit turn-off pulse width at V (TX
TS
110
ns
Collision turn-on delay
Collision turn-off delay
10 & 14
10 & 14
10 & 14
10 & 14
11 & 14
11 & 14
12 & 14
12 & 14
7
bits
bits
MHz
ns
20
g
Collision frequency (CD
Collision pulse width (CD
)
8.5
35
12.5
70
g
)
CP
g
CD Heartbeat delay (TX to CD
g
)
0.6
0.5
20
1.6
1.5
60
ms
HON
HW
JA
g
CD Heartbeat duration (CD
)
1.0
29
ms
g
Jabber activation delay (TX to TXO and CD
g
)
ms
ms
g
Jabber reset unjab time (TX to TXO and CD
g
)
250
500
750
JR
Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: All currents into device pins are positive, all currents out of device pins are negative. All voltages referenced to ground unless otherwise specified.
e
b
e
9V and T 25 C.
A
Note 3: All typicals are given for V
§
EE
8
11.0 Timing and Load Diagrams
TL/F/11085–7
FIGURE 8. Receiver Timing
TL/F/11085–8
FIGURE 9. Transmitter Timing
TL/F/11085–9
FIGURE 10. Collision Timing
TL/F/11085–10
FIGURE 11. Heartbeat Timing
9
11.0 Timing and Load Diagrams (Continued)
TL/F/11085–11
FIGURE 12. Jabber Timing
s
g
g
7 ns
Input jitter at RX
TL/F/11085–12
s
g
g
6 ns
Output jitter at RX
FIGURE 13. Receive Jitter Timing
TL/F/11085–13
*The 50 mH inductance is for testing purposes. Pulse transformers with higher inductances are recommended (seeFigure 4)
FIGURE 14. Test Loads
10
12.0 Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N)
Order Number DP8392CN or DP8392CN-1
NS Package Number N16E
11
Ý
Lit. 103054
12.0 Physical Dimensions inches (millimeters) (Continued)
28-Lead Plastic Chip Carrier
Order Number DP8392CV or DP8392CV-1
NS Package Number V28A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax:
(
49) 0-180-530 85 86
@
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
Email: cnjwge tevm2.nsc.com
a
a
a
a
Deutsch Tel:
English Tel:
Fran3ais Tel:
Italiano Tel:
(
(
(
(
49) 0-180-530 85 85
49) 0-180-532 78 32
49) 0-180-532 93 58
49) 0-180-534 16 80
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
©2020 ICPDF网 联系我们和版权申明