DM512K32ST6-12 [ETC]
Enhanced DRAM (EDRAM) Module ; 增强型DRAM （ EDRAM ）模块
| 型号： | DM512K32ST6-12 |
| 厂家： | 
ETC |
| 描述： | Enhanced DRAM (EDRAM) Module
|
| 文件： | 总19页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DM512K32ST6/DM512K36ST6 Multibank EDO
512Kb x 32/512Kb x 36 EDRAM SIMM
Product Specification
Enhanced
Memory Systems Inc.
Features
Architecture
The DM512K36ST6
achieves 512K x 36 density by
■ 4KByte SRAM Cache Memory for 12ns Random Reads Within Four
Actives Pages (Multibank Cache)
■ Fast DRAM Array for 30ns Access to Any New Page
■ Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
■ 1KByte Wide DRAM to SRAM Bus for 56.8 Gigabytes/Sec Cache Fill
■ On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
on Writes
■ EDO Mode for 83 MHz Non-Interleave Burst Rate
■ Hidden Precharge and Refresh Cycles
mounting five 512K x 8
EDRAMs, packaged in 44-pin
plastic TSOP-II packages, on a
multi-layer substrate. Four
2203 devices and one
DM2213 device provide data
and parity storage. The
DM512K32 contains four
■ Extended 64ms Refresh Period for Low Standby Power
■ Standard CMOS/TTL Compatible I/O Levels and +5 Volt Supply
■ Compatibility with JEDEC 512K x 32/36 DRAM SIMM Configuration
Allows Performance Upgrade in System
2203 devices for data only.
The EDRAM memory
module architecture is very
similar to a standard 2MB
■ Industrial Temperature Range Option
DRAM module with the
addition of an integrated
Description
cache and on-chip control which allows it to operate much like a
page mode or static column DRAM.
The Enhanced Memory Systems 2MB EDRAM SIMM module
provides a single memory module solution for the main memory or
local memory of fast embedded control, DSP, and other high
performance systems. Due to its fast 12ns cache row register, the
EDRAM memory module supports zero-wait-state burst read
operations at up to 83MHz bus rates in a non-interleave configuration
and >100MHz bus rates with a two-way interleave configuration.
On-chip write posting and fast page mode operation supports
12ns write and burst write operations. On a cache miss, the fast
DRAM array reloads the entire 1KByte cache over a 1KByte-wide bus
in 18ns for an effective bandwidth of 56.8 Gbytes/sec. This means
very low latency and fewer wait states on a cache miss than a non-
integrated cache/DRAM solution. The JEDEC compatible 72-bit SIMM
configuration allows a single memory controller to be designed to
support either JEDEC slow DRAMs or high speed EDRAMs to provide
a simple upgrade path to higher system performance.
The EDRAM’s SRAM cache is integrated into the DRAM array as
tightly coupled row registers. The 512K x 32/36 EDRAM SIMM has a
total of four independent DRAM memory banks each with its own 256
x 32/36 SRAM row register. Memory reads always occur from the
cache row register of one of these banks as specified by row address
bits A and A (bank select). When the internal comparator detects
8
9
that the row address matches the last row read from any of the four
DRAM banks (page hit), the SRAM is accessed and data is available
on the output pins in 12ns from column address input. Subsequent
reads within the page (burst reads or random reads) can continue at
12ns cycle time. When the row address does not match the last row
read from any of the four DRAM banks (page miss), the new DRAM
row is accessed and loaded into the appropriate SRAM row register
and data is available on the output pins
all within 30ns from row enable.
Subsequent reads within the page (burst
Functional Diagram
reads or random reads) can continue at
12ns cycle time. During either read hit or
/CAL
Column
0-3, P
A
- A
7
Address
Latch
0
read miss operations, the EDO option
Column Decoder
extends data output time to allow use of
4 - 256 X 36 Cache Pages
(Row Registers)
the full 83Mbyte/second bandwidth.
4 - 9 Bit
Comparators
Since reads occur from the SRAM
Sense Amps
& Column Write Select
cache, the DRAM precharge can occur
/G
A - A
10
I/O
Control
and
Data
Latches
during burst reads. This eliminates the
0
4 - Last Row
Read Address
Latches
DQ
0-35
precharge time delay suffered by other
DRAMs and SDRAMs when accessing a
new page. The EDRAM has an
/S
Memory
Array
2Mbyte + Parity
Row
Address
Latch
/WE
independent on-chip refresh counter and
dedicated refresh control pin to allow the
DRAM array to be refreshed concurrently
with cache read operations (hidden
refresh).
V
CC
C
1-5
A
- A
V
0
9
SS
/F
W/R
/RE
Row Adress
and
Refresh
Control
Refresh
Counter
0, 2
The information contained herein is subject to change without notice. Enhanced reserves the
right to change or discontinue this product without notice.
© 1996 Enhanced Memory Sytems Inc, 1850 Ramtron Drive, Colorado Springs, CO
Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2117-000
80921
During EDRAM read accesses, data is accessed in EDO mode. possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM
to hide precharge and refresh operation during reads and
maximize hit rate by maintaining page cache contents during write
operations even if data is written to another memory page. These
capabilities, in conjunction with the faster basic DRAM and cache
speeds of the EDRAM, minimize processor wait states.
The column address is latched on the falling edge of /CAL while the
output data latch is transparent. On the rising edge of /CAL the
output data is latched while the column address latch is
transparent. The EDO mode allows the output data valid time to be
extended so that the next column address can be latched sooner. A
dedicated output enable (/G) with 5ns access time allows high
speed two-way interleave without an external multiplexer.
Memory writes are posted to the input data latch and directed
to the DRAM array. During a write hit, the on-chip address
comparator activates a parallel write path to the SRAM cache to
maintain coherency. Random or page mode writes can be posted
5ns after column address and data are available. The EDRAM
allows 12ns page mode cycle time for both write hits and write
misses. Memory writes do not affect the contents of the cache row
register except during a cache hit. Since the DRAM array can be
written to at SRAM speeds, there is no need for complex writeback
schemes.
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to any of the four pages of data contained in the SRAM cache row
registers. There are four cache row registers, one for each of the
four banks of DRAM. These registers are specified by the bank
select row address bits A and A . The contents of these cache row
9
registers is always equal 8to the last row that was read from each of
the four internal DRAM banks (as modified by any write hit data).
DRAM Read Hit
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance over standard slow 4Mb DRAMs.
By eliminating the need for SRAMs and cache controllers, system
cost, board space, and power can all be reduced.
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
last row read address latch for the bank specified by row address
bits A (LRR: a 9-bit row address latch for each internal DRAM
bank 8w-9hich is reloaded on each /RE active read miss cycle). If the
row address matches the LRR, the requested data is already in the
SRAM cache and no DRAM memory reference is initiated. The data
specified by the row and column address is available at the output
Functional Description
The EDRAM is designed to provide optimum memory
performance with high speed microprocessors. As a result, it is
Four Bank Cache Architecture
Bank 3
Bank 2
Bank 1
Bank 0
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA
0-10
CA
0-7
D0-35
512K Byte
Array
512K Byte
Array
512K Byte
Array
512K Byte
Array
A
Data-In
Latch
0-10
256 x 36
Cache
256 x 36
Cache
256 x 36
Cache
256 x 36
Cache
CA
0-7
Bank 0
Bank 1
Bank 2
Bank 3
(0,0)
(0,1)
(1,0)
(1,1)
1 of 4 Selector
RA , RA
8
9
Data-Out
Latch
CAL
0-3, P
G
S
Q 0-35
2-58
pins at the greater of times tRAC1, tAC, tGQV, and tASC + tCLV. Since no of any write sequence (after /CAL and /WE are brought high and tRE
DRAM activity is initiated, /RE can be brought high after time tRE1, is satisfied), /RE can be brought high to precharge the memory.
and a shorter precharge time, tRP1, is required. Additional locations Cache reads can be performed concurrently with precharge (see
within the currently active page may be accessed concurrently with “/RE Inactive Operation”). When /RE is inactive, the cache reads
precharge by providing new column addresses to the multiplex
address inputs.
will occur from the page accessed during the last /RE active read
cycle. During write sequences, a write operation is not performed
unless both /CAL and /WE are low. As a result, the /CAL input can
be used as a byte write select in multi-chip systems.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
DRAM Write Miss
and /F high. The EDRAM will compare the new row address to the
A DRAM write request is initiated by clocking /RE while W/R,
/WE, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified for row
LRR address latch for the bank specified by row address bits A
8-9
(LRR: a 9-bit row address latch for each internal DRAM bank
which is reloaded on each /RE active read miss cycle). If the row
address does not match the LRR, the requested data is not in SRAM address bits A (LRR: a 9-bit row address latch for each internal
8-9
cache and a new row is fetched from the DRAM. The EDRAM will
load the new row data into the SRAM cache and update the LRR
latch. The data at the specified column address is available at the
output pins at the greater of times tRAC1, tAC, tGQV, and tASC + tCLV.
/RE may be brought high after time tRE since the new row data is
safely latched into SRAM cache. This allows the EDRAM to
precharge the DRAM array while data is accessed from SRAM
cache. Additional locations within the currently active page may be
accessed by providing new column addresses to the multiplex
address inputs.
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address does not match any of the LRRs, the EDRAM will
write data to the DRAM page in the appropriate bank and the
contents of the current cache is not modified. The write address
and data are posted to the DRAM as soon as the column address is
latched by bringing /CAL low and the write data is latched by
bringing /WE low (both /CAL and /WE must be high when initiating
the write cycle with the falling edge of /RE). The write address and
data can be latched very quickly after the fall of /RE (tRAH + tASC for
the column address and tDS for the data). During a write burst
sequence, the second write data can be posted at time tRSW after
/RE. Subsequent writes within a page can occur with write cycle
time tPC. During a write miss sequence cache reads are inhibited
and the output buffers are disabled (independently of /G) until
time tWRR after /RE goes high. At the end of a write sequence (after
/CAL and /WE are brought high and tRE is satisfied), /RE can be
brought high to precharge the memory. Cache reads can be
performed concurrently with the precharge (see “/RE Inactive
Operation”). When /RE is inactive, the cache reads will occur from
the page accessed during the last /RE active read cycle. During
write sequences, a write operation is not performed unless both
/CAL and /WE are low. As a result, /CAL can be used as a byte write
select in multi-chip systems.
DRAM Write Hit
A DRAM write request is initiated by clocking /RE while W/R,
/WE, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified by row
address bits A (LRR: a 9-bit row address latch for each internal
8-9
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address matches the LRR, the EDRAM will write data to
both the DRAM page in the appropriate bank and its corresponding
SRAM cache simultaneously to maintain coherency. The write
address and data are posted to the DRAM as soon as the column
address is latched by bringing /CAL low and the write data is
latched by bringing /WE low (both /CAL and /WE must be high
when initiating the write cycle with the falling edge of /RE). The
write address and data can be latched very quickly after the fall of
/RE (tRAH + tASC for the column address and tDS for the data).
During a write burst sequence, the second write data can be posted
at time tRSW after /RE. Subsequent writes within a page can occur
with write cycle time tPC. With /G enabled and /WE disabled, read
operations may be performed while /RE is activated in write hit
mode. This allows read-modify-write, write-verify, or random read-
write sequences within the page with 12ns cycle times. At the end
/RE Inactive Operation
Data may be read from the SRAM cache without clocking /RE.
This capability allows the EDRAM to perform cache read
operations during precharge and refresh cycles to minimize wait
states. It is only necessary to select /S and /G and provide the
appropriate column address to read data. In this mode of
operation, the cache reads will occur from the page accessed
EDRAM Basic Operating Modes
Function
/S
L
/RE
↓
W/R
L
/F
H
H
H
H
L
A
Comment
No DRAM Reference, Data in Cache
DRAM Row to Cache
0-10
Read Hit
Row = LRR
Read Miss
L
↓
L
Row ≠ LRR
Write Hit
L
↓
H
Row = LRR
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
Cache Reads Enabled
Write Miss
L
↓
H
Row ≠ LRR
Internal Refresh
Low Power Standby
Unallowed Mode
X
H
H
↓
X
X
X
X
Standby Current
H
L
X
X
H
X
H = High; L = Low; X = Don’t Care; ↓ = High-to-Low Transition; LRR = Last Row Read
2-59
during the last /RE active read cycle. /CAL is clocked to latch the
column address and data.
This option is desirable when the external control logic is
capable of fast hit/miss comparison. In this case, the controller
can avoid the time required to perform row/column multiplexing
on hit cycles.
Initialization Cycles
A minimum of eight /RE active initialization cycles (read,
write, or refresh) are required before normal operation is
guaranteed. Following these start-up cycles, two read cycles to
different row addresses must be performed for each of the four
internal banks of DRAM to initialize the internal cache logic. Row
address bits A and A define the four internal DRAM banks.
8
9
EDO Mode Operation
Unallowed Mode
The EDRAM SIMM has an on-board data latch to latch output
data from the SRAM cache while a new cache address is being
specified. EDO mode pipelines the fetching of new data from the
cache with the transfer of the previous data to the bus. EDO allows
non-interleave data transfers at up to a 83 MHz data rate. In this
mode, static column and page mode read operations are not
supported. All read operations require /CAL to be clocked to latch
the input address and enable the output data to propagate through
the output latch to the output pins.
Read, write, or /RE only refresh operations must not be
initiated to unselected memory banks by clocking /RE when /S is
high.
Reduced Pin Count Operation
It is possible to simplify the interface to the 2MByte SIMM to
reduce the number of control lines. /RE and /RE could be tied
together externally to provide a single ro0w enable.2 W/R and /G can
be tied together if reads are not performed during write hit cycles.
This external wiring simplifies the interface without any
performance impact.
Write-Per-Bit Operation
The DM512K36ST6 SIMM provides a write-per-bit capability
to selectively modify individual parity bits (DQ8, 17, 26, 35) for byte
write operations. The parity device (DM2213) is selected via
/CAL . Byte write selection to non-parity bits is accomplished via
CAL P . The bits to be written are determined by a bit mask data
wor0d-3which is placed on the parity I/O data pins prior to clocking
/RE. The logic one bits in the mask data select the bits to be
written. As soon as the mask is latched by /RE, the mask data is
removed and write data can be placed on the databus. The mask
is only specified on the /RE transition. During page mode write
operations, the same mask is used for all write operations.
Pin Descriptions
/RE0,2 — Row Enable
These inputs are used to initiate DRAM read and write
operations and latch a row address and the states of W/R and /F. It
is not necessary to clock /RE to read data from the EDRAM SRAM
row registers. On read operations, /RE can be brought high as
soon as data is loaded into cache to allow early precharge.
/CAL 0-3, P — Column Address Latch
These inputs are used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low,
the column address is closed and the output of the latch contains
the address present while /CAL was high. /CAL can be toggled
when /RE is low or high. However, /CAL must be high during the
high-to-low transition of /RE except for /F refresh cycles. The
output data is latched when /CAL is high.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles where /S can be disabled.
W/R — Write/Read
This input along with /F specifies the type of DRAM operation
initiated on the low going edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, it is possible to perform
an /RE only refresh using an externally supplied row address. /RE
refresh is performed by executing a write cycle (W/R and /F are
high) where /CAL is not clocked. This is necessary so that the
current cache contents and LRR are not modified by the refresh
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when /F is low on
the low going edge of /RE.
/WE — Write Enable
operation. All combinations of addresses A must be sequenced
0-9
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are
low.
every 64ms refresh period. A does not need to be cycled. Read
10
refresh cycles are not allowed because a DRAM refresh cycle does
not occur when a read refresh address matches the LRR address
latch.
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In
this mode, the internal DRAM circuitry is powered down to reduce
standby current.
/S — Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in its low power mode. /S
2-60
Interconnect Diagram
Edge
Connecter
J1
DQ0
2
4
6
8
DQ1
DQ2
DQ3
DQ4
20
22
24
26
36
49
51
53
55
57
61
63
65
37
3
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
+5V
100KΩ
5
7
9
21
23
25
27
35
50
52
54
56
58
60
62
64
38
+5V
U3
Parity*
U5
1
5
11
17
22
31
VCC
VCC
VCC
VCC
VCC
VCC
U4
U2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
27
28
29
30
35
36
37
38
39
40
41
3
8
12
13
14
15
16
17
18
28
31
32
19
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
U1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DM2213T
512K x 8
EDRAM
14
19
23
34
44
DM2203T
512K x 8
EDRAM
DM2203T
512K x 8
EDRAM
DM2203T
512K x 8
EDRAM
W/R
/WE
/F
/S
/G
43
26
2
42
12
10
24
W/R
/WE
/F
/S
/G
QLE
/HIT
48
47
68
69
67
DM2203T
512K x 8
EDRAM
+5V
100KΩ
R6 - R10
/CAL0
/CAL0
/CAL1
/CAL2
/CAL3
/CALP
/RE0
40
43
41
42
46
44
34
/CAL1
/CAL2
/CAL3
/CALP
/RE0
/RE2
/RE2
VCC
VCC
VCC
VCC
VCC
10
11
30
59
66
C1
C2
C3
C4
C5
VSS
VSS
VSS
VSS
VSS
1
29
39
71
72
PD
70
*DM2213 and R1-4 are not present on the DM512K32ST6.
2-61
Pinout
Interconnect
Interconnect
Pin No. Function (Component Pin)
Organization
Ground
Pin No. Function (Component Pin)
Organization
Parity I/O for Byte 2
Parity I/O for Byte 4
Ground
C (3, 8, 14, 19,
1
2
GND
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
+5 Volts
+5 Volts
A0
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ17*
DQ35*
GND
/CAL0
/CAL2
/CAL3
/CAL1
/RE0
U3 (6)
23, 34, 44)
U1 (4)
Byte 1 I/O 1
Byte 3 I/O 1
Byte 1 I/O 2
Byte 3 I/O 2
Byte 1 I/O 3
Byte 3 I/O 3
Byte 1 I/O 4
Byte 3 I/O 4
U3 (9)
C (3, 8, 14, 19,
23, 34, 44)
3
U4 (4)
U1 (6)
U4 (6)
U1 (7)
U4 (7)
U1 (9)
U4 (9)
4
U1 (32)
U4 (32)
U5 (32)
U2 (32)
U1, 2 (33)
Byte 1 Column Address Latch
Byte 3 Column Address Latch
Byte 4 Column Address Latch
Byte 2 Column Address Latch
Row Enable (Bytes 1,2)
Reserved for 2Mb x 36
Parity Column Address Latch
Write Enable
5
6
7
8
9
NC
C (1, 5,11, 17,
22, 31)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
V
/CALP*
/WE
U3 (32)
C (26)
C (43)
U2 (4)
U5 (4)
U2 (6)
U5 (6)
U2 (7)
U5 (7)
U2 (9)
U5 (9)
U2 (13)
U5 (13)
CC
C (1, 5, 11, 17,
V
CC
22, 31)
C (27)
Address
W/R
W/R Mode Control
Byte 2 I/O 1
A1
C (28)
Address
DQ9
A2
C (29)
Address
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
+5 Volts
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
+5 Volts
/G
Byte 4 I/O 1
A3
C (30)
Address
Byte 2 I/O 2
A4
C (35)
Address
Byte 4 I/O 2
A5
C (36)
Address
Byte 2 I/O 3
A6
C (37)
Address
Byte 4 I/O 3
A10
C (41)
Address
Byte 2 I/O 4
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
U1 (13)
U4 (13)
U1 (15)
U4 (15)
U1 (16)
U4 (164
U1 (18)
U4 (18)
C (38)
Byte 1 I/O 5
Byte 3 I/O 5
Byte 1 I/O 6
Byte 3 I/O 6
Byte 1 I/O 7
Byte 3 I/O 7
Byte 1 I/O 8
Byte 3 I/O 8
Address
Byte 4 I/O 4
Byte 2 I/O 5
Byte 4 I/O 5
C (1, 5, 11, 17,
22, 31)
V
CC
U5 (15)
U2 (15)
U5 (16)
U2 (16)
U5 (18)
U2 (18)
Byte 4 I/O 6
Byte 2 I/O 6
Byte 4 I/O 7
Byte 2 I/O 7
Byte 4 I/O 8
Byte 2 I/O 8
C (3, 8, 14, 19,
23, 34, 44)
C (1, 5, 11, 17,
22, 31)
GND
+5 Volts
A8
Ground
C (1, 5, 11, 17,
22, 31)
V
V
CC
CC
C (39)
C (40)
Address
C (12)
Output Enable
Refresh Mode Control
Chip Select
A9
Address
/F
C (2)
NC
Reserved for 2Mb x 36
Row Enable (Bytes 3,4, Parity)
Parity I/O for Byte 3
Parity I/O for Byte 1
/S
C (42)
/RE2
DQ26*
DQ8*
U3, 4, 5 (33)
U3 (7)
PD
Signal GND
C (3, 8, 14, 19,
23, 34, 44)
C (3, 8, 14, 19
33, 34, 44)
Presence Detect
Ground
GND
GND
U3 (4)
Ground
C = Common to All Memory Chips, U1 = Chip 1, etc.
*No Connect for DM512K32ST6
2-62
must remain active throughout any read or write operation. With
the exception of /F refresh cycles, /RE should never be clocked
when /S is inactive.
V Power Supply
CC These inputs are connected to the +5 volt power supply.
V Ground
SS
These inputs are connected to the power supply ground
DQ0-35 — Data Input/Output
connection.
These bidirectional data pins are used to read and write data
to the EDRAM. On the DM512K36 SIMM, the parity pins are also
used to specify the bit mask used during parity write operations.
A
0-10 — Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 8-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
Absolute Maximum Ratings
(Beyond Which Permanent Damage Could Result)
Capacitance
Description
Ratings
- 1 ~ 7v
Description
Max*
22/24pf
16pf
Pins
Input Voltage (V )
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
A
0-10
IN
Output Voltage (VOUT
)
- 1 ~ 7v
/RE
0
Power Supply Voltage (V
)
- 1 ~ 7v
CC
14/18pf
17pf
/RE
2
Ambient Operating Temperature (T )
-40 ~ 85°C
-55 ~ 150°C
A
/G
Storage Temperature (T )
S
DQ
I/O Capacitance
Input Capacitance
Input Capacitance
9pf
0-35
Static Discharge Voltage
(Per MIL-STD-883 Method 3015)
Class 1
50mA*
10pf
24pf
/CAL
0-3, P
W/R, /WE, /F, /S
Short Circuit O/P Current (IOUT
)
* One output at a time per device; short duration
* DM512K32ST6/DM512K36ST6, respectively
V Timing Reference Point at V and V
IH
AC Test Load and Waveforms
IN
IL
V
OUT Timing Referenced to 1.5 Volts V
IH
Load Circuit
5.0V
R1= 828Ω
Input Waveforms
V
IH
V
IH
Output
R2 = 295Ω
V
IL
V
IL
C L = 50pf
GND
≤5ns
≤5ns
2-63
Electrical Characteristics
(T = 0 to 70°C, Commercial; -40 to 85°C, Industrial)
A
Symbol
Parameters
Supply Voltage
Max
Min
Test Conditions
All Voltages Referenced to V
V
4.75V
5.25V
SS
CC
V
Input High Voltage
Input Low Voltage
Output High Level
Output Low Level
2.4V
-1.0V
2.4V
6.5V
0.8V
IH
V
IL
V
I
= - 5mA
= 4.2mA
OUT
OH
V
0.4V
-50µA
-50µA
I
OUT
OL
I
I
Input Leakage Current
Output Leakage Current
-50µA
-50µA
OV ≤ V ≤ 6.5V, All Other Pins Not Under Test = 0V
IN
i(L)
OV
V
, OV
V 5.5V
≤
OUT
≤
≤
IN
O(L)
Operating Current — DM512K32ST6
33MHz Typ(1)
440mA
Symbol
Operating Current
Random Read
-15 Max
720mA /RE, /CAL, /G and Addresses Cycling: t = t Minimum
-12 Max
Test Condition
Notes
I
900mA
580mA
440mA
760mA
540mA
4mA
2, 3
CC1
C
C
I
Fast Page Mode Read
Static Column Read
Random Write
260mA
460mA /CAL, /G and Addresses Cycling: t = t Minimum
2, 4
2, 4
2, 3
2, 4
PC PC
CC2
I
220mA
540mA
200mA
4mA
360mA
600mA
420mA
4mA
/G and Addresses Cycling: t = t Minimum
SC SC
CC3
I
/RE, /CAL, /WE and Addresses Cycling: t = t Minimum
C
C
CC4
I
Fast Page Mode Write
/CAL, /WE and Addresses Cycling: t = t Minimum
PC PC
CC5
I
Standby
All Control Inputs Stable ≥ V - 0.2V, Outputs Driven
CC6
CC
I
1
Average Typical
120mA
—
—
See "Estimating EDRAM Operating Power" Application Note
CCT
Operating Current
Operating Current — DM512K36ST6
33MHz Typ(1)
550mA
-15 Max
Symbol
Operating Current
Random Read
-12 Max
Test Condition
Notes
I
1125mA
900mA /RE, /CAL, /G and Addresses Cycling: t = t Minimum
2, 3
CC1
C
C
I
Fast Page Mode Read
Static Column Read
Random Write
325mA
725mA
550mA
950mA
675mA
5mA
575mA /CAL, /G and Addresses Cycling: t = t Minimum
2, 4
2, 4
2, 3
2, 4
PC PC
CC2
I
275mA
675mA
250mA
5mA
450mA
750mA
525mA
5mA
/G and Addresses Cycling: t = t Minimum
SC SC
CC3
I
/RE, /CAL, /WE and Addresses Cycling: t = t Minimum
C
C
CC4
I
Fast Page Mode Write
/CAL, /WE and Addresses Cycling: t = t Minimum
PC PC
CC5
I
Standby
All Control Inputs Stable ≥ V - 0.2V, Outputs Driven
CC6
CC
I
1
Average Typical
150mA
—
—
See "Estimating EDRAM Operating Power" Application Note
CCT
Operating Current
(1) “33MHz Typ” refers to worst case I expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested
CC
or guaranteed.
(2) I is dependent on cycle rates and is measured with CMOS levels and the outputs open.
CC
(3) I is measured with a maximum of one address change while /RE = V .
CC
IL
(4) I is measured with a maximum of one address change while /CAL = V .
CC
IH
2-64
Switching Characteristics (V = 5V ± 5%, T = 0 to 70°C, Commercial; -40 to 85°C, Industrial)
CC
A
-12
Min
-15
Symbol
Description
Units
Max
Min
Max
(1)
t
t
Column Address Access Time
12
15
ns
ns
AC
Column Address Valid to /CAL Inactive (Write Cycle)
Address Valid to /CAL Inactive
12
15
15
ACH
t
12
5
ns
ACI
AQX
ASC
ASR
C
t
t
t
t
t
t
t
t
t
Column Address Change to Output Data Invalid
Column Address Setup Time
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
Row Address Setup Time
5
5
55
65
25
6
Row Enable Cycle Time
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only
Column Address Latch Active Time
20
5
C1
CAE
CAH
CH
Column Address Hold Time
0
0
5
5
Column Address Latch High Time (Latch Transparent)
/CAL Inactive Lead Time to /RE Inactive (Write Cycles Only)
-2
-2
CHR
t
t
t
0
0
Column Address Latch High to Write Enable Low (Multiple Writes)
Column Address Latch Low to Data Valid
ns
ns
ns
CHW
CLV
7
7
5
5
Column Address Latch Low to Data Invalid
CQH
t
t
t
t
t
t
t
t
Column Address Latch High to Data Valid
Column Address Latch Setup Time to Row Enable
/WE Low to /CAL Inactive
15
15
ns
ns
ns
ns
ns
ns
ns
ns
CQV
CRP
CWL
DH
5
5
0
1
5
5
5
5
0
Data Input Hold Time
1.5
5
Mask Hold Time From Row Enable (Write-Per-Bit)
Mask Setup Time to Row Enable (Write-Per-Bit)
Data Input Setup Time
DMH
DMS
DS
5
(1)
GQV
Output Enable Access Time
5
5
5
5
5
5
(2,3)
GQX
t
t
t
t
t
t
t
t
t
Output Enable to Output Drive Time
Output Turn-Off Delay From Output Disabled (/G↑)
/F and W/R Mode Select Hold Time
0
0
0
0
ns
ns
(4,5)
GQZ
0
0
ns
ns
ns
ns
ns
MH
/F and W/R Mode Select Setup Time
/CAL, /G, and /WE Hold Time For /RE-Only Refresh
/CAL, /G, and /WE Setup Time For /RE-Only Refresh
Column Address Latch Cycle Time
5
5
MSU
NRH
NRS
PC
0
0
5
5
12
15
(1)
RAC
Row Enable Access Time, On a Cache Miss
30
15
35
17
ns
ns
(1)
Row Enable Access Time, On a Cache Hit (Limit Becomes t
Row Enable Access Time for a Cache Write Hit
Row Address Hold Time
)
RAC1
AC
(1,6)
t
t
t
30
35
ns
ns
ns
RAC2
RAH
RE
1
1.5
35
Row Enable Active Time
30
100000
100000
2-65
Switching Characteristics (continued)
(V = 5V ± 5%, (T = 0 to 70°C, Commercial; -40 to 85°C, Industrial; C = 50pF)
CC
A
L
-12
-15
Symbol
Description
Units
Min
Max
64
Min
Max
64
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle
Refresh Period
8
10
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RE1
REF
Output Enable Don't Care From Row Enable (Write, Cache Miss), O/P Hi Z
Row Enable High to Output Turn-On After Write Miss
Row Precharge Time
9
0
10
0
RGX
RQX1
(2,6)
12
15
(7)
RP
20
8
25
10
0
Row Precharge Time, Cache Hit (Row=LRR) Read Cycle
Read Hold Time From Row Enable (Write Only)
Last Write Address Latch to End of Write
Row Enable to Column Address Latch Low For Second Write
Last Write Enable to End of Write
RP1
RRH
RSH
RSW
RWL
SC
0
12
35
12
12
0
15
40
15
15
0
Column Address Cycle Time
Select Hold From Row Enable
SHR
(1)
Chip Select Access Time
12
12
8
15
15
10
SQV
(2,3)
0
0
Output Turn-On From Select Low
0
0
SQX
(4,5)
Output Turn-Off From Chip Select
SQZ
SSR
T
5
Select Setup Time to Row Enable
5
1
Transition Time (Rise and Fall)
10
1
10
12
5
Write Enable Cycle Time
15
5
WC
WCH
WHR
WI
Column Address Latch Low to Write Enable Inactive Time
Write Enable Hold After /RE
(7)
0
0
5
Write Enable Inactive Time
5
5
5
Write Enable Active Time
WP
(1)
12
12
12
15
15
15
Data Valid From Write Enable High
WQV
(2,5)
Data Output Turn-On From Write Enable High
Data Turn-Off From Write Enable Low
Write Enable Setup Time to Row Enable
Write to Read Recovery (Following Write Miss)
0
0
5
0
0
5
WQX
(3,4)
WQZ
WRP
WRR
12
15
(1) V Timing Reference Point at 1.5V
OUT
(2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to V or V
OH
OL
(3) Minimum Specification is Referenced from V and Maximum Specification is Referenced from V on Input Control Signal
IH
IL
(4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to V or V
OH
OL
(5) Minimum Specification is Referenced from V and Maximum Specification is Referenced from V on Input Control Signal
IL
IH
(6) Access Parameter Applies When /CAL Has Not Been Asserted Prior to t
RAC2
(7) For Write-Per-Bit Devices, t
is Limited By Data Input Setup Time, t
WHR
DS
2-66
/RE Inactive Cache Read Hit (EDO Mode)
/RE
0, 2
/F
W/R
tACI
tCAH
A
A
0-10
0-7
A
Column 1
tASC
Column 2
tASC
Row
0-10
tCAH
tCH
tCAE
/CAL
0-3, P
tPC
tCQV
tCLV
tCQH
/WE
tAC
tCLV
Open
Data 1
Data 2
DQ
0-35
tAC
tGQX
tGQZ
tGQV
/G
tSQX
tSQV
tSQZ
/S
Don’t Care or Indeterminate
NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
2. Latched data becomes invalid when /S is inactive.
2-67
/RE Active Cache Read Hit (EDO Mode)
tC1
tRE1
/RE
0,2
tRP1
tMSU
tMH
/F
tMSU
tMH
W/R
tACI
tASR
tRAH
tCAH
A
Row
Column 1
Column 2
tASC
Row
0-10
tASC
tCAH
tCRP
tCH
tCAE
/CAL
tPC
0-3, P
tCQV
/WE
tCLV
tCLV
tCQH
tAC
tRAC1
Open
Data 1
Data 2
DQ
0-35
tAC
tGQX
tGQZ
tGQV
/G
/S
tSHR
tSQZ
tSSR
Don’t Care or Indeterminate
NOTES: 1. Latched data becomes invalid when /S is inactive.
2-68
/RE Active Cache Read Miss (EDO Mode)
tC
tRE
/RE
tRP
0, 2
tMSU
tMH
/F
tMSU
tMH
W/R
tACI
tASR
tRAH
tCAH
A0-10
A0-7
A0-7
Row
Column 1
tASC
Column 2
Row
A
0-10
tASC
tCRP
tCAH
tCH
tCAE
/CAL
0-3, P
tPC
tCQV
tCLV
/WE
tCLV
tAC
tRAC
tCQH
Open
Data 1
Data 2
DQ
0-35
tAC
tGQZ
/G
/S
tGQX
tSHR
tSSR
tGQV
tSQZ
Don’t Care or Indeterminate
NOTES: 1. Latched data becomes invalid when /S is inactive.
2-69
Burst Write (Hit or Miss) Followed By /RE Inactive Cache Reads
tRE
/RE
0,2
tMSU
tRP
tCHR
tMH
/F
tMSU
tMH
W/R
tASR
tCAH
tRAH
Column 1
tASC
tRSW
A
A
A
0-7
0-7
0-7
A
Row
Column 2
tACH
Column n
tCAH
0-10
tACH
A
0-10
tASC
tCAH
tRSH
tCRP
tCWL
tCWL
tCAE
tCAE
tCH
tCHW
/CAL
0-3, P
tCAE
tRRH
tWCH
tWP
tPC
tWCH
tWP
tWRP
/WE
tWI
tWRR
tWHR
tWC
tDS
tCLV
tAC
tRWL
tDH
tDS
tDH
DQ
Open
Data 1
Data 2
Cache (Column n)
0-35
tRQX1
tGQX
/G
tGQV
tSSR
/S
Don’t Care or Indeterminate
NOTES: 1. /G becomes a don’t care after t during a write miss.
RGX
2-70
Read/Write During Write Hit Cycle (Can Include Read-Modify-Write)
tC
tRE
/RE
0,2
tRP
tMSU
tMH
/F
tMSU
tMH
W/R
tCHR
tASR
tAC
tASC
tRAH
A
0-7
A
Row
Column 1
Column 2
tACH
Column 3
0-10
tASC
tRSH
tASC
tCAH
tCRP
tCAE
tWCH
tCAE
/CAL
0-3,P
tCLV
tPC
tCQV
tCWL
tWP
tWRP
tRRH
/WE
tWHR
tRAC2
tRWL
tWQV
tCLV
tDS
tAC
DQ
Read Data
Write Data
tDH
tGQZ
Read Data
0-35
tGQZ
tGQX
tGQV
tWQX
tGQV
/G
tSSR
/S
Don’t Care or Indeterminate
NOTES: 1. If column address one equals column address two, then a read-modify-write cycle is performed.
2-71
Write-Per-Bit Cycle (/G=High)
tRE
tRP
/RE
0, 2
tRSH
tCAE
tCHR
tACH
/CAL
0-3,P
tRAH
tASC
tASR
tCAH
A0-7
A
Row
Column
0-10
tMSU
tMH
tCWL
W/R
tRWL
tWCH
tDMH
tDMS
DQ
Mask
Data
0-35
tDS
tRRH
tWRP
tDH
tWP
/WE
tWHR
tMSU
/F
/S
tMH
tSSR
tSHR
Don’t Care or Indeterminate
NOTES: 1. Data mask bit high (1) enables bit write; data mask bit low (0) inhibits bit write.
2. Write-per-bit cycle valid only for DM512K36 ST6.
3. Write-per-bit waveform applies to parity bits only (DQ 8, 17, 26, 35).
2-72
/F Refresh Cycle
tRE
/RE
0, 2
tMSU
tRP
tMH
/F
Don’t Care or Indeterminate
NOTES: 1. During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don’t care.
2. /RE inactive cache reads may be performed in parallel with /F refresh cycles.
/RE-Only Refresh
tC
tRE
/RE
tRP
0,2
tASR
tRAH
A0-10
Row
tNRS
tNRH
,/WE, /G
/CAL
0-3,P
tMSU
tMH
W/R, /F
/S
tSSR
tSHR
Don’t Care or Indeterminate
NOTES: 1. All binary combinations of A must be refreshed every 64ms interval. A does not have to be cycled, but must remain valid
0-9
10
during row address setup and hold times.
2. /RE refresh is write cycle with no /CAL active cycle.
2-73
Mechanical Data
72 Pin SIMM Module
4.245 (107.82)
4.255 (108.08)
Inches (mm)
3.984 (101.19)
0.133 (3.38)
0.123 (3.12)
0.127 (3.22)
0.400
(10.16)
R4 R3 C3 R1 R2
C1
C2
R8
C4
R9
C5
R7
0.225
U1
U4
U3
U5
U2
0.945 (24.00)
0.955 (24.26)
(5.72)
0.010
(.254)
R6
R10
1
72
0.050 (1.27)
0.040 (1.02)
0.042 (1.07)
0.047 (1.19)
0.054 (1.37)
0.100
(2.54)
0.245 (6.22)
0.255 (6.48)
0.060 (1.52)
0.075 (1.90)
0.085 (2.16)
0.104 (2.65)
RAD.
0.064 (1.63)
0.062 (1.57) RAD.
0.250 (6.35)
1.750 (44.45)
0.250 (6.35)
3.750 (95.25)
2.125 (53.98)
U1-2, U4-5 — Enhanced DM2203T-XX, 512K x 8 EDRAMs, 300 Mil TSOP
U5 — Enhanced DM2213T-XX, 512K x 8 EDRAM with write-per-bit (not present on DM512K32ST6)
C1-C5 — 0.22µF Chip Capacitors
R1-R4, R6-R10 — 100KΩ Chip Resistors
Socket — AMP 822030-3 or Equivalent
Part Numbering System
DM512K36ST6 - 12I
Special Configurations
No Designator = 00 to 700C Commerical Temperature
I = 400 to 850C Industrial Temperature
Access Time from Cache in Nanoseconds
12ns
15ns
Configuration
6 = +5 Volt, Multibank EDO
Packaging System
T = 300 Mil, Plastic TSOP-II
Memory Module Configuration
S = SIMM
I/O Width
32 = 32 Bits
36 = 36 Bits
Memory Depth (Kilobits)
Dynamic Memory
The information contained herein is subject to change without notice. Enhanced Memory Systems Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in
an Enhanced product, nor does it convey or imply any license under patent or other rights.
2-74
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