DM512K64DT6-12 [RAMTRON]
Cache DRAM Module, 512KX64, 30ns, MOS, DIMM-168;
| 型号： | DM512K64DT6-12 |
| 厂家： | 
RAMTRON INTERNATIONAL CORPORATION |
| 描述： | Cache DRAM Module, 512KX64, 30ns, MOS, DIMM-168 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总26页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DM512K64DT6/DM512K72DT6 Multibank EDO
EDRAM
512Kb x 64/512Kb x 72 Enhanced DRAM DIMM
Enhanced
Memory Systems Inc.
Product Specification
Features
■ 8Kbytes SRAM Cache Memory for 12ns Random Reads Within Four ■ On-chip Cache Hit/Miss Comparators Automatically Maintain Cache
Active Pages (Multibank Cache)
Coherency on Writes
■ Fast 4Mbyte DRAM Array for 30ns Access to Any New Page
■ Write Posting Registers for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
■ Hidden Precharge & Refresh Cycles
■ Extended 64ms Refresh Period for Low Standby Power
■ CMOS/TTL Compatible I/O and +5 Volt Power Supply
■ Output Latch Enable Allows Extended Data Output (EDO) for
Faster System Operation
■ 2Kbyte Wide DRAM to SRAM Bus for 113.6 Gigabytes/Second
Cache Fill Rate
■ A Hit Pin Outputs Status on On-chip Page Hit/Miss Comparators to
Simplify Control
Description
Architecture
The DM512K72DT6 achieves
512Kb x 72 density by mounting
The Enhanced Memory Systems 4MB enhanced DRAM
(EDRAM)DIMM module provides a single memory module solution
for the main memory or local memory of fast 64-bit embedded
computers, communications switches, and other high performance
systems. Due to its fast non-interleave architecture, the EDRAM DIMM
module supports zero-wait-state burst read or write operation to
83MHz. The EDRAM outperforms conventional SRAM plus DRAM or
synchronous DRAM memory systems by minimizing wait states on
initial reads (hit or miss) and eliminating writeback delays.
Each 4Mbyte DIMM module has 8Kbytes of SRAM cache
organized as four 256 x 72 row registers with 12ns initial access
time. On a cache miss, the fast DRAM array reloads an entire 2Kbyte
row register over a 2Kbyte-wide bus in just 18ns for an effective cache
fill rate of 113.6 Gbytes/second. During write cycles, a write posting
register allows the initial write to be posted as early as 5ns after
column address is available. EDRAM supports direct non-interleave
page writes at up to 83MHz. An on-chip hit/miss comparator
automatically maintains cache coherency during writes.
nine 512Kx8 EDRAMs, packaged
in low profile 44-pin TSOP-II
packages on one side of the multi-
layer substrate. Three high drive
series terminated buffer chips
buffer address and control lines.
Twelve surface mount capacitors
are used to decouple the power
supply bus. The DM512K64DT
contains eight 512Kx8 EDRAMs.
The parity data component is not
populated.
The EDRAM memory module architecture is very similar to two
standard 2MB DRAM SIMM modules configured in a 64-bit wide,
non-interleave configuration. The EDRAM module adds an integrated
cache and cache control logic which allow the cache to operate much
like a page mode or static column DRAM.
The EDRAM’s SRAM cache is
integrated into the DRAM array as tightly
coupled row registers. Memory reads
always occur from the 256 x 72 cache
row register associated with a 1MB
Functional Diagram
A
0-7
Column
Add
Latch
CAL
0-8
Column Decoder
segment of DRAM. When the on-chip
4- 256 X 72 Cache Pages
(Row Register)
comparator detects a page hit, only the
4-Bit
Comp
/QLE
SRAM is accessed and data is available
Sense Amps
& Column Write Select
/G
in 12ns from column address (the /HIT
I/O
Control
and
Data
Latches
4- Last
Row
Read
Add
Latches
output is low to indicate a page hit).
DQ
When a page miss is detected, the entire
new DRAM row is loaded into cache and
data is available at the output within
30ns from row enable (the /HIT output
is high to indicate a page miss).
0-71
A
0-10
/S
Memory
Array
(4 Mbyte + Parity)
Row
Add
Latch
/WE
Subsequent reads within a page (burst
reads or random reads) will continue at
12ns cycle time. Since reads occur from
the SRAM cache, the DRAM precharge
can occur simultaneously without
degrading performance. The on-chip
refresh counter with independent
V
CC
A
0-9
C
1-12
/F
W/R
/RE
Row Add
and
Refresh
Control
V
SS
Refresh
Counter
PD
© 1996 Enhanced Memory Systems Inc. 1850 Ramtron Drive, Colorado Springs, CO
Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2123-000
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
refresh bus allows the EDRAM to be refreshed during cache reads.
Memory writes can be posted as early as 6.5ns after row
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table.
enable and are directed to the DRAM array. During a write hit, the
on-chip address comparator activates a parallel write path to the
SRAM cache to maintain coherency. Memory writes do not affect
the contents of the cache row register except during write hits.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior system performance at less cost, power, and
area than systems implemented with complex synchronous SRAM
cache, cache controllers, and multilevel data busses.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to any of the four pages of data contained in the SRAM cache row
registers. There are four cache row registers, one for each of the
four banks of DRAM. These registers are specified by the bank
select row address bits A and A . The contents of these cache row
9
registers is always equal 8to the last row that was read from each of
the four internal DRAM banks (as modified by any write hit data).
Functional Description
DRAM Read Hit
The EDRAM is designed to provide optimum memory
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
last row read address latch for the bank specified by row address
bits A (LRR: a 9-bit row address latch for each internal DRAM
bank 8w-9hich is reloaded on each /RE active read miss cycle). If the
row address matches the LRR, the requested data is already in the
SRAM cache and no DRAM memory reference is initiated. The data
specified by the row and column address is available at the output
pins at the greater of times tAC or tGQV. The /HIT output is driven
low at time tHV after /RE to indicate the shorter access time to the
performance with high speed microprocessors. As a result, it is
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM
to hide precharge and refresh operation during reads and
maximize hit rate by maintaining page cache contents during write
operations even if data is written to another memory page. These
capabilities, in conjunction with the faster basic DRAM and cache
speeds of the EDRAM, minimize processor wait states.
Four Bank Cache Architecture
HIT0
HIT1
HIT2
HIT3
/HIT
Bank 3
Bank 2
Bank 1
Bank 0
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA
0-10
CA
0-7
D0-71
1M Array
1M Array
1M Array
1M Array
A
Data-In
Latch
0-10
256 x 72
Cache
256 x 72
Cache
256 x 72
Cache
256 x 72
Cache
CA
0-7
Bank 0
Bank 1
Bank 2
Bank 3
(0,0)
(0,1)
(1,0)
(1,1)
1 of 4 Selector
RA , RA
8
9
CAL
QLE
Data-Out
Latch
G
S
Q0-71
2-138
external control logic. Since no DRAM activity is initiated, /RE can by bringing /WE low (both /CAL and /WE must be high when
initiating the write cycle with the falling edge of /RE). The write
address and data can be latched very quickly after the fall of /RE
(tRAH + tASC for the column address and tDS for the data). During a
write burst sequence, the second write data can be posted at time
be brought high after time tRE1, and a shorter precharge time, tRP1,
is required. Additional locations within the currently active page
may be accessed concurrently with precharge by providing new
column addresses to the multiplex address inputs. New data is
available at the output at time tAC after each column address change
in static column mode. During any read cycle, it is possible to
operate in either static column mode with /CAL=high or page
mode with /CAL clocked to latch the column address. In page
tRSW after /RE. Subsequent writes within a page can occur with write
cycle time tPC. With /G enabled and /WE disabled, read operations
may be performed while /RE is activated in write hit mode. This
allows read-modify-write, write-verify, or random read-write
sequences within the page with 12ns cycle times. During a write hit
sequence, the /HIT output is driven low. At the end of any write
sequence (after /CAL and /WE are brought high and tRE is satisfied),
/RE can be brought high to precharge the memory. Cache reads can
be performed concurrently with precharge (see “/RE Inactive
Operation”). When /RE is inactive, the cache reads will occur from
the page accessed during the last /RE active read cycle.
mode, data valid time is determined by either tAC and tCQV
.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
LRR address latch for the bank specified by row address bits A
8-9
(LRR: a 9-bit row address latch for each internal DRAM bank
which is reloaded on each /RE active read miss cycle). If the row
address does not match the LRR, the requested data is not in SRAM
cache and a new row is fetched from the DRAM. The EDRAM will
load the new row data into the SRAM cache and update the LRR
latch. The data at the specified column address is available at the
output pins at the greater of times tRAC, tAC, and tGQV. The /HIT
output is driven high at time tHV after /RE to indicate the longer
access time to the external control logic. /RE may be brought high
after time tRE since the new row data is safely latched into SRAM
cache. This allows the EDRAM to precharge the DRAM array while
data is accessed from SRAM cache. Additional locations within the
currently active page may be accessed by providing new column
addresses to the multiplex address inputs. New data is available at
the output at time tAC after each column address change in static
column mode. During any read cycle, it is possible to operate in
either static column mode with /CAL=high or page mode with /CAL
clocked to latch the column address. In page mode, data valid time
DRAM Write Miss
A DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified for row
address bits A (LRR: a 9-bit row address latch for each internal
8-9
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address does not match any of the LRRs, the EDRAM will
write data to the DRAM page in the appropriate bank and the
contents of the current cache is not modified. The write address and
data are posted to the DRAM as soon as the column address is
latched by bringing /CAL low and the write data is latched by
bringing /WE low (both /CAL and /WE must be high when initiating
the write cycle with the falling edge of /RE). The write address and
data can be latched very quickly after the fall of /RE (tRAH + tASC for
the column address and tDS for the data). During a write burst
sequence, the second write data can be posted at time tRSW after
/RE. Subsequent writes within a page can occur with write cycle
time tPC. During a write miss sequence, the /HIT output is driven
high, cache reads are inhibited, and the output buffers are disabled
(independently of /G) until time tWRR after /RE goes high. At the end
of a write sequence (after /CAL and /WE are brought high and tRE is
satisfied), /RE can be brought high to precharge the memory. Cache
reads can be performed concurrently with the precharge (see “/RE
Inactive Operation”). When /RE is inactive, the cache reads will
occur from the page accessed during the last /RE active read cycle.
is determined by either tAC and tCQV
DRAM Write Hit
A DRAM write request is initiated by clocking /RE while W/R,
.
/CAL, /WE, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified by row
address bits A (LRR: a 9-bit row address latch for each internal
8-9
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address matches the LRR, the EDRAM will write data to
both the DRAM page in the appropriate bank and its corresponding
SRAM cache simultaneously to maintain coherency. The write
address and data are posted to the DRAM as soon as the column
address is latched by bringing /CAL low and the write data is latched
/RE Inactive Operation
Data may be read from the SRAM cache without clocking /RE.
This capability allows the EDRAM to perform cache read
EDRAM Basic Operating Modes
A
Function
/S
L
/RE
↓
W/R
L
/F
H
H
H
H
L
Comment
0-10
Read Hit
Row = LRR
No DRAM Reference, Data in Cache
DRAM Row to Cache
Read Miss
L
↓
L
Row ≠ LRR
Write Hit
L
↓
H
Row = LRR
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
Write Miss
L
↓
H
Row ≠ LRR
Internal Refresh
Low Power Standby
Unallowed Mode
X
H
H
↓
X
X
X
X
H
L
X
X
H
Standby Current
X
H = High ; L = Low; X = Don ’t Care; ↓ = High -to-Low Tran sition ; LRR = Last Row Read
2-139
operations during precharge and refresh cycles to minimize wait
states. It is only necessary to select /S and /G and provide the
appropriate column address to read data as shown in the table
below. In this mode of operation, the cache reads will occur from
the page and bank accessed during the last /RE active read cycle.
To perform a cache read in static column mode, /CAL is held high,
and the cache contents at the specified column address will be
valid at time tAC after address is stable. To perform a cache read in
page mode, /CAL is clocked to latch the column address. When /RE
is inactive, the hit pin is not driven and is in a high impedance
state.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles where /S can be disabled.
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, an /RE only refresh may
be performed using an externally supplied row address. /RE
refresh is performed by executing a write cycle (W/R, /G, and /F
are high) where /CAL is not clocked. This is necessary so that the
current cache contents and LRR are not modified by the refresh
This option is desirable when the external control logic is
capable of fast hit/miss comparison. In this case, the controller can
avoid the time required to perform row/column multiplexing on hit
cycles.
Function
/S
L
/G
L
/CAL
H
A
0-7
operation. All combinations of addresses A must be sequenced
0-9
every 64ms refresh period. A does not need to be cycled. Read
Cache Read (Static Column)
Cache Read (Page Mode)
Col Adr
Col Adr
10
refresh cycles are not allowed because a DRAM refresh cycle does
not occur when a read refresh address matches the LRR address
latch.
L
L
↕
EDO Mode and Output Latch Enable Operation
Low Power Mode
The QLE and /CAL inputs can be used to create extended data
output (EDO) mode timings in either static column or page modes.
The DM512K32DT6 has an output latch enable (QLE) that can be
used to extend the data output valid time. The output latch enable
operates as shown in the following table.
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce
standby current.
Initialization Cycles
When QLE is low, the latch is transparent and the EDRAM
operates identically to the standard EDRAMs. When /CAL is high
during a static column mode read, the QLE input can be used to
latch the output to extend the data output valid time. QLE can be
held high during page mode reads. In this case, the data outputs
are latched while /CAL is high and open when /CAL is not high.
A minimum of eight /RE active initialization cycles (read,
write, or refresh) are required before normal operation is
guaranteed. Following these start-up cycles, two read cycles to
different row addresses must be performed for each of the four
internal banks of DRAM to initialize the internal cache logic. Row
address bits A and A define the four internal DRAM banks.
8
9
Unallowed Mode
QLE
L
/CAL
X
Comments
Read, write, or /RE only refresh operations must not be
performed to unselected memory banks by clocking /RE when /S is
high.
Output Transparent
↕
H
Output Latched When QLE=H (Static Column EDO)
Output Latched When /CAL=H (Page Mode EDO)
Reduced Pin Count Operation
Although it is desirable to use all EDRAM control pins to
H
↕
optimize system performance, the interface to the EDRAM may be
simplified to reduce the number of control lines by either tying pins
to ground or by tying one or more control inputs together. The /S
input can be tied to ground if the low power standby mode is not
required. The QLE input can be tied low if output latching is not
required, or it can be tied high if “extended data out” (hyper page
mode) is required. The /HIT output pin is not necessary for device
operation. The W/R and /G inputs can be tied together if reads are
not required during a write hit cycle. The simplified control interface
still allows the fast page read/write cycle times, fast random read/
write times, and hidden precharge functions available with the EDRAM.
Write-Per-Bit Operation
The DM512K72 DIMM offers a write-per-bit capability to
selectively modify individual parity bits (DQ
)
for byte write operations. The parity device 8(,D1M7, 2262,1353,)44i,s5s3e, 6le2c, 7te1d
via /CAL . Byte write selection to non-parity bits is accomplished via
/CAL .8The bits to be written are determined by a bit mask data
0-7
word which is placed on the parity I/O data pins prior to clocking
/RE. The logic one bits in the mask data select the bits to be
written. As soon as the mask is latched by /RE, the mask data is
removed and write data can be placed on the data bus. The mask is
only specified on the /RE transition. During page mode burst write
operations, the same mask is used for all write operations.
Pin Descriptions
/RE — Row Enable
These inputs are used to initiate DRAM read and write
operations and latch a row address. It is not necessary to clock /RE
to read data from the EDRAM SRAM row register. On read
operations, /RE can be brought high as soon as data is loaded into
cache to allow early precharge.
ECC Operation
The DM512K72DT6-xxN supports error correction coding
(ECC) by replacing the parity chip with a normal DM2203 device.
This version does not support write-per-bit parity operation.
2-140
these pins are also used to specify the bit mask used during write
operations.
/CAL — Column Address Latch
0-8
These inputs are used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low,
the column address latch contains the address present at the time
/CAL went low. Individual /CAL inputs are provided for each byte of
EDRAM to allow byte write capability.
A
0-10 — Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 8-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
W/R — Write/Read
This input along with /F input specifies the type of DRAM
operation initiated on the low going edge of /RE. When /F is high,
W/R specifies either a write (logic high) or read operation (logic
low).
QLE — Output Latch Enable
This input enables the EDRAM output latches. When QLE is
low, the output latch is transparent. Data is latched when both /CAL
and QLE are high. This allows output data to be extended during
either static column or page mode read cycles.
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when it is low on the
low going edge of /RE.
/HIT — Hit Pin
This output pin will be driven during /RE active read or write
cycles to indicate the hit/miss status of the cycle.
/WE — Write Enable
PD — Presence Detect
This input controls the latching of write data on the input data
pins. A write operation is initiated when both the /CAL for the
specified byte and /WE are low.
This output will indicate if the DIMM module is inserted in a
socket. When a DIMM is inserted, this pin is grounded. When no
DIMM is present, the pin is open.
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
V Power Supply
CC These inputs are connected to the +5 volt power supply.
V Ground
SS
/S — Chip Select
These inputs are connected to the power supply ground
connection.
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in a powered-down condition.
Read or write cycles must not be executed when /S is high. /S must
remain low throughout any read or write operation. Only /F refresh
operation can be executed when, /S is not enabled.
DQ0-71 — Data Input/Output
These CMOS/TTL bidirectional data pins are used to read and
write data to the EDRAM. On the DM2213 write-per-bit memory,
2-141
Pinout
Interconnect
Interconnect
Pin No. Function (Component Pin)
Organization
Ground
Pin No. Function (Component Pin)
Organization
Ground
1
2
Vss
85
86
87
88
VSS
U1-4
U1-6
U1-7
U1-9
Byte 0, I/O 0
Byte 0, I/O 1
Byte 0, I/O 2
Byte 0, I/O 3
+5 Volts
DQ36
U2-4
U2-6
U2-7
Byte 4, I/O 0
Byte 4, I/O 1
Byte 4, I/O 2
DQ0
DQ1
DQ2
DQ3
DQ
3
37
DQ38
4
5
89
90
91
92
93
94
95
96
97
98
99
100
DQ39
VDD
U2-9
Byte 4 I/O 3
+5 Volts
6
V
DD
7
DQ4
U1-13
U1-15
U1-16
U1-18
U5-4
Byte 0, I/O 4
Byte 0, I/O 5
Byte 0, I/O 6
Byte 0, I/O 7
Parity, I/O 0
Ground
DQ40
DQ41
DQ42
DQ 43
DQ 44
VSS
U2-13
U2-15
U2-16
U2-18
Byte 4 I/O 4
Byte 4 I/O 5
Byte 4, I/O 6
Byte 4, I/O 7
Parity, I/O 4
Ground
8
DQ5
9
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DQ7
U5-13
DQ8
VSS
DQ 45
DQ 46
DQ47
DQ48
U4-4
U4-6
U4-7
U4-9
Byte 5, I/O 0
Byte 5, I/O 1
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
DQ16
DQ17
U3-4
U3-6
U3-7
U3-9
U3-13
Byte 1, I/O 0
Byte 1, I/O 1
Byte 1, I/O 2
Byte 1, I/O 3
Byte 1, I/O 4
+5 Volts
Byte 5, I/O 2
Byte 5, I/O 3
101
102
103
DQ49
U4-13
Byte 5, I/O 4
VDD
+5 Volts
DQ50
U4-15
U4-16
U4-18
U5-15
Byte 5, I/O 5
U3-15
U3-16
U3-18
U5-6
Byte 1, I/O 5
Byte 1 I/O 6
Byte 1 I/O 7
Parity, I/O 1
Ground
DQ51
DQ52
DQ53
Byte 5, I/O 6
Byte 5, I/O 7
Parity, I/O 5
Ground
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
V
V
SS
SS
V
Ground
V
Ground
SS
SS
VDD
VDD
/F
+5 Volts
V
+5 Volts
DD
+5 Volts
VDD
/WE
/CAL0
/CAL2
/S
+5 Volts
U10D-49
U3-32
Refresh Pin
Byte 1 /CAL
Byte 3 /CAL
U10A-8
U1-32
Write Enable
Byte 0 /CAL
Byte 2 /CAL
Chip Select
Output Enable
Ground
/CAL1
/CAL3
N.C.
W/R
U8-32
U6-32
N.C.
U10A-14
U10B-15
U10D-43
Write/Read Mode
Ground
/G
V
VSS
A0
SS
A1
A3
A5
A7
A9
U10C-42
U10C-36
U11D-49
U11D-43
U11C-42
Address 1
Address 3
Address 5
Address 7
Address 9
U10B-21
U11A-8
Address 0
Address 2
A2
A4
U11A-14
U11B-15
U11B-21
U11C-36
Address 4
Address 6
Address 8
Address 10
A6
A8
N.C.
N.C.
VDD
N.C.
N.C.
A10
N.C.
+5 Volts
VDD
VDD
+5 Volts
N.C.
N.C.
+5 Volts
QLE
U12A-8
Output Latch Enable
2-142
Pinout
Interconnect
Interconnect
Pin No. Function (Component Pin)
Organization
Ground
Pin No. Function (Component Pin)
Organization
V
43
127
VSS
Ground
Ground
SS
44
45
N.C.
128
129
130
VSS
N.C.
/RE
U12A-14
Row Enable
Byte 4 /CAL
Byte 6 /CAL
N.C.
N.C.
Byte 5
Byte 7
/CAL5
/CAL7
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
/CAL4
/CAL6
N.C.
U2-32
U7-32
N.C.
U4-32
U9-32
131
/CAL8
VDD
132
133
134
135
136
137
138
139
140
141
142
143
U5-32
Parity
V
+5 Volts
+5 Volts
DD
V
+5 Volts
VDD
+5 Volts
DD
V
Ground
V
Ground
SS
SS
DQ54
DQ 55
VSS
U7-4
U7-6
Byte 6, I/O 0
Byte 6, I/O 1
Ground
DQ18
DQ19
U6-4
U6-6
Byte 2, I/O 0
Byte 2, I/O 1
Ground
V
SS
DQ56
U7-7
Byte 6, I/O 2
Byte 6, I/O 3
Byte 6, I/O 4
DQ20
DQ21
DQ22
DQ23
VDD
U6-7
Byte 2, I/O 2
Byte 2, I/O 3
Byte 2, I/O 4
Byte 2, I/O 5
+5 Volts
DQ 57
DQ 58
DQ59
VDD
U7-9
U6-9
U7-13
U7-15
U6-13
U6-15
Byte 6, I/O 5
+5 Volts
DQ24
PD
U6-16
Byte 2, I/O 6
Ground
144
145
146
DQ60
U7-16
Byte 6, I/O 6
Hit Output
/Hit
U12C-36
U12C-42
N.C.
N.C.
N.C.
N.C.
N.C.
U12B-15
U12B-21
147
148
V
Ground
V
Ground
SS
SS
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ61
U7-18
Byte 6, I/O 7
Parity, I/O 6
Byte 7, I/O 0
DQ25
DQ26
DQ27
U6-18
U5-7
U8-4
Byte 2, I/O 7
Parity, I/O 2
Byte 3, I/O 0
Ground
DQ62
DQ63
U5-16
U9-4
V
Ground
V
SS
SS
DQ
Byte 7, I/O 1
Byte 7, I/O 2
Byte 7, I/O 3
Byte 7, I/O 4
+5 Volts
DQ28
DQ29
DQ30
DQ31
U8-6
U8-7
U8-9
U8-13
Byte 3, I/O 1
Byte 3, I/O 2
Byte 3, I/O 3
Byte 3, I/O 4
+5 Volts
U9-6
U9-7
U9-9
U9-13
64
DQ65
DQ66
DQ67
V
VDD
SS
U9-15
Byte 7, I/O 5
Byte 7, I/O 6
DQ68
DQ69
DQ70
DQ32
DQ33
U8-15
U8-16
U8-18
U5-9
Byte 3, I/O 5
Byte 3, I/O 6
Byte 3, I/O 7
Parity, I/O 3
Ground
U9-16
U9-18
U5-18
Byte 7, I/O 7
Parity, I/O 7
Ground
DQ34
DQ35
VSS
DQ71
V
SS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
V
+5 Volts
+5 Volts
VDD
VDD
+5 Volts
DD
V
+5 Volts
DD
2-143
Buffer Diagrams
DIMM Edge
Connector
U12A
U12D
2
3
5
48
47
45
QLE Bank0A
QLE Bank0B
QLE Bank0C
N.C.
N.C.
N.C.
QLE 8
43
42
6
44
QLE Bank0D
N.C.
9
55
54
52
/RE Bank0A
/RE Bank0B
/RE Bank0C
N.C.
N.C.
N.C.
10
12
/RE 14
49
45
13
51
/RE Bank0D
N.C.
1
58
U12B
U11A
16
17
19
2
3
5
BMO Bank0A
BMO Bank0B
BMO Bank0C
A2 Bank0A
A2 Bank0B
A2 Bank0C
15
A2 8
147
34
35
20
6
BMO Bank0D
A2 Bank0D
23
24
26
9
BE Bank0A
BE Bank0B
BE Bank0C
A4 Bank0A
A4 Bank0B
A4 Bank0C
10
12
21
A4 14
63
27
13
BE Bank0D
A4 BankOD
VDD
28
1
U12C
U11B
34
33
31
BM2 Bank0A
BM2 Bank0B
BM2 Bank0C
16
17
19
A6 Bank0A
A6 Bank0B
A6 Bank0C
36
A6 15
145
146
36
37
30
BM2 Bank0d
20
A6 Bank0D
41
40
38
BM1 Bank0A
BM1 Bank0B
BM1 Bank0C
23
24
26
A8 Bank0A
A8 Bank0B
A8 Bank0C
42
A8 21
37
BM1 Bank0D
27
A8 BankOD
VDD
29
28
Note: Address and control buffers add a minimum of 1.5ns and a maximum of 3.8ns delay to each signal path.
2-144
Buffer Diagrams
DIMM Edge
Connector
U11C
U10B
34
33
31
16
17
19
A10 Bank0A
A10 Bank0B
A10 Bank0C
/G Bank0A
/G Bank0B
/G Bank0C
A10 36
/G 15
38
31
30
20
A10 Bank0D
/G Bank0D
41
40
38
23
24
26
A9 Bank0A
A9 Bank0B
A9 Bank0C
A0 Bank0A
A0 Bank0B
A0 Bank0C
A9 42
A0 21
121
33
37
27
A9 Bank0D
A0 Bank0D
29
28
U11D
U10C
48
47
45
34
33
31
A7 Bank0A
A7 Bank0B
A7 Bank0C
A3 Bank0A
A3 Bank0B
A3 Bank0C
A7 43
A3 36
120
119
118
117
44
30
A7 Bank0D
A3 Bank0D
55
54
52
41
40
38
A5 Bank0A
A5 Bank0B
A5 Bank0C
A1 Bank0A
A1 Bank0B
A1 Bank0C
A5 49
A1 42
51
37
A5 Bank0D
A1 Bank0D
58
29
IDT74FCT162344ETPA
U10D
U10A
48
47
45
2
3
5
VDD
W/R Bank0A
W/R Bank0B
W/R Bank0C
/WE Bank0A
/WE Bank0B
/WE Bank0C
4
11
18
Vcc
Vcc
7
W/R 43
/WE 8
115
111
27
30
22
44
6
W/R Bank0D
/WE Bank0D
25
35 Vcc
50 Vcc
55
54
52
9
/F Bank0A
/F Bank0B
/F Bank0C
/S Bank0A
/S Bank0B
/S Bank0C
32
39
46
10
12
/F 49
/S 14
.22µf
51
13
/F BankOD
/S Bank0D
53
58
1
Note: Address and control buffers add a minimum of 1.5ns and a maximum of 3.8ns delay to each signal path.
2-145
Interconnect Diagram
DQ0-71
U9
U8
Byte 7
*
U5*
Bank 0D
Byte 3
U7
Bank 0D
Parity
U6
DM2203T
Bank 0C
Byte 6
DM2203T
U4
Byte 2
Bank 0C
U3
DM2213T
Bank 0C
Byte 5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
27
28
29
30
35
36
37
38
39
40
41
U2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
DM2203T
Byte 1
U1
Bank 0B
DM2203T
Byte 4
Bank 0B
Byte 0
Bank 0A
Bank 0A
DM2203T
DM2203T
W/R
/WE
/F
43
26
2
42
12
10
33
W/R
/WE
/F
/S
/G
QLE
/RE
DM2203T
/S
DM2203T
/G
QLE
/RE
HIT
/CAL0
/CAL4
/CAL1
/CAL5
/CAL2
/CAL6
/CAL8
/CAL3
/CAL 7
Note: For reference to buffer connection, append bank name to address or clock name, i.e., A10 + Bank 0A = A10BANK0A. Refer to Buffer Interconnect Diagram for
detailed buffer connections. DQ0-71 and /CAL0-8 are directly connected to pins.
* Not Present on DM512K64
2-146
Pin Names
Pin Names
Function
Pin Names
/WE
Function
A
Address Inputs
Row Enable
Write Enable
Output Enable
Refresh Control
Chip Select
0-10
/G
/RE
DQ0-71
/CAL0-8
W/R
Data In/Data Out
Column Address Latch
Write/Read Control
Power (+5V)
/F
/S
/HIT
QLE
NC
Hit Output
V
Output Latch Enable
Not Connected
CC
V
Ground
SS
Absolute Maximum Ratings
Capacitance
(Beyon d Wh ich Perm an en t Dam age Cou ld Resu lt)
Description
Ratings
Description
Max
Pins
Input Voltage (V )
- 1 ~ V +1
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
I/O Capacitance
14pf
14pf
10pf
14pf
15pf
A
0-10
IN
CC
Output Voltage (VOUT
)
- 1 ~ V +1
CC
/CAL0-8
/G, QLE
W/R, /F
DQ0-71
Power Supply Voltage (V )
- 1 ~ 7v
CC
Ambient Operating Temperature (TA)
Storage Temperature (TS)
-40 ~ +70°C
-55 ~ 150°C
Static Discharge Voltage
(Per MIL-STD-883 Method 3015)
Class 1
50mA*
/RE, /S
/HIT
Input Capacitance
Input Capacitance
12pf
12pf
Short Circuit O/P Current (IOUT
)
*On e ou tpu t at a tim e; sh ort du ration .
AC Test Load and Waveforms
VIN Tim in g Referen ce Poin t at VIL an d VIH
V
Tim in g Referen ced to 1.5 Volts
OUT
5.0V
R1 = 828Ω
V
V
IH
IH
Output
V
V
IL
IL
GND
R2 = 295Ω
CL = 50pf
≤5ns
≤5ns
Load Circuit
Input Waveforms
2-147
Electrical Characteristics
TA = 0 - 70°C (Com m ercial)
Symbol
Parameters
Max
Min
Test Conditions
All Voltages Referenced to V
V
Supply Voltage
4.75V
5.25V
CC
SS
V
Input High Voltage
Input Low Voltage
Output High Level
Output Low Level
Input Leakage Current
Output Leakage Current
2.4V
-1.0V
2.4V
V +1
IH
CC
V
0.8V
IL
VOH
VOL
IOUT = - 5mA
IOUT = 4.2mA
0.4V
90µA
90µA
V
-90µA
-90µA
0V ≤ V ≤ 6.5V, All Other Pins Not Under Test = 0V
i(L)
IN
V
0V ≤ V , 0V ≤ VOUT ≤ 5.5V
0(L)
IN
DM512K72DT6
33MHz Typ(1)
1166mA
-15 Max
Symbol
Operating Current
-12 Max
Test Condition
Notes
ICC1
Random Read
2465mA 1970mA /RE, /CAL, /G and Addresses Cycling: tC = tC Minimum
1745mA 1385mA /CAL, /G and Addresses Cycling: tPC = tPC Minimum
1430mA 1160mA /G and Addresses Cycling: tAC = tAC Minimum
2, 3
ICC2
ICC3
ICC4
ICC5
ICC6
ICCT
Fast Page Mode Read
Static Column Read
Random Write
761mA
2, 4
2, 4
2, 3
2, 4
671mA
1391mA
626mA
11mA
2150mA
/RE, /CAL, /WE and Addresses Cycling: tC = tC Minimum
1700mA
Fast Page Mode Write
Standby
1655mA 1295mA /CAL, /WE and Addresses Cycling: tPC = tPC Minimum
11mA
—
11mA
—
All Control Inputs Stable ≥ VCC - 0.2V, Outputs Driven
1
Average Typical
446mA
See "Estimating EDRAM Operating Power" Application Note
Operating Current
DM512K64DT6
33MHz Typ(1)
1056mA
-15 Max
Symbol
Operating Current
-12 Max
Test Condition
Notes
ICC1
Random Read
2240mA 1790mA /RE, /CAL, /G and Addresses Cycling: tC = tC Minimum
1600mA 1270mA /CAL, /G and Addresses Cycling: tPC = tPC Minimum
1320mA 1070mA /G and Addresses Cycling: tAC = tAC Minimum
2, 3
ICC2
ICC3
ICC4
ICC5
ICC6
ICCT
Fast Page Mode Read
Static Column Read
Random Write
696mA
2, 4
2, 4
2, 3
2, 4
616mA
1256mA
576mA
10mA
1960mA
/RE, /CAL, /WE and Addresses Cycling: tC = tC Minimum
1550mA
Fast Page Mode Write
Standby
1520mA 1190mA /CAL, /WE and Addresses Cycling: tPC = tPC Minimum
10mA
—
10mA
—
All Control Inputs Stable ≥ VCC - 0.2V, Outputs Driven
1
Average Typical
416mA
See "Estimating EDRAM Operating Power" Application Note
Operating Current
(1) “33MHz Typ” refers to worst case ICC expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested
or guaranteed.
(2) ICC is dependent on cycle rates and is measured with CMOS levels and the outputs open.
(3) ICC is measured with a maximum of one address change while /RE = V
IL
(4) ICC is measured with a maximum of one address change while /CAL = V
IH
2-148
Switching Characteristics Note: These parameters do not include buffer delays. See pages 2-144-5 for derating factors.VCC = 5V ± 5%, TA = 0 to 70°C, CL = 50pf
-12
-15
Symbol
Description
Units
Min
Max
Min
Max
(1)
t
Column Address Access Time
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC
t
t
t
t
t
t
t
t
t
t
t
t
Column Address Valid to /CAL Inactive (Write Cycle)
Address Valid to /CAL Inactive (QLE High)
Column Address Hold From QLE High (/CAL=H)
Address Valid to QLE High
12
12
0
15
15
0
ACH
ACI
AHQ
AQH
AQX
ASC
ASR
C
12
5
15
5
Column Address Change to Output Data Invalid
Column Address Setup Time
5
5
Row Address Setup Time
5
5
65
25
6
55
20
5
Row Enable Cycle Time
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only
Column Address Latch Active Time
C1
CAE
CAH
CH
Column Address Hold Time
0
0
5
5
Column Address Latch High Time (Latch Transparent)
/CAL Inactive Lead Time to /RE Inactive (Write Cycles Only)
t
-2
-2
CHR
t
0
0
Column Address Latch High to Write Enable Low (Multiple Writes)
Column Address Latch Low to Data Valid (QLE High)
Column Address Latch Low to Data Invalid (QLE High)
Column Address Latch High to Data Valid
Column Address Latch Inactive to Data Invalid
Column Address Latch Setup Time to Row Enable
/WE Low to /CAL Inactive
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CHW
CLV
CQH
CQV
CQX
CRP
CWL
DH
t
7
7
t
t
t
t
t
t
t
t
t
0
0
15
15
5
5
5
0
1
5
5
5
5
5
0
Data Input Hold Time
1.5
5
Mask Hold Time From Row Enable (Write-Per-Bit)
Mask Setup Time to Row Enable (Write-Per-Bit)
Data Input Setup Time
DMH
DMS
DS
5
(1)
GQV
t
t
t
t
t
t
t
t
t
t
t
Output Enable Access Time
5
5
5
5
5
5
5
5
(2,3)
GQX
Output Enable to Output Drive Time
0
0
0
0
(4,5)
GQZ
Output Turn-Off Delay From Output Disabled (/G↑)
Hit Valid From Row Enable
HV
Hit Turn-Off From Row Enable Going High
/F and W/R Mode Select Hold Time
0
0
0
0
HZ
MH
MSU
/F and W/R Mode Select Setup Time
/CAL, /G, and /WE Hold Time For /RE-Only Refresh
/CAL, /G, and /WE Setup Time For /RE-Only Refresh
Column Address Latch Cycle Time
5
5
0
0
NRH
NRS
5
5
12
0
15
0
PC
QLE High to /CAL Inactive
QCI
QH
t
QLE High Time
5
5
2-149
Switching Characteristics Note: These parameters do not include buffer delays. See pages 2-144-5 for derating factors.VCC = 5V ± 5%, TA = 0 to 70°C, CL = 50pf
-12
-15
Symbol
Description
Units
Min
5
Max
Min
5
Max
t
QLE Low Time
ns
ns
ns
ns
ns
ns
ns
QL
t
t
t
t
t
Data Hold From QLE Inactive
Data Valid From QLE Low
2
2
QQH
QQV
7.5
30
15
7.5
35
17
(1)
RAC
Row Enable Access Time, On a Cache Miss
Row Enable Access Time, On a Cache Hit (Limit Becomes t
Row Address Hold Time
(1)
)
RAC1
AC
1
30
8
1.5
35
10
RAH
RE
t
t
t
t
t
t
t
Row Enable Active Time
100000
100000
Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle
Refresh Period
ns
ms
ns
ns
ns
ns
RE1
REF
RGX
RQX1
RP
64
12
64
15
Output Enable Don't Care From Row Enable (Write, Cache Miss), DQ = Hi-Z
Row Enable High to Output Turn-On After Write Miss
Row Precharge Time
9
0
10
(2,5)
20
8
25
10
Row Precharge Time, Cache Hit (Row=LRR) Read Cycle
RP1
t
t
0
0
15
40
15
Write Enable Don’t Care From Row Enable (Write Only)
Last Write Address Latch to End of Write
ns
ns
RRH
RSH
12
t
t
t
t
Row Enable to Column Address Latch Low For Second Write
Last Write Enable to End of Write
Column Address Cycle Time
35
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RSW
RWL
15
0
SC
Select Hold From Row Enable
SHR
(1)
SQV
t
t
t
t
t
t
t
t
t
t
t
t
Chip Select Access Time
12
12
8
15
15
10
(2,3)
SQX
0
0
Output Turn-On From Select Low
Output Turn-Off From Chip Select
Select Setup Time to Row Enable
Transition Time (Rise and Fall)
0
0
(4,5)
SQZ
SSR
T
5
5
1
10
1
10
12
5
Write Enable Cycle Time
15
5
WC
WCH
WHR
WI
Column Address Latch Low to Write Enable Inactive Time
Write Enable Hold After /RE
(6)
0
0
5
Write Enable Inactive Time
5
5
5
Write Enable Active Time
WP
(1)
12
12
12
15
15
15
Data Valid From Write Enable High
Data Output Turn-On From Write Enable High
WQV
(2,5)
0
0
5
0
0
5
WQX
(3,4)
WQZ
t
t
t
Data Turn-Off From Write Enable Low
ns
ns
ns
Write Enable Setup Time to Row Enable
WRP
WRR
Write to Read Recovery (Following Write Miss)
12
15
(1) V Timing Reference Point at 1.5V; (2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to V or V ; (3) Minimum Specification is Referenced from V and Maximum
OUT OH OL IH
Specification is Referenced from V on Input Control Signal; (4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to V or V ; (5) Minimum Specification is Referenced from V and
IL
OH OL
IL
Maximum Specification is Referenced from V on Input Control Signal; (6) On DM2213, t
Minimum is t
IH
WHR
DS
2-150
/RE Inactive Cache Read Hit (Static Column Mode)
/RE
/F
W/R
A
0-7
A
Column 1
tSC
Column 2
tSC
Column 3
tSC
Column 4
0-10
/CAL
0-8
/WE
tAC
tAC
tAC
tAC
tAQX
tAQX
tAQX
Open
tGQX
Data 1
Data 2
Data 3
Data 4
tGQZ
DQ
0-71
tGQV
/G
tSQX
tSQV
tSQZ
/S
/HIT
Open
Don’t Care or Indeterminate
NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
2-151
/RE Inactive Cache Read Hit (Page Mode)
/RE
/F
W/R
tCAH
A
0-7
A
Column 1
tASC
Column 2
tASC
Row
0-10
tCAH
tCAE
tPC
tCH
/CAL
0-8
tCQV
/WE
tAC
tCQX
Data 1
Data 2
DQ
0-71
tAC
tGQX
tGQZ
tGQV
/G
tSQX
tSQV
tSQZ
/S
Open
/HIT
Don’t Care or Indeterminate
NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
2-152
/RE Active Cache Read Hit (Static Column Mode)
tC1
tRE1
tMSU
/RE
tRP1
tMH
/F
tMSU
tMH
W/R
tASR
tRAH
A
0-7
A
Row
Column 1
tSC
Column 2
tSC
Column 3
tSC
Column 4
0-10
tCRP
/CAL
0-8
/WE
tAC
tAC
tAC
tAC
tRAC1
tAQX
tAQX
tAQX
Open
tGQX
Data 1
Data 2
Data 3
Data 4
tGQZ
DQ
0-71
tGQV
/G
tSHR
tSQZ
tSSR
/S
tHV
Open
tHZ
Open
/HIT
Don’t Care or Indeterminate
2-153
/RE Active Cache Read Hit (Page Mode)
tC1
tRE1
tMSU
/RE
tRP1
tMH
/F
tMSU
tMH
W/R
tASR
tRAH
A
tCAH
0-7
A
Row
Column 1
tASC
Column 2
tASC
Row
0-10
tCRP
tCAH
tCAE
tPC
tCH
/CAL
0-8
tCQV
/WE
tAC
tCQX
tRAC1
Open
Data 1
Data 2
DQ
0-71
tAC
tGQX
tGQZ
tGQV
/G
tSHR
tSQZ
tSSR
/S
t HV
Open
tHZ
Open
/HIT
Don’t Care or Indeterminate
2-154
/RE Active Cache Read Miss (Static Column Mode)
tC
tRE
/RE
/F
tRP
tMSU
tMSU
tASR
tMH
tMH
tRAH
W/R
tSC
Column 1
A
A
0-7
A
A
0-10
0-10
0-7
Row
Column 2
Row
A
0-10
tCRP
/CAL
0-8
tAQX
/WE
tAC
tAC
tRAC
tAQX
Open
Data 1
Data 2
DQ
0-71
tGQX
tGQV
tGQZ
/G
tSHR
tSSR
tSQZ
/S
tHV
Open
tHZ
/HIT
Open
Don’t Care or Indeterminate
2-155
/RE Active Cache Read Miss (Page Mode)
tC
tRE
/RE
tRP
tMSU
tMH
/F
tMSU
tMH
W/R
tASR
tRAH
tCAH
A
A
A
A
0-10
0-10
0-7
0-7
Row
Column 1
Column 2
tASC
Row
A
0-10
tASC
tCRP
tCAH
tCAE
tCH
/CAL
/WE
tPC
tCQV
tAC
tCQX
tRAC
Open
Data 1
Data 2
DQ
0-71
tAC
tGQZ
/G
tGQX
tSHR
tSSR
tGQV
tSQZ
/S
tHV
Open
tHZ
/HIT
Open
Don’t Care or Indeterminate
2-156
Output Latch Enable Operation (Static Column EDO Mode Read)
/CAL
0-8
tAC
tAC
A
Column 1
Column 2
0-7
tAQX
tAHQ
tQQH
DQ
Data 1
Data 2
0-71
tAQH
tQQV
tQL
QLE
tQH
Output Latch Enable Operation (Page Mode EDO Read)
tPC
tQCI
tCAE
/CAL
0-8
tACI
tCLV
tCH
tAC
tAC
A
Column 1
Column 2
0-7
tAQX
tCQH
DQ
Data 1
Data 2
0-71
tCQV
QLE
Output Latch Enable Operation (Asynchronous Access)
tPC
tCAE
tCH
/CAL
0-8
tQCI
tACI
tACI
tACI
A
Column 1
tAC
Column 2
tCQV
Column 3
tCQV
0-7
tAC
tAC
DQ
Data 1
tQQH
Data 2
Data 3
0-71
tQQV
tQQV
tQQV
QLE
tQQH
tQL
tQH
2-157
Burst Write (Hit or Miss) Followed By /RE Inactive Cache Reads
tRE
/RE
tMSU
tRP
tMH
/F
tMSU
tMH
W/R
tASR
tCAH
A
tRAH
tRSW
A
A
0-7
0-7
0-7
A
Row
Column 1
Column 2
tACH
Column n
0-10
tACH
A
0-10
tASC
tCAH
tRSH
tCRP
tCWL
tCWL
tCHR
tCAE
tCAE
/CAL
tCH
tCHW
0-8
tWCH
tWP
tPC
tWCH
tWP
tWRP
tRRH
/WE
tWI
tWRR
tWHR
tWC
tDS
tRWL
tDH
tDS
tDH
tAC
DQ
Open
Data 1
Data 2
Cache (Column n)
0-71
tGQX
/G
tGQV
tSSR
/S
tHV
Open
tHZ
/HIT
Open
Don’t Care or Indeterminate
NOTES: 1. /G becomes a don’t care after t during a write miss.
RGX
2-158
Read/Write During Write Hit Cycle (Can Include Read-Modify-Write)
tC
tRE
/RE
tRP
tMSU
tMH
/F
tMSU
tMH
W/R
tASR
tAC
tRAH
tCAH
A
0-7
A
Row
Column 1
Column 2
Column 3
0-10
tACH
tRSH
tCRP
tASC
tCAE
tWCH
tCHR
/CAL
0-8
tCQV
tCWL
tWP
tWRP
tRRH
/WE
tWHR
tAQX
tDS
tRWL
tAC
tWQV
DQ
Read Data
Write Data
tDH
tGQZ
Read Data
0-71
tGQX
tGQV
tGQZ
tWQX
tGQV
/G
tSSR
/S
tHV
Open
tHZ
Open
/HIT
Don’t Care or Indeterminate
NOTES: 1. If column address one equals column address two, then a read-modify-write cycle is performed.
2-159
Write-Per-Bit Cycle (/G=High)
tRE
tRP
/RE
tCHR
tRSH
tCAE
tACH
/CAL
0-8
tRAH
tASC
tASR
tCAH
A
0-7
A
Row
Column
0-10
tMH
tMSU
tCWL
W/R
tRWL
tWCH
tDMH
tDMS
DQ
Mask
Data
0-71
tDS
tRRH
tWRP
tDH
tWP
/WE
tWHR
tMSU
/F
/S
tMH
tSSR
tSHR
tHV
Open
tHZ
/HIT
Open
Don’t Care or Indeterminate
NOTES: 1. Data mask bit high (1) enables bit write; data mask bit low (0) inhibits bit write.
2. Write-per-bit cycle valid only for DM512K72DT6.
2-160
/F Refresh Cycle
tRE
/RE
/F
tMSU
tRP
tMH
Don’t Care or Indeterminate
NOTES: 1. During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don’t care.
2. /RE inactive cache reads may be performed in parallel with /F refresh cycles.
/RE-Only Refresh
tC
tRE
/RE
tRP
tASR
tRAH
A
ROW
0-10
tNRS
tNRH
/CAL , /WE, /G
0-8
tMSU
W/R, /F
tMH
tSSR
tSHR
/S
tHV
tHZ
/HIT
Open
Open
Don’t Care or Indeterminate
NOTES: 1. All binary combinations of A must be refreshed every 64ms interval. A does not have to be cycled, but must remain valid
0-9
10
during row address setup and hold times.
2. /RE refresh is write cycle with no /CAL active cycle.
2-161
Mechancial Data
168 Pin DIMM Module Configuration
Inches (mm)
5.250(133.35)
U1
C1
U2
C2 U3
C3
U4
C4 U5
C5
U6
C6
U77
C7
U8
C8
U9
C9
.104 (2.64)
U1
U2
U3
U4
U5
U6
U7
U8
U9
1.500
R1
R2
R3
0.700
U10
U11
U12
.050 (1.27)
2.585 (65.66)
0.050 (1.27)
0.040 (1.04)
Enhanced DM2203T-xx, 512Kx8 EDRAM, 300 Mil TSOP
U1-4, U6-9 —
U5 —
Enhanced DM2213T-xx, 512Kx8 EDRAM with Write-per-bit (not present on DM512K64DT)
U10-12 —
IDT 74FCT162344ETPA Address/Clock Driver or Equivalent
0.22µF Chip Capacitor
Robinson Nugent DIMS - 168BD5-TR or Equivalent
C1-12 —
Socket —
Part Numbering System
DM512K72DT 6- 12 N
Error Check Mode (72-bit Only)
Blank - Write-per-bit Parity
N - ECC (No Write-per-bit)
Access Time from Cache in Nanoseconds
12ns
15ns
Packaging System
T = 300 Mil, Plastic TSOP - II
Memory Module Configuration
D= DIMM
I/O Width
64 = 64 Bits
72 = 72 Bits
Memory Depth
512K
1M
Dynamic Memory
The information contained herein is subject to change without notice. Enhanced Memory Systems Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in
an Enhanced product, nor does it convey or imply any license under patent or other rights.
2-162
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