DEMO-HSMP38-XX [ETC]
Demonstration Circuit Board ; 演示电路板
| 型号： | DEMO-HSMP38-XX |
| 厂家： | 
ETC |
| 描述： | Demonstration Circuit Board
|
| 文件： | 总8页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Surface Mount RF PIN Low
Distortion Attenuator Diodes
Technical Data
HSMP-381x Series and
HSMP-481x Series
Features
Package Lead Code
Identification, SOT-23
( Top View)
Package Lead Code
Identification, SOT-323
( Top View)
• Diodes Optimized for:
– Low Distortion Attenuating
– Microwave Frequency
Operation
SINGLE
3
SERIES
3
SERIES
SINGLE
• Surface Mount Packages
– Single and Dual Versions
– Tape and Reel Options
Available
1
2
1
2
B
C
#0
#2
COMMON
ANODE
3
COMMON
CATHODE
3
COMMON
ANODE
COMMON
CATHODE
• Low Failure in Time ( FIT)
Rate[1]
Note:
1. For more information see the
Surface Mount PIN Reliability Data
Sheet.
1
2
1
2
E
F
#4
#3
DUAL CATHODE
DUAL CATHODE
3
Description/Applications
The HSMP-381x series is
1
2
4810
481B
specifically designed for low
distortion attenuator applica-
tions. The HSMP-481x products
feature ultra low parasitic
inductance in the SOT-23 and
SOT-323 packages. They are
specifically designed for use at
frequencies which are much
higher than the upper limit for
conventional diodes.
A SPICE model is not available
for PIN diodes as SPICE does not
provide for a key PIN diode
characteristic, carrier lifetime.
2
Absolute Maximum Ratings[1] TC = +25°C
Symbol Parameter
Unit
SOT-23
SOT-323
If
Forward Current (1 µs Pulse) Amp
1
Same as VBR
150
1
Same as VBR
150
PIV
Tj
Peak Inverse Voltage
Junction Temperature
Storage Temperature
Thermal Resistance[2]
V
°C
Tstg
θjc
°C
-65 to 150
500
-65 to 150
150
°C/W
Notes:
1. Operation in excess of any one of these conditions may result in permanent damage to
the device.
2.
TC = +25°C, where TC is defined to be the temperature at the package pins where
contact is made to the circuit board.
Electrical Specifications TC = +25°C ( Each Diode)
Conventional Diodes
Minimum Maximum Maximum
Minimum
High
Maximum
Low
Part
Package
Breakdown
Total
Total
Number Marking Lead
Voltage
Resistance Capacitance Resistance Resistance
HSMP-
Code
Code Configuration
VBR ( V)
RT ( Ω)
CT ( pF)
RH ( Ω)
RL ( Ω)
3810
3812
3813
3814
381B
381C
381E
381F
E0[1]
E2[1]
E3[1]
E4[1]
E0[2]
E2[2]
E3[2]
E4[2]
0
2
Single
100
3.0
0.35
1500
10
Series
3
4
Common Anode
Common Cathode
Single
B
C
E
F
Series
Common Anode
Common Cathode
Test Conditions
VR = VBR
Measure
IF = 100 mA
f = 100 MHz
VR = 50 V
f = 1 MHz
IR = 0.01 mA IF = 20 mA
f = 100 MHz f= 100 MHz
IR ≤ 10 µA
High Frequency ( Low Inductance, 500 MHz – 3 GHz) PIN Diodes
Minimum Maximum
Typical
Total
Maximum
Total
Typical
Total
Part
Package
Breakdown
Series
Number Marking Lead
Voltage
Resistance Capacitance Capacitance Inductance
HSMP-
Code
Code Configuration
VBR ( V)
RS (Ω)
CT ( pF)
CT ( pF)
LT ( nH)
4810
481B
EB
EB
B[1] Dual Cathode
B[2] Dual Cathode
100
3.0
0.35
0.4
1.0
Test Conditions
VR = VBR
Measure
IR ≤ 10 µA
IF = 100 mA
VR = 50 V
f = 1 MHz
VR = 50 V f = 500 MHz–
f = 1 MHz
VR = 0 V
3 GHz
Notes:
1. Package marking code is white.
2. Package laser marked.
3
Typical Parameters at TC = 25°C
Part Number
HSMP-
Series Resistance
Carrier Lifetime
Reverse Recovery Time
Trr (ns)
Total Capacitance
CT ( pF)
RS ( Ω)
τ ( ns)
381x
75
1500
300
0.27 @ 50 V
f = 1 MHz
Test Conditions
IF = 1 mA
IF = 50 mA
V = 10 V
R
f = 100 MHz
IR = 250 mA
IF = 20 mA
90% Recovery
Typical Parameters at TC = 25°C ( unless otherwise noted) , Single Diode
120
110
100
90
10000
1000
100
10
0.45
0.40
0.35
0.30
0.25
0.20
Diode Mounted as a
Series Attenuator
in a 50 Ohm Microstrip
and Tested at 123 MHz
TA = +85°C
T
T
A = +25°C
A = –55°C
1 MHz
80
70
30 MHz
60
50
frequency>100 MHz
1
0.01
40
1000
0.15
0.1
1
10
100
100
10
0
2
4
6
8
10 12 14 16 18 20
I
– FORWARD BIAS CURRENT (mA)
REVERSE VOLTAGE (V)
DIODE RF RESISTANCE (OHMS)
F
Figure 1. RF Capacitance vs. Reverse
Bias.
Figure 3. 2nd Harmonic Input
Intercept Point vs. Diode RF
Resistance.
Figure 2. RF Resistance vs. Forward
Bias Current.
100
10
Typical Applications for Multiple Diode Products
VARIABLE BIAS
1
RF IN/OUT
INPUT
0.1
125°C 25°C –50°C
0.01
0
0.2
0.4
0.6
0.8
1.0 1.2
V
– FORWARD VOLTAGE (mA)
F
Figure 4. Forward Current vs.
Forward Voltage.
FIXED
BIAS
VOLTAGE
Figure 5. Four Diode π Attenuator. See Application Note 1048
for Details.
4
Typical Applications for HSMP-481x Low Inductance Series
3
Microstrip Series
Connection for
HSMP-481x Series
In order to take full advantage of
the low inductance of the
HSMP-481x series when using
them in series applications,
both lead 1 and lead 2 should be
connected together, as shown in
Figure 7.
1
2
HSMP-481x
Figure 7. Circuit Layout.
Figure 6. Internal Connections.
Microstrip Shunt
Connections for
50 OHM MICROSTRIP LINES
1.5 nH
1.5 nH
HSMP-481x Series
In Figure 8, the center
conductor of the microstrip
line is interrupted and
R
j
0.3 pF
leads 1 and 2 of the
HSMP-481x series diode are
placed across the resulting gap.
This forces the 1.5 nH lead
inductance of leads 1 and 2 to
appear as part of a low pass
filter, reducing the shunt
0.3 nH
0.3 nH
PAD CONNECTED TO
GROUND BY TWO
VIA HOLES
0.08
≈ 0.9 + 2.5
Rj
Ib
Figure 8. Circuit Layout.
Figure 9. Equivalent Circuit.
parasitic inductance and
increasing the maximum
available attenuation. The
0.3 nHof shunt inductance
external to the diode is created
by the via holes, and is a good
estimate for 0.032" thick material.
5
Typical Applications for HSMP-481x Low Inductance Series ( continued)
Co-Planar Waveguide
Groundplane
Co-Planar Waveguide
Shunt Connection for
Center Conductor
HSMP-481x Series
Co-Planar waveguide, with
Groundplane
ground on the top side of the
printed circuit board, is shown
in Figure 10. Since it eliminates
the need for via holes to ground,
it offers lower shunt parasitic
Figure 10. Circuit Layout.
inductance and higher maximum
attenuation when compared to a
microstrip circuit.
R
0.3 pF
j
0.75 nH
Figure 11. Equivalent Circuit.
Equivalent Circuit Model
HSMS-381x Chip*
R
R
s
j
2.5 Ω
Cj
RT = 2.5 + Rj
CT = CP + Cj
80
0.18 pF*
* Measured at -20 V
Rj =
Ω
I0.9
I = Forward Bias Current in mA
*See AN1124 for package models.
6
SMT Assembly
passes through one or more
Assembly Information
SOT-323 PCB Footprint
Reliable assembly of surface
mount components is a complex
process that involves many
material, process, and equipment
factors, including: method of
heating (e.g., IR or vapor phase
reflow, wave soldering, etc.)
circuit board material, conductor
thickness and pattern, type of
solder alloy, and the thermal
conductivity and thermal mass of
components. Components with a
preheat zones. The preheat zones
increase the temperature of the
board and components to prevent
thermal shock and begin evaporat-
ing solvents from the solder paste.
The reflow zone briefly elevates
the temperature sufficiently to
produce a reflow of the solder.
A recommended PCB pad layout
for the miniature SOT-323 (SC-70)
package is shown in Figure 12
(dimensions are in inches). This
layout provides ample allowance
for package placement by auto-
mated assembly equipment
without adding parasitics that
could impair the performance.
The rates of change of tempera-
ture for the ramp-up and cool-
down zones are chosen to be low
0.026
low mass, such as the SOT-323/-23 enough to not cause deformation
package, will reach solder reflow
temperatures faster than those
with a greater mass.
of the board or damage to compo-
nents due to thermal shock. The
maximum temperature in the
0.07
reflow zone (T ) should not
MAX
Agilent’s diodes have been
qualified to the time-temperature
profile shown in Figure 14. This
profile is representative of an IR
reflow type of surface mount
assembly process.
exceed 235°C.
0.035
These parameters are typical for a
surface mount assembly process
for Agilent diodes. As a general
guideline, the circuit board and
components should be exposed
only to the minimum tempera-
tures and times necessary to
achieve a uniform reflow of
solder.
0.016
Figure 12. PCB Pad Layout
( dimensions in inches) .
After ramping up from room
temperature, the circuit board
with components attached to it
(held in place with solder paste)
SOT-23 PCB Footprint
0.037
0.95
0.037
0.95
250
200
TMAX
0.079
2.0
0.035
0.9
150
Reflow
Zone
0.031
0.8
100
inches
DIMENSIONS IN
mm
Preheat
Zone
Cool Down
Zone
50
0
Figure 13. PCB Pad Layout.
0
60
120
180
240
300
TIME (seconds)
Figure 14. Surface Mount Assembly Profile.
7
Package Dimensions
Outline SOT-323 ( SC-70)
Outline 23 ( SOT-23)
PACKAGE
MARKING
CODE (XX)
1.02 (0.040)
0.89 (0.035)
1.30 (0.051)
REF.
DATE CODE (X)
0.54 (0.021)
0.37 (0.015)
DATE CODE (X)
PACKAGE
MARKING
CODE (XX)
3
2.20 (0.087)
2.00 (0.079)
1.35 (0.053)
1.15 (0.045)
X X X
1.40 (0.055)
1.20 (0.047)
2.65 (0.104)
2.10 (0.083)
X X X
2
1
0.650 BSC (0.025)
0.50 (0.024)
0.45 (0.018)
2.04 (0.080)
1.78 (0.070)
0.425 (0.017)
TYP.
2.20 (0.087)
1.80 (0.071)
TOP VIEW
0.10 (0.004)
0.00 (0.00)
0.30 REF.
0.152 (0.006)
0.066 (0.003)
3.06 (0.120)
2.80 (0.110)
1.02 (0.041)
0.85 (0.033)
0.20 (0.008)
0.10 (0.004)
1.00 (0.039)
0.80 (0.031)
0.25 (0.010)
0.15 (0.006)
10°
0.30 (0.012)
0.10 (0.004)
0.69 (0.027)
0.45 (0.018)
0.10 (0.004)
0.013 (0.0005)
DIMENSIONS ARE IN MILLIMETERS (INCHES)
SIDE VIEW
END VIEW
DIMENSIONS ARE IN MILLIMETERS (INCHES)
Package Characteristics
Lead Material ................................... Copper (SOT-323); Alloy 42 (SOT-23)
Lead Finish ............................................................................ Tin-Lead 85-15%
Maximum Soldering Temperature .............................. 260°C for 5 seconds
Minimum Lead Strength .......................................................... 2 pounds pull
Typical Package Inductance .................................................................. 2 nH
Typical Package Capacitance ..............................0.08 pF (opposite leads)
Ordering Information
Specify part number followed by option. For example:
HSMP
-
381x
- XXX
Bulk or Tape and Reel Option
Part Number; x = Lead Code
Surface Mount PIN
Option Descriptions
-BLK = Bulk, 100 pcs. per antistatic bag
-TR1 = Tape and Reel, 3000 devices per 7" reel
-TR2 = Tape and Reel, 10,000 devices per 13" reel
Tape and Reeling conforms to Electronic Industries RS-481, “Taping of
Surface Mounted Components for Automated Placement.”
Device Orientation
REEL
TOP VIEW
4 mm
END VIEW
8 mm
CARRIER
TAPE
###
###
###
###
USER
FEED
DIRECTION
Note: “###” represents Package Marking Code,
Date Code.
COVER TAPE
Tape Dimensions
For Outline SOT-323 ( SC-70 3 Lead)
P
P
D
2
P
0
E
F
W
C
D
1
t
(CARRIER TAPE THICKNESS)
T (COVER TAPE THICKNESS)
t
1
K
8° MAX.
5° MAX.
0
A
B
0
0
DESCRIPTION
SYMBOL
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
A
B
K
P
D
2.24 ± 0.10
2.34 ± 0.10
1.22 ± 0.10
4.00 ± 0.10
1.00 + 0.25
0.088 ± 0.004
0.092 ± 0.004
0.048 ± 0.004
0.157 ± 0.004
0.039 + 0.010
0
0
0
BOTTOM HOLE DIAMETER
1
0
PERFORATION
DIAMETER
PITCH
POSITION
D
P
E
1.55 ± 0.05
4.00 ± 0.10
1.75 ± 0.10
0.061 ± 0.002
0.157 ± 0.004
0.069 ± 0.004
CARRIER TAPE WIDTH
THICKNESS
W
8.00 ± 0.30
0.315 ± 0.012
t
0.255 ± 0.013 0.010 ± 0.0005
5.4 ± 0.10 0.205 ± 0.004
0.062 ± 0.001 0.0025 ± 0.00004
1
COVER TAPE
WIDTH
C
TAPE THICKNESS
T
t
DISTANCE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
F
3.50 ± 0.05
0.138 ± 0.002
CAVITY TO PERFORATION
(LENGTH DIRECTION)
P
2
2.00 ± 0.05
0.079 ± 0.002
www.semiconductor.agilent.com
Data subject to change.
Copyright © 1999 Agilent Technologies
5968-5427E (11/99)
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