CY29977 [ETC]
Clocks and Buffers ; 时钟和缓冲器\n
ETC 
77
CY29977
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Features
Table 1. Frequency Table[1]
• Output frequency up to 125 MHz
• Supports PowerPC® and Pentium® processors
• 12 clock outputs: frequency configurable
• Configurable Output Disable
• Two reference clock inputs for dynamic toggling
• Oscillator or crystal reference Input
• Spread spectrum compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Industrial temperature range: –40°C to +85°C
• 52-Pin TQFP package
VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0
FVCO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8x
12x
16x
20x
8x
12x
16x
20x
4x
6x
8x
10x
4x
6x
8x
10x
Note:
1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz.
.
Block Diagram
Pin Configuration
XIN
XOUT
VCO_SEL
PLL_EN
REF_SEL
Sync
Frz
D
D
QA0
Q
Q
0
1
Phase
Detector
VCO
TCLK0
TCLK1
0
1
QA1
QA2
52 51 50 49 48 47 46 45 44 43 42 41 40
LPF
VSS
QB0
VSS
MR#/OE
SCLK
1
39
38
37
36
35
34
33
32
31
30
29
28
27
TCLK_SEL
QA3
FB_IN
2
VDDC
QB1
3
Sync
Frz
QB0
QB1
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
4
VSS
5
QB2
QB3
QB2
6
VDDC
QB3
7
CY29977
8
FB_IN
VSS
9
MR#/OE
Sync
Frz
D Q
QC0
QC1
10
11
12
13
TCLK1
Power-On
Reset
/2, /6, /4, /12
/2, /6, /4, /10
/8, /2, /6, /4
FB_OUT
VDDC
FB_SEL0
XIN
XOUT
Sync
Frz
2
QC2
D
SELA(0,1)
Q
VDD
QC3
2
2
SELB(0,1)
SELC(0,1)
14 15 16 17 18 19 20 21 22 23 24 25 26
Sync
Frz
FB_OUT
D
D
Q
Q
/4, /6, /8, /10
Sync Pulse
Sync
Frz
3
SYNC
FB_SEL(0:2)
Data Generator
SCLK
Output Disable
Circuitry
12
SDATA
INV_CLK
Cypress Semiconductor Corporation
Document #: 38-07414 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised December 27, 2002
CY29977
Pin Description[2]
Pin No.
Pin Name
PWR
I/O
I
Type
PU
Description
11
XIN
Oscillator Input. Connect to a crystal
12
XOUT
I
PD
Oscillator Output. Connect to a crystal
9
TCLK0
TCLK1
QA(3:0)
QB(3:0)
QC(3:0)
FB_OUT
I
PU
External Reference/Test Clock Input.
10
I
PU
External Reference/Test Clock Input.
44, 46, 48, 50
32, 34, 36, 38
16, 18, 21, 23
29
VDDC
VDDC
VDDC
VDDC
O
O
O
O
Clock Outputs. See Table 2 for frequency selections.
Clock Outputs. See Table 2 for frequency selections.
Clock Outputs. See Table 2 for frequency selections.
Feedback Clock Output. Connect to FB_IN for normal operation.
The divider ratio for this output is set by FB_SEL(0:2). See Table 1.
A bypass delay capacitor at this output will control Input Refer-
ence/Output Banks phase relationships.
25
SYNC
VDDC
O
Synchronous Pulse Output. This output is used for system syn-
chronization. The rising edge of the output pulse is in sync with both
the rising edges of QA (0:3) and QC(0:3) output clocks regardless of
the divider ratios selected.
42, 43
40, 41
19, 20
5, 26, 27
52
SELA(1,0)
SELB(1,0)
SELC(1,0)
FB_SEL(2:0)
VCO_SEL
I
I
I
I
I
PU
PU
PU
PU
PU
Frequency Select Inputs. These inputs select the divider ratio at
QA(0:3) outputs. See Table 2.
Frequency Select Inputs. These inputs select the divider ratio at
QB(0:3) outputs. See Table 2.
Frequency Select Inputs. These inputs select the divider ratio at
QC(0:3) outputs. See Table 2.
Feedback Select Inputs. These inputs select the divide ratio at
FB_OUT output. See Table 1.
VCO Divider Select Input. When set LOW, the VCO output is divid-
ed by 2. When set HIGH, the divider is bypassed. See Table 1.
31
6
FB_IN
I
I
PU
PU
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
PLL_EN
PLL Enable Input. When asserted HIGH, PLL is enabled. When
LOW, PLL is bypassed.
7
8
2
REF_SEL
TCLK_SEL
MR#/OE
I
I
I
PU
PU
PU
Reference Select Input. When HIGH, the PECL clock is selected.
When LOW, TCLK (0,1) is the reference clock.
TCLK Select Input. When LOW, TCLK0 is selected and when HIGH
TCLK1 is selected.
Master Reset/Output Enable Input. When asserted LOW, resets all
of the internal flip-flops and also disables all of the outputs. When
pulled HIGH, releases the internal flip-flops from reset and enables
all of the outputs.
14
INV_CLK
I
PU
InvertedClockInput. WhensetHIGH,QC(2,3)outputsareinverted.
When set LOW, the inverter is bypassed.
3
4
SCLK
I
I
PU
PU
Serial Clock Input. Clocks data at SDATA into the internal register.
SDATA
Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
17, 22, 28,
VDDC
3.3V Power Supply for Output Clock Buffers.
33,37, 45, 49
13
VDD
VSS
3.3V Supply for PLL
Common Ground
1, 15, 24, 30,
35, 39, 47, 51
Note:
2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power (<0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Document #: 38-07414 Rev. *A
Page 2 of 9
CY29977
puts, refer to Table 1 for a Frequency table. The VCO frequen-
cy is then divided down to provide the required output frequen-
cies. These dividers are set by SELA(0,1), SELB(0,1),
SELC(0,1) select inputs, seeTable 2 below. For situations
were the VCO needs to run at relatively low frequencies and
hence might not be stable, assert VCO_SEL LOW to divide the
VCO frequency by 2. This will maintain the desired output re-
lationships, but will provide an enhanced PLL lock range.
Description
The CY29977 has an integrated PLL that provides low-skew
and low-jitter clock outputs for high-performance microproces-
sors. Three independent banks of four outputs as well as an
independent PLL feedback output, FB_OUT, provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the VCO is configured to
run between 200 MHz to 480 MHz. This allows a wide range
of output frequencies up to125 MHz.
The CY29977 is also capable of providing inverted output
clocks. When INV_CLK is asserted high, QC2 and QC3 output
clocks are inverted. These clocks could be used as feedback
outputs to the CY29977 or a second PLL device to generate
early or late clocks for a specific design. This inversion does
not affect the output to output skew.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select in-
Table 2.
VCO_SEL
SELA1
SELA0
QA
SELB1
SELB0
QB
SELC1
SELC0
QC
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/4
VCO/12
VCO/8
VCO/24
VCO/2
VCO/6
VCO/4
VCO/12
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/4
VCO/12
VCO/8
VCO/20
VCO/2
VCO/6
VCO/4
VCO/10
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/16
VCO/4
VCO/12
VCO/8
VCO/8
VCO/2
VCO/6
VCO/4
Document #: 38-07414 Rev. *A
Page 3 of 9
CY29977
Zero Delay Buffer
Glitch-Free Output Frequency Transitions
When used as a zero delay buffer the CY29977 will likely be
in a nested clock tree application. For these applications the
CY29977 offers a low-voltage PECL clock input as a PLL ref-
erence. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far superior
skew performance. The CY29977 then can lock onto the
LVPECL reference and translate with near zero delay to
low-skew outputs.
Customarily, when output buffers have their internal counters
changed “on the fly.’ their output clock periods will:
• Containshortor“runt”clockperiods. Theseareclock cycles
in which the cycle(s) are shorter in period than either the
old or new frequency that is being transitioned to.
• Contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old
or new frequency that is being transitioned to.
By using one of the outputs as a feedback to the PLL the prop-
agation delay through the device is eliminated. The PLL works
to align the output edge with the input reference edge, thus
producing a near zero delay. The reference frequency affects
the static phase offset of the PLL and thus the relative delay
between the inputs and outputs. Because the static phase off-
set is a function of the reference clock, the Tpd of the CY29977
is a function of the configuration used.
This device specifically includes logic to guarantee that runt
and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed “on the fly”
while it is operating: SELA, SELB, SELC, and VCO_SEL.
Document #: 38-07414 Rev. *A
Page 4 of 9
CY29977
SYNC Output
In situations were output frequency relationships are not inte-
ger multiples of each other the SYNC output provides a signal
for system synchronization. The CY29977 monitors the rela-
tionship between the QA and the QC output clocks. It provides
a low going pulse, one period in duration, one period prior to
the coincident rising edges of the QA and QC outputs. The
duration and the placement of the pulse depend on the higher
of the QA and QC output frequencies. The following timing
diagram (Figure 1) illustrates various waveforms for the SYNC
output. Note that the SYNC output is defined for all possible
combinations of the QA and QC outputs even though under
some relationships the lower frequency clock could be used
as a synchronizing signal.
VCO
1:1 Mode
2:1 Mode
QA
QC
SYNC
QA
QC
SYNC
3:1 Mode
QC
QA
SYNC
3:2 Mode
QA
QC
SYNC
4:1 Mode
QC
QA
SYNC
4:3 Mode
QA
QC
SYNC
6:1 Mode
QA
QC
SYNC
Figure 1.
Document #: 38-07414 Rev. *A
Page 5 of 9
CY29977
data. An output is frozen when a logic ‘0’ is programmed and
enabled when a logic ‘1’ is written. The enabling and freezing
of individual outputs is done in such a manner as to eliminate
the possibility of partial “runt” clocks.
Power Management
The individual output enable/freeze control of the CY29977
allows the user to implement unique power-management
schemes into the design. The outputs are stopped in the logic
‘0’ state when the freeze control bits are activated. The serial
input register contains one programmable freeze enable bit for
12 of the 14 output clocks. The QC0 and FB_OUT outputs can
not be frozen with the serial port, this avoids any potential lock
up situation should an error occur in the loading of the serial
The serial input register is programmed through the SDATA
input by writing a logic ‘0’ start bit followed by 12 NRZ freeze
enable bits. The period of each SDATA bit equals the period of
the free running SCLK signal. The SDATA is sampled on the
rising edge of SCLK.
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Figure 2.
Table 3. Suggested Oscillator Crystal Parameters
Parameter
TC
Description
Conditions
Min.
Typ.
Max.
±100
±100
5
Unit
PPM
PPM
PPM/Yr
pF
Frequency Tolerance
Note 3
TS
Frequency Temperature Stability (TA - 10 to +60C) Note 3
TA
Aging
(First 3 years @ 25C) Note 3
The crystal’s rated load. Note 3
Note 4
CL
Load Capacitance
20
40
RESR
Effective Series
80
Ohms
Resistance (ESR)
Notes:
3. For best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal meets or exceeds these
specifications.
4. Larger values may cause this device to exhibit oscillator start-up problem.
Document #: 38-07414 Rev. *A
Page 6 of 9
CY29977
Maximum Ratings[5]
Input Voltage Relative to VSS:............................. VSS – 0.3V
Input Voltage Relative to VDD: ............................. VDD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature:................................–40°C to +85°C
Maximum Power Supply: ................................................5.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, Vin and Vout should be constrained to the
range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic volt-
age level (either VSS or VDD).
DC Parameters: VDD = VDDC = 3.3V ±10%, TA = –40°C to +85°C
Parameter
VIL
Description
Input Low Voltage
Conditions
Min.
VSS
2.0
Typ.
Max.
0.8
Unit
V
VIH
Input High Voltage
VDD
–120
120
0.5
V
IIL
Input Low Current (@VIL = VSS
)
Note 6
µA
µA
V
IIH
Input High Current (@VIH = VDD
Output Low Voltage
)
VOL
VOH
IDDC
IDD
IOL = 20 mA, Note 7
IOH = –20 mA, Note 7
All VDDC and VDD
VDD only
Output High Voltage
2.4
V
Quiescent Supply Current
PLL Supply Current
10
15
15
4
mA
mA
pF
Cin
Input Pin Capacitance
AC Parameters:[8] VDD = VDDC = 3.3V ±10%, TA = –40°C to +85°C
Parameter Description Conditions
Tr/Tf TCLK Input Rise / Fall
Min.
Typ.
Max.
3.0
Note 9
25
Unit
ns
Fref
Reference Input Frequency
Crystal Oscillator Frequency
Reference Input Duty Cycle
PLL VCO Lock Range
Note 9
10
MHz
MHz
%
Fxtal
FrefDC
Fvco
Tlock
Tr/Tf
Fout
See Table 3
25
75
200
480
10
MHz
ms
Maximum PLL lock Time
Output Clocks Rise / Fall Time[10]
0.8V to 2.0V
Q (÷2)
0.15
1.2
125
120
80
ns
Maximum Output Frequency
MHz
Q (÷4)
Q (÷6)
Q (÷8)
60
FoutDC
Output Duty Cycle[10]
45
2
55
%
ns
ns
ps
ps
tpZL, tpZH
tpLZ, tpHZ
TCCJ
Output Enable Time[10](all outputs)
Output Disable Time[10](all outputs)
Cycle to Cycle Jitter[10](peak to peak)
Any Output to Any Output Skew[10,11]
10
2
8
±100
TSKEW
All outputs at same
frequency
350
550
270
Outputs at different
frequencies
ps
ps
Tpd
Propagation Delay[11,12] TCLK0/1
Q FB(÷8)
–270
Notes:
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply srquencing is NOT required.
6. Inputs have pull-up/pull-down resistors that effect input current.
7. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
8. Parameters are guaranteed by design and characterization. Not 100% tested in production.
9. Maximum and minimum input reference is limited by VC0 lock range.
10. Outputs loaded with 30 pF each.
11. 50Ω transmission line terminated into VDD/2.
Document #: 38-07414 Rev. *A
Page 7 of 9
CY29977
12. Tpd is specified for a 50-MHz input reference. Tpd is the static phase error of the device and does not include jitter.
Ordering Information
Part Number
Package Name
Package Type
Production Flow
Industrial, -40°C to +85°C
CY29977AI
A52
52-Pin TQFP
Package Drawing and Dimensions
52-Lead Thin Plastic Quad Flat Pack (10x10x1.4 mm) A52
51-85131-**
PowerPC is a registered trademark of International Business Machines.
Pentium is a registered trademark of Intel Corporation.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07414 Rev. *A
Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29977
Document Title: CY29977 3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Document Number: 38-07414
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
114664
Description of Change
05/17/02
12/27/02
HWT
RBI
New Data Sheet
Add power up requirements to maximum ratings information.
*A
122923
Document #: 38-07414 Rev. *A
Page 9 of 9
相关型号：
©2020 ICPDF网 联系我们和版权申明