CY29FCT520ATSOCTG4 [TI]
8-Bit Multi-Level Pipeline Register 24-SOIC -40 to 85;
| 型号： | CY29FCT520ATSOCTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Bit Multi-Level Pipeline Register 24-SOIC -40 to 85 时钟 光电二极管 外围集成电路 |
| 文件： | 总13页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C – MAY 1994 – REVISED NOVEMBER 2001
D, P, OR SO PACKAGE
(TOP VIEW)
Function, Pinout, and Drive Compatible
With FCT, F Logic, and AM29520
Reduced V
Equivalent FCT Functions
(Typically = 3.3 V) Version of
V
OH
1
24
23
22
21
20
19
18
17
16
15
14
I
I
CC
0
0
1
0
1
2
3
4
5
6
7
S
S
Y
Y
Y
Y
Y
Y
Y
Y
2
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
3
D
D
D
D
D
D
D
D
1
4
0
5
1
6
I
Supports Partial-Power-Down Mode
2
off
7
Operation
3
8
4
Matched Rise and Fall Times
9
5
Fully Compatible With TTL Input and
Output Logic Levels
10
11
12
6
CLK
GND
7
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
13 OE
– 1000-V Charged-Device Model (C101)
Single- and Dual-Pipeline Operation Modes
Multiplexed Data Inputs and Outputs
CY29FCT520T
– 64-mA Output Sink Current
32-mA Output Source Current
CY29FCT520ATDMB, CY29FCT520BTDMB
– 32-mA Output Sink Current
12-mA Output Source Current
3-State Outputs
description
The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1,
and B2, which are configured by the instruction inputs I , I as a single four-level pipeline or as two two-level
0
1
pipelines. The contents of any register can be read at the multiplexed output at any time by using the
multiplex-selection controls (S and S ).
0
1
The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input.
Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2
selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.
In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
unless otherwise noted. On all other products, production
testing of all parameters.
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C – MAY 1994 – REVISED NOVEMBER 2001
PIPELINE INSTRUCTION TABLE
I = 1 I = 2
= 0
I = 0
I = 3
I
1
= 0
I
0
= 0
I
1
I
0
= 1
I
1
= 1
I
0
= 0
I
1
= 1
I = 1
0
A1
A2
B1
A1
B1
B2
A1
A2
B1
A1
B1
B2
A2
B2
A2
B2
Single four-level
Dual two-level
Hold
ORDERING INFORMATION
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
6.0
6.0
CY29FCT520CTSOC
CY29FCT520CTSOCT
CY29FCT520BTSOC
CY29FCT520BTSOCT
CY29FCT520ATPC
SOIC – SO
29FCT520C
Tape and reel
Tube
7.5
SOIC – SO
DIP – P
29FCT520B
–40°C to 85°C
Tape and reel
Tube
7.5
14.0
14.0
14.0
CY29FCT520ATPC
29FCT520A
Tube
CY29FCT520ATSOC
CY29FCT520ATSOCT
SOIC – SO
Tape and reel
5962-9220504MLA
(CY29FCT520BTDMB)
Tube
Tube
8.0
–55°C to 125°C
CDIP – D
5962-9220502MLA
(CY29FCT520ATDMB)
16.0
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUT
S
S
0
1
1
1
A1
A2
B1
B2
1
0
0
0
1
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C – MAY 1994 – REVISED NOVEMBER 2001
logic diagram
D –D
0
7
8
Instruction
I
I
0
1
Register
Controls
MUX
CLK
Octal Register
A1
Octal Register
B1
Multiplex
Selection
S
0
S
1
Octal Register
A2
Octal Register
B2
MUX
OE
8
Y –Y
0
7
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θ (see Note 1): P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
JA
(see Note 2): SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C – MAY 1994 – REVISED NOVEMBER 2001
recommended operating conditions (see Note 3)
CY29FCT520ATDMB
CY29FCT520BTDMB
CY29FCT520T
MIN NOM MAX
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.8
–12
32
0.8
–32
64
V
IL
I
I
mA
mA
°C
OH
OL
T
A
–55
125
–40
85
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation.
CC
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CY29FCT520ATDMB
CY29FCT520T
CY29FCT520BTDMB
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
= 4.5 V,
= 4.75 V,
= 4.5 V,
I
I
I
I
I
I
I
= –18 mA
= –18 mA
–0.7
–1.2
CC
CC
CC
IN
V
V
IK
–0.7
–1.2
IN
= –12 mA
= –15 mA
= –32 mA
= 32 mA
= 64 mA
2.4
3.3
OH
OH
OH
OL
OL
V
OH
2.4
2
3.3
V
V
CC
= 4.75 V
V
V
= 4.5 V,
0.3
0.2
0.55
CC
V
V
V
V
OL
= 4.75 V,
0.3
0.2
0.55
CC
All inputs
hys
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 0 V,
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= V
= V
5
±1
±1
IN
IN
IN
IN
IN
IN
CC
CC
I
µA
I
5
= 2.7 V
= 2.7 V
= 0.5 V
= 0.5 V
I
IH
µA
±1
I
I
I
µA
µA
IL
±1
±1
= 4.5 V
= 0 V
±1
off
OS
OUT
OUT
OUT
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
–60
–120
–225
‡
mA
= 0 V
–60
–120
–225
10
= 2.7 V
10
–10
0.2
2
IN
IN
IN
IN
IN
IN
I
I
I
µA
µA
OZH
OZL
CC
= 2.7 V
= 0.5 V
= 0.5 V
≤ 0.2 V,
≤ 0.2 V,
–10
0.2
2
V
V
≥ V
≥ V
– 0.2 V
– 0.2 V
0.1
0.5
IN
CC
mA
mA
0.1
0.5
IN
CC
§
= 5.5 V, V = 3.4 V , f = 0, Outputs open
IN
1
∆I
CC
§
= 5.25 V, V = 3.4 V , f = 0, Outputs open
IN
1
†
‡
Typical values are at V
CC
= 5 V, T = 25°C.
A
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus
and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise,
prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In
any sequence of parameter tests, I
tests should be performed last.
OS
§
Per TTL-driven input (V = 3.4 V); all other inputs at V
or GND
IN CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C – MAY 1994 – REVISED NOVEMBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
CY29FCT520ATDMB
CY29FCT520T
CY29FCT520BTDMB
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
= 5.5 V, Outputs open,
CC
One bit switching at 50% duty cycle, OE = GND,
0.06
0.12
V
≤ 0.2 V or V ≥ V
– 0.2 V
IN
IN CC
mA/
MHz
¶
I
CCD
V
CC
= 5.25 V, Outputs open,
One bit switching at 50% duty cycle, OE = GND,
0.06
0.12
V
IN
≤ 0.2 V or V ≥ V
– 0.2 V
IN CC
V
V
≤ 0.2 V or
One bit switching
at f = 5 MHz at
1
50% duty cycle
IN
IN
0.7
1.2
1.4
3.4
≥ V
CC
– 0.2 V
V
= 5.5 V,
CC
V
IN
= 3.4 V or GND
Outputs open,
Eight bits
switching at
V
V
≤ 0.2 V or
f
= 10 MHz,
IN
IN
0
||
2.8
5.6
≥ V
CC
– 0.2 V
OE = GND
f
= 5 MHz at
1
||
V
IN
= 3.4 V or GND
5.1 14.3
50% duty cycle
#
I
C
mA
V
V
≤ 0.2 V or
One bit switching
at f = 5 MHz at
1
50% duty cycle
IN
IN
0.7
1.2
1.4
3.4
≥ V
CC
– 0.2 V
V
= 5.25 V,
CC
Outputs open,
= 10 MHz,
V
IN
= 3.4 V or GND
Eight bits
switching at
V
IN
V
IN
≤ 0.2 V or
f
0
||
5.6
2.8
≥ V
CC
– 0.2 V
OE = GND
f
= 5 MHz at
1
||
V
IN
= 3.4 V or GND
5.1 14.3
50% duty cycle
C
C
5
9
10
12
5
9
10
12
pF
pF
i
o
†
¶
#
Typical values are at V
CC
= 5 V, T = 25°C.
A
This parameter is derived for use in total power-supply calculations.
= I + ∆I × D × N + I (f /2 + f × N )
I
C
CC
CC
H
T
CCD
0
1
1
Where:
I
I
∆I
D
N
= Total supply current
= Power-supply current with CMOS input levels
C
CC
CC
H
T
= Power-supply current for a TTL high input (V = 3.4 V)
IN
= Duty cycle for TTL inputs high
= Number of TTL inputs at D
H
I
f
f
= Dynamic current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
CCD
0
1
N
= Number of inputs changing at f
1
1
All currents are in milliamperes and all frequencies are in megahertz.
||
Values for these conditions are examples of the I
CC
formula.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C – MAY 1994 – REVISED NOVEMBER 2001
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY29FCT520ATDMB CY29FCT520BTDMB
UNIT
MIN
MAX
MIN
MAX
t
t
Pulse duration, CLK high or low
8
6
ns
ns
w
Data
6
2.8
4.5
2
Setup time, before CLK↑
su
I
6
Data
I
2
t
h
ns
Hold time, after CLK↑
2
2
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY29FCT520AT CY29FCT520BT CY29FCT520CT
UNIT
MIN
MAX
MIN
5.5
2.5
4
MAX
MIN
5.5
2.5
4
MAX
t
t
Pulse duration, CLK high or low
7
ns
ns
w
Data
5
Setup time, before CLK↑
su
I
5
Data
I
2
2
2
t
h
ns
Hold time, after CLK↑
2
2
2
switching characteristics over operating free-air temperature range (see Figure 1)
CY29FCT520ATDMB
CY29FCT520BTDMB
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
2
MAX
16
MIN
2
MAX
8
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PHZ
PLZ
PZH
PZL
CLK
Y
Y
2
16
2
8
2
15
2
8
S
0
or S
ns
1
2
15
2
8
1.5
1.5
1.5
1.5
13
1.5
1.5
1.5
1.5
7.5
7.5
8
ns
OE
OE
Y
Y
13
16
ns
16
8
switching characteristics over operating free-air temperature range (see Figure 1)
CY29FCT520AT
CY29FCT520BT
CY29FCT520CT
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
2
MAX
14
MIN
2
MAX
7.5
7.5
7.5
7.5
7
MIN
2
MAX
t
t
t
t
t
t
t
t
6
6
6
6
6
6
6
6
PLH
PHL
PLH
PHL
PHZ
PLZ
PZH
PZL
CLK
Y
Y
2
14
2
2
2
13
2
2
S
0
or S
ns
1
2
13
2
2
1.5
1.5
1.5
1.5
12
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
OE
OE
Y
Y
12
7
15
7.5
7.5
ns
15
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY29FCT520T
MULTILEVEL PIPELINE REGISTER
WITH 3-STATE OUTPUTS
SCCS011C – MAY 1994 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
S1
500 Ω
From Output
Under Test
From Output
Under Test
Test
Point
TEST
S1
t
/t
Open
7 V
PLH PHL
t /t
C
= 50 pF
C
= 50 pF
L
L
500 Ω
500 Ω
PLZ PZL
/t
(see Note A)
(see Note A)
t
Open
PHZ PZH
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0 V
1.5 V
Timing Input
Data Input
t
w
t
h
t
3 V
su
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
t
t
t
PLH
PHL
PLH
PZL
PZH
PLZ
≈3.5 V
V
Output
Waveform 1
(see Note B)
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
V
OL
t
t
PHL
PHZ
V
V
V
OH
OH
Output
Waveform 2
(see Note B)
Out-of-Phase
Output
– 0.3 V
OH
1.5 V
1.5 V
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2013
PACKAGING INFORMATION
Orderable Device
5962-9220502MLA
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
CDIP
CDIP
PDIP
PDIP
SOIC
SOIC
SOIC
JT
24
24
24
24
24
24
24
1
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125 5962-9220502ML
A
5962-9220504MLA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
JT
NT
1
TBD
A42
-55 to 125 5962-9220504ML
A
CY29FCT520ATPC
CY29FCT520ATPCE4
CY29FCT520ATSOC
CY29FCT520ATSOCE4
CY29FCT520ATSOCG4
15
15
25
25
25
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
CY29FCT520ATPC
CY29FCT520ATPC
29FCT520A
NT
Pb-Free
(RoHS)
DW
DW
DW
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
29FCT520A
Green (RoHS
& no Sb/Br)
29FCT520A
CY29FCT520ATSOCT
CY29FCT520ATSOCTE4
CY29FCT520ATSOCTG4
CY29FCT520BTSOC
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
24
24
24
24
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
-40 to 85
29FCT520A
Call TI
Call TI
25
25
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
29FCT520B
29FCT520B
29FCT520B
CY29FCT520BTSOCE4
CY29FCT520BTSOCG4
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
24
24
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
CY29FCT520CTSOCE4
CY29FCT520CTSOCG4
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
24
24
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2013
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
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