CY26049-1 [ETC]
Clocks and Buffers ; 时钟和缓冲器\n
| 型号： | CY26049-1 |
| 厂家： | 
ETC |
| 描述： | Clocks and Buffers
|
| 文件： | 总6页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE
INFORMATION
CY26049-1
FailSafe™ PacketClock™
Global Communications Clock Generator
Features
Benefits
• Fully integrated phase-locked loop (PLL)
• FailSafe™ output
• PLL driven by a crystal oscillator that is phase-aligned
with external reference
• Two 6.312-MHz outputs from 8-kHz input
• Low-jitter, high-accuracy outputs
• 3.3V ± 5% operation
• Integrated high-performance PLL tailored for telecommuni-
cationsfrequencysynthesiseliminatestheneedforexternal
loop filter components
• When reference is off, DCXO maintains clock outputs and
SAFE pin indicates FailSafe conditions
• DCXO maintains continuous operation should the input
reference clock fail
• Glitch-free transition simplifies system design
• 16-lead TSSOP
• Works with commonly available, low-cost 18.432-MHz
crystal
• Zero-ppm error for all output frequencies
• Compatible across industry standard design platforms
• Industry standard package with 6.4 × 5.0 mm2 footprint and
a height profile of just 1.1 mm
Logic Block Diagram
external pullable crystal
(18.432MHz)
XOUT
XIN
input reference clock
(typical 8kHz)
PHASE
LOCKED
LOOP
FAILSAFETM
CONTROL
ICLK
CLKA
6.312MHz
DIGITAL
CONTROLED
CRYSTAL
OUTPUT
DIVIDERS
CLKB
6.312MHz
OSCILLATOR
SAFE
ICLK detected
Cypress Semiconductor Corporation
Document #: 38-07488 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised September 8, 2003
ADVANCE
INFORMATION
CY26049-1
Pin Configuration
CY26049-1
16-pin TSSOP
Top View
ICLK
1
2
3
4
5
6
7
8
16 NC
CLKB
15
NC
NC
14 NC
NC
13 NC
VDD
VSS
CLKA
XIN
12 VDD
11 VSS
10 SAFE
9
XOUT
Pin Description
Pin Number Pin Name
Pin Description
1
2
ICLK
NC
Reference Input Clock: 8kHz.
No Connect.
3
NC
No Connect.
4
NC
No Connect.
5
VDD
VSS
CLKA
XIN
Voltage Supply: 3.3V.
Ground.
6
7
Clock Output: 6.312 MHz.
Pullable Crystal Input: 18.432 MHz.
8
9
XOUT Pullable Crystal Output: 18.432 MHz.
10
11
12
13
14
15
16
SAFE
VSS
VDD
NC
High = reference ICLK within range, Low = reference ICLK out of range.
Ground.
Voltage Supply: 3.3V.
No Connect.
NC
No Connect.
CLKB
NC
Clock Output: 6.312 MHz.
No Connect.
Selector Guide
Part Number
Input Frequency Range
Outputs
Output Frequencies
CY26049ZC-1 Reference Input Clock: 8 kHz
2
6.312 MHz
Crystal: 18.432-MHz pullable Crystal per Cypress Specification
In the event of a reference clock failure the DCXO maintains
the last frequency of the reference clock. The unique feature
of the CY26049-1 is that the DCXO is in fact the primary
clocking source. When the reference clock is restored, the
DCXO automatically resynchronizes to the reference. The
status of the reference clock input, as detected by the
CY26049-1, is reported by the SAFE pin.
Description
CY26049-1 is a FailSafe frequency synthesizer with a
reference clock input and two 6.312-MHz outputs. The device
provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure. The continuous, glitch-free operation is achieved by
using a DCXO, which serves as a primary clock source. The
FailSafe control circuit synchronizes the DCXO oscillator with
the reference as long as the reference is within the pull range
of the crystal.
Document #: 38-07488 Rev. *A
Page 2 of 6
ADVANCE
INFORMATION
CY26049-1
Data Retention @ Tj=125°C..................................> 10 years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) MIL-STD-883.................... 2000V
Absolute Maximum Conditions
Supply Voltage (VDD) ........................................–0.5 to +7.0V
DC Input Voltage........................................–0.5V to VDD+0.5
Storage Temperature (Non-condensing).....–55°C to +125°C
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Junction Temperature ................................ –40°C to +125°C
Recommended Pullable Crystal Specifications[1]
Parameter
Description
Comments
Min.
Typ.
Max. Unit
FNOM
Nominal crystal frequency
Parallel resonance, fundamental
mode, AT cut
–
18.432
–
MHz
CLNOM
R1
Nominal load capacitance
–
–
3
14
–
–
25
–
pF
Equivalent series resistance (ESR)
Fundamental mode
Ω
R3/R1
Ratio of third overtone mode ESR to
fundamental mode ESR
Ratio used because typical R1 values
are much less than the maximum spec
–
DL
Crystal drive level
No external series resistor assumed
–
400
–
0.5
–
2
–
mW
ppm
F3SEPHI
F3SEPLO
C0
Third overtone separation from 3*FNOM High side
Third overtone separation from 3*FNOM Low side
Crystal shunt capacitance
–
–200 ppm
–
–
7
pF
fF
C0/C1
C1
Ratio of shunt to motional capacitance
Crystal motional capacitance
180
14.4
–
250
21.6
18
Recommended Operating Conditions
Parameter
Description
Min.
3.15
0
Typ.
Max.
Unit
V
VDD
TAC
Operating Voltage
3.3
–
3.45
70
Ambient Temperature (Commercial Temperature)
Max Output Load Capacitance
° C
pF
CLOAD
tpu
–
–
15
Power-up time for all VDDs to reach minimum specified
voltage (power ramps must be monotonic)
0.05
–
500
ms
DC Electrical Specifications (Commercial Temp: 0° to 70°C)
Parameter
IOH
Description
Output High Current
Output Low Current
Input High Voltage
Input High Voltage
Input High Current
Input Low Current
Input Capacitance
Supply Current
Test Conditions
VOH = VDD – 0.5, VDD = 3.3V (source)
VOL = 0.5, VDD = 3.3V (sink)
CMOS Levels
Min.
Typ.
24
24
–
Max.
–
Unit
mA
mA
VDD
VDD
µA
12
12
0.7
–
IOL
VIH
VIL
IIH
–
–
CMOS Levels
–
0.3
10
10
7
VIH = VDD
–
5
IIL
VIL = 0V
–
5
µA
CIN
IDD
–
–
pF
CLOAD = 15 pF, VDD = 3.45V
–
–
30
mA
AC Electrical Specifications (Commercial Temp: 0° to 70° C)
Parameter
fICLK-E
LR
Description
Frequency, Input Clock
FailSafe Lock Range[2]
Test Conditions
Input Clock Frequency, External Mode
Range of reference ICLK for Safe = High
Min. Typ. Max. Unit
–
8.00
–
–
kHz
–250
+250 ppm
DC = t2/t1 Output Duty Cycle
Duty Cycle defined in Figure 1, measured at 50% of VDD 45
50
–
55
250
50
3
%
ps
ps
ms
TPJIT1
Clock Jitter; output > 5 MHz Period Jitter, Peak to Peak, 10,000 periods
–
RMS Period Jitter, RMS
–
–
–
t6
PLL Lock Time
Time for PLL to lock within ± 150 ppm of target frequency
–
Notes:
1. Ecliptek ECX-5761-18.432M meets these specifications.
2. Dependent on crystals chosen and crystal specs.
Document #: 38-07488 Rev. *A
Page 3 of 6
ADVANCE
INFORMATION
CY26049-1
AC Electrical Specifications (Commercial Temp: 0° to 70° C) (continued)
Parameter
Description
Test Conditions
Min. Typ. Max. Unit
tfs_lock
Failsafe Lock Time
Time for PLL to lock to ICLK (outputs phase aligned with
ICLK and Safe = High)
–
–
7
s
ferror
ER
Frequency Synthesis Error Actual mean frequency error vs. target
–
0
–
2
ppm
V/ns
Rising Edge Rate
Output Clock Edge Rate, Measured from 20% to 80% of 0.8
VDD, CLOAD = 15pF. See Figure 2.
1.4
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 20% to 80% of 0.8
1.4
2
V/ns
V
DD, CLOAD = 15pF. See Figure 2.
Voltage and Timing Definitions
t1
t2
CLK
50%
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t4
t3
80%
20%
CLK
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
Test Circuit
ICLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
CLKB
CLOAD
VDD
VDD
0.1uF
0.1uF
CLKA
10
9
CLOAD
18.432 MHz
Ordering Information
Ordering Code
CY26049ZC-1
Package Type
Operating Temperature Range
16-lead TSSOP
16-lead TSSOP—Tape and Reel
Commercial 0 to 70°C
Commercial 0 to 70°C
CY26049ZC-1T
Document #: 38-07488 Rev. *A
Page 4 of 6
ADVANCE
INFORMATION
CY26049-1
Package Drawing and Dimensions
16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
51-85091-**
FailSafeandPacketClock are trademarks of Cypress Semiconductor. Allproduct andcompany names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-07488 Rev. *A
Page 5 of 6
ADVANCE
INFORMATION
CY26049-1
Document History Page
Document Title: CY26049-1 FailSafe PacketClock Global Communications Clock Generator
Document Number: 38-07488
Issue
Date
Orig. of
Change
REV.
**
ECN No.
120007
128089
Description of Change
11/01/02
09/11/03
CKN
IJA
New Data Sheet
*A
Changed title to FailSafe PacketClock Global Communications Clock
Generator from FailSafe Communications Clock Generator
Changed some wording of Features in Features and Benefits column
Changed a few definitions in Pin Description table
Replaced Recommended Pullable Crystal Specifications table
Document #: 38-07488 Rev. *A
Page 6 of 6
相关型号：
CY26049ZXC-36
Clock Generator, 155.52MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16
CYPRESS
CY26049ZXI-36
Clock Generator, 155.52MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16
CYPRESS
©2020 ICPDF网 联系我们和版权申明