CS8412-IP [ETC]
Digital Audio Interface Receiver(555.21 k) ; 数字音频接口接收机（ 555.21 K）\n
| 型号： | CS8412-IP |
| 厂家： | 
ETC |
| 描述： | Digital Audio Interface Receiver(555.21 k)
|
| 文件： | 总36页 (文件大小：554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8411 CS8412
Semiconductor Corporation
Digital Audio Interface Receiver
Features
General Description:
The CS8411/12 are monolithic CMOS devices which re-
ceive and decode audio data according to the
AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340 interface
standards. The CS8411/12 receive data from a trans-
mission line, recover the clock and synchronization
signals, and de-multiplex the audio and digital data. Dif-
ferential or single ended inputs can be decoded.
Monolithic CMOS Receiver
•
•
Low-Jitter, On-Chip Clock Recovery
256×Fs Output Clock Provided
Supports: AES/EBU, IEC 958,
•
The CS8411 has a configurable internal buffer memory,
read via a parallel port, which may be used to buffer
channel status, auxiliary data, and/or user data.
S/PDIF, & EIAJ CP-340
Professional and Consumer Formats
The CS8412 de-multiplexes the channel, user, and va-
lidity data directly to serial output pins with dedicated
output pins for the most important channel status bits.
Extensive Error Reporting
•
Repeat Last Sample on Error Option
On-Chip RS422 Line Receiver
•
•
ORDERING INFORMATION:
TABLE OF CONTENTS:
page 33
page 34
Configurable Buffer Memory (CS8411)
VA+
22
FILT AGND
20 21
MCK
VD+ DGND
19
7
8
26
CS8411
SDATA
SCK
Audio
Serial Port
12
11
FSYNC
13
9
A4/FCK
A3 - A0
D7- D0
RXP
RXN
RS422
Receiver
4
8
Clock & Data
Recovery
De-Mux
10
Configurable
Buffer
24
23
Memory
CS
IEnable & Status
RD/WR
25
14
INT
ERF
MCK
VA+
22
FILT AGND
20 21
VD+ DGND
M3 M2 M1 M0
17 18 24 23
19
7
8
CS8412
26
12
11
SDATA
SCK
Audio
Serial Port
9
FSYNC
RXP
RXN
RS422
Receiver
Clock & Data
Recovery
De-Mux
10
1
C
14
28
Registers
U
Mux
13
Mux
VERF
16
6
5
4
3
2
27
25
ERF
15
CBL
CS12/
FCK
SEL
C0/ Ca/ Cb/ Cc/ Cd/ Ce/
E0 E1 E2 F0 F1 F2
This document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Preliminary Product Information
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
NOV ’93
DS61PP4
1
CS8411 CS8412
ABSOLUTE MAXIMUM RATINGS (GND = 0V, all voltages with respect to ground)
Parameter
Symbol
Min
Max
Units
Power Supply Voltage
VD+, VA+
6.0
V
Input Current, Any Pin Except Supply
Input Voltage, Any Pin except RXP, RXN
Input Voltage, RXP and RXN
Note 1
I
±10
VD+ + 0.3
12
mA
V
in
V
-0.3
-12
-55
-65
IN
V
V
IN
Ambient Operating Temperature (power applied)
Storage Temperature
T
A
125
°C
°C
T
150
stg
Notes:
1. Transient currents of up to 100 mA will not cause SCR latch-up.
WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(GND = 0V; all voltages with respect to ground)
Parameter
Symbol
Min
Typ
Max
Units
Power Supply Voltage
Supply Current
VD+, VA+
4.5
5.0
5.5
V
VA+
VD+
I
A
20
7
35
10
mA
mA
I
D
Ambient Operating Temperature: CS8411/12-CP or -CS Note 2
CS8411/12-IP or -IS
T
0
25
70
85
°C
°C
A
D
-40
Power Consumption
P
135
248
mW
Notes:
2. The ’-CP’ and ’-CS’ parts are specified to operate over 0 to 70 °C but are tested at 25 °C only.
The ’-IP’ and ’-IS’ parts are tested over the full -40 to 85 °C temperature range.
DIGITAL CHARACTERISTICS
(T = 25 °C for suffixes ’-CP’ & ’-CS’, T = -40 to 85 °C for ’-IP’ & ’-IS’; VD+, VA+ = 5V ± 10%)
A
A
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
except RXP, RXN
except RXP, RXN
V
2.0
V
IH
V
+0.8
V
V
IL
(I = 200µA)
V
VD+ - 1.0
O
OH
(I = -3.2mA)
O
V
0.4
10
V
OL
I
1.0
µA
in
Input Sample Frequency (Note 3)
CS8411/12-CP or -CS
F
S
25
30
55
50
kHz
kHz
CS8411/12-IP or -IS
F
S
Master Clock Frequency
MCK Clock Jitter
Note 3
MCK
6.4
256×F
200
14.08
MHz
ps RMS
%
S
t
j
MCK Duty Cycle (high time/cycle time)
50
Notes:
3. FS is defined as the incoming audio sample frequency per channel.
Specifications are subject to change without notice.
2
DS61PP4
CS8411 CS8412
DIGITAL CHARACTERISTICS - RS422 RECEIVERS
(RXP, RXN pins only; VD+, VA+ = 5V ± 10%)
Parameter
(-7V < V
Symbol
Min
Typ
Max
Units
kΩ
Input Resistance
< 7V)
Note 4
Z
10
CM
IN
Differential Input Voltage, RXP to RXN (-7V < V
< 7V) Note 4,5
V
200
mV
CM
TH
Input Hysteresis
V
50
mV
HYST
Notes:
4. V
- Input Common Mode Range
CM
5. When the receiver inputs are configured for single ended operation (e.g. consumer configuration) the signal
amplitude must exceed 400mVp-p for the differential voltage on RXP to RXN to exceed 200mV. This represents
SWITCHING CHARACTERISTICS - CS8411 PARALLEL PORT
(T = 25 °C for suffixes ’-CP’ and ’-CS’; T = -40 to 85 °C for suffixes ’-IP’ and ’-IS’;
A
A
VD+, VA+ = 5V ± 10%; Inputs: Logic 0 = DGND, logic 1 = VD+; C = 20 pF)
L
Parameter
ADDRESS valid to CS low
Symbol
Min
Typ
Max
Units
t
13.5
ns
adcss
CS high to ADDRESS invalid
RD/WR valid to CS low
CS low to RD/WR invalid
CS low
t
0
ns
ns
ns
ns
ns
ns
ns
ns
csadh
t
10
35
35
32
0
rwcss
t
csrwi
t
csl
DATA valid to CS rising
CS high to DATA invalid
CS falling to DATA valid
CS rising to DATA Hi-Z
RD/WR low (writing)
RD/WR low (writing)
RD/WR high (reading)
RD/WR high (reading)
t
dcssw
t
csdhw
t
35
csddr
t
5
csdhr
A4 - A0
adcss
t
t
csadh
CS
t
csl
t
t
rwcss
csrwi
RD/WR
Writing
t
t
dcssw
csdhw
D7 - D0
RD/WR
Reading
t
t
csddr
csdhr
D7 - D0
CS8411 Parallel Port Timing
DS61PP4
3
CS8411 CS8412
SWITCHING CHARACTERISTICS - SERIAL PORTS
(T = 25 °C for suffixes ’-CP’ and ’-CS’; T = -40 to 85 °C for suffixes ’-IP’ and ’-IS’;
A
A
VD+, VA+ = 5V ± 10%; Inputs: Logic 0 = DGND, logic 1 = VD+; C = 20 pF)
L
Parameter
Master Mode
Symbol
Min
Typ
Max
Units
SCK Frequency
Notes 5,6
Note 6
f
OWR×32
OWR×32
Hz
Hz
sck
Slave Mode
Master Mode
Slave Mode
Slave Mode
TBD
20
SCK falling to FSYNC delay
SCK Pulse Width Low
SCK Pulse Width High
Notes 6,7
Note 6
t
-20
40
40
20
20
ns
sfdm
t
ns
sckl
Note 6
t
ns
sckh
SCK rising to FSYNC edge delay Slave Mode
FSYNC edge to SCK rising setup Slave Mode
SCK falling (rising) to SDATA valid
Notes 6,7
Notes 6,7
t
ns
sfds
t
ns
fss
Note 7
t
20ns
ssv
C, U, CBL valid to FSYNC edge CS8412
Note 7
t
1/f
cuvf
sck
s
MCK to FSYNC edge delay
FSYNC from RXN/RXP
t
15
ns
mfd
Notes:
5. The output word rate, OWR, refers to the frequency at which an audio sample is output from the part.
(A stereo pair is two audio samples.) Therefore, in Master mode, there are always 32 SCK periods
in one audio sample. In Slave mode 32 SCK periods must be provided in most serial port formats.
6. In master mode SCK and FSYNC are outputs. In Slave mode they are inputs. In the CS8411, control
reg. 2 bit 1, MSTR, selects master. In the CS8412, formats 1 & 3 are slaves.
7. The table above assumes data is output on the falling edge and latched on the rising edge. With both
parts the edge is selectable. The table is defined for the CS8411 with control reg. 2 bit 0, SCED, set
to one, and for the CS8412 in formats 2, 3, 5 - 7. For the other formats, the table and figure edges
must be reversed (i.e.. "rising" to "falling" and vice versa).
FSYNC
t
t
fss
sfds
t
t
sckl sckh
MCK
t
mfd
SCK
FSYNC
t
ssv
FSYNC Generated From Received Data
SDATA
MSB
C, U
Mode 1
t
cuvf
FSYNC
FSYNC
t
t
t
t
fss
sfds
sckl sckh
t
sfdm
t
sckf
SCK
SCK
t
ssv
t
ssv
SDATA
SDATA
MSB
Mode 3
Serial Output Timing - Slave Mode
Serial Output Timing - Master Mode & C, U Port
4
DS61PP4
CS8411 CS8412
+5V digital
+5V analog
0.1 uF
5 k
22
7
0.1 uF
19
VA+
VD+
MCK
21
9
Audio
AGND
11
12
26
FSYNC
SCK
Data
Processor
SDATA
RXP
Receiver
Circuit
25
14
24
23
ERF
CS8411
10
(See Appendix A)
INT
CS
Audio
RXN
FILT
Data
Processor
20
RD/WR
A0 - A4
or
Micro-
controller
1 k
DGND
8
D0 - D7
0.047 uF
Figure 1. CS8411 Typical Connection Diagram
+5V digital
+5V analog
0.1 uF
22
7
0.1 uF
19
VA+
VD+
MCK
21
9
Audio
AGND
28
12
26
VERF
SCK
Data
Processor
Receiver
Circuit
RXP
RXN
SDATA
11
10
FSYNC
(See Appendix A)
CS8412
13
16
25
Micro-
controller
or
CS12/FCK
Channel Status
and/or
1
C
U
SEL
14
15
Logic
Error/Frequency
Reporting
ERF
CBL
6 C / E-F bits
20
FILT
DGND
1 k
8
0.047 uF
Figure 2. CS8412 Typical Connection Diagram
DS61PP4
5
CS8411
GENERAL DESCRIPTION
Clocks and Jitter Attenuation
The primary function of these chips is to recover
audio data and low jitter clocks from a digital
audio transmission line. The clocks that can be
The CS8411/12 are monolithic CMOS circuits
that receive and decode audio and digital data ac-
cording to the AES/EBU, IEC 958, S/PDIF, and
EIAJ CP-340 interface standards. Both chips con-
tain RS422 line receivers and Phase-Locked
Loops (PLL) that recover the clock and synchro-
nization signals, and de-multiplex the audio and
digital data. The CS8411 contains a configurable
internal buffer memory, read via a parallel port,
which can buffer channel status, user, and option-
ally auxiliary data. The CS8412 de-multiplexes
the channel status, user, and validity information
directly to serial output pins with dedicated pins
for the most important channel status bits. Both
chips also contain extensive error reporting as
well as incoming sample frequency indication for
auto-set applications.
generated are MCK (256×F ), SCK (64×F ), and
S
S
FSYNC (F or 2×F ). MCK is the output of the
S
S
voltage controlled oscillator which is a compo-
nent of the PLL. The PLL consists of phase and
frequency detectors, a second-order loop filter,
and a voltage controlled oscillator. All compo-
nents of the PLL are on chip with the exception
of a resistor and capacitor used in the loop filter.
This filter is connected between the FILT pin and
AGND. The closed-loop transfer function, which
specifies the PLL’s jitter attenuation charac-
teristics, is shown in Figure 3. The loop will
begin to attenuate jitter at approximately 25 kHz
with another pole at 80 kHz, and will have 50 dB
of attenuation by 1MHz. Since most data jitter in-
troduced by the transmission line is high in
frequency, it will be strongly attenuated.
Familiarity with the AES/EBU and IEC 958
specifications are assumed throughout this docu-
ment. The App Note, Overview of Digital Audio
Interface Data Structures, contains information on
digital audio specifications; however, it is not
meant to be a complete reference. To guarantee
compliance, the proper standards documents
should be obtained. The AES/EBU standard,
AES3-1985, should be obtained from the Audio
Engineering Society or ANSI (ANSI document #
ANSI S4.40-1985); the IEC 958 standard from
the International Electrotechnical Commission;
and the EIAJ CP-340 standard from the Japanese
Electronics Bureau.
Multiple frequency detectors are used to mini-
mize the time it takes the PLL to lock to the
incoming data stream and to prevent false lock
conditions. When the PLL is not locked to the in-
coming data stream, the frequency detectors pull
the VCO frequency within the lock range of the
PLL. When no digital audio data is present, the
VCO frequency is pulled to its minimum value.
As a master, SCK is always MCK divided by
four, producing a frequency of 64×F . In the
S
CS8411, FSYNC can be programmed to be a di-
vided version of MCK or it can be generated
directly from the incoming data stream. In the
CS8412, FSYNC is always generated from the in-
coming data stream. When FSYNC is generated
from the data, its edges are extracted at times
when intersymbol interference is at a minimum.
This provides a sample frequency clock that is as
spectrally pure as the digital audio source clock
for moderate length transmission lines. For long
transmission lines, the CS8411 can be pro-
Line Receiver
The RS422 line receiver can decode differential
as well as single ended inputs. The receiver con-
sists of a differential input Schmitt trigger with
50mV of hysteresis. The hysteresis prevents noisy
signals from corrupting the phase detector. Ap-
pendix A contains more information on how to
configure the line receivers for differential and
single ended signals.
6
DS61PP4
CS8411
0 dB
25dB
50dB
75dB
100dB
1kHz
10kHz
100kHz
1MHz
10MHz
Jitter Frequency
Figure 3. Jitter Attenuator Characteristics
grammed to generate FSYNC from MCK instead
of from the incoming data.
occupy the same address space. A bit in control
register 1 selects the two registers, either status or
interrupt enable, that occupy addresses 0 and 1 in
the memory map. The address bus and the
RD/WR line should be valid when CS goes low.
If RD/WR is low, the value on the data bus will
be written into the buffer memory at the specified
address. If RD/WR is high, the value in the buffer
memory, at the specified address, is placed on the
data bus. Detailed timing for the parallel port can
be found in the Switching Characteristics - Paral-
lel Port table.
CS8411 DESCRIPTION
The CS8411 is more flexible than the CS8412 but
requires a microcontroller or DSP to load internal
registers. The CS8412 does not have internal reg-
isters so it may be used in a stand-alone mode
where no microprocessor or DSP is available.
The CS8411 accepts data from a transmission
line coded according to the digital audio interface
standards. The I.C. recovers clock and data, and
separates the audio data from control information.
The audio data is output through a configurable
serial port and the control information is stored in
internal dual-port RAM. Extensive error reporting
is available via internal registers with the option
of repeating the last sample when an error occurs.
A block diagram of the CS8411 is shown in Fig-
ure 4
The memory space on the CS8411 is allocated as
shown in Figure 5. There are three defined buffer
modes selectable by two bits in control register 1.
Further information on the buffer modes can be
found in the Control Registers section.
Status and IEnable Registers
The status and interrupt enable registers occupy
the same address space. The IER/SR bit in control
register 1 selects whether the status registers
(IER/SR = 0) or the IEnable registers (IER/SR =
1) occupy addresses 0 and 1. Upon power-up, the
control and IEnable registers contain all zeros;
therefore, the status registers are visible and all
interrupts are disabled. The IER/SR bit must be
set to make the IEnable registers visible.
Parallel Port
The parallel port accesses two status registers,
two interrupt enable registers, two control regis-
ters, and 28 bytes of dual-port buffer memory.
The status registers and interrupt enable registers
DS61PP4
7
CS8411
VA+
22
FILT AGND MCK
20 21 19
11
Bi-phase
Decoder
FSYNC
Audio
Serial
Port
12
26
SCK
9
RXP
RXN
Clock & Data
Recovery
De-Multiplexor
SDATA
10
Control
Registers
Confidence
Flag
2 X 8
crc
check
aux
Buffer
Memory
7
8
user
C.S.
VD+
28 X 8
DGND
slipped
14
25
parity
validity
crc
INT
IEnable
&
Status
ERF
coding
24
23
no lock
confidence
CS
4 X 8
RD/WR
Frequency
Comparator
4
8
13
A4/ A0- D0-
FCK A3 D7
Figure 4. CS8411 Block Diagram
Status register 1 (SR1), shown in Figure 6, re-
ports all the conditions that can generate a pulse
of four SCLK cycles on the interrupt pin (INT).
The three least significant bits, FLAG2-FLAG0,
are used to monitor the ram buffer. These bits
continually change and indicate the position of
the buffer pointer which points to the buffer
memory location currently being written. Each
flag has a corresponding interrupt enable bit in
IEnable register 1 which, when set, allows a tran-
sition on the flag to generate a pulse on the
interrupt pin. FLAG0 and FLAG1 cause inter-
rupts on both edges whereas FLAG2 causes an
interrupt on the rising edge only. Further informa-
tion, including timing, on the flags can be found
in the Buffer Memory section.
The next five bits; ERF, SLIP, CCHG,
CRCE/CRC1, and CSDIF/CRC2, are latches
which are set when their corresponding condi-
tions occur, and are reset when SR1 is read.
Interrupt pulses are generated the first time that
condition occurs. If the status register is not read,
further instances of that same condition will not
generate another interrupt. ERF is the error flag
bit and is set when the ERF pin goes high. It is an
OR’ing of the errors listed in status register 2,
bits 0 through 4, AND’ed with their associated in-
terrupt enable bits in IEnable register 2.
SLIP is only valid when the audio port is in slave
mode (FSYNC and SCK are inputs to the
CS8411). This flag is set when an audio sample is
dropped or reread because the audio data output
from the part is at a different frequency than the
8
DS61PP4
CS8411
data received from the transmission line. CCHG
is set when any bit in channel status bytes 0
through 3, stored in the buffer, changes from one
block to the next. In buffer modes 0 and 1, only
one channel of channel status data is buffered, so
CCHG is only affected by that channel.
(CS2/CS1 in CR1 selects which channel is buff-
ered.) In buffer mode 2 both channels are
buffered, so both channels affect CCHG. This bit
is updated after each byte (0 to 3) is written to the
buffer. The two most significant bits in SR1,
CRCE/CRC1 and CSDIF/CRC2, are dual func-
tion flags. In buffer modes 0 and 1, they are
CRCE and CSDIF, and in buffer mode 2, they are
CRC1 and CRC2. In buffer modes 0 and 1, the
channel selected by the CS2/CS1 bit is stored in
RAM and CRCE indicates that a CRC error oc-
curred in that channel. CSDIF is set if there is any
difference between the channel status bits of each
channel. In buffer mode 2 channel status from
both channels is buffered, with CRC1 indicating a
CRC error in channel 1 and CRC2 indicating a
CRC error in channel 2. CRCE, CRC1, and
CRC2 are updated at the block boundary. Block
boundary violations also cause CRC1,2 or CRCE
to be set.
IEnable register 1, which occupies the same ad-
dress space as status register 1, contains interrupt
enable bits for all conditions in status register 1.
A "1" in a bit location enables the same bit loca-
tion in status register 1 to generate an interrupt
pulse. A "0" masks that particular status bit from
causing an interrupt.
Status 1 / IEnable 1
Status 2 / IEnable 2
Control Register 1
Control Register 2
0
1
2
3
4
5
User Data
6
Status register 2 (SR2) reports all the conditions
that can affect the error flag bit in SR1 and the
error pin (ERF), and can specify the received
clock frequency. As previously mentioned, the
first five bits of SR2 are AND’ed with their inter-
rupt enable bits (in IER2) and then OR’ed to
create ERF. The V, PARITY, CODE, LOCK, and
7
U
N
D
E
F
I
N
E
D
8
1st Four
Bytes of
Left C. S.
Data
1st Four
Bytes of
C. S. Data
1st Four
Bytes of
C. S. Data
9
A
B
C
Left
C. S.
Data
A
D
D
R
E
S
S
D
C. S.
Data
E
Last
20 Bytes
Channel
Status
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
1st Four
Bytes of
Right
7
6
5
4
3
2
1
0
X:00
SR1
Data
CSDIF/ CRCE/
CRC2 CRC1
CCHG
SLIP
ERF FLAG2 FLAG1 FLAG0
C. S. Data
IER1
SR1:
INTERRUPT ENABLE BITS FOR ABOVE
Right
C. S.
Data
Auxiliary
Data
CSDIF: CS different between sub-frames. Buf. modes 0 & 1.
CRC2: CRC Error - sub-frame 2. Buffer mode 2 only.
CRCE: CRC Error - selected sub-frame. Buffer modes 0 & 1.
CRC1: CRC Error - sub-frame 1. Buffer mode 2 only.
CCNG: Channel Status changed
SLIP: Slipped an audio sample
ERF: Error Flag. ORing of all errors in SR2.
FLAG2: High for first four bytes of channel status
FLAG1: Memory mode dependent - See Figure 11
FLAG0: High for last two bytes of user data.
IER1:
Enables the corresponding bit in SR1.
A "1" enables the interrupt. A "0" masks the interrupt.
0
1
2
3
Memory Mode
Figure 5. CS8411 Buffer Memory Map
Figure 6. Status/IEnable Register 1
DS61PP4
9
CS8411
CONF bits are latches which are set when their
corresponding conditions occur, and are reset
when SR2 is read. The ERF pin is asserted each
time the error occurs assuming the interrupt en-
able bit in IER2 is set for that particular error.
When the ERF pin is asserted, the ERF bit in SR1
is set. If the ERF bit was not set prior to the ERF
pin assertion, an interrupt will be generated (as-
suming bit 3 in IER1 is set). Although the ERF
pin is asserted for each occurrence of an enabled
error condition, the ERF bit will only cause an
interrupt once if SR1 is not read.
The upper three bits in SR2, FREQ2-FREQ0, can
report the receiver frequency when the receiver is
locked. These bits are only valid when FCEN in
control register 1 is set, and a 6.144 MHz clock is
applied to the FCK pin. When FCEN is set, the
A4/FCK pin is used as FCK and A4 is internally
set to zero; therefore, only the lower half of the
buffer can be accessed. Table 2 lists the frequency
ranges reported. The FREQ bits are updated three
times per block and the clock on the FCK pin
must be valid for two thirds of a block for the
FREQ bits to be accurate. The vast majority of
audio systems must meet the 400 ppm tolerance
listed in the table. The 4% tolerance is provided
for unique situations where the approximate fre-
quency needs to be known, even though that
frequency is outside the normal audio specifica-
tions.
V is the validity status bit which is set any time
the received validity bit is high. PARITY is set
when a parity error is detected. CODE is set when
a biphase coding error is detected. LOCK is as-
serted when the receiver PLL is not locked and
occurs when there is no input on RXP/RXN, or if
the received frequency is out of the receiver lock
range (25 kHz to 55 kHz). Lock is achieved after
receiving three frame preambles followed by one
block preamble, and is lost after four consecutive
frame preambles are not received. CONF is the
confidence flag which is asserted when the re-
ceived data eye opening is less than half a bit
period. This indicates the transmission link is
poor and does not meet specifications.
IEnable register 2 has corresponding interrupt en-
able bits for the first five bits in SR2. A "1"
enables the condition in SR2 to cause ERF to go
high, while a "0" masks that condition. Bit 5 is
unused and bits 6 and 7, the two most significant
bits, are factory test bits and must be set to zero
when writing to this register. The CS8411 sets
these bits to zero on power-up.
Control Registers
The CS8411 contains two control registers. Con-
trol register 1 (CR1), at address 2, selects system
level features, while control register 2 (CR2), at
address 3, configures the audio serial port.
X:01
SR2
7
6
5
4
3
2
1
0
FREQ2 FREQ1 FREQ0 CONF LOCK CODE PARITY
V
IER2 TEST1 TEST0
INT. ENABLE BITS FOR ABOVE
SR2:
FREQ2: The 3 FREQ bits indicate incoming sample freq.
In control register 1, when RST is low, all outputs
are reset except MCK (FSYNC and SCLK are
high impedance). After the user sets RST high,
the CS8411 comes fully out of reset when the
block boundary is found. The serial port, in mas-
ter mode, will begin to operate as soon as RST
goes high. B0 and B1 select one of three buffer
modes listed in Table 1 and illustrated in Figure 5.
In all modes four bytes of user data are stored. In
mode 0, one entire block of channel status is
stored. In mode 1 eight bytes of channel status
FREQ1:
FREQ0:
(must have 6.144 MHz clock on FCK pin
and FCEN must be "1")
CONF: Confidence error
LOCK: Out-of-Lock error
CODE: Coding violation
PARITY: Parity error
V: Validity bit high
IER2:
TEST1,0: (0 on power-up) Must stay at "0".
INT. ENABLES: Enables the corresponding bit in SR2.
A "1" enables the interrupt. A "0" masks the interrupt.
Figure 7. Status/IEnable Register 2
10
DS61PP4
CS8411
and sixteen bytes of auxiliary data are stored. In
mode 2, eight bytes of channel status from each
sub-frame are stored. The buffer modes are dis-
cussed in more detail in the Buffer Memory
section. The next bit, CS2/CS1, selects the par-
ticular sub-frame of channel status to buffer in
modes 0 and 1, and has no effect in mode 2.
When CS2/CS1 is low, sub-frame 1 is buffered,
and when CS2/CS1 is high, sub-frame 2 is buff-
ered. IER/SR selects which set of registers, either
IEnable or status, occupy addresses 0 and 1.
When IER/SR is low, the status registers occupy
the first two addresses, and when IER/SR is high,
the IEnable registers occupy those addresses.
FCEN enables the internal frequency counter. A
6.144 MHz clock must be connected to the FCK
pin as a reference. The value of the FREQ bits in
SR2 are not valid until two thirds of a block of
data is received. Since FCK and A4, the most sig-
nificant address bit, occupy the same pin, A4 is
internally set to zero when FCEN is high. Since
A4 is forced to zero, the upper half of the buffer
is not accessible while using the frequency com-
pare feature. FPLL determines how FSYNC is
derived. When FPLL is low, FSYNC is derived
from the incoming data, and when FPLL is high,
it is derived from the internal phase-locked loop.
Control Register 2 configures the serial port
which consists of three pins: SCK, SDATA, and
FSYNC. SDATA is always an output, but SCK
and FSYNC can be configured as inputs or out-
puts. FSYNC and SDATA can have a variety of
relationships to each other, and the polarity of
SCK can be controlled. The large variety of audio
data formats provides an easy interface to most
DSPs and other audio processors. SDATA is nor-
mally just audio data, but special modes are
provided that output received biphase data, or re-
ceived NRZ data with zeros substituted for
preamble. Another special mode allows an asyn-
chronous SCK input to read audio data from the
serial port without slipping samples. In this mode
FSYNC and SDATA are outputs synchronized to
the SCK input. Since SCK is asynchronous to the
received clock, the number of SCK cycles be-
tween FSYNC edges will vary.
X:03
7
6
5
4
3
2
1
0
CR2 ROER SDF2 SDF1 SDF0 FSF1 FSF0 MSTR SCED
ROER: Repeat previous value on error (audio data)
SDF2: with SDF0 & SDF1, select serial data format.
SDF1: with SDF0 & SDF2, select serial data format.
SDF0: with SDF1 & SDF2, select serial data format.
FSF1: with FSF0, select FSYNC format.
2
X:02
7
6
5
4
3
1
0
CR1 FPLL FCEN IER/SR CS2/CS1 B1
B0
RST
FSF0: with FSF1, select FSYNC format.
MSTR: When set, SCK and FSYNC are outputs.
SCED: When set, falling edge of SCK outputs data.
When clear, rising edge of SCK outputs data.
FPLL: 0 - FSYNC from RXP/RXN, 1 - FSYNC from PLL
FCEN: enables freq. comparator (FCK must be 6.144 MHz).
IER/SR: [X:00,01] 0 - status, 1 - interrupt enable registers.
CS2/CS1: ch. status to buffer; 0 - sub-frame 1, 1 - sub-frame 2.
B1: with B0, selects the buffer memory mode.
Figure 9. Control Register 2
B0: with B1, selects the buffer memory mode.
RST: Resets internal counters. Set to "1" for normal operation.
FREQ2 FREQ1 FREQ0
Sample Frequency
Out of Range
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Figure 8. Control Register 1
48kHz ± 4%
44.1 kHz ± 4%
B1
B0
Mode
Buffer Memory Contents
32 kHz ± 4%
0
0
1
1
0
1
0
1
0
1
2
3
Channel Status
Auxiliary Data
48 kHz ± 400 ppm
44.1 kHz ± 400 ppm
44.056 kHz ± 400 ppm
32 kHz ± 400 ppm
Independent Channel Status
Reserved
Table 1. Buffer Memory Modes
Table 2. Incoming Sample Frequency Bits
DS61PP4
11
CS8411
ROER, when set, causes the last audio sample to
be reread if the error pin, ERF, is active. When
out of lock, the CS8411 will output zeros if
ROER is set and output random data if ROER is
not set. The conditions that activate ERF are those
reported in SR2 and enabled in IER2. Figure 10
illustrates the modes selectable by SDF2-SDF0
and FSF1-FSF0. MSTR, which in most applica-
tions will be set to one, determines whether
FSYNC and SCK are outputs (MSTR = 1) or in-
puts (MSTR = 0). When FSYNC and SCK are
inputs (slave mode) the audio data can be read
twice or missed if the device controlling FSYNC
and SCK is on a different time-base than the
CS8411. If the audio data is read twice or missed,
the SLIP bit in SR1 is set. SCED selects the SCK
edge to output data on. SCED high causes data to
be output on the falling edge, and SCED low
causes data to be output on the rising edge.
FSF MSTR
32 Bits
32 Bits
10 (bit)
00
01
10
0
0
0
FSYNC Input
FSYNC Input
FSYNC Input
11
00
01
10
11
0
1
1
1
1
FSYNC Input
FSYNC Output
FSYNC Output
FSYNC Output
FSYNC Output
16 Clocks
16 Clocks
16 Clocks
16 Clocks
32 Clocks
32 Clocks
32 Clocks
32 Clocks
Left Sample
24 Bits, Incl. Aux
Right Sample
24 Bits, Incl. Aux
SDF
Name
210 (bit)
MSB
LSB
LSB
MSB
MSB
000
001
MSB First - 32
24 Bits, Incl. Aux
24 Bits, Incl. Aux
MSB Last
LSB
MSB
LSB
LSB
LSB
MSB
LSB
LSB
LSB
LSB
MSB
LSB
LSB
LSB
16 Bits
16 Bits
LSB Last - 16
LSB Last - 18
LSB Last - 20
011
101
111
MSB
18 Bits
MSB
18 Bits
MSB
MSB
20 Bits
20 Bits
MSB
MSB
SPECIAL MODES:
SDF
210 MSTR
24 Bits, Incl. Aux
24 Bits, Incl. Aux
Name
MSB
MSB
MSB
MSB
MSB
LSB
LSB
MSB
MSB
100
0
Async SCK
24 Bits, Incl. Aux
16 Bits
24 Bits, Incl. Aux
16 Bits
110
0
MSB First - 24
LSB
LSB
010
0
MSB First - 16
LSB MSB
MSB VUCP
LSB MSB
MSB VUCP
AUX
32 Bits
32 Bits
LSB
AUX
LSB
AUX
010*
100*
1
1
NRZ Data
Bi-Phase Mark Data
Bi-Phase Mark Data
Bi-Phase Data
* Error flags are not accurate in these modes
Figure 10. CS8411 Serial Port SDATA and FSYNC Timing
12
DS61PP4
CS8411
Audio Serial Port
SDATA can take on five formats in the normal
serial port modes. The first format (see Fig-
ure 10), MSB First, has the MSB aligned with the
start of a sample frame. Twenty-four audio bits
are output including the auxiliary bits. This mode
is compatible with many DSPs. If the auxiliary
bits are used for something other than audio data,
they must be masked off. The second format,
MSB Last, outputs data LSB first with the MSB
aligned to the end of the sample frame. This for-
mat is conducive to serial arithmetic. Both of the
above formats output all audio bits from the re-
ceived data. The last three formats are LSB Last
formats that output the most significant 16, 18,
and 20 bits respectively, with the LSB aligned to
the end of the sample frame. These formats are
used by many interpolation filters.
The audio serial port outputs the audio data por-
tion from the received data and consists of three
pins: SCK, SDATA, and FSYNC. SCK clocks the
data out on the SDATA line. The edge that SCK
uses to output data is programmable from CR2.
FSYNC delineates the audio samples and may in-
dicate the particular channel, left or right.
Figure 10 illustrates the multitude of formats that
SDATA and FSYNC can take.
NORMAL MODES
SCK and FSYNC can be inputs (MSTR = 0) or
outputs (MSTR = 1), and are usually program-
med as outputs. As outputs, SCK contains 32
periods for each sample and FSYNC has four for-
mats. The first two output formats of FSYNC
(shown in Figure 10) delineate each word and the
identification of the particular channel must be
kept track of externally. This may be done using
the rising edge of FLAG2 to indicate the next
data word is left channel data. The last two output
formats of FSYNC also delineate each channel
with the polarity of FSYNC indicating the par-
ticular channel. The last format has FSYNC
change one SCK cycle before the frame contain-
SPECIAL MODES
Five special modes are included for unique appli-
cations. In these modes, the master bit, MSTR,
must be defined as shown in Figure 10. In the
first mode, Asynchronous SCK, FSYNC (which
is an output in this mode) is aligned to the incom-
ing SCK. This mode is useful when the SCK is
locked to an external event and cannot be derived
from MCK. Since SCK is asynchronous, the
number of SCK cycles per sample frame will
vary. The data output will be MSB first, 24 bits,
and aligned to the beginning of a sample frame.
The second and third special modes are unique in
that they contain 24 and 16 SCK cycles respec-
tively per sample frame, whereas all normal
modes contain 32 SCK cycles. In these two
modes, the data is MSB first and fills the entire
frame. The fourth special mode outputs NRZ data
including the V, U, C, and P bits and the preamble
replaced with zeros. SCK is an output with
32 SCK cycles per sample frame. The fifth mode
outputs the biphase data recovered from the trans-
mission line with 64 SCK cycles output per
sample frame, with data changing on the rising
edge.
2
ing the data and may be used to generate an I S
compatible interface.
When SCK is programmed as an input, 32 SCK
cycles per sample must be provided. (There are
two formats in the Special Modes section where
SCK can have 16 or 24 clocks per sample.) The
four modes where FSYNC is an input are similar
to the FSYNC output modes. The first two re-
quire a transition of FSYNC to start the sample
frame, whereas the last two are identical to the
corresponding FSYNC output modes. If the cir-
cuit generating SCK and FSYNC is not locked to
the master clock of the CS8411, the serial port
will eventually be reread or a sample will be
missed. When this occurs, the SLIP bit in SR1
will be set.
DS61PP4
13
CS8411
Normally, data recovered by the CS8411 is de-
layed by two frames in propagating through the
part, but in the fourth and fifth special modes, the
data is delayed only a few bit periods before be-
ing output. However, error codes, and the C, U
and V bits follow the normal a pathway with a
two frame delay (so that the error code would be
output with the offending data in the other
modes). As a result, in special modes four and
five, the error codes are nearly two frames behind
the data output on SDATA.
part will write next, thereby indicating which two
bytes are free to be read.
FLAG1 is buffer mode dependent and is dis-
cussed in the individual buffer mode sections. A
transition of FLAG1 will generate an interrupt if
the appropriate interrupt enable bit is set.
FLAG2 is set high after channel status byte 23,
the last byte of the block, is written and set low
after channel status byte 3 is written to the buffer
memory. FLAG2 is unique in that only the rising
edge can cause an interrupt if the appropriate in-
terrupt enable bit in IER1 is set.
Buffer Memory
In all buffer modes, the status, mask, and control
registers are located at addresses 0-3, and the user
data is buffered at locations 4 through 7. The par-
allel port can access any location in the user data
buffer at any time; however, care should be taken
not to read a location when that location is being
updated internally. This internal writing is done
through a second port of the buffer and is done in
a cyclic manner. As data is received, the bits are
assembled in an internal 8-bit shift register which,
when full, is loaded into the buffer memory. The
first bit received is stored in D0 and, after D7 is
received, the byte is written into the proper buffer
memory location.
Figure 11 illustrates the flag timing for an entire
channel status block which includes 24 bytes of
channel status data per channel and 384 audio
samples. The lower portion of Figure 11 expands
the first byte of channel status showing eight pairs
of data, with a pair defined as a frame. This is
further expanded showing the first sub-frame
(A0) to contain 32 bits defined as per the digital
audio standards. When receiving stereo, chan-
nel A is left and channel B is right.
For all three buffer modes, the three most signifi-
cant bits in SR1, shown in Figure 6, can be used
to monitor the channel status data. In buffer
mode 2, bits 7 and 6 change definition and are de-
scribed in that section. Channel status data, as
described in the standards, is independent for
each channel. Each channel contains its own
block of channel status data, and in most systems,
both channels will contain the same channel
status data. Buffer modes 0 and 1 operate on one
block of channel status with the particular block
selected by the CS2/CS1 bit in CR1. CSDIF, bit 7
in SR1, indicates when the channel status data for
each channel is not the same even though only
one channel is being buffered. CRCE, bit 6 in
SR1, indicates a CRC error occurred in the buff-
ered channel. CCHG, bit 5 in SR1, is set when
any bit in the buffered channel status bytes 0 to 3,
change from one block to the next.
The user data is received one bit per sub-frame.
At the channel status block boundary, the internal
pointer for writing user data is initialized to 04H
(Hex). After receiving eight user bits, the byte is
written to the address indicated by the user
pointer which is then incremented to point to the
next address. After receiving all four bytes of user
data, 32 audio samples, the user pointer is set to
04H again and the cycle repeats. FLAG0, in SR1
can be used to monitor the user data buffer. When
the last byte of the user buffer, location 07H, is
written, FLAG0 is set low and when the second
byte, location 05H, is written, FLAG0 is set high.
If the corresponding bit in the interrupt enable
register (IER1, bit 0) is set, a transition of FLAG0
will generate a low pulse on the interrupt pin. The
level of FLAG0 indicates which two bytes the
14
DS61PP4
CS8411
BUFFER MODE 0
FLAG1 in status register 1, SR1, can be used to
monitor the channel status buffer. In mode 0,
FLAG1 is set low after channel status byte 23 (the
last byte) is written, and is set high when channel
status byte 15, location 17H is written. If the cor-
responding interrupt enable bit in IER1 is set, a
transition of FLAG1 will generate a pulse on the
interrupt pin. Figure 12 illustrates the memory
write sequence for buffer mode 0 along with flag
timing. The arrows on the flag timing indicate
when an interrupt will occur if the appropriate in-
terrupt enable bit is set. FLAG0 can cause an
interrupt on either edge, which is only shown in
the expanded portion of the figure for clarity.
The user data buffer previously described is iden-
tical for all modes. Buffer mode 0 allocates the
rest of the buffer to channel status data. This
mode stores an entire block of channel status in
24 memory locations from address 08H to 1FH.
Channel status (CS) data is different from user
data in that channel status data is independent for
each channel. A block of CS data is defined as
one bit per frame, not one bit per sub-frame;
therefore, there are two blocks of channel status.
The CS2/CS1 bit in CR1 selects which channel is
stored in the buffer. In a typical system sending
stereo data, the channel status data for each chan-
nel would be identical.
Block
(384 Audio Samples)
Flag 2
Flag 1
Mode 0
Flag 1
Modes 1 & 2
Flag 0
23
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
Channel Status Byte
0
1
(Expanded)
Frame
B 1
A 2
B 2
A 0
B 0
A 1
B 7
A 7
(Expanded)
Sub-frame
Audio Data
27 28 29 30 31
MSB
bit
0
3
4
Aux Data
7 8
Preamble
V
U
C
P
LSB
Validity
User Data
Channel Status Data
Parity Bit
Figure 11. CS8411 Status Register Flag Timing
DS61PP4
15
CS8411
Block
(384 Audio Samples)
FLAG2
FLAG1
FLAG0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
0
1
C.S. Byte
1F 08
0B 0C
C.S. Address
08
(Expanded)
FLAG0
C.S. Addr.
1F
07
08
05
09
07
0A
05
0B
(Addresses are in Hex)
User Addr.
04
06
04
06
07
Figure 12. CS8411 Buffer Memory Write Sequence - MODE 0
Block
(384 Audio Samples)
FLAG2
FLAG1
FLAG0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
0
1
C.S. Byte
08
0B 0C
0F 0C
0F 0C
0F 0C
0F 0C
0F 08
C.S. Address
(Addresses are in Hex)
(Expanded)
FLAG1
FLAG0
C.S. Addr. 0F
08
05
17 18
09
0A
0B
07
1F
User Addr. 07
04
13,14
06
1B,1C
07
04
13,14
05
06
Aux. Addr. 1F 10
1F 10
17 18
1B,1C
Figure 13. CS8411 Buffer Memory Write Sequence - MODE 1
16
DS61PP4
CS8411
BUFFER MODE 1
determines whether the channel status pointer is
writing to the first four-byte section of the chan-
nel status buffer or the second four-byte section,
while FLAG1 indicates which two bytes of the
section are free to update.
In buffer mode 1, eight bytes are allocated for
channel status data and sixteen bytes for auxiliary
data as shown in Figure 5. The user data buffer is
the same for all modes. The channel status buffer,
locations 08H to 0FH, is divided into two sec-
tions. The first four locations always contain the
first four bytes of channel status, identical to
mode 0, and are written once per channel status
block. The second four locations, addresses 0CH
to 0FH, provide a cyclic buffer for the last
20 bytes of channel status data. The channel
status buffer is divided in this fashion because the
first four bytes are the most important ones;
whereas, the last 20 bytes are often not used (ex-
cept for byte 23, CRC).
The auxiliary data buffer, locations 10H to 1FH,
is written to in a cyclic manner similar to the
other buffers. Four auxiliary data bits are received
per audio sample (sub-frame) and, since the aux-
iliary data is four times larger than the user data,
the auxiliary data buffer on the CS8411 is four
times larger allowing FLAG0 to be used to moni-
tor both.
BUFFER MODE 2
In buffer mode 2, two 8-byte buffers are available
to independently buffer each channel of channel
status data. Both buffers are identical to the chan-
nel status buffer in mode 1 and are written to
simultaneously, with locations 08H to 0FH con-
taining CS data for channel A and locations 10H
to 17H containing CS data for channel B. Both
FLAG1 and FLAG2 can be used to monitor this
buffer as shown in Figure 13. FLAG1 is set high
when CS byte 1, location 09H, is written and is
toggled when every other byte is written. FLAG2
is set high after CS byte 23 is written and set low
after CS byte 3, location 0BH, is written. FLAG2
Block
(384 Audio Samples)
FLAG2
FLAG1
FLAG0
C.S. Byte
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
0
1
08
0B 0C
13 14
0F 0C
0F 0C
17 14
0F 0C
17 14
0F 0C
17 14
0F 08
Left C.S. Ad.
Right C.S. Ad.
10
17 14
14 10
(Addresses are in Hex)
(Expanded)
FLAG1
FLAG0
Left C.S. Ad.
Right C.S. Ad.
User Address
08
10
05
09
11
07
0A
12
05
0B
13
04
06
04
06
07
Figure 14. CS8411 Buffer Memory Write Sequence - MODE 2
DS61PP4
17
CS8411
CS buffers can be monitored using FLAG1 and
FLAG2 as described in the BUFFER MODE 1
section.
SCK is 64 times the incoming sample frequency,
and is the same SCK output in master mode. The
FSYNC shown is valid for all master modes ex-
2
cept the I S compatible mode. The interrupt pulse
The two most significant bits in SR1 change defi-
nition for buffer mode 2. These two bits, when
set, indicate CRC errors for their respective chan-
nels. A CRC error occurs when the internal
calculated CRC for channel status bytes 0
through 22 does not match channel status byte 23.
CCHG, bit 5 in SR1, is set when any bit in the
first four channel status bytes of either channel
changes from one block to the next. Since chan-
nel status doesn’t change very often, this bit may
be monitored rather than checking all the bits in
the first four bytes. These bits are illustrated in
Figure 6.
is shown to be 4 SCK periods wide and goes low
5 SCK periods after the RAM is written. Using
the above information, the entire data buffer may
be read starting with the next byte to be updated
by the internal pointer.
ERF Pin Timing
ERF signals that an error occurred while receiv-
ing the audio sample that is currently being read
from the serial port. ERF changes with the active
edge of FSYNC and is high during the errorred
sample. ERF is affected by the error conditions
reported in SR2: CONF, LOCK, CODE, PARITY,
and V. Any of these conditions may be masked off
using the corresponding bits in IER2. The ERF
pin will go high for each error that occurs. The
ERF bit in SR1 is different from the ERF pin in
that it only causes an interrupt the first time an
error occurs until SR1 is read. More information
on the ERF pin and bit is contained at the end of
the Status and IEnable Registers section.
Buffer Updates and Interrupt Timing
As mentioned previously in the buffer mode sec-
tions, conflicts between externally reading the
buffer RAM and the CS8411 internally writing to
it may be averted by using the flag levels to avoid
the section currently being addressed by the part.
However, if the interrupt line, along with the
flags, is utilized, the actual byte that was just up-
dated can be determined. In this way, the entire
buffer can be read without concern for internal
updates. Figure 15 shows the detailed timing for
the interrupt line, flags, and the RAM write line.
SCK
FSYNC
IWRITE
Left 191
Right 191
Left 0
___
INT
(FLAG0,1)
___
INT (FLAG2)
FSF1,0= 1 0
MSTR = 1
SCED = 1
Figure 15. RAM/Buffer-Write and Interrupt Timing
18
DS61PP4
CS8411
PIN DESCRIPTIONS:
CS8411
1
28
DATA BUS BIT 2
DATA BUS BIT 3
DATA BUS BIT 4
DATA BUS BIT 5
DATA BUS BIT 6
D2
D3
D4
D5
D6
D1
D0
DATA BUS BIT 1
DATA BUS BIT 0
SERIAL OUTPUT DATA
ERROR FLAG
2
27
26
25
24
23
22
21
20
19
18
17
16
15
3
SDATA
ERF
CS
RD/WR
VA+
AGND
FILT
MCK
A0
4
5
CHIP SELECT
6
DATA BUS BIT 7
D7
READ/WRITE SELECT
ANALOG POWER
ANALOG GROUND
FILTER
MASTER CLOCK
ADDRESS BUS BIT 0
ADDRESS BUS BIT 1
ADDRESS BUS BIT 2
ADDRESS BUS BIT 3
7
DIGITAL POWER
DIGITAL GROUND
RECEIVE POSITIVE
RECEIVE NEGATIVE
FRAME SYNC
VD+
DGND
RXP
RXN
FSYNC
SCK
A4/FCK
INT
8
9
10
11
12
13
14
SERIAL DATA CLOCK
ADD BUS BIT 4 / FCLOCK
INTERRUPT
A1
A2
A3
Power Supply Connections
VD+ - Positive Digital Power, PIN 7.
Positive supply for the digital section. Nominally +5 volts.
VA+ - Positive Analog Power, PIN 22.
Positive supply for the analog section. Nominally +5 volts. This supply should be as
quiet as possible since noise on this pin will directly affect the jitter performance of the
recovered clock.
DGND - Digital Ground, PIN 8.
Ground for the digital section. DGND should be connected to same ground as AGND.
AGND - Analog Ground, PIN 21.
Ground for the analog section. AGND should be connected to same ground as DGND.
Audio Output Interface
SCK - Serial Clock, PIN 12.
Serial clock for SDATA pin which can be configured (via control register 2) as an input
or output, and can sample data on the rising or falling edge. As an input, SCK must
contain 32 clocks for every audio sample in all normal audio serial port formats.
DS61PP4
19
CS8411
FSYNC - Frame Sync, PIN 11.
Delineates the serial data and may indicate the particular channel, left or right. Also,
FSYNC may be configured as an input or output. The format is based on bits in control
register 2.
SDATA - Serial Data, PIN 26.
Audio data serial output pin.
ERF - Error Flag, PIN 25.
Signals that an error has occurred while receiving the audio sample currently being read
from the serial port. The errors that cause ERF to go high are enumerated in status
register 2 and enabled by setting the corresponding bit in IEnable register 2.
A4/FCK - Address Bus Bit 4/Frequency Clock, PIN 13.
This pin has a dual function and is controlled by the FCEN bit in control register 1. A4
is the address bus pin as defined below. When used as FCK, an internal frequency
comparator compares a 6.144 MHz clock input on this pin to the received clock
frequency and stores the value in status register 1 as three FREQ bits. These bits
indicate the incoming frequency as well as the tolerance. When defined as FCK, A4 is
internally set to 0.
Parallel Interface
CS - Chip Select, PIN 24.
This input is active low and allows access to the 32 bytes of internal memory. The
address bus and RD/WR must be valid while CS is low.
RD/WR - Read/Write, PIN 23.
If RD/WR is low when CS goes active (low), the data on the data bus is written to
internal memory. If RD/WR is high when CS goes active, the data in the internal
memory is placed on the data bus.
A4-A0 - Address Bus, PINS 13, 15-18.
Parallel port address bus that selects the internal memory location to be read from or
written to. Note that A4 is the dual function pin A4/FCK as described above.
D0-D7 - Data Bus, PINS 27-28, 1-6.
Parallel port data bus used to check status, read or write control words, or read internal
buffer memory.
20
DS61PP4
CS8411
INT - Interrupt, PIN 14.
Open drain output that can signal the state of the internal buffer memory as well as error
information. A 5kΩ resistor to VD+ is typically used to support logic gates. All bits
affecting INT are maskable to allow total control over the interrupt mechanism.
Receiver Interface
RXP, RXN - Differential Line Receivers, PINS 9, 10.
RS422 compatible line receivers. Described in detail in Appendix A.
Phase Locked Loop
MCK - Master Clock, PIN 19.
Low jitter clock output of 256 times the received sample frequency.
FILT - Filter, PIN 20.
An external 1kΩ resistor and 0.047µF capacitor are required from the FILT pin to
analog ground.
DS61PP4
21
CS8412
CS8412 DESCRIPTION
The line receiver and jitter performance are de-
scribed in the sections directly preceding the
CS8411 sections in the beginning of this data
sheet.
The CS8412 does not need a microprocessor to
handle the non-audio data (although a micro may
be used with the C and U serial ports). Instead,
dedicated pins are available for the most impor-
tant channel status bits. The CS8412 is a
monolithic CMOS circuit that receives and de-
codes digital audio data which was encoded
according to the digital audio interface standards.
It contains an RS422 line receiver and clock and
data recovery utilizing an on-chip phase-locked
loop. The audio data is output through a configur-
able serial port that supports 14 formats. The
channel status and user data have their own serial
pins and the validity flag is OR’ed with the ERF
flag to provide a single pin, VERF, indicating that
the audio output may not be valid. This pin may
be used by interpolation filters that provide error
correction. A block diagram of the CS8412 is il-
lustrated in Figure 16.
Audio Serial Port
The audio serial port is used primarily to output
audio data and consists of three pins: SCK,
FSYNC, and SDATA. These pins are configured
via four control pins: M0, M1, M2, and M3. M3
selects between eight normal serial formats (M3 =
0), and six special formats (M3 = 1).
NORMAL MODES (M3 = 0)
When M3 is low, the normal serial port formats
shown in Figure 17 are selected using M2, M1,
and M0. These formats are also listed in Table 3,
wherein the first word past the format number
(Out-In) indicates whether FSYNC and SCK are
M3 M2
17 18
M1
24
M0
23
VA+
FILT
AGND
MCK
22
20
21
19
Timing
9
Clock & Data
Recovery
RXP
RXN
11
12
FSYNC
SCK
10
Audio
Serial
Port
Bi-phase
Decoder
and
Frame
Sync
De-Multiplexer
26
1
SDATA
C
Confidence
Flag
7
8
VD+
CRC
check
R
e
g
i
14
28
Parity
Check
DGND
U
13
VERF
CS12/
FCK
s
t
Channel
Error
Encoder
Frequency
Comparator
15
25
Status
Latch
e
r
CBL
ERF
s
16
SEL
Multiplexer
6
5
4
3
2
27
C0/
E0
Ca/
E1
Cb/
E2
Cc/
F0
Cd/
F1
Ce/
F2
Figure 16. CS8412 Block Diagram
22
DS61PP4
CS8412
outputs from the CS8412 or are inputs. The next
word (L/R-WSYNC) indicates whether FSYNC
indicates the particular channel or just delineates
each word. If an error occurs (ERF = 1) while
using one of these formats, the previous valid
audio data for that channel will be output. As long
as ERF is high, that same data word will be out-
put. If the CS8412 is not locked, it will output all
zeroes. In some modes FSYNC and SCK are out-
puts and in others they are inputs. In Table 3,
LSBJ is short for LSB justified where the LSB is
justified to the end of the audio frame and the
MSB varies with word length. As outputs the
CS8412 generates 32 SCK periods per audio
sample (64 per stereo sample) and, as inputs, 32
SCK periods must be provided per audio sample.
When FSYNC and SCK are inputs, one stereo
sample is double buffered. For those modes
which output 24 bits of audio data, the auxiliary
bits will be included. If the auxiliary bits are not
used for audio data, they must be masked off.
Format 11 is similar to format 0 except that SCK
is an input and FSYNC is an output. In this mode
FSYNC and SDATA are synchronized to the in-
coming SCK, and the number of SCK periods
between FSYNC edges will vary since SCK is
not synchronous to received data stream. This
mode may be useful when writing data to storage.
Format 12 is similar to format 7 except that
SDATA is the entire data word received from the
transmission line including the C, U, V, and P
bits, with zeros in place of the preamble. In for-
mat 13 SDATA contains the entire biphase
encoded data from the transmission line including
the preamble, and SCK is twice the normal fre-
quency. The normal two frame delay of data from
input to output is reduced to only a few bit peri-
ods in formats 12 and 13. However, the C, U, V
bits and error codes follow their normal pathways
and therefore follow the output data by nearly
two frames. Figure 18 illustrates formats 12 and
13. Format 14 is reserved and not presently used,
and format 15 causes the CS8412 to go into a re-
set state. While in reset all outputs will be inactive
except MCK. The CS8412 comes out of reset at
the first block boundary after leaving the reset
state.
SPECIAL MODES (M3 = 1)
When M3 is high, the special audio modes de-
scribed in Table 4 are selected via M2, M1, and
M0. In formats 8, 9, and 10, SCK, FSYNC, and
SDATA are the same as in formats 0, 1, and 2 re-
spectively; however, the recovered data is output
as is even if ERF is high, indicating an error. (In
modes 0-2 the previous valid sample is output.)
Similarly, when out of lock, the CS8412 will still
output all the recovered data, which should be ze-
ros if there is no input to the RXP, RXN pins.
C, U, VERF, ERF, and CBL Serial Outputs
The C and U bits and CBL are output one SCK
period prior to the active edge of FSYNC in all
2
serial port formats except 2 and 3 (I S modes).
The active edge of FSYNC may be used to latch
C, U, and CBL externally. In formats 2 and 3,
M2
M1
M0
Format
M2
M1
M0
Format
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 - Out, L/R, 16-24 Bits
1 - In, L/R, 16-24 Bits
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 - Format 0 - No repeat on error
9 - Format 1 - No repeat on error
10 - Format 2 - No repeat on error
11 - Format 0 - Async. SCK input
12 - Received NRZ Data
2 - Out, L/R, I2S Compatible
3 - In, L/R, I2S Compatible
4 - Out, WSYNC, 16-24 Bits
5 - Out, L/R, 16 Bits LSBJ
6 - Out, L/R, 18 Bits LSBJ
7 - Out, L/R, MSB Last
13 - Received Bi-phase Data
14 - Reserved
15 - CS8412 Reset
Table 3. Normal Audio Port Modes (M3=0)
DS61PP4
Table 4. Special Audio Port Modes (M3=1)
23
CS8412
FMT
No.
M2 M1 M0
Right
Right
FSYNC (out)
SCK (out)
Left
Left
0
0
0
0
LSB
LSB
MSB
MSB
MSB
MSB
LSB
LSB
MSB
SDATA (out)
FSYNC (in)
1
0
0
1
SCK (in)
MSB
SDATA (out)
Left
FSYNC (out)
SCK (out)
Right
2
0
1
0
SDATA (out)
LSB
MSB
MSB
LSB
MSB
MSB
MSB
FSYNC (in)
SCK (in)
Left
Right
3
4
0
1
1
0
1
0
SDATA (out)
MSB
LSB
MSB
LSB
Right
FSYNC (out)
SCK (out)
Left
SDATA (out)
MSB
LSB
LSB
MSB
Right
MSB
FSYNC (out)
SCK (out)
Left
5
6
1
1
0
1
1
0
SDATA (out)
LSB
MSB
LSB
LSB
MSB
LSB
16 Bits
16 Bits
FSYNC (out)
SCK (out)
Right
Left
MSB
LSB
LSB
MSB
Right
LSB
SDATA (out)
18 Bits
18 Bits
FSYNC (out)
Left
7
1
1
1
SCK (out)
SDATA (out)
MSB
LSB
MSB
Figure 17. CS8412 Audio Serial Port Formats
24
DS61PP4
CS8412
No.
12
Right
Right
FSYNC (out)
SCK (out)
Left
SDATA (out)
V U C P
V U C P
AUX LSB
Left
MSB
MSB
AUX LSB
MSB
MSB
13
FSYNC (out)
SCK (out)
SDATA (out)
AUX
V U C P
AUX
V U C P
LSB
LSB
Figure 18. Special Audio Port Formats 12 and 13
the C and U bits and CBL are updated with the
active edge of FSYNC. The validity + error flag
(VERF) and the error flag (ERF) are always up-
dated at the active edge of FSYNC. This timing is
illustrated in Figure 19.
dicates a serious error occurred on the transmis-
sion line. There are three errors that cause ERF to
go high: a parity error or biphase coding violation
during that sample, or an out of lock PLL re-
ceiver. Timing for the above pins is illustrated in
Figure 19.
The C output contains the channel status bits with
CBL rising indicating the start of a new channel
status block. CBL is high for the first four bytes
of channel status (32 frames or 64 samples) and
low for the last 20 bytes of channel status
(160 frames or 320 samples). The U output con-
tains the User Channel data. The V bit is OR’ed
with the ERF flag and output on the VERF pin.
This indicates that the audio sample may be in
error and can be used by interpolation filters to
interpolate through the error. ERF being high in-
Multifunction Pins
There are seven multifunction pins which contain
either error and received frequency information,
or channel status information, selectable by SEL.
ERROR AND FREQUENCY REPORTING
When SEL is low, error and received frequency
information are selected. The error information is
encoded on pins E2, E1, and E0, and is decoded
CBL
C0,
Ca-Ce
SDATA Right 191
FSYNC
Left 0
Right 0
Left 1
Right 31
Left 32
Right 191
Left 0
ERF,
VERF
C, U
Figure 19. CBL Timing
DS61PP4
25
CS8412
as shown in Table 5. When an error occurs, the
corresponding error code is latched. Clearing is
then accomplished by bringing SEL high for
more than eight MCK cycles. The errors have a
priority associated with their error code, with va-
lidity having the lowest priority and no lock
having the highest priority. Since only one code
can be displayed, the error with the highest prior-
ity that occurred since the last clearing will be
selected.
ity error occurs when the incoming sub-frame
does not have even parity as specified by the
standards. The biphase coding error indicates a
biphase coding violation occurred. The no lock
error indicates that the PLL is not locked onto the
incoming data stream. Lock is achieved after re-
ceiving three frame preambles then one block
preamble, and is lost after not receiving four con-
secutive frame preambles.
The received frequency information is encoded
on pins F2, F1, and F0, and is decoded as shown
in Table 6. The on-chip frequency comparator
compares the received clock frequency to an ex-
ternally supplied 6.144 MHz clock which is input
on the FCK pin. The ’F’ pins are updated three
times during a channel status block including
prior to the rising edge of CBL. CBL may be
used to externally latch the ’F’ pins. The clock on
FCK must be valid for two thirds of a block for
the ’F’ pins to be accurate.
The validity flag indicates that the validity bit for
a previous sample was high since the last clearing
of the error codes. The confidence flag occurs
when the received data eye opening is less than
half a bit period. This indicates that the quality of
the transmission link is poor and does not meet
the digital audio interface standards. The slipped
sample error can only occur when FSYNC and
SCK of the audio serial port are inputs. In this
case, if FSYNC is asynchronous to the received
data rate, periodically a stereo sample will be
dropped or reread depending on whether the read
rate is slower or faster than the received data rate.
When this occurs, the slipped sample error code
will appear on the ’E’ pins. The CRC error is up-
dated at the beginning of a channel status block,
and is only valid when the professional format of
channel status data is received. This error is indi-
cated when the CS8412 calculated CRC value
does not match the CRC byte of the channel
status block or when a block boundary changes
(as in removing samples while editing). The par-
CHANNEL STATUS REPORTING
When SEL is high, channel status is displayed on
C0, and Ca-Ce for the channel selected by CS12.
If CS12 is low, channel status for sub-frame 1 is
displayed, and if CS12 is high, channel status for
sub-frame 2 is displayed. The contents of Ca-Ce
depend upon the C0 professional/consumer bit.
The information reported is shown in Table 7.
E2
E1
E0
Error
F2
0
F1
0
F0
0
Sample Frequency
Out of Range
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No Error
Validity Bit High
Confidence Flag
Slipped Sample
CRC Error (PRO only)
Parity Error
0
0
1
48kHz ± 4%
0
1
0
44.1kHz ± 4%
0
1
1
32kHz ± 4%
1
0
0
48kHz ± 400 ppm
44.1kHz ± 400 ppm
44.056kHz ± 400 ppm
32kHz ± 400 ppm
1
0
1
Bi-Phase Coding Error
No Lock
1
1
0
1
1
1
Table 5. Error Decoding
Table 6. Sample Frequency Decoding
26
DS61PP4
CS8412
Professional Channel Status (C0 = 0)
The audio standards, in consumer mode, describe
bit 15, L, as the generation status which indicates
whether the audio data is an original work or a
copy (1st generation or higher). The definition of
the L bit is reversed for three category codes: two
broadcast codes, and laser-optical (CD’s). There-
fore, to interpret the L bit properly, the category
code must be decoded. The CS8412 does this de-
coding internally and provides the ORIG signal
that, when low, indicates that the audio data is
original over all category codes.
When C0 is low, the received channel status block
is encoded according to the professional/broad-
cast format. The Ca through Ce pins are defined
for some of the more important professional bits.
As listed in Table 7, Ca is the inverse of channel
status bit 1. Therefore, if the incoming channel
status bit 1 is 1, Ca, defined as C1, will be 0. C1
indicates whether audio (C1 = 1) or non-audio
(C1 = 0) data is being received. Cb and Cc, de-
fined as EM0 and EM1 respectively, indicate
emphasis and are encoded versions of channel
status bits 2, 3, and 4. The decoding is listed in
Table 8. Cd, defined as C9, is the inverse of chan-
nel status bit 9, which gives some indication of
channel mode. (Bit 9 is also defined as bit 1 of
byte 1.) When Ce, defined as CRCE, is low, the
CS8412 calculated CRC value does not match the
received CRC value. This signal may be used to
qualify Ca through Cd. If Ca through Ce are be-
ing displayed, Ce going low can indicate not to
update the display.
SCMS
The consumer audio standards also mention a se-
rial copy management system, SCMS, for dealing
with copy protection of copyrighted works.
SCMS is designed to allow unlimited duplication
of the original work, but no duplication of any
copies of the original. This system utilizes the
channel status bit 2, Copy, and channel status
bit 15, L or generation status, along with the cate-
gory codes. If the Copy bit is 0, copyright
protection is asserted over the material. Then, the
L bit is used to determine if the material is an
original or a duplication. (As mentioned in the
previous paragraph, the definition of the L bit can
be reversed based on the category codes.) There
are two category codes that get special attention:
general and A/D converters without C or L bit in-
formation. For these two categories the SCMS
standard requires that equipment interfacing to
these categories set the C bit to 0 (copyright pro-
tection asserted) and the L bit to 1 (original). To
support this feature, Ce, in the consumer mode, is
defined as IGCAT (ignorant category) which is
low for the "general" (0000000) and "A/D con-
verter without copyright information" (01100xx)
categories.
Consumer Channel Status (C0 = 1)
When C0 is high, the received channel status
block is encoded according to the consumer for-
mat. In this case Ca through Ce are defined
differently as shown in Table 7. Ca is the inverse
of channel status bit 1, C1, indicating audio (C1 =
1) or non-audio (C1 = 0). Cb is defined as the
inverse of channel status bit 2, C2, which indi-
cates copy inhibit/copyright information. Cc,
defined as C3, is the emphasis bit of channel
status, with C3 low indicating the data has had
pre-emphasis added.
Pin
Professional
Consumer
C0
Ca
Cb
Cc
Cd
Ce
0 (low)
C1
1 (high)
C1
EM1
EM0
C2
C3
C4
0
0
1
1
0
1
0
1
1
1
1
0
1
1
0
0
1
0
0
0
EM0
EM1
C9
C2
C3
ORIG
IGCAT
CRCE
Table 7. Channel Status Pins
Table 8. Emphasis Encoding
DS61PP4
27
CS8412
PIN DESCRIPTIONS:
CS8412
1
28
CHANNEL STATUS OUTPUT
CS d / FREQ REPORT 1
CS c / FREQ REPORT 0
CS b / ERROR CONDITION 2
CS a / ERROR CONDITION 1
CS 0 / ERROR CONDITION 0
DIGITAL POWER
C
Cd/F1
Cc/F0
Cb/E2
Ca/E1
C0/E0
VD+
DGND
RXP
RXN
VERF
Ce/F2
SDATA
ERF
M1
VALIDITY + ERROR FLAG
CS e / FREQ REPORT 2
SERIAL OUTPUT DATA
ERROR FLAG
SERIAL PORT MODE SELECT 1
SERIAL PORT MODE SELECT 2
ANALOG POWER
ANALOG GROUND
FILTER
MASTER CLOCK
2
27
26
25
24
23
22
21
20
19
18
17
16
15
3
4
5
6
M0
7
VA+
AGND
FILT
MCK
M2
M3
SEL
CBL
8
DIGITAL GROUND
RECEIVE POSITIVE
RECEIVE NEGATIVE
9
10
11
12
13
14
FRAME SYNC
SERIAL DATA CLOCK
CHANNEL SELECT / FCLOCK CS12/FCK
FSYNC
SCK
SERIAL PORT MODE SELECT 2
SERIAL PORT MODE SELECT 3
FREQ/CS SELECT
USER DATA OUTPUT
U
CS BLOCK START
Power Supply Connections
VD+ - Positive Digital Power, PIN 7.
Positive supply for the digital section. Nominally +5 volts.
VA+ - Positive Analog Power, PIN 22.
Positive supply for the analog section. Nominally +5 volts.
DGND - Digital Ground, PIN 8.
Ground for the digital section. DGND should be connected to same ground as AGND.
AGND - Analog Ground, PIN 21.
Ground for the analog section. AGND should be connected to same ground as DGND.
Audio Output Interface
SCK - Serial Clock, PIN 12.
Serial clock for SDATA pin which can be configured (via the M0, M1, M2, and M3
pins) as an input or output, and can sample data on the rising or falling edge. As an
output, SCK will generate 32 clocks for every audio sample. As an input, 32 SCK
periods per audio sample must be provided in all normal modes.
FSYNC - Frame Sync, PIN 11.
Delineates the serial data and may indicate the particular channel, left or right, and may
be an input or output. The format is based on M0, M1, M2, and M3 pins.
28
DS61PP4
CS8412
SDATA - Serial Data, PIN 26.
Audio data serial output pin.
M0, M1, M2, M3 - Serial Port Mode Select, PINS 23, 24, 18, 17.
Selects the format of FSYNC and the sample edge of SCK with respect to SDATA. M3
selects between eight normal modes (M3 = 0), and six special modes (M3 = 1).
Control Pins
VERF - Validity + Error Flag, PIN 28.
A logical OR’ing of the validity bit from the received data and the error flag. May be
used by interpolation filters to interpolate through errors.
U - User Bit, PIN 14.
Received user bit serial output port. FSYNC may be used to latch this bit externally.
C - Channel Status Output, PIN 1.
Received channel status bit serial output port. FSYNC may be used to latch this bit
externally.
CBL - Channel Status Block Start, PIN 15.
The channel status block output is high for the first four bytes of channel status and low
for the last 16 bytes.
SEL - Select, PIN 16.
Control pin that selects either channel status information (SEL = 1) or error and
frequency information (SEL = 0) to be displayed on six of the following pins.
C0, Ca, Cb, Cc, Cd, Ce - Channel Status Output Bits, PINS 2-6, 27.
These pins are dual function with the ’C’ bits selected when SEL is high. Channel status
information is displayed for the channel selected by CS12. C0, which is channel status
bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further controls the
definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
CS12 - Channel Select, PIN 13.
This pin is also dual function and is selected by bringing SEL high. CS12 selects
sub-frame 1 (when low) or sub-frame 2 (when high) to be displayed by channel status
pins C0 and Ca through Ce.
FCK - Frequency Clock, PIN 13.
Frequency Clock input that is enabled by bringing SEL low. FCK is compared to the
received clock frequency with the value displayed on F2 through F0. Nominal input
value is 6.144 MHz.
DS61PP4
29
CS8412
E0, E1, E2 - Error Condition, PINS 4-6.
Encoded error information that is enabled by bringing SEL low. The error codes are
prioritized and latched so that the error code displayed is the highest level of error since
the last clearing of the error pins. Clearing is accomplished by bring SEL high for more
than 8 MCK cycles.
F0, F1, F2 - Frequency Reporting Bits, PINS 2-3, 27.
Encoded sample frequency information that is enabled by bringing SEL low. A proper
clock on FCK must be input for at least two thirds of a channel status block for these
pins to be valid. They are updated three times per block, starting at the block boundary.
ERF - Error Flag, PIN 25.
Signals that an error has occurred while receiving the audio sample currently being read
from the serial port. Three errors cause ERF to go high: a parity or biphase coding
violation during the current sample, or an out of lock PLL receiver.
Receiver Interface
RXP, RXN - Differential Line Receivers, PINS 9, 10.
RS422 compatible line receivers.
Phase Locked Loop
MCK - Master Clock, PIN 19.
Low jitter clock output of 256 times the received sample frequency.
FILT - Filter, PIN 20.
An external 1kΩ resistor and 0.047µF capacitor is required from FILT pin to analog
ground.
30
DS61PP4
CS8411 CS8412
APPENDIX A: RS422 Receiver Information
flowing down the shield of the cable that could
result when boxes with different ground poten-
tials are connected. Generally, it is good practice
to ground the shield to the chassis of the trans-
mitting unit, and connect the shield through a
capacitor to chassis ground at the receiver. How-
ever, in some cases it is advantagous to have the
ground of two boxes held to the same potential,
and the cable shield might be depended upon to
make that electrical connection. Generally, it
The RS422 receivers on the CS8411 and
CS8412 are designed to receive both the profes-
sional and consumer interfaces, and meet all
specifications listed in the digital audio stand-
ards. Figure A1 illustrates the internal schematic
of the receiver portion of both chips. The re-
ceiver has a differential input. A Schmitt trigger
is incorporated to add hysteresis which prevents
noisy signals from corrupting the phase detector.
8k
8k
Professional Interface
16 k
9
RXP
The digital audio specifications for professional
use call for a balanced receiver, using XLR con-
nectors, with 110Ω ± 20% impedance. (The
XLR connector on the receiver should have fe-
male pins with a male shell.) Since the receiver
has a very high impedance, a 110Ω resistor
should be placed across the receiver terminals to
match the line impedance, as shown in Fig-
ure A2, and, since the part has internal biasing,
no external biasing network is needed. If some
isolation is desired without the use of transform-
ers, a 0.01µF capacitor should be placed on the
input of each pin (RXP and RXN) as shown in
Figure A3. However, if transformers are not
used, high frequency energy could be coupled
between transmitter and receiver causing degra-
dation in analog performance.
+
_
16 k
4 k
10 RXN
4 k
Figure A1. RS422 Receiver Internal Circuit
CS8411/12
RXP
XLR
* See Text
110
110
Twisted
Pair
RXN
1
Figure A2. Professional Input Circuit
CS8411/12
XLR
0.01 uF
0.01 uF
* See Text
110
RXP
110
Twisted
Pair
Although transformers are not required by AES
they are strongly recommended. The EBU re-
quires transformers. Figures A2 and A3 show an
optional DC blocking capacitor on the transmis-
sion line. A 0.1 to 0.47µF ceramic capacitor may
be used to block any DC voltage that is acciden-
tally connected to the digital audio receiver. The
use of this capacitor is an issue of robustness as
the digital audio transmission line does not have
a DC voltage component.
RXN
1
Figure A3. Transformerless Professional Circuit
CS8411/12
0.01 uF
RCA Phono
RXP
75
75
Coax
RXN
0.01
uF
Grounding the shield of the cable is a tricky is-
sue. In the configuration of systems, it is
important to avoid ground loops and DC current
Figure A4. Consumer Input Circuit
DS61PP4
31
CS8411 CS8412
may be a good idea to provide the option of
grounding or capacitively coupling to ground
with a "ground-lift" circuit.
Consumer Interface
In the case of the consumer interface, the stand-
ards call for an unbalanced circuit having a
receiver impedance of 75Ω ±5%. The connector
for the consumer interface is an RCA phono
plug (fixed socket described in Table IV of
IEC 268-11). The receiver circuit for the con-
sumer interface is shown in Figure A4.
The following are a few typical transformers:
TTL/CMOS Levels
The circuit shown in Figure A5 may be used
when external RS422 receivers or TTL/CMOS
logic drive the CS8411/12 receiver section.
Pulse Engineering
Telecom Products Group
7250 Convoy Ct.
San Diego, CA 92111
(619) 268-2400
Part Number: PE65612
TTL/CMOS
Gate
CS8411/12
RXP
0.01 uF
RXN
0.01
uF
Schott Corporation
1000 Parkers Lane Rd.
Wayzata, MN 55391
(615) 889-8800
Figure A5. TTL/CMOS Interface
Part Number: 67125450
67128990 - lower cost
67129000 - surface mount
67129600 - single shield
Transformers
The transformer used in the professional inter-
face should be capable of operation from 1.5 to
7 MHz, which is the audio data rate of 25 kHz
to 55 kHz after biphase-mark encoding. Trans-
formers provide isolation from ground loop,
60 Hz noise, and common mode noise and inter-
ference. One of the important considerations
when choosing transformers is minimizing shunt
capacitance between primary and secondary
windings. The higher the shunt capacitance, the
lower the isolation between primary and secon-
dary and the more coupling that can occur for
high frequency energy. This energy appears in
the form of common mode noise on the receive
side ground and has the potential to degrade ana-
log performance. Therefore, shielded
transformers optimized for minimum primary to
secondary capacitance may be desirable.
Scientific Conversions Inc.
42 Truman Dr.
Novato, CA 94947
(415) 892-2323
Part Number: SC916-01 - single shield
SC916-01A - improved version
SC937-01 - low profile
SC937-02 - surface mount
32
DS61PP4
CS8411 CS8412
ORDERING GUIDE
Model
Temperature Range
Package
CS8411-CP
CS8411-IP
CS8411-CS
CS8411-IS
0 to 70 °C*
-40 to 85 °C
0 to 70 °C*
-40 to 85 °C
28-Pin Plastic .6" DIP
28-Pin Plastic .6" DIP
28-Pin Plastic SOIC
28-Pin Plastic SOIC
CS8412-CP
CS8412-IP
CS8412-CS
CS8412-IS
0 to 70 °C*
-40 to 85 °C
0 to 70 °C*
-40 to 85 °C
28-Pin Plastic .6" DIP
28-Pin Plastic .6" DIP
28-Pin Plastic SOIC
28-Pin Plastic SOIC
* Although the ’-CP’ and ’-CS’ suffixed parts are guaranteed to operate over 0 to 70 °C, they are tested
at 25 °C only. If testing over temperature is desired, the ’-IP’ and ’-IS’ suffixed parts are
tested over their specified temperature range.
DS61PP4
33
MILLIMETERS
MIN NOM MAX MIN NOM MAX
INCHES
15
14
28
1
DIM
28 pin
Plastic DIP
E1
3.94 4.32
0.51 0.76
0.36 0.46
1.02 1.27
0.20 0.25
36.45 36.83
13.72 13.97
2.41 2.54
A
A1
B
B1
C
D
E1
e1
eA
L
0.200
0.040
0.022
5.08 0.155 0.170
1.02 0.020 0.030
0.56 0.014 0.018
1.65 0.040 0.050 0.065
0.38 0.008 0.010 0.015
37.21 1.435 1.450 1.465
D
A
0.560
0.105
0.625
0.150
15°
14.22 0.540 0.550
2.67 0.095 0.100
SEATING
PLANE
L
A1
15.24
3.18
0°
-
-
-
15.87 0.600
3.81 0.125
-
-
-
e1
C
B1
B
eA
15°
0°
NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
INCHES
MILLIMETERS
pins
MIN
MIN NOM MAX
NOM MAX
16
20
24
28
9.91
0.390
0.490
0.590
0.690
10.16 10.41
0.400 0.410
0.500 0.510
0.600 0.610
0.700 0.710
12.45
12.70 12.95
14.99
17.53
15.24 15.50
17.78 18.03
D
MILLIMETERS
MIN NOM MAX MIN
INCHES
NOM MAX
DIM
SOIC
A
A
2.54 2.67
0.095
2.41
0.127
2.29
0.100 0.105
E
E
1
-
0.300 0.005
-
0.012
1
A
2.41 2.54 0.090 0.095 0.100
2
b
0.33 0.46 0.51
0.013 0.018 0.020
c
D
E
E
0.280 0.381
0.203
0.008
0.011 0.015
see table above
10.11 10.41 10.67 0.398
0.410 0.420
0.292 0.295 0.298
0.040 0.050 0.055
7.42 7.49 7.57
1.14 1.27 1.40
1
A
A
e
2
A
µ
c
0.41
0°
L
µ
0.89 0.016
-
-
-
-
0.035
8°
L
1
0°
8°
b
e
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