CS8415A [CIRRUS]
96 kHz DIGITAL AUDIO INTERFACE RECEIVER; 96千赫数字音频接口接收器
| 型号： | CS8415A |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | 96 kHz DIGITAL AUDIO INTERFACE RECEIVER |
| 文件： | 总42页 (文件大小：736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8415A
96 kHz Digital Audio Interface Receiver
Features
General Description
The CS8415A is a monolithic CMOS device which re-
ceives and decodes one of 7 channels of audio data
according to the IEC60958, S/PDIF, EIAJ CP1201, or
AES3. The CS8415A has a serial digital audio output
port and comprehensive control ability through a 4-wire
microcontroller port. Channel status and user data are
assembled in block sized buffers, making read access
easy.
! Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF compatible receiver
! +5 V Analog Supply (VA)
! +3 V to +5 V Digital Interface Supply (VL)
! 7:1 S/PDIF Input MUX
! Flexible 3-wire serial digital output port
! 8 kHz to 96 kHz sample frequency range
! Low jitter clock recovery
! Pin and microcontroller read access to
Channel Status and User data
A low jitter clock recovery mechanism yields a very
clean recovered clock from the incoming AES3 stream.
Stand-alone operation allows systems with no micro-
controller to operate the CS8415A with dedicated output
pins for channel status data.
! Microcontroller and standalone modes
! Differential cable receiver
! On-chip Channel Status and User data buffer
Target applications include A/V receivers, CD-R, DVD
receivers, multimedia speakers, digital mixing consoles,
effects processors, set-top boxes, and computer and
automotive audio systems.
memories
! Auto-detection of compressed audio input
streams
! Decodes CD Q sub-code
! OMCK System Clock Mode
ORDERING INFOMATION
CS8415A-CS 28-pin SOIC
CS8415A-CZ 28-pin TSSOP -10 to +70°C
CS8415A-IS 28-pin SOIC -40 to +85°C
CS8415A-IZ 28-pin TSSOP -40 to +85°C
-10 to +70°C
CDB8415A
Evaluation Board
I
VL+ DGND
OMCK
VA+ AGND FILT
Receiver
RERR RMCK
RXN0
OLRCK
OSCLK
SDOUT
Clock &
Data
Recovery Decoder
AES3
S/PDIF
C & U bit
Data
Buffer
Serial
Audio
Output
RXP6
RXP5
RXP4
RXP3
RXP2
RXP1
RXP0
7:1
MUX
Control
Port &
Registers
Misc.
Control
H/S RST
EMPH U
SDA/
SCL/ AD1/ AD0/ INT
CDOUT CCLK CDIN CS
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Preliminary Product Information
Cirrus Logic, Inc.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2002
JAN ‘03
DS470PP4
(All Rights Reserved)
1
CS8415A
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5
SPECIFIED OPERATING CONDITIONS ................................................................................. 5
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5
DC ELECTRICAL CHARACTERISTICS................................................................................... 6
DIGITAL INPUT CHARACTERISTICS ..................................................................................... 6
DIGITAL INTERFACE SPECIFICATIONS................................................................................ 6
SWITCHING CHARACTERISTICS .......................................................................................... 6
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS................................................. 7
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE...................................... 8
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C MODE...................................... 9
2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 10
3. GENERAL DESCRIPTION ..................................................................................................... 11
3.1 AES3 and S/PDIF Standards Documents ........................................................................ 11
4. SERIAL AUDIO OUTPUT PORT ............................................................................................ 12
5. AES3 RECEIVER .................................................................................................................... 14
5.1 7:1 S/PDIF Input Multiplexer ............................................................................................ 14
5.2 OMCK System Clock Mode ............................................................................................. 14
5.3 PLL, Jitter Attenuation, and Varispeed ............................................................................ 14
5.4 Error Reporting and Hold Function .................................................................................. 14
5.5 Channel Status Data Handling ......................................................................................... 15
5.6 User Data Handling .......................................................................................................... 15
5.7 Non-Audio Auto-Detection ............................................................................................... 15
5.8 Mono Mode Operation ..................................................................................................... 15
6. CONTROL PORT DESCRIPTION AND TIMING .................................................................... 17
6.1 SPI Mode ......................................................................................................................... 17
6.2 I2C Mode ......................................................................................................................... 17
6.3 Interrupts .......................................................................................................................... 18
7. CONTROL PORT REGISTER SUMMARY ............................................................................. 19
7.1 Memory Address Pointer (MAP) ....................................................................................... 19
8. CONTROL PORT REGISTER BIT DEFINITIONS .................................................................. 20
8.1 Control 1(01h)................................................................................................................... 20
8.2 Control 2 (02h).................................................................................................................. 20
8.3 Clock Source Control (04h)............................................................................................... 21
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to <http://www.cirrus.com/corporate/contacts/sales.cfm>
IIMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor-
mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the infor-
mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this
information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus
and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only
for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma-
terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANT-
ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use
those components in a standard I2C system.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
2
CS8415A
8.4 Serial Audio Output Port Data Format (06h) .................................................................... 21
8.5 Interrupt 1 Status (07h) (Read Only) ................................................................................ 22
8.6 Interrupt 2 Status (08h) (Read Only) ................................................................................ 23
8.7 Interrupt 1 Mask (09h) ...................................................................................................... 23
8.8 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB(0Bh).......................................... 23
8.9 Interrupt 2 Mask (0Ch)...................................................................................................... 24
8.10 Interrupt 2 Mode MSB (0Dh) and Interrupt 2 Mode LSB(0Eh) ....................................... 24
8.11 Receiver Channel Status (0Fh) (Read Only).................................................................. 24
8.12 Receiver Error (10h) (Read Only)................................................................................... 25
8.13 Receiver Error Mask (11h) ............................................................................................. 26
8.14 Channel Status Data Buffer Control (12h)...................................................................... 26
8.15 User Data Buffer Control (13h)....................................................................................... 27
8.16 Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only) ........................................... 27
8.17 OMCK/RMCK Ratio (1Eh) (Read Only).......................................................................... 27
8.18 C-bit or U-bit Data Buffer (20h - 37h) ............................................................................. 27
8.19 CS8415A I.D. and Version Register (7Fh) (Read Only)................................................. 27
9. PIN DESCRIPTION - SOFTWARE MODE ............................................................................. 28
10. HARDWARE MODE ............................................................................................................. 30
10.1 Serial Audio Port Formats ............................................................................................. 30
11. PIN DESCRIPTION - HARDWARE MODE .......................................................................... 31
12. APPLICATIONS .................................................................................................................. 33
12.1 Reset, Power Down and Start-up .................................................................................. 33
12.2 ID Code and Revision Code .......................................................................................... 33
12.3 Power Supply, Grounding, and PCB layout ................................................................... 33
13. PACKAGE DIMENSIONS ................................................................................................... 34
14. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS ............. 36
14.1 AES3 Receiver External Components ........................................................................... 36
14.2 Isolating Transformer Requirements ............................................................................. 36
15. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 38
15.1 AES3 Channel Status (C) Bit Management ................................................................... 38
15.2 Accessing the E buffer ................................................................................................... 38
15.2.1 Reserving the first 5 bytes in the E buffer ......................................................... 38
15.2.2 Serial Copy Management System (SCMS) ....................................................... 39
15.2.3 Channel Status Data E Buffer Access .............................................................. 39
15.2.3.1 One Byte mode ................................................................................. 39
15.2.3.2 Two Byte mode ................................................................................. 39
15.3 AES3 User (U) Bit Management .................................................................................... 39
16. APPENDIX C: PLL FILTER .................................................................................................. 40
16.1 General .......................................................................................................................... 40
16.2 External Filter Components ........................................................................................... 41
16.2.1 General ............................................................................................................. 41
16.2.2 Capacitor Selection ........................................................................................... 41
16.2.3 Circuit Board Layout ......................................................................................... 41
16.2.4 Component Value Selection ............................................................................. 42
16.2.5 Jitter Attenuation ............................................................................................... 42
3
CS8415A
LIST OF TABLES
Table 1. Control Register Map Summary...................................................................................... 19
Table 2. Equivalent Software Mode Bit Definitions ....................................................................... 30
Table 3. Hardware Mode Start-up Options.................................................................................... 30
Table 4. External PLL Component Values .................................................................................... 42
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing....................................................................................... 7
Figure 2. Audio Port Slave Mode and Data Input Timing................................................................ 7
Figure 3. SPI Mode Timing.............................................................................................................. 8
Figure 4. I2C Mode timing............................................................................................................... 9
Figure 5. Recommended Connection Diagram for Software Mode............................................... 10
Figure 6. Serial Audio Output Example Formats........................................................................... 13
Figure 7. AES3 Receiver Timing for C & U pin output data .......................................................... 16
Figure 8. Control Port Timing in SPI Mode.................................................................................... 17
Figure 9. Control Port Timing in I2C Mode.................................................................................... 18
Figure 9. Hardware Mode.............................................................................................................. 30
Figure 10. Professional Input Circuit ............................................................................................. 36
Figure 11. Transformerless Professional Input Circuit .................................................................. 36
Figure 12. Consumer Input Circuit ................................................................................................ 37
Figure 13. S/PDIF MUX Input Circuit ............................................................................................ 37
Figure 14. TTL/CMOS Input Circuit............................................................................................... 37
Figure 15. Channel Status Data Buffer Structure.......................................................................... 38
Figure 16. Flowchart for Reading the E Buffer.............................................................................. 38
Figure 17. PLL Block Diagram ...................................................................................................... 40
Figure 18. Recommended Layout Example.................................................................................. 41
Figure 19. Jitter Attenuation Characteristics of PLL with Fs=32 to 96 kHz Filter Components..... 42
4
CS8415A
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per-
formance characteristics and specifications are derived from measurements taken at nominal supply voltages and
T = 25 °C.)
A
SPECIFIED OPERATING CONDITIONS (AGND, DGND = 0 V, all voltages with respect to 0V)
Parameter
Symbol
Min
Typ
Max
Units
Power Supply Voltage
VA+
VL+
4.5
2.85
5.0
3.3 or 5.0
5.5
5.5
V
V
(Note 1)
Ambient Operating Temperature:
‘-CS’ & ‘-CZ’
‘-IS’ & ‘-IZ’
T
-10
-40
-
-
+70
+85
°C
A
2
Notes: 1. I C protocol is supported only in 5V mode.
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; all voltages with respect to 0V. Operation
beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these
extremes.)
Parameter
Symbol
Min
-
Max
6.0
Units
V
Power Supply Voltage
VL+,VA+
Input Current, Any Pin Except Supplies
Input Voltage
(Note 2)
I
-
±10
mA
V
in
V
-0.3
-55
-65
(VL+) + 0.3
125
in
Ambient Operating Temperature (power applied)
Storage Temperature
T
°C
A
T
150
°C
stg
Notes: 2. Transient currents of up to 100mA will not cause SCR latch-up.
5
CS8415A
DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V; all voltages with respect to 0 V.)
Parameters
Symbol
Min
Typ
Max
Units
Power-down Mode (Note 3)
Supply Current in power down
VA+
VL+ = 3 V
VL+ = 5 V
-
-
-
20
60
60
-
-
-
µA
µA
µA
Normal Operation (Note 4)
Supply Current at 48 kHz frame rate
VA+
VL+ = 3 V
VL+ = 5 V
-
-
-
6.3
30.1
46.5
-
-
-
mA
mA
mA
Supply Current at 96 kHz frame rate
VA+
VL+ = 3 V
VL+ = 5 V
-
-
-
6.6
44.8
76.6
-
-
-
mA
mA
mA
Notes: 3. Power Down Mode is defined as RST = LO with all clocks and data lines held static.
4. Normal operation is defined as RST = HI.
DIGITAL INPUT CHARACTERISTICS
Parameters
Symbol
Min
Typ
±1
Max
±10
-
Units
µA
Input Leakage Current
Differential Input Voltage, RXP0 to RXN0
I
-
-
in
V
200
mV
TH
DIGITAL INTERFACE SPECIFICATIONS (AGND = DGND = 0 V; all voltages with respect to 0 V.)
Parameters
Symbol
Min
Max
Units
High-Level Output Voltage (I = -3.2 mA)
V
(VL+) - 1.0
-
V
OH
OH
Low-Level Output Voltage (I = 3.2 mA)
V
-
0.4
V
V
V
OH
OL
High-Level Input Voltage, except RX
V
2.0
-0.3
(VL+) + 0.3
0.4/0.8
n
IH
Low-Level Input Voltage, except RX
(Note 5)
V
IL
n
Notes: 5. At 5V mode, V = 0.8V (Max), at 3V mode, V =0.4V (Max).
IL
IL
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = 0V, Logic 1 = VL+; C = 20 pF)
L
Parameter
RST pin Low Pulse Width
Symbol
Min
200
8.0
-
Typ
Max
-
Units
µs
-
-
PLL Clock Recovery Sample Rate Range
RMCK output jitter
108.0
kHz
200
50
-
ps RMS
%
RMCK output duty cycle
(Note 6)
40
60
Notes: 6. Cycle-to-cycle using 32-96kHz external PLL filter components.
6
CS8415A
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL+; C = 20 pF)
L
Parameter
OSCLK Active Edge to SDOUT Output Valid
Master Mode
Symbol
Min
Typ
Max
Units
(Note 7)
t
-
-
20
ns
dpd
RMCK to OSCLK active edge delay
RMCK to OLRCK delay
(Note 7)
(Note 8)
t
0
0
-
-
-
10
10
-
ns
ns
%
smd
t
lmd
OSCLK and OLRCK Duty Cycle
Slave Mode
50
OSCLK Period
(Note 9)
t
36
14
14
20
20
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
sckw
OSCLK Input Low Width
OSCLK Input High Width
t
sckl
t
sckh
lrckd
OSCLK Active Edge to OLRCK Edge
(Note 7,8,10)
t
OLRCK Edge Setup Before OSCLK Active Edge
(Note
t
lrcks
7,8,11)
Notes: 7. The active edges of OSCLK are programmable.
8. The polarity OLRCK is programmable.
9. No more than 128 SCLK per frame.
10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK
has changed.
11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.
OSCLK
OLRCK
(input)
(output)
t
t
t
sckh
t
lrckd
lrcks
sckl
OLRCK
(output)
OSCLK
(input)
t
smd
t
lmd
t
sckw
RMCK
(output)
t
dpd
Hardware Mode
Software Mode
RMCK
(output)
SDOUT
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input Timing
7
CS8415A
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL+; C = 20 pF)
L
Parameter
CCLK Clock Frequency
Symbol
Min
0
Typ
Max
Units
MHz
µs
(Note 12)
f
t
-
-
-
-
-
-
-
-
-
-
-
-
6.0
-
sck
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
1.0
20
66
66
40
15
-
csh
t
-
ns
css
t
-
ns
scl
sch
dsu
CCLK High Time
t
-
ns
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
t
-
ns
(Note 13)
t
-
ns
dh
t
50
25
25
100
100
ns
pd
t
-
ns
r1
Fall Time of CDOUT
t
-
ns
f1
r2
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 14)
(Note 14)
t
-
ns
t
-
ns
f2
Notes: 12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum
allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should
be safe for all possible conditions.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For f <1 MHz.
sck
CS
t
t
scl
sch
t
t
csh
css
CCLK
t
t
r2
f2
CDIN
t
dsu
t
dh
t
pd
CDOUT
Figure 3. SPI Mode Timing
8
CS8415A
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C MODE
(Note 15, Inputs: Logic 0 = 0 V, Logic 1 = VL+; C = 20 pF)
L
Parameter
SCL Clock Frequency
Symbol
Min
-
Typ
Max
Units
kHz
µs
f
t
-
-
-
-
-
-
-
-
-
-
-
100
scl
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
4.7
4.0
4.7
4.0
4.7
0
-
-
buf
t
µs
hdst
t
-
µs
low
Clock High Time
t
-
µs
high
Setup Time for Repeated Start Condition
t
-
µs
sust
SDA Hold Time from SCL Falling
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
(Note 16)
t
-
µs
hdd
t
250
-
-
ns
sud
t
25
25
-
ns
r
t
-
ns
f
t
4.7
µs
susp
2
Notes: 15. I C protocol is supported only in 5V mode.
16. Data must be held for sufficient time to bridge the 25 ns transition time of SCL.
Repeated
Start
Stop
t
Start
Stop
SDA
SCL
t
t
t
t
buf
t
high
hdst
f
susp
hdst
t
t
t
t
t
sust
sud
r
hdd
low
Figure 4. I2C Mode timing
9
CS8415A
2. TYPICAL CONNECTION DIAGRAM
Ferrite *
Bead
+3.3V or +5V
Digital
+5V
Analog
Supply *
0.1µF
Supply
0.1µF
VA+
VL+
CS8415A
RXP6
RXP5
RXP4
RXP3
RXP2
RXP1
RXP0
RXN0
OLRCK
OSCLK
SDOUT
3-wire Serial
Audio Input
Device
**
AES3/
SPDIF
Sources
SDA/CDOUT
AD0/CS
SCL/CCLK
AD1/CDIN
INT
Clock Control
RMCK
Microcontroller
U
EMPH
RERR
/AD2
DGND2
Hardware
Control
H/S
RST
AGND FILT
DGND
RFILT
CFILT
CRIP
* A separate analog supply is only necessary in applications where RMCK is used
for a jitter sensitive task. For applications where RMCK is not used for a jitter
sensitive task, connect VA+ to VD+ via a ferrite bead. Keep the decoupling
capacitor between VA+ and AGND.
Please see section 5.1 "7:1 S/PDIF Input Multiplexer" and Appendix A for typical
input configurations and recommended input circuits.
**
Figure 5. Recommended Connection Diagram for Software Mode
10
CS8415A
3. GENERAL DESCRIPTION
3.1
AES3 and S/PDIF Standards
Documents
The CS8415A is a monolithic CMOS device which
receives and decodes audio data according to the
AES3, IEC60958, S/PDIF, and EIAJ CP1201 inter-
face standards.
This data sheet assumes that the user is familiar
with the AES3 and S/PDIF data formats. It is advis-
able to have current copies of the AES3 and
IEC60958 specifications on hand for easy refer-
ence.
Input data is either differential or single-ended. A
low jitter clock is recovered from the incoming data
using a PLL. The decoded audio data is output
through a configurable, 3-wire output port. The
channel status and user data are assembled in
block sized buffers and may be accessed through
an SPI or I2C microcontroller port. For systems
with no microcontroller, a stand alone mode allows
direct access to channel status and user data out-
put pins.
The latest AES3 standard is available from the Au-
dio Engineering Society or ANSI at www.aes.org or
www.ansi.org. Obtain the latest IEC60958 stan-
dard from ANSI or from the International Electro-
technical Commission at www.iec.ch. The latest
EIAJ CP-1201 standard is available from the Jap-
anese Electronics Bureau.
Cirrus Logic Application Note 22: Overview of Dig-
ital Audio Interface Data Structures contains a use-
ful tutorial on digital audio specifications, but it
should not be considered a substitute for the stan-
dards.
Target applications include AVR, CD-R, DAT,
DVD, multimedia speakers, MD and VTR equip-
ment, mixing consoles, digital audio transmission
and receiving equipment, high quality D/A and A/D
converters, effects processors, set-top TV boxes,
and computer audio systems.
The paper An Understanding and Implementation
of the SCMS Serial Copy Management System for
Digital Audio Transmission, by Clifton Sanchez, is
an excellent tutorial on SCMS. It is available from
the AES as preprint 3518.
Figure 5 shows the supply and external connec-
tions to the CS8415A, when configured for opera-
tion with a microcontroller.
11
CS8415A
tus block start signal is only available in hardware
mode, as the RCBL pin.
4. SERIAL AUDIO OUTPUT PORT
A 3-wire serial audio output port is provided. The
port can be adjusted to suit the attached device
setting the control registers. The following param-
eters are adjustable: master or slave, serial clock
frequency, audio data resolution, left or right justifi-
cation of the data relative to left/right clock, option-
al one-bit cell delay of the first data bit, the polarity
of the bit clock and the polarity of the left/right
clock. By setting the appropriate control bits, many
formats are possible.
In master mode, the left/right clock and the serial
bit clock are outputs, derived from the recovered
RMCK clock. In slave mode, the left/right clock and
the serial bit clock are inputs. The left/right clock
must be synchronous to the appropriate master
clock, but the serial bit clock can be asynchronous
and discontinuous if required. By appropriate
phasing of the left/right clock and control of the se-
rial clocks, multiple CS8415A’s can share one se-
rial port. The left/right clock should be continuous,
but the duty cycle can be less than the specified
typical value of 50% if enough serial clocks are
present in each phase to clock all the data bits.
When in slave mode, the serial audio output port
must not be set for right-justified data. When using
the serial audio output port in slave mode with an
OLRCK input which is asynchronous to the incom-
ing AES3 data, then an interrupt bit(OSLIP) is pro-
vided to indicate when repeated or dropped
samples occur.The CS8415A allows immediate
mute of the serial audio output port audio data by
the MUTESAO bit of Control Register 1.
Figure 6 shows a selection of common output for-
mats, along with the control bit settings. It should
be noted that in right justified mode, the serial au-
dio output data is "MSB extended". This means
that in a sub-frame where the MSB of the data is
'1', all bits preceding the MSB in the sub-frame will
also be '1'. Conversely, in a sub-frame where the
MSB of the data is '0', all bits preceding the MSB in
the sub-frame will also be '0'.
A special AES3 direct output format is included,
which allows the serial output port access to the V,
U, and C bits embedded in the serial audio data
stream. The P bit is replaced by a Z bit that marks
the start of each block. The received channel sta-
12
CS8415A
Right
OLRCK
OSCLK
SDOUT
Left
Left
Justified
(Out)
MSB
LSB
MSB
LSB
MSB
Left
Right
MSB
OLRCK
OSCLK
SDOUT
I2 S
(Out)
LSB
MSB
LSB
MSB
Right
OLRCK
Left
Right
Justified
(Out)
OSCLK
SDOUT
MSB Ex
MSB Extended
MSB Extended
LSB
MSB
LSB
MSB
LSB
Right
OLRCK
OSCLK
SDOUT
Left
AES3
Direct
(Out)
LSB
MSB
V
U
C
Z
MSB
V
U
C
Z
LSB
LSB
SOMS*
SOSF*
SORES[1:0]* SOJUST*
SODEL* SOSPOL* SOLRPOL*
Left Justified
X
X
X
X
XX
XX
0
0
0
1
0
0
0
1
2
I S
Right Justified
AES3 Direct
1
X
X
XX
11
1
0
0
0
0
0
0
0
X
X = don’t care to match format, but does need to be set to the desired setting
* See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 6. Serial Audio Output Example Formats
13
CS8415A
note that internal circuitry associated with RMCK is
not driven by OMCK. This means that OSCLK and
OLRCK continue to be derived from the PLL and
are not usable in this mode. This function is avail-
able only in software mode.
5. AES3 RECEIVER
The CS8415A includes an AES3 digital audio re-
ceiver. A comprehensive buffering scheme pro-
vides read access to the channel status and user
data. This buffering scheme is described in Appen-
dix B.
5.3
PLL, Jitter Attenuation, and
Varispeed
The AES3 receiver accepts and decodes audio
and digital data according to the AES3, IEC60958
(S/PDIF), and EIAJ CP-1201 interface standards.
The receiver consists of a differential input stage,
driven through pins RXP0 and RXN0, a PLL based
clock recovery circuit, and a decoder which sepa-
rates the audio data from the channel status and
user data.
Please see Appendix C for general description of
the PLL, selection of recommended PLL filter com-
ponents, and layout considerations. Figure 5
shows the recommended configuration of the two
capacitors and one resistor that comprise the PLL
filter.
5.4
Error Reporting and Hold Function
External components are used to terminate and
isolate the incoming data cables from the
CS8415A. These components are detailed in Ap-
pendix A.
While decoding the incoming AES3 data stream,
the CS8415A can identify several kinds of error, in-
dicated in the Receiver Error register. The UN-
LOCK bit indicates whether the PLL is locked to
the incoming AES3 data. The V bit reflects the cur-
rent validity bit status. The CONF (confidence) bit
is the logical OR of BIP and UNLOCK. The BIP (bi-
phase) error bit indicates an error in incoming bi-
phase coding. The PAR (parity) bit indicates a re-
ceived parity error.
5.1
7:1 S/PDIF Input Multiplexer
The CS8415A employs a 7:1 S/PDIF Input Multi-
plexer to accommodate up to seven channels of in-
put digital audio data. Digital audio data is single-
ended and input through the RXP0-6 pins. When
any portion of the multiplexer is implemented, un-
used RXP pins should be tied to ground, and
RXN0 must be ac-coupled to ground. The multi-
plexer select line control is accessed through bits
MUX2:0 in the Control 2 register. The multiplexer
defaults to RXP0. Therefore, the default configura-
tion is for a differential signal to be input through
RXP0 & RXN0. Please see Appendix A for recom-
mended input circuits.
The error bits are "sticky": they are set on the first
occurrence of the associated error and will remain
set until the user reads the register through the
control port. This enables the register to log all un-
masked errors that occurred since the last time the
register was read.
The Receiver Error Mask register allows masking
of individual errors. The bits in this register serve
as masks for the corresponding bits of the Receiv-
er Error Register. If a mask bit is set to 1, the error
is unmasked, which implies the following: its occur-
rence will be reported in the receiver error register,
induce a pulse on RERR, invoke the occurrence of
a RERR interrupt, and affect the current audio
sample according to the status of the HOLD bits.
The HOLD bits allow a choice of holding the previ-
ous sample, replacing the current sample with zero
(mute), or not changing the current audio sample.
If a mask bit is set to 0, the error is masked, which
implies the following: its occurrence will not be re-
ported in the receiver error register, will not induce
a pulse on RERR or generate a RERR interrupt,
and will not affect the current audio sample. The
5.2
OMCK System Clock Mode
A special clock switching mode is available that al-
lows the clock that is input through the OMCK pin
to be output through the RMCK pin. This feature is
controlled by the SWCLK bit in register 1 of the
control registers. When the PLL loses lock, the fre-
quency of the VCO drops to 300 kHz. The clock
switching mode allows the clock input through
OMCK to be used as a clock in the system without
any disruption when the PLL loses lock, for exam-
ple, when the input is removed from the receiver.
When SWCLK is enabled and this mode is imple-
mented, RMCK is an output and is not bi-direction-
al. This clock switching is done glitch free. Please
14
CS8415A
QCRC and CCRC errors do not affect the current
audio sample, even if unmasked.
5.7
Non-Audio Auto-Detection
An AES3 data stream may be used to convey non-
audio data, thus it is important to know whether the
incoming AES3 data stream is digital audio or not.
This information is typically conveyed in channel
status bit 1 (AUDIO), which is extracted automati-
cally by the CS8415A. However, certain non-audio
sources, such as AC-3 or MPEG encoders, may
not adhere to this convention, and the bit may not
be properly set. The CS8415A AES3 receiver can
detect such non-audio data. This is accomplished
by looking for a 96-bit sync code, consisting of
0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and
0x4E1F. When the sync code is detected, an inter-
nal AUTODETECT signal will be asserted. If no ad-
ditional sync codes are detected within the next
4096 frames, AUTODETECT will be de-asserted
until another sync code is detected. The AUDIO bit
in the Receiver Channel Status register is the logi-
cal OR of AUTODETECT and the received chan-
nel status bit 1. If non-audio data is detected, the
data is still processed exactly as if it were normal
audio. It is up to the user to mute the outputs as re-
quired.
5.5
Channel Status Data Handling
The first 2 bytes of the Channel Status block are
decoded into the Receiver Channel Status regis-
ter. The setting of the CHS bit in the Channel Sta-
tus Data Buffer Control register determines
whether the channel status decodes are from the A
channel (CHS = 0) or B channel (CHS = 1).
The PRO (professional) bit is extracted directly.
For consumer data, the COPY (copyright) bit is ex-
tracted, and the category code and L bits are de-
coded to determine SCMS status, indicated by the
ORIG (original) bit. If the category code is set to
General on the incoming AES3 stream, copyright
will always be indicated even when the stream in-
dicates no copyright. Finally, the AUDIO bit is ex-
tracted and used to set an AUDIO indicator, as
described in the Non-Audio Auto-Detection section
below.
If 50/15 µs pre-emphasis is detected, the state of
the EMPH pin is adjusted accordingly.
The encoded channel status bits which indicate
sample word length are decoded according to
AES3-1992 or IEC 60958. Audio data routed to the
serial audio output port is unaffected by the word
length settings; all 24 bits are passed on as re-
ceived.
5.8
Mono Mode Operation
An AES3 stream may be used in more than one
way to transmit 96 kHz sample rate data. One
method is to double the frame rate of the current
format. This results in a stereo signal with a sample
rate of 96 kHz, carried over a single twisted pair
cable. An alternate method is implemented using
the 2 sub-frames in a 48 kHz frame rate AES3 sig-
nal to carry consecutive samples of a mono signal,
resulting in a 96 kHz sample rate stream. This al-
lows older equipment, whose AES3 transmitters
and receivers are not rated for 96 kHz frame rate
operation, to handle 96 kHz sample rate informa-
tion. In this “mono mode”, 2 AES3 cables are need-
ed for stereo data transfer. The CS8415A offers
mono mode operation, controlled through the
MMR control register bit.
Appendix A describes the overall handling of
Channel Status and User data.
5.6
User Data Handling
The incoming user data is buffered in a user acces-
sible buffer. Received User data may also be out-
put to the U pin under the control of a control
register bit. Depending on the clocking options se-
lected, there may not be a clock available to qualify
the U data output. Figure 7 illustrates the timing. If
the incoming user data bits have been encoded as
Q-channel subcode, the data is decoded and pre-
sented in 10 consecutive register locations. An in-
terrupt may be enabled to indicate the decoding of
a new Q-channel block, which may be read
through the control port.
The receiver mono mode effectively doubles Fs
compared to the input frame rate. The clock output
on the RMCK pin tracks Fs, and so is doubled in
frequency compared to stereo mode. The receiver
will run at a frame rate of Fs/2, and the serial audio
output port will run at Fs. Sub-frame A data will be
15
CS8415A
routed to both the left and right data fields on SD-
OUT. Similarly, sub-frame B data will be routed to
both the left and right data fields of the next word
clock cycle of SDOUT.
CS8415A is kept in normal stereo mode, and re-
ceives AES3 data arranged in mono mode, then
the serial audio output port will run at 48 kHz, with
left and right data fields representing consecutive
audio samples.
Using mono mode is only necessary if the serial
audio output port must run at 96 kHz. If the
RCBL
Out
VLRCK
C, U
Ouput
RCBL and C output are only available in hardware mode.
RCBL goes high 2 frames after receipt of a Z pre-amble, and is high for 16 frames.
VLRCK is a virtual word clock, which may not exist, but is used to illustrate the CU timing.
VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.
If the serial audio output port is in master mode, VLRCK = OLRCK.
If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required.
C, U transitions are aligned within ±1% of VLRCK period to VLRCK edges
Figure 7. AES3 Receiver Timing for C & U pin output data
16
CS8415A
must be 0010000. The eighth bit is a read/write in-
dicator (R/W), which should be low to write. The
next eight bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next eight bits are the
data which will be placed into the register designat-
ed by the MAP. During writes, the CDOUT output
stays in the Hi-Z state. It may be externally pulled
high or low with a 47 KΩ resistor, if desired.
6. CONTROL PORT DESCRIPTION AND
TIMING
The control port is used to access the registers, al-
lowing the CS8415A to be configured for the de-
sired operational modes and formats. In addition,
Channel Status and User data may be read
through the control port. The operation of the con-
trol port may be completely asynchronous with re-
spect to the audio sample rates. However, to avoid
potential interference problems, the control port
pins should remain static if no operation is re-
quired.
The control port has 2 modes: SPI and I2C, with the
CS8415A acting as a slave device. SPI mode is
selected if there is a high to low transition on the
AD0/CS pin, after the RST pin has been brought
high. I2C mode is selected by connecting the
AD0/CS pin to VL+ or DGND, thereby permanently
selecting the desired AD0 bit address state.
There is a MAP auto increment capability, enabled
by the INCR bit in the MAP register. If INCR is a ze-
ro, the MAP will stay constant for successive read
or writes. If INCR is set to a 1, the MAP will autoin-
crement after each byte is read or written, allowing
block reads or writes of successive registers.
To read a register, the MAP has to be set to the
correct address by executing a partial write cycle
which finishes (CS high) immediately after the
MAP byte. The MAP auto increment bit (INCR)
may be set or not, as desired. To begin a read,
bring CS low, send out the chip address and set
the read/write bit (R/W) high. The next falling edge
of CCLK will clock out the MSB of the addressed
register (CDOUT will leave the high impedance
state). If the MAP auto increment bit is set to 1, the
data for successive registers will appear consecu-
tively.
6.1
SPI Mode
In SPI mode, CS is the CS8415A chip select sig-
nal, CCLK is the control port bit clock (input into the
CS8415A from the microcontroller), CDIN is the in-
put data line from the microcontroller, CDOUT is
the output data line to the microcontroller. Data is
clocked in on the rising edge of CCLK and out on
the falling edge.
2
6.2
I C Mode
Figure 8 shows the operation of the control port in
SPI mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and
In I2C mode, SDA is a bidirectional data line. Data
is clocked into and out of the part by the clock,
CS
C C LK
C H IP
C H IP
M A P
DATA
A D D R E S S
ADDRESS
0010000
0010000
R/W
LSB
MSB
byte 1
R/W
C D IN
byte n
High Impedance
LSB
LSB
MSB
MSB
C D O U T
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 8. Control Port Timing in SPI Mode
17
CS8415A
SCL, with the clock to data relationship as shown
in Figure 9. There is no CS pin. Each individual
CS8415A is given a unique address. Pins AD0 and
AD1 form the two least significant bits of the chip
address and should be connected to VL+ or DGND
as desired. The EMPH pin is used to set the AD2
bit by connecting a resistor from the EMPH pin to
VL+ or to DGND. The state of the pin is sensed
while the CS8415A is being reset. The upper 4 bits
of the 7-bit address field are fixed at 0010. To com-
municate with a CS8415A, the chip address field,
which is the first byte sent to the CS8415A, should
match 0010 followed by the settings of the EMPH,
AD1, and AD0. The eighth bit of the address is the
R/W bit. If the operation is a write, the next byte is
the Memory Address Pointer (MAP) which selects
the register to be read or written. If the operation is
a read, the contents of the register pointed to by
the MAP will be output. Setting the auto increment
bit in MAP allows successive reads or writes of
consecutive registers. Each byte is separated by
an acknowledge bit. The ACK bit is output from the
CS8415A after each input byte is read, and is input
to the CS8415A from the microcontroller after each
transmitted byte. I2C mode is supported only with
VL+ in 5V mode.
6.3
Interrupts
The CS8415A has a comprehensive interrupt ca-
pability. The INT output pin is intended to drive the
interrupt input pin on the host microcontroller. The
INT pin may be set to be active low, active high or
active low with no active pull-up transistor. This last
mode is used for active low, wired-OR hook-ups,
with multiple peripherals connected to the micro-
controller interrupt input pin.
Many conditions can cause an interrupt, as listed in
the interrupt status register descriptions. Each
source may be masked off through mask register
bits. In addition, each source may be set to rising
edge, falling edge, or level sensitive. Combined
with the option of level sensitive or edge sensitive
modes within the microcontroller, many different
configurations are possible, depending on the
needs of the equipment designer.
Note 1
Note 2
Note 3
ACK
0010
AD2-0
DATA7-0
R/W ACK DATA7-0 ACK
SDA
SCL
Start
Stop
Figure 9. Control Port Timing in I2C Mode
Notes: 1. AD2 is derived from a resistor attached to the EMPH pin.
AD1 and AD0 are determined by the state of the corresponding pins.
2. If operation is a write, this byte contains the Memory Address Pointer, MAP.
3. If operation is a read, the last bit of the read should be NACK (high).
18
CS8415A
7. CONTROL PORT REGISTER SUMMARY
Addr
Function
7
6
5
4
3
2
1
0
(HEX)
01
02
Control 1
SWCLK
0
HOLD1
RUN
SOSF
OSLIP
0
MUTESAO
0
0
MMR
0
INT1
MUX2
0
INT0
MUX1
0
0
MUX0
1
Control 2
0
HOLD0
RMCKF
04
Clock Source Control
Serial Output Format
Interrupt 1 Status
0
0
0
06
SOMS
SORES1
SORES0
SOJUST
0
SODEL SOSPOL SOLRPOL
07
0
0
0
DETC
0
RERR
0
08
Interrupt 2 Status
0
0
0
DETU
0
0
DETCM
DETC1
DETC0
0
QCH
0
09
Interrupt 1 Mask
0
OSLIPM
OSLIP1
OSLIP0
0
0
0
RERRM
RERR1
RERR0
0
0A
0B
0C
0D
0E
0F
10
Interrupt 1 Mode (MSB)
Interrupt 1 Mode (LSB)
Interrupt 2 Mask
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DETUM
DETU1
DETU0
PRO
V
QCHM
QCH1
QCH0
COPY
BIP
Interrupt 2 Mode (MSB)
Interrupt 2 Mode (LSB)
Receiver CS Data
Receiver Errors
0
0
0
0
0
0
0
0
0
0
0
AUX3
AUX2
QCRC
QCRCM
0
AUX1
CCRC
CCRCM
BSEL
0
AUX0
UNLOCK
UNLOCKM
CBMR
0
AUDIO
CONF
CONFM
0
ORIG
PAR
PARM
CHS
0
0
0
0
0
11
Receiver Error Mask
CS Data Buffer Control
U Data Buffer Control
Q sub-code Data
VM
BIPM
CAM
DETUI
12
DETCI
0
13
0
0
14-1D
1E
OMCK/RMCK Ratio
C or U Data Buffer
ORR7
ID3
ORR6
ID2
ORR5
ID1
ORR4
ID0
ORR3
VER3
ORR2
VER2
ORR1
VER1
ORR0
VER0
20-37
7F
ID and Version
Table 1. Control Register Map Summary
7.1
Memory Address Pointer (MAP)
7
6
5
4
3
2
1
0
INCR
MAP6
MAP5
MAP4
MAP3
MAP2
MAP1
MAP0
INCR - Auto Increment Address Control Bit
Default = ‘0’
0 - Disabled
1 - Enabled
MAP6:MAP0 - Register address
Note: Reserved registers must not be written to during normal operation. Some reserved registers are used for
test modes, which can completely alter the normal operation of the CS8415A.
19
CS8415A
8. CONTROL PORT REGISTER BIT DEFINITIONS
8.1
Control 1(01h)
7
6
5
4
3
2
1
0
SWCLK
0
MUTESAO
0
0
INT1
INT0
0
SWCLK - Controls output of OMCK on RMCK when PLL loses lock
Default = ‘0’
0 - RMCK default function
1 - OMCK output on RMCK pin
MUTESAO - Mute control for the serial audio output port
Default = ‘0’
0 - Disabled
1 - Enabled
INT1:0 - Interrupt output pin (INT) control
Default = ‘00’
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
8.2
Control 2 (02h)
7
6
5
4
3
2
1
0
0
HOLD1
HOLD0
RMCKF
MMR
MUX2
MUX1
MUX0
HOLD1:0 - Determine how received audio sample is affected when a receiver error occurs
Default = ‘00’
00 - Hold the last valid audio sample
01 - Replace the current audio sample with 00 (mute)
10 - Do not change the received audio sample
11 - Reserved
RMCKF - Select recovered master clock output pin frequency.
Default = ‘0’
0 - RMCK is equal to 256 * Fs
1 - RMCK is equal to 128 * Fs
MMR - Select AES3 receiver mono or stereo operation
Default = ‘0’
0 - Normal stereo operation
1 - A and B subframes treated as consecutive samples of one channel of data.
Data is duplicated to both left and right parallel outputs of the AES receiver block.
The sample rate (Fs) is doubled compared to MMR=0
20
CS8415A
MUX2:0 - 7:1 S/PDIF Input Multiplexer Select Line Control
Default = ‘000’
000 - RXP0
001 - RXP1
010 - RXP2
011 - RXP3
100 - RXP4
101 - RXP5
110 - RXP6
111 - Reserved
8.3
Clock Source Control (04h)
7
6
5
4
3
2
1
0
0
RUN
0
0
0
0
0
0
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var-
ious Receiver/Transmitter/Transceiver modes may be selected.
RUN - Controls the internal clocks, allowing the CS8415A to be placed in a “powered down”, low
current consumption, state.
Default = ‘0’
0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port is
operational, allowing registers to be read or changed. Reading and writing the U and C data
buffers is not possible. Power consumption is low.
1 - Normal part operation. This bit must be written to the 1 state to allow the CS8415A to begin
operation. All input clocks should be stable in frequency and phase when RUN is set to 1.
8.4
Serial Audio Output Port Data Format (06h)
7
6
5
4
3
2
1
0
SOMS
SOSF
SORES1
SORES0
SOJUST
SODEL
SOSPOL
SOLRPOL
SOMS - Master/Slave Mode Selector
Default = ‘0’
0 - Serial audio output port is in slave mode
1 - Serial audio output port is in master mode
SOSF - OSCLK frequency (for master mode)
Default = ‘0’
0 - 64*Fs
1 - 128*Fs
SORES1:0 - Resolution of the output data on SDOUT
Default = ‘00’
00 - 24-bit resolution
01 - 20-bit resolution
10 - 16-bit resolution
11 - Direct copy of the received NRZ data from the AES3 receiver (including C, U, and V bits,
the time slot normally occupied by the P bit is used to indicate the location of the block start,
21
CS8415A
SDOUT pin only, serial audio output port clock must be derived from the AES3 receiver recov-
ered clock)
SOJUST - Justification of SDOUT data relative to OLRCK
Default = ‘0’
0 - Left-justified
1 - Right-justified (master mode only)
SODEL - Delay of SDOUT data relative to OLRCK, for left-justified data formats
Default = ‘0’
0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge
1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge
SOSPOL - OSCLK clock polarity
Default = ‘0’
0 - SDOUT sampled on rising edges of OSCLK
1 - SDOUT sampled on falling edges of OSCLK
SOLRPOL - OLRCK clock polarity
Default = ‘0’
0 - SDOUT data is for the left channel when OLRCK is high
1 - SDOUT data is for the right channel when OLRCK is high
8.5
Interrupt 1 Status (07h) (Read Only)
7
6
5
4
3
2
1
0
0
OSLIP
0
0
0
DETC
0
RERR
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register
was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true.
Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults
to 00h.
OSLIP - Serial audio output port data slip interrupt
When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port
data source, This bit will go high every time a data sample is dropped or repeated.
DETC - D to E C-buffer transfer interrupt.
The source for this bit is true during the D to E buffer transfer in the C bit buffer management
process.
RERR - A receiver error has occurred.
The Receiver Error register may be read to determine the nature of the error which caused the
interrupt.
22
CS8415A
8.6
Interrupt 2 Status (08h) (Read Only)
7
6
5
4
3
2
1
0
0
0
0
0
DETU
0
QCH
0
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register
was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true.
Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults
to 00h.
DETU - D to E U-buffer transfer interrupt. (Block Mode only)
The source of this bit is true during the D to E buffer transfer in the U bit buffer management
process.
QCH - A new block of Q-subcode data is available for reading.
The data must be completely read within 588 AES3 frames after the interrupt occurs to avoid
corruption of the data by the next block.
8.7
Interrupt 1 Mask (09h)
7
6
5
4
3
2
1
0
0
OSLIPM
0
0
0
DETCM
0
RERRM
The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is unmasked,
meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked,
meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre-
sponding bits in Interrupt 1 register. This register defaults to 00h.
8.8
Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB(0Bh)
7
0
0
6
5
0
0
4
0
0
3
0
0
2
1
0
0
0
OSLIP1
OSLIP0
DETC1
DETC0
RERR1
RERR0
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to
set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be-
comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active
on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in-
terrupt condition. Be aware that the active level(Actice High or Low) only depends on the INT[1:0] bits. These regis-
ters default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
8.9
Interrupt 2 Mask (0Ch)
7
6
5
4
3
2
1
0
0
0
0
0
DETUM
0
QCHM
0
The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is unmasked,
meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked,
meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre-
23
CS8415A
sponding bits in Interrupt 2 register. This register defaults to 00h.
8.10 Interrupt 2 Mode MSB (0Dh) and Interrupt 2 Mode LSB(0Eh)
7
0
0
6
0
0
5
0
0
4
0
0
3
2
0
0
1
0
0
0
DETU1
DETU0
QCH1
QCH0
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to
set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be-
comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active
on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in-
terrupt condition. Be aware that the active level(Actice High or Low) only depends on the INT[1:0] bits. These regis-
ters default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
8.11 Receiver Channel Status (0Fh) (Read Only)
7
6
5
4
3
2
1
0
AUX3
AUX2
AUX1
AUX0
PRO
AUDIO
COPY
ORIG
The bits in this register can be associated with either channel A or B of the received data. The desired channel is
selected with the CHS bit of the Channel Status Data Buffer Control Register.
AUX3:0 - Incoming auxiliary data field width, as indicated by the incoming channel status bits, de-
coded according to IEC60958 and AES3.
0000 - Auxiliary data is not present
0001 - Auxiliary data is 1 bit long
0010 - Auxiliary data is 2 bits long
0011 - Auxiliary data is 3 bits long
0100 - Auxiliary data is 4 bits long
0101 - Auxiliary data is 5 bits long
0110 - Auxiliary data is 6 bits long
0111 - Auxiliary data is 7 bits long
1000 - Auxiliary data is 8 bits long
1001 - 1111 Reserved
PRO - Channel status block format indicator
0 - Received channel status block is in consumer format
1 - Received channel status block is in professional format
AUDIO - Audio indicator
0 - Received data is linearly coded PCM audio
1 - Received data is not linearly coded PCM audio
COPY - SCMS copyright indicator
0 - Copyright asserted
1 - Copyright not asserted
If the category code is set to General in the incoming AES3 stream, copyright will always be indicated by COPY,
even when the stream indicates no copyright.
24
CS8415A
ORIG - SCMS generation indicator, decoded from the category code and the L bit.
0 - Received data is 1st generation or higher
1 - Received data is original
Note: COPY and ORIG will both be set to 1 if the incoming data is flagged as professional, or if the receiver is not
in use.
8.12 Receiver Error (10h) (Read Only)
7
6
5
4
3
2
1
0
0
QCRC
CCRC
UNLOCK
V
CONF
BIP
PAR
This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occurrence of the error,
and will stay high until the register is read. Reading the register resets all bits to 0, unless the error source is still
true. Bits that are masked off in the receiver error mask register will always be 0 in this register. This register defaults
to 00h.
QCRC - Q-subcode data CRC error indicator. Updated on Q-subcode block boundaries
0 - No error
1 - Error
CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries,
valid in Pro mode
0 - No error
1 - Error
UNLOCK - PLL lock status bit. Updated on CS block boundaries.
0 - PLL locked
1 - PLL out of lock
V - Received AES3 Validity bit status. Updated on sub-frame boundaries.
0 - Data is valid and is normally linear coded PCM audio
1 - Data is invalid, or may be valid compressed audio
CONF - Confidence bit. Updated on sub-frame boundaries.
0 - No error
1 - Confidence error. This is the logical OR of BIP and UNLOCK.
BIP - Bi-phase error bit. Updated on sub-frame boundaries.
0 - No error
1 - Bi-phase error. This indicates an error in the received bi-phase coding.
PAR - Parity bit. Updated on sub-frame boundaries.
0 - No error
1 - Parity error
8.13 Receiver Error Mask (11h)
7
6
5
4
3
2
1
0
0
QCRCM
CCRCM
UNLOCKM
VM
CONFM
BIPM
PARM
The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a mask bit is set
to 1, the error is unmasked, meaning that its occurrence will appear in the receiver error register, will affect the RERR
pin, will affect the RERR interrupt, and will affect the current audio sample according to the status of the HOLD bit.
If a mask bit is set to 0, the error is masked, meaning that its occurrence will not appear in the receiver error register,
25
CS8415A
will not affect the RERR pin, will not affect the RERR interrupt, and will not affect the current audio sample. The
CCRC and QCRC bits behave differently from the other bits: they do not affect the current audio sample even when
unmasked. This register defaults to 00h.
8.14 Channel Status Data Buffer Control (12h)
7
6
5
4
3
2
1
0
0
0
BSEL
CBMR
DETCI
0
CAM
CHS
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
Default = ‘0’
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
CBMR - Control for the first 5 bytes of channel status “E” buffer
Default = ‘0’
0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data
1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data
DETCI - D to E C-data buffer transfer inhibit bit.
Default = ‘0’
0 - Allow C-data D to E buffer transfers
1 - Inhibit C-data D to E buffer transfers
CAM - C-data buffer control port access mode bit
Default = ‘0’
0 - One byte mode
1 - Two byte mode
CHS - Channel select bit
Default = ‘0’
0 - Channel A information is displayed at the EMPH pin and in the receiver channel status reg-
ister. Channel A information is output during control port reads when CAM is set to 0 (One
Byte Mode)
1 - Channel B information is displayed at the EMPH pin and in the receiver channel status reg-
ister. Channel B information is output during control port reads when CAM is set to 0 (One
Byte Mode)
8.15 User Data Buffer Control (13h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
DETUI
0
DETUI - D to E U-data buffer transfer inhibit bit (valid in block mode only).
Default = ‘0’
0 - Allow U-data D to E buffer transfers
1 - Inhibit U-data D to E buffer transfers
26
CS8415A
8.16 Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only)
The following 10 registers contain the decoded Q-channel subcode data
7
6
5
4
3
2
1
0
CONTROL
CONTROL
CONTROL
CONTROL
ADDRESS
ADDRESS
ADDRESS
ADDRESS
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
INDEX
INDEX
INDEX
INDEX
INDEX
INDEX
INDEX
INDEX
MINUTE
SECOND
FRAME
MINUTE
SECOND
FRAME
MINUTE
SECOND
FRAME
MINUTE
SECOND
FRAME
MINUTE
SECOND
FRAME
MINUTE
SECOND
FRAME
MINUTE
SECOND
FRAME
MINUTE
SECOND
FRAME
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ABS MINUTE
ABS SECOND
ABS FRAME
ABS MINUTE
ABS SECOND
ABS FRAME
ABS MINUTE
ABS MINUTE
ABS MINUTE
ABS MINUTE
ABS MINUTE
ABS MINUTE
ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND
ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME
Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 14h is Q[0]
while bit 0 of address 0Eh is Q[7]. Similarly bit 0 of address 1Dh corresponds to Q[79].
8.17 OMCK/RMCK Ratio (1Eh) (Read Only)
7
6
5
4
3
2
1
0
ORR7
ORR6
ORR5
ORR4
ORR3
ORR2
ORR1
ORR0
This register allows the calculation of the incoming sample rate by the host microcontroller from the
equation ORR=Fso/Fsi. The Fso is determined by OMCK, whose frequency is assumed to be 256
Fso. ORR is represented as an unsigned 2-bit integer and a 6-bit fractional part. The value is mean-
ingful only after the PLL has reached lock. For example, if the OMCK is 12.288MHz, Fso would be
48KHz (48KHz = 12.288MHz/256). Then if the input sample rate is also 48KHz, you would get 1.0
from the ORR register.(The value from the ORR register is hexadecimal, so the actual value you will
63
get is 40h). If F /F > 3 / , ORR will saturate at the value FFh. Also, there is no hysteresis on
SO SI
64
ORR. Therefore a small amount of jitter on either clock can cause the LSB ORR[0] to oscillate.
ORR7:6 - Integer part of the ratio (Integer value=Integer(SRR[7:6]))
ORR5:0 - Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64)
8.18 C-bit or U-bit Data Buffer (20h - 37h)
Either channel status data buffer E or user data buffer E is accessible through these register addresses.
8.19 CS8415A I.D. and Version Register (7Fh) (Read Only)
7
6
5
4
3
2
1
0
ID3
ID2
ID1
ID0
VER3
VER2
VER1
VER0
ID3:0 - ID code for the CS8415A. Permanently set to 0100
VER3:0 - CS8415A revision level. Revision A is coded as 0001
27
CS8415A
9. PIN DESCRIPTION - SOFTWARE MODE
SDA/CDOUT
AD0/CS
1
2
28 SCL/CCLK
27 AD1/CDIN
EMPH 3*+
RXP0 4*
RXN0 5*
VA+ 6*
AGND 7*
FILT 8*
26
25
RXP6
RXP5
*24 H/S
*23 VL+
*22 DGND
*21 OMCK
RST 9*
20
U
RMCK 10*
RERR 11*
19 INT
*18 SDOUT
*17 OLRCK
*16 OSCLK
12
13
14
RXP1
RXP2
RXP3
15
RXP4
* Pins which remain the same function in all modes.
+ Pins which require a pull up or pull down resistor
to select the desired startup option.
Serial Control Data I/O (I2C) / Data Out (SPI) (Input/Output) - In I2C mode, SDA is the control I/O data
line. SDA is open drain and requires an external pull-up resistor to VL+. In SPI mode, CDOUT is the out-
put data from the control port interface on the CS8415A
SDA/CDOUT
AD0/CS
1
2
Address Bit 0 (I2C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the
CS8415A into SPI control port mode. With no falling edge, the CS8415A defaults to I2C mode. In I2C
mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the
CS8415A
3
Pre-Emphasis (Output) - EMPH is low when the incoming Channel Status data indicates 50/15 µs pre-
emphasis. EMPH is high when the Channel Status data indicates no pre-emphasis or indicates pre-
emphasis other than 50/15 µs. This is also a start-up option pin, and requires a 47 kΩ resistor to either
VL+ or DGND, which determines the AD2 address bit for the control port in I2C mode
EMPH
RXP0
RXN0
4
5
AES3/SPDIF Receiver Port (Input) - Differential line receiver inputs carrying AES3 data. RXP0 may be
used as a single-ended input as part of 7:1 S/PDIF Input MUX. If RXP0 is used in MUX, RXN0 must be
ac coupled to ground.
RXP1
RXP2
RXP3
RXP4
RXP5
RXP6
12 Additional AES3/SPDIF Receiver Port (Input) - Single-ended receiver inputs carrying AES3 or S/PDIF
13 digital data. These inputs, along with RXP0, comprise the 7:1 S/PDIF Input Multiplexer and select line
14 control is accessed using the MUX2:0 bits in the Control 2 register. Please note that any unused inputs
15 should be tied to ground. See Appendix A for recommended input circuits.
25
26
VA+
6
Positive Analog Power (Input) - Positive supply for the analog section. Nominally +5 V. This supply
should be as quiet as possible since noise on this pin will directly affect the jitter performance of the
recovered clock
AGND
FILT
7
8
9
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-
nected to a common ground area under the chip.
PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. See
“Appendix C: PLL Filter” on page 40 for recommended schematic and component values.
Reset (Input) - When RST is low, the CS8415A enters a low power mode and all internal states are
reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are
stable in frequency and phase. This is particularly true in hardware mode with multiple CS8415A devices
where synchronization between devices is important
RST
28
CS8415A
RMCK
RERR
10 Input Section Recovered Master Clock (Output) - Input section recovered master clock output when
PLL is used. Frequency defaults to 256x the sample rate (Fs) and may be set to 128x.
11 Receiver Error (Output) - When high, indicates a problem with the operation of the AES3 receiver. The
status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause
RERR to go high are: validity, parity error, bi-phase coding error, confidence, QCRC and CCRC errors,
as well as loss of lock in the PLL. Each condition may be optionally masked from affecting the RERR pin
using the Receiver Error Mask Register. The RERR pin tracks the status of the unmasked errors: the pin
goes high as soon as an unmasked error occurs and goes low immediately when all unmasked errors go
away
OSCLK
OLRCK
16 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin
17 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT
pin. Frequency will be the output sample rate (Fs)
SDOUT
INT
18 Serial Audio Output Data (Output) - Audio data serial output pin
19 Interrupt (Output) - Indicates errors and key events during the operation of the CS8415A. All bits affect-
ing INT may be unmasked through bits in the control registers. The condition(s) that initiated interrupt are
readable through a control register. The polarity of the INT output, as well as selection of a standard or
open drain output, is set through a control register. Once set true, the INT pin goes false only after the
interrupt status registers have been read and the interrupt status bits have returned to zero
U
20 User Data (Output) - Outputs User data from the AES3 receiver, see Figure 7 for timing information
OMCK
21 System Clock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the
Control 1 register, the clock signal input on this pin is output through RMCK. OMCK serves as reference
signal for OMCK/RMCK ratio expressed in register 0x1E
DGND
22 Digital Ground (Input) - Ground for the digital circuitry in the chip. DGND and AGND should be con-
nected to a common ground area under the chip.
VL+
H/S
23 Positive Digital Power (Input) - Positive supply for the digital section. Typically +3 to +5 V.
24 Hardware/Software Mode Control (Input) - Determines the method of controlling the operation of the
CS8415A, and the method of accessing CS and U data. In software mode, device control and CS and U
data access is primarily through the control port, using a microcontroller. Hardware mode provides an
alternate mode of operation and access to the CS and U data through dedicated pins. This pin should be
permanently tied to VL+ or DGND
Address Bit 1 (I2C) / Serial Control Data in (SPI) (Input) - In I2C mode, AD1 is a chip address pin. In
SPI mode, CDIN is the input data line for the control port interface
AD1/CDIN
SCL/CCLK
27
28 Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and
out of the CS8415A. In I2C mode, SCL requires an external pull-up resistor to VL+
29
CS8415A
(master mode only, see Figure 7).The current au-
dio sample is passed unmodified to the serial audio
output port if the validity bit is high, or a parity, bi-
phase, or PLL lock error occurs.
10.HARDWARE MODE
The CS8415A has a hardware mode which allows
using the device without a microcontroller. Hard-
ware mode is selected by connecting the H/S pin
to VL+. Various pins change function in hardware
mode, described in the hardware mode pin defini-
tion section.
10.1 Serial Audio Port Formats
In hardware mode, only a limited number of alter-
native serial audio port formats are available.
Table 2 defines the equivalent software mode bit
settings for each format. Start-up options are
shown in Table 3, and allow choice of the serial au-
dio output port as a master or slave, and the serial
audio port format.
Hardware mode data flow is shown in Figure 9. Au-
dio data is input through the AES3 receiver, and
routed to the serial audio output port. The PRO,
COPY, ORIG, EMPH, and AUDIO channel status
bits are output on pins. The decoded C and U bits
are also output, clocked at both edges of OLRCK
V L+
H/S
RXP
RXN
AES3 Rx
&
Decoder
OLRCK
OSCLK
SDOUT
Serial
Audio
Output
C
U
C & U bit Data Buffer
RMCK RERR NVERR CHS
COPY ORIG EMPH PRO AUDIO RCBL
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 9. Hardware Mode
SOSF
SORES1/0
SOJUST
SODEL
SOSPOL SOLRPOL
OF1 - Left Justified
OF2 - I2S 24-bit data
0
0
00
00
0
0
0
1
0
0
0
1
OF3 - Right Justified, master mode only
OF4 - Direct AES3 data
0
0
00
11
1
0
0
0
0
0
0
0
Table 2. Equivalent Software Mode Bit Definitions
SDOUT
ORIG
-
EMPH
Function
LO
-
Serial Output Port is Slave
Serial Output Port is Master
Left Justified
HI
-
-
-
LO
LO
HI
LO
HI
LO
HI
-
I2S 24-bit data
-
Right Justified
-
HI
Direct AES3 data
Table 3. Hardware Mode Start-up Options
30
CS8415A
11.PIN DESCRIPTION - HARDWARE MODE
COPY
1
COPY Channel Status Bit (Output) - Reflects the state of the Copyright Channel Status bit in the incom-
ing AES3 data stream. If the category code is set to General, copyright will be indicated whatever the
state of the Copyright bit.
VL2+
VL+
VL3+
2
23
27
Positive Digital Power (Input) - Typically +3 to +5V.
3
Pre-Emphasis (Output) - EMPH is low when the incoming Channel Status data indicates 50/15 µs pre-
emphasis. EMPH is high when the Channel Status data indicates no pre-emphasis or indicates pre-
emphasis other than 50/15 µs. This pin is also a start-up option which, along with ORIG, determines the
serial port format. A 47 kΩ resistor to either VL+ or DGND is required.
EMPH
RXP0
RXN0
4
5
AES3/SPDIF Receiver Port (Input) - Differential line receiver inputs for the AES3 biphase encoded data.
See Appendix A for recommended circuits.
VA+
6
7
8
9
Positive Analog Power (Input) - Nominally +5 V. This supply should be as quiet as possible since noise
on this pin will directly affect the jitter performance of the recovered clock.
AGND
FILT
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-
nected to a common ground area under the chip.
PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. See
“Appendix C: PLL Filter” on page 40 for recommended schematic and component values.
Reset (Input) - When RST is low, the CS8415A enters a low power mode and all internal states are
reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are
stable in frequency and phase. This is particularly true in hardware mode with multiple CS8415A devices
where synchronization between devices is important.
RST
RMCK
RERR
10 Recovered Master Clock (Output) - Recovered master clock output when PLL is locked to the incoming
AES3 stream. Frequency is 256x the sample rate (Fs).
11 Receiver Error (Output) - When high, indicates an error condition in the AES3 receiver. The status of
this pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to go
high are: validity bit high, parity error, bi-phase coding error, and loss of lock by the PLL.
31
CS8415A
RCBL
12
13
Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status
block. RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames
while COPY, ORIG, AUDIO, EMPH and PRO are updated, and returns low for the remainder of the
block. RCBL changes on rising edges of RMCK.
PRO
CHS
PRO Channel Status Bit (Output) - Reflects the state of the Professional/Consumer Channel Status
bit in the incoming AES3 data stream. Low indicates Consumer and high indicates Professional.
14 Channel Select (Input) - Selects which sub-frame’s channel status data is output on the EMPH,
COPY, ORIG, PRO and AUDIO pins. Channel A is selected when CHS is low, channel B is selected
when CHS is high.
NVERR
15
No Validity Receiver Error Indicator (Output) - A high output indicates a problem with the operation of
the AES3 receiver. The status of this pin is updated once per frame of incoming AES3 data. Conditions
that cause NVERR to go high are: parity error, and bi-phase coding error, and loss of lock by the PLL.
OSCLK
OLRCK
16 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin.
17 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT
pin. Frequency will be the output sample rate (Fs).
SDOUT
AUDIO
18 Serial Audio Output Data (Output) - Audio data serial output pin. This pin is also a start-up option which
determines if the serial audio port is master or slave. A 47 kΩ resistor to either VL+ or DGND is required.
19
Audio Channel Status Bit (Output) - Reflects the state of the audio/non audio Channel Status bit in
the incoming AES3 data stream. When this bit is low a valid audio stream is indicated.
DGND3
DGND2
DGND
20 Digital Ground (Input) - Ground for the digital circuitry in the chip. DGND and AGND should be con-
21 nected to a common ground area under the chip.
22
24 Hardware/Software Mode Control (Input) - Determines the method of controlling the operation of the
CS8415A, and the method of accessing CS and U data. In software mode, device control and CS and U
data access is primarily through the control port, using a microcontroller. Hardware mode provides an
alternate mode of operation and access to the CS and U data through dedicated pins. This pin should be
permanently tied to VL+ or DGND.
H/S
U
25 User Data (Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling edges
of OLRCK.
C
26 Channel Status Data (Output) - Outputs channel status data from the AES3 receiver, clocked by the ris-
ing and falling edges of OLRCK.
ORIG
28
Original Channel Status (Output) - SCMS generation indicator. This is decoded from the incoming cat-
egory code and the L bit in the Channel Status bits. A low output indicates that the source of the audio
data stream is a copy not an original. A high indicates that the audio data stream is original. This pin is
also a start-up option which, along with EMPH, determines the serial audio port format. A 47 kΩ resistor
to either VL+ or DGND is required.
32
CS8415A
ily members are resident in the same system, al-
lowing common software modules.
12. APPLICATIONS
12.1 Reset, Power Down and Start-up
The CS8415A 4-bit revision code is also available.
This allows the software driver for the CS8415A to
identify which revision of the device is in a particu-
lar system, and modify its behavior accordingly. To
allow for future revisions, it is strongly recommend
that the revision code is read into a variable area
within the microcontroller, and used wherever ap-
propriate as revision details become known.
When RST is low, the CS8415A enters a low pow-
er mode and all internal states are reset, including
the control port and registers, and the outputs are
muted. When RST is high, the control port be-
comes operational and the desired settings should
be loaded into the control registers. Writing a 1 to
the RUN bit will then cause the part to leave the low
power state and begin operation. After the PLL has
settled, the serial audio outputs will be enabled.
12.3 Power Supply, Grounding, and PCB
layout
Some options within the CS8415A are controlled
by a start-up mechanism. During the reset state,
some of the output pins are reconfigured internally
to be inputs. Immediately upon exiting the reset
state, the level of these pins is sensed. The pins
are then switched to be outputs. This mechanism
allows output pins to be used to set alternative
modes in the CS8415A by connecting a 47 KΩ re-
sistor to between the pin and either VL+ (HI) or
DGND (LO). For each mode, every start-up option
select pin MUST have an external pull-up or pull-
down resistor. In software mode, the only start-up
option pin is EMPH, which is used to set a chip ad-
dress bit for the control port in I2C mode. The hard-
ware mode uses many start-up options, which are
detailed in the hardware definition section at the
end of this data sheet.
For most applications, the CS8415A can be oper-
ated from a single +5 V supply, following normal
supply decoupling practices, see Figure 5. Note
that the I2C protocol is supported only in 5V mode.
For applications where the recovered input clock,
output on the RMCK pin, is required to be low jitter,
then use a separate, quiet, analog +5 V supply for
VA+, decoupled to AGND. In addition, a separate
region of analog ground plane around the FILT,
AGND, VA+, RXP0-6 and RXN0 pins is recom-
mended.
Extensive use of power and ground planes, ground
plane fill in unused areas and surface mount de-
coupling capacitors are recommended. Decou-
pling capacitors should be mounted on the same
side of the board as the CS8415A to minimize in-
ductance effects, and all decoupling capacitors
should be as close to the CS8415A as possible.
12.2 ID Code and Revision Code
The CS8415A has a register that contains a 4-bit
code to indicate that the addressed device is a
CS8415A. This is useful when other CS84XX fam-
33
CS8415A
13.PACKAGE DIMENSIONS
28L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1
b
c
D
∝
L
SEATING
PLANE
A
e
A1
INCHES
NOM
0.098
0.008
0.017
0.011
0.705
0.295
0.050
0.407
0.026
4°
MILLIMETERS
NOM
2.50
DIM
A
A1
b
C
D
E
e
H
L
MIN
0.093
0.004
0.013
0.009
0.697
0.291
0.040
0.394
0.016
0°
MAX
0.104
0.012
0.020
0.013
0.713
0.299
0.060
0.419
0.050
8°
MIN
2.35
0.10
0.33
0.23
17.70
7.40
1.02
10.00
0.40
0°
MAX
2.65
0.30
0.51
0.32
18.10
7.60
1.52
10.65
1.27
8°
0.20
0.42
0.28
17.90
7.50
1.27
10.34
0.65
4°
∝
JEDEC #: MS-013
Controlling Dimension is Millimeters
34
CS8415A
28L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
A
E
∝
A1
b2
e
L
END VIEW
SEATING
PLANE
SIDE VIEW
1
2 3
TOP VIEW
INCHES
MILLIMETERS
NOTE
DIM
A
A1
A2
b
D
E
E1
e
L
MIN
NOM
--
0.004
MAX
0.47
0.006
0.04
MIN
--
0.05
0.80
0.19
NOM
--
0.10
MAX
--
0.002
0.03150
0.00748
0.378 BSC
0.248
0.169
--
1.20
0.15
1.00
0.30
9.80 BSC
6.50
4.50
--
0.035
0.90
0.0096
0.382 BSC
0.2519
0.1732
0.026 BSC
0.024
0.012
0.386 BSC
0.256
0.177
--
0.245
9.70 BSC
6.40
4.40
0.65 BSC
0.60
2,3
1
9.60 BSC
6.30
4.30
--
1
0.020
0°
0.029
8°
0.50
0°
0.75
8°
4°
4°
∝
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
35
CS8415A
In the configuration of systems, it is important to
avoid ground loops and DC current flowing down
the shield of the cable that could result when boxes
with different ground potentials are connected.
Generally, it is good practice to ground the shield
to the chassis of the transmitting unit, and connect
the shield through a capacitor to chassis ground at
the receiver. However, in some cases it is advan-
tageous to have the ground of two boxes held to
the same potential, and the cable shield might be
depended upon to make that electrical connection.
Generally, it may be a good idea to provide the op-
tion of grounding or capacitively coupling the shield
to the chassis.
14.APPENDIX A: EXTERNAL
AES3/SPDIF/IEC60958 RECEIVER
COMPONENTS
14.1 AES3 Receiver External
Components
The CS8415A AES3 receiver is designed to accept
both the professional and consumer interfaces.
The digital audio specifications for professional
use call for a balanced receiver, using XLR con-
nectors, with 110 Ω ±20% impedance. The XLR
connector on the receiver should have female pins
with a male shell. Since the receiver has a very
high input impedance, a 110 Ω resistor should be
placed across the receiver terminals to match the
line impedance, as shown in Figure 10. Although
transformers are not required by the AES, they are,
however, strongly recommended.
In the case of the consumer interface, the stan-
dards call for an unbalanced circuit having a re-
ceiver impedance of 75 Ω ±5%. The connector for
the consumer interface is an RCA phono socket.
The receiver circuit for the consumer interface is
shown in Figure 12. Figure 13 shows an imple-
mentation of the Input S/PDIF Multiplexer using the
consumer interface.
If some isolation is desired without the use of trans-
formers, a 0.01 µF capacitor should be placed in
series with each input pin (RXP0 and RXN0) as
shown in Figure 11. However, if a transformer is
not used, high frequency energy could be coupled
into the receiver, causing degradation in analog
performance.
The circuit shown in Figure 14 may be used when
external RS422 receivers, optical receivers or oth-
er TTL/CMOS logic outputs drive the CS8415A re-
ceiver section.
Figures 10 and 11 show an optional DC blocking
capacitor (0.1 µF to 0.47 µF) in series with the ca-
ble input. This improves the robustness of the re-
ceiver, preventing the saturation of the
transformer, or any DC current flow, if a DC voltage
is present on the cable.
14.2 Isolating Transformer Requirements
Please refer to the application note AN134: AES
and SPDIF Recommended Transformers for re-
sources on transformer selection.
5A
CS841
CS8415A
XLR
XLR
* See Text
0.01 µF
0.01 µF
* See Text
RXP0
RXP0
RXN0
110 Ω
Twisted
Pair
110 Ω
Twisted
Pair
110 Ω
110 Ω
RXN0
1
1
Figure 10. Professional Input Circuit
Figure 11. Transformerless Professional Input Circuit
36
CS8415A
.01µF
.01µF
RXP6
75 Ω
Coax
75 Ω
CS8415A
RXP0
0.01 µF
RCA Phono
75 Ω
RXP5
75 Ω
Coax
75 Ω
.
.
.
75 Ω
75 Ω
Coax
.01µF
RXN0
RXP0
75 Ω
Coax
0.01 µF
RXN0
.01µF
Figure 12. Consumer Input Circuit
Figure 13. S/PDIF MUX Input Circuit
TTL/CMOS
Gate
CS8415A
0.01 µF
RXP0
RXN0
0.01 µF
Figure 14. TTL/CMOS Input Circuit
37
CS8415A
The user can configure the interrupt enable regis-
ter to cause interrupts to occur whenever D to E
buffer transfers occur. This allows determination of
the allowable time periods to interact with the E
buffer.
15.APPENDIX B: CHANNEL STATUS AND
USER DATA BUFFER MANAGEMENT
15.1 AES3 Channel Status (C) Bit
Management
The CS8415A contains sufficient RAM to store a
full block of C data for both A and B channels (192
x 2 = 384 bits), and also 384 bits of U information.
The user may read from these buffer RAMs
through the control port.
Also provided is a D to E inhibit bit. This may be
used whenever “long” control port interactions are
occurring.
A flowchart for reading the E buffer is shown in
Figure 16. Since a D to E interrupt just occurred af-
ter reading, there is a substantial time interval until
the next D to E transfer (approximately 24 frames
worth of time). This is usually plenty of time to ac-
cess the E data without having to inhibit the next
transfer.
The buffering scheme involves 2 block-sized buff-
ers, named D and E, as shown in Figure 15. The
MSB of each byte represents the first bit in the se-
rial C data stream. For example, the MSB of byte 0
(which is at control port address 20h) is the con-
sumer/professional bit for channel status block A.
15.2.1 Reserving the first 5 bytes in the E
buffer
The first buffer (D) accepts incoming C data from
the AES receiver. The 2nd buffer (E) accepts entire
blocks of data from the D buffer. The E buffer is
also accessible from the control port, allowing
reading of the C data.
D to E buffer transfers periodically overwrite the
data stored in the E buffer. The CS8415A has the
capability of reserving the first 5 bytes of the E buff-
er for user writes only. When this capability is in
use, internal D to E buffer transfers will NOT affect
the first 5 bytes of the E buffer. Therefore, the user
can set values in these first 5 E bytes once, and the
settings will persist until the next user change. This
mode is enabled using the Channel Status Data
Buffer Control register.
15.2 Accessing the E buffer
The user can monitor the incoming data by reading
the E buffer, which is mapped into the register
space of the CS8415A, through the control port.
A
B
D to E interrupt occurs
Optionally set D to E inhibit
Read E data
8-bits 8-bits
From
AES3
D
E
Receiver
24
words
Received
Data
Buffer
If set, clear D to E inhibit
Return
Control Port
Figure 16. Flowchart for Reading the E Buffer
Figure 15. Channel Status Data Buffer Structure
38
CS8415A
worth of information in 1 byte's worth of access
time. If the control port's autoincrement addressing
is used in combination with this mode, multi-byte
accesses such as full-block reads can be done es-
pecially efficiently.
15.2.2 Serial Copy Management System
(SCMS)
In software mode, the CS8415A allows read ac-
cess to all the channel status bits. For consumer
mode SCMS compliance, the host microcontroller
needs to read and interpret the Category Code,
Copy bit and L bit appropriately.
15.2.3.2 Two Byte mode
There are those applications in which the A and B
channel status blocks will not be the same, and the
user is interested in accessing both blocks. In
these situations, two byte mode should be used to
access the E buffer.
In hardware mode, the SCMS protocol can be fol-
lowed by either using the COPY and ORIG output
pins, or by using the C bit serial output pin. These
options are documented in the hardware mode
section of this data sheet.
In this mode, a read will cause the CS8415A to out-
put two bytes from its control port. The first byte out
will represent the A channel status data, and the
2nd byte will represent the B channel status data.
15.2.3 Channel Status Data E Buffer
Access
The E buffer is organized as 24 x 16-bit words. For
each word the MS Byte is the A channel data, and
the LS Byte is the B channel data (see Figure 15).
15.3 AES3 User (U) Bit Management
Entire blocks of U data are buffered using a cas-
cade of 2 block-sized RAMs to perform the buffer-
ing. The user has access to the second of these
buffers, denoted the E buffer, through the control
port. The U buffer access only operates in two byte
mode, since there is no concept of A and B blocks
for user data. The arrangement of the data is as fol-
lowings:
Bit15[A7]Bit14[B7]Bit13[A6]Bit12[B6]...Bit1[A0]Bit
0[B0]. The arrangement of the data in the each
byte is that the MSB is the first received bit and is
the first transmitted bit. The first byte read is the
first byte received, and the first byte sent is the first
byte transmitted. If you read two bytes from the E
buffer, you will get the following arrangement:
A[7]B[7]A[6]B[6]....A[0]B[0].
There are two methods of accessing this memory,
known as one byte mode and two byte mode. The
desired mode is selected by setting a control regis-
ter bit.
15.2.3.1 One Byte mode
In many applications, the channel status blocks for
the A and B channels will be identical. In this situ-
ation, if the user reads a byte from one of the chan-
nel's blocks, the corresponding byte for the other
channel will be the same. One byte mode takes ad-
vantage of the often identical nature of A and B
channel status data. When reading data in one
byte mode, a single byte is returned, which can be
from channel A or B data, depending on a register
control bit.
One byte mode saves the user substantial control
port access time, as it effectively accesses 2 bytes
39
CS8415A
the AES3 stream to provide lock update informa-
tion to the PLL. This results in the PLL being im-
mune to data dependent jitter affects because the
AES3 preambles do not vary with the data.
16.APPENDIX C: PLL FILTER
16.1 General
An on-chip Phase Locked Loop (PLL) is used to re-
cover the clock from the incoming data stream.
Figure 17 is a simplified diagram of the PLL in
these parts. When the PLL is locked to an AES3 in-
put stream, it is updated at each preamble in the
AES3 stream. This occurs at twice the sampling
frequency, FS. When the PLL is locked to ILRCK,
it is updated at FS so that the duty cycle of the input
doesn’t affect jitter.
The PLL has the ability to lock onto a wide range of
input sample rates with no external component
changes. If the sample rate of the input subse-
quently changes, for example in a varispeed appli-
cation, the PLL will only track up to ±12.5% from
the nominal center sample rate. The nominal cen-
ter sample rate is the sample rate that the PLL first
locks onto upon application of an AES3 data
stream or after enabling the CS8415A clocks by
setting the RUN control bit. If the 12.5% sample
rate limit is exceeded, the PLL will return to its wide
lock range mode and re-acquire a new nominal
center sample rate.
There are some applications where low jitter in the
recovered clock, presented on the RMCK pin, is
important. For this reason, the PLL has been de-
signed to have good jitter attenuation characteris-
tics, as shown in Figure 19. In addition, the PLL
has been designed to only use the preambles of
INPUT
Phase
RMCK
VCO
Comparator
and Charge Pump
Rfilt
Crip
Cfilt
÷
N
Figure 17. PLL Block Diagram
40
CS8415A
they can be mounted close to the FILT pin to
minimize trace inductance. For CRIP, a C0G or
NPO dielectric is recommended, and for CFILT, an
X7R dielectric is preferred. Avoid capacitors with
large temperature co-efficients, or capacitors with
high dielectric constants, that are sensitive to
shock and vibration. These include the Z5U and
Y5V dielectrics.
16.2 External Filter Components
16.2.1 General
The PLL behavior is affected by the external filter
component values. Figure 5 shows the recom-
mended configuration of the two capacitors and
one resistor that comprise the PLL filter. In Table
4, the component values shown for the 32 to
96kHz range have the highest corner frequency jit-
ter attenuation curve, takes the shortest time to
lock, and offers the best output jitter performance.
The component values shown for the 8 to 96kHz
range allows the lowest input sample rate to be 8
kHz, and increases the lock time of the PLL. Lock
times are worst case for an Fsi transition of 96 kHz.
16.2.3 Circuit Board Layout
Board layout and capacitor choice affect each
other and determine the performance of the PLL.
Figure 18 contains a suggested layout for the PLL
filter components and for bypassing the analog
supply voltage. The 0.1 µF bypass capacitor is in a
1206 form factor. RFILT and the other three
capacitors are in an 0805 form factor. The traces
are on the top surface of the board with the IC so
that there is no via inductance. The traces
themselves are short to minimize the inductance in
the filter path. The VA+ and AGND traces extend
back to their origin and are shown only in truncated
form in the drawing.
16.2.2 Capacitor Selection
The type of capacitors used for the PLL filter can
have a significant effect on receiver performance.
Large or exotic film capacitors are not necessary
as their leads and the required longer circuit board
traces add undesirable inductance to the circuit.
Surface mount ceramic capacitors are a good
choice because their own inductance is low, and
1000
pF
Crip
Cfilt
.1µF
Figure 18. Recommended Layout Example
41
CS8415A
16.2.4 Component Value Selection
The external PLL component values are listed in
Table 4.
Fs Range R
8 - 96
(kΩ) C
(µF) C
(nF) PLL Lock Time (ms)
RIP
FILT
FILT
0.909
3.0
1.8
0.047
33
2.2
56
60
32 - 96
Table 4. External PLL Component Values
ues. The AES3 and IEC60958-4 specifications
state a maximum of 2dB jitter gain or peaking.
16.2.5 Jitter Attenuation
Shown in Figure 19 is the jitter attenuation plot
when used with the 36-96kHz PLL component val-
5
0
−5
−10
−15
−20
10−1
100
101
102
103
104
105
Jitter Frequency (Hz)
Figure 19. Jitter Attenuation Characteristics of PLL with Fs=32 to 96 kHz Filter Components
42
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