CN8333EXF [ETC]
PCM Transceiver ; PCM收发器
| 型号： | CN8333EXF |
| 厂家： | 
ETC |
| 描述： | PCM Transceiver
|
| 文件： | 总48页 (文件大小：1179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
This document contains information on a product under development. The parametric information
contains target parameters that are subject to change.
CN8331/CN8332/CN8333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Distinguishing Features
The CN8333 is a three-channel, E3/DS3/STS-1 fully-integrated Line Interface Unit (LIU).
It is configured via external pins and does not need a microprocessor interface.
Each channel has an independent equalizer on the receive side requiring no user
configuration. Also, each channel has a programmable transmit pulse shaper that can
be set to ensure that the cross-connect pulse mask requirement is met for transmit
cable length up to 450 feet. The CN8332 is a dual-channel, and the CN8331 is a
single-channel LIU with performance identical to the CN8333.
The CN8333 gives the user new economies of scale in concentrator applications
where three DS3 or STS-1 channels are concentrated into a single STS-3 channel. By
including three independent transceivers on a chip, significant external components are
eliminated, with the exception of 1:1 coupling transformers, termination resistors, and
supply bypass capacitors.
•
Can be used as a data transceiver
over a maximum of 900 feet of Type
734/728 coaxial cable or equivalent
in an on-premise environment
•
•
Programmable pulse filtering to meet
cross-connect pulse masks (ANSI
T1.102-1993)
Meets jitter specifications of Bellcore
GR499 and GR253
•
•
Large input dynamic range
Alarms for coding violation and loss
of signal
•
•
Full diagnostic loopback capability
Uses a minimum of external
components
NOTE: In this document "x" is used to represent the number of channels:
x = 1 (CN8331), x = 2 (CN8332), and x = 3 (CN8333).
•
•
Compatible with ITU-T G.703, G.823
Independent power down mode per
channel
Functional Block Diagram (only one Channel is shown)
•
Easily interfaced to the DS3/E3
Framer IC (CN8342/3/4/6/8 and
CN8330)
Selectable B3ZS/HDB3
encoding/decoding
XOE
LBO
E3MODE
•
•
PDB
Superior input receiver sensitivity
(< 25mV)
TPOS
TLINEP
Pulse
Shaper
LINE
DRIVER
TNEG
TCLK
Physical Characteristics
ENCODER
TLINEM
•
•
•
80-pin ETQFP package
Single 3.3 V power supply
1 W maximum power dissipation
(CN8333)
TCLK
TAIS
•
•
•
–40 °C to +85 °C temperature range
5 V-tolerant pins
TTL digital pins
RLOOP
LLOOP
DATA
MUX
REFCLK
Applications
RPOS
RNEG
RCLK
•
•
•
•
•
•
•
Digital Cross Connect Systems
Routers
ATM Switches
Channelized Line Aggregation Units
Test Equipment
Channel Service Units
Multiplexers
PDATA
P
N
RLINEP
RLINEM
Clock/
Data
Recovery
Receiver
NDATA
DECODER
DATCLK
ALOS
RLOS
REQH
Data Sheet
100604B
March 23, 2000
CN8333EVM
TX B3ZS/HDB3 analog out
CH1
NRZTX DATA and CLK in
CH1
NRZRX DATA and CLK out
RX B3ZS/HDB3 analog in
TX B3ZS/HDB3 analog out
L
I
N
E
F
R
A
M
E
NRZTX DATA and CLK in
CN8333
CH2
CH2
NRZRX DATA and CLK out
RX B3ZS/HDB3 analog in
TX B3ZS/HDB3 analog out
S
I
D
E
S
I
D
E
NRZTX DATA and CLK in
CH3
CH3
NRZRX DATA and CLK out
RX B3ZS/HDB3 analog in
Clock Input
Loss of Signal
Code Violation
Control
100604_009
Ordering Information
Model Number
Package
Operating Temperature
CN8331EXF
CN8332EXF
CN8333EXF
80-Pin ETQFP
80-Pin ETQFP
80-Pin ETQFP
–40 °C to 85 °C
–40 °C to 85 °C
–40 °C to 85 °C
© 2000, Conexant Systems, Inc.
All Rights Reserved.
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provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no
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100604B
Conexant
Preliminary Information/Conexant Proprietary and Confidential
Table of Contents
Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
1.0
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2.0
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
AMI B3ZS/HDB3 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Transmit Pulse Mask Templates and Power Measurements . . . . . . . . . . . . . . . . . . . . . . . 2-6
Alarm Indication Signal (AIS) Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Jitter Generation (Intrinsic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
Receive Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
AGC/VGA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Receive Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
The PLL Clock Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Loss Of Signal (LOS) Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
B3ZS/HDB3 Decoder With Bipolar Violation Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Data Squelching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.4 Additional CN8331/CN8332/CN8333 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.4.1
2.4.2
2.4.3
Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Loopback Multiplexers (MUXes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.5 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
100604B
Conexant
iii
Preliminary Information/Conexant Proprietary and Confidential
Table of Contents
CN8331/CN8332/CN8333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.6.1
2.6.2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.8 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
3.0
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 PCB Design Considerations for CN8331/CN8332/CN8333 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
Power Supply and Ground Plane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Other Passive Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Recommended Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1 Applicable Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1 Evaluation Module Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
iv
Conexant
100604B
Preliminary Information/Conexant Proprietary and Confidential
CN8331/CN8332/CN8333
List of Figures
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
List of Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 3-1.
Figure B-1.
CN8331 Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
CN8332 Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
CN8333 Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Typical Application Of Single CN833x Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Pulse Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Transmit Pulse Mask for E3 Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Transmit Pulse Mask for DS3 and STS-1 Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
AIS Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Minimum Input Jitter Tolerance Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Mechanical Drawing—Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Typical Connection of CN8333 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Recommended Schematic for the CN833x Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
100604B
Conexant
v
Preliminary Information/Conexant Proprietary and Confidential
List of Figures
CN8331/CN8332/CN8333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
vi
Conexant
100604B
Preliminary Information/Conexant Proprietary and Confidential
CN8331/CN8332/CN8333
List of Tables
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
List of Tables
Table 1-1.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
CN8331/CN8332/CN8333 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
AC Characteristics (Logic Timing). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
100604B
Conexant
vii
Preliminary Information/Conexant Proprietary and Confidential
List of Tables
CN8331/CN8332/CN8333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
viii
Conexant
100604B
Preliminary Information/Conexant Proprietary and Confidential
1
1.0 Pin Description
1.1 Pin Assignments
Figures 1-1 (CN8331), 1-2 (CN8332), and 1-3 (CN8333) illustrate pin
assignments for the 80-pin Exposed Thin Quad Flat Package (ETQFP). Table 1-1
lists the pin definitions and gives additional information for each pin. The
input/output (I/O) column is coded as follows:
I = Input
O = Output
I/O = Bidirectional
P = Power
When a channel is disabled (i.e., the PDBx pin is tied low or not connected),
all receive and transmit analog circuitry powers down. Analog inputs (RLINE) are
ignored and analog outputs (TLINE) are high impedance. Digital inputs of a
powered-down channel are still active, but ignored. Overall noise on the device
can be lowered by not driving the digital inputs of a powered-down channel.
NOTE: When power is disconnected from the device, TLINE pins are low
impedance to ground if driven by more than one forward-bias diode
voltage (0.7 V) below ground. Additionally, driving TLINE, a
forward-bias diode voltage above the VGG pin, creates a low impedance
path from the TLINE pin to the VGG pin. Otherwise, the TLINE pins are
high impedance.
100604B
Conexant
1-1
Preliminary Information/Conexant Proprietary and Confidential
1.0 Pin Description
CN8331/CN8332/CN8333
1.1 Pin Assignments
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure 1-1. CN8331 Pin Diagram
VSS
NC
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
DVDDC
ENDECDIS
PD
2
NC
3
VDD
4
RLOOP
LLOOP
RNEG/RLCV
RPOS/RNRZ
RCLK
VDD
5
NC
6
NC
7
VSS
8
TVSS
TLINEP
TLINEN
TVDD
RVDD
RLINEP
RLINEN
RVSS
VSS
9
RLOS
10
11
12
13
14
15
16
17
18
19
20
TAIS
CN8331
TCLK
TPOS/TNRZ
TNEG/NC
REFCLK
REQH
XOE
LBO
NC
E3MODE
NC
NC
VDD
DVSSC
100604_002
1-2
Conexant
100604B
Preliminary Information/Conexant Proprietary and Confidential
RVDD2
RLINE2P
RLINE2N
RVSS2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RBIAS
VGG
RESET
GPD
PD2
PD1
RLOOP2
LLOOP2
DVSSIO
RLOOP1
LLOOP1
DVDDIO
LBO1
LBO2
XOE2
XOE1
REQH2
REQH1
RNEG2/RLCV2
RPOS2/RNRZ2
RCLK2
RNEG1/RLCV1
RPOS1/RNRZ1
RCLK1
RLOS2
RLOS1
REFCLK2
TNEG2/NC2
TPOS2/TNRZ2
TCLK2
REFCLK1
TNEG1/NCI
TPOS1/TNRZ1
TCLK1
TAIS2
TAIS1
RVDD3
RLINE3P
RLINE3N
RVSS3
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RBIAS
VGG
RESET
GPD
PD3
PD1
RLOOP3
LLOOP3
DVSSIO
RLOOP1
LLOOP1
DVDDIO
LBO1
LBO3
XOE3
XOE1
REQH3
REQH1
RNEG3/RLCV3
RPOS3/RNRZ3
RCLK3
RNEG1/RLCV1
RPOS1/RNRZ1
RCLK1
RLOS3
RLOS1
REFCLK3
TNEG3/NC3
TPOS3/TNRZ3
TCLK3
REFCLK1
TNEG1/NCI
TPOS1/TNRZ1
TCLK1
TAIS3
TAIS1
CN8331/CN8332/CN8333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions (1 of 6)
Pin #
Signal Name
Description
I/O/P
Notes
CN8331 CN8332 CN8333
Coaxial Line Pins
14
15
—
—
—
—
10
11
—
—
—
—
6
6
RLINEP/
RLINE1P
Line 1 positive receive
data
I
I
Differential inputs for each channel from its
respective receive coax line. The RX expects
balanced differential inputs, usually
achieved using a 1:1 transformer.
The inputs are internally DC biased to 1.9 V.
7
7
RLINEN/
RLINE1N
Line 1 negative receive
data
22
23
—
—
2
14
15
22
23
2
RLINE2P
RLINE2N
RLINE3P
RLINE3N
Line 2 positive receive
data
I
Line 2 negative receive
data
I
Line 3 positive receive
data
I
Line 3 negative receive
data
I
TLINEP/
TLINE1P
Line 1 positive transmit
data
O
O
O
O
O
O
Differential, coax-driver balanced outputs
for pulse-shaped AMI B3ZS/HDB3 encoded
waveforms for each channel.
3
3
TLINEN/
TLINE1N
Line 1 negative transmit
data
These pins should be connected to the
primary side of the 1:1 transformer through
two backmatch resistors (see Appendix B).
18
19
—
—
10
11
18
19
TLINE2P
TLINE2N
TLINE3P
TLINE3N
Line 2 positive transmit
data
Line 2 negative transmit
data
Line 3 positive transmit
data
Line 3 negative transmit
data
Digital Data Pins
54
55
68
69
68
69
RPOS/
RPOS1/
RNRZ/
RNRZ1
RX1 AMI + data/ NRZ
data output
O
O
Resynchronized receive data intended to be
strobed out by the corresponding RCLK.
When ENDECDIS = 1, these outputs are
positive and negative AMI data (RPOS and
RNEG).
RNEG/
RNEG1/
RX1 AMI – data/line
code violation
RLCV/ RLCV1
When ENDECDIS = 0, these outputs are
decoded NRZ data (RNRZ) and line code
violation (RLCV). A line code violation is
indicated when RLCV = 1.
—
—
—
—
33
32
—
—
54
55
33
32
RPOS2/
RNRZ2
RX2 AMI + data/ NRZ
data output
O
O
O
O
RNEG2/
RLCV2
RX2 AMI – data/line
code violation
See notes on the ENDECDIS pin, next page.
RPOS3/
RNRZ3
RX3 AMI + data/ NRZ
data output
RNEG3/
RLCV3
RX3 AMI – data/line
code violation
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1.0 Pin Description
CN8331/CN8332/CN8333
1.1 Pin Assignments
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions (2 of 6)
Pin #
Signal Name
Description
I/O/P
Notes
CN8331 CN8332 CN8333
53
—
—
49
67
34
—
63
67
53
34
63
RCLK/ RCLK1
RCLK2
Receive clock Ch1
Receive clock Ch2
Receive clock Ch3
O
O
O
I
Recovered clock for each channel receiver,
intended for strobing the corresponding
RDAT into the following framer or logic.
RCLK3
TPOS/
TPOS1/
Ch1 transmit Positive
rail or NRZ data
Synchronized transmit data intended to be
strobed in by the corresponding TCLK.
TNRZ/ TNRZ1
48
64
64
TNEG/
TNEG1/
NC/
Ch1 transmit Negative
rail or no connect data
I
When ENDECDIS = 1, these inputs are
expected to be positive and negative AMI
data (TPOS and TNEG).
NC1
When ENDECDIS = 0, these inputs are
expected to be uncoded NRZ data (TNRZ)
and no connects (NC).
—
—
—
—
38
37
—
—
49
48
38
37
TPOS2/
TNRZ2
Ch2 transmit
Positive/NRZ data
I
I
I
I
TNEG2/ NC2 Ch2 transmit Negative
data
See notes on the ENDECDIS pin.
TPOS3/
TNRZ3
Ch3 transmit
Positive/NRZ data
TNEG3/ NC3 Ch3 transmit Negative
data
50
—
—
52
—
—
62
39
—
66
35
—
62
50
39
66
52
35
TCLK/ TCLK1
TCLK2
Transmit clock Ch1
Transmit clock Ch2
Transmit clock Ch3
Loss of signal Ch1
Loss of signal Ch2
Loss of signal Ch3
I
Transmit bit clock input for strobing with
transmit data into the CN833x.
I
TCLK3
I
RLOS/ RLOS1
RLOS2
O
O
O
Loss Of Signal (LOS) indication for each
channel, as determined by insufficient pulse
density. Signal loss detected when RLOS =
1. An LOS will be asserted when 175±75
zeros occur in a row and deasserted when
the pulse density is between 28% and 33%
(DS3/STS-1) (i.e., a 1’s density).
RLOS3
1-6
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CN8331/CN8332/CN8333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions (3 of 6)
Pin #
Signal Name
Description
I/O/P
Notes
CN8331 CN8332 CN8333
Control Signals
59
59
59
ENDECDIS
Encoder/decoder
disable (for all
channels)
I
1 = Dual rail pulse coded data format. Input
transmit data pins TPOS, TNRZ, TNEG and
NC are interpreted as TPOS and TNEG
(encoded positive and negative rail data).
Output receive data pins RPOS and RNRZ,
and RNEG and RLCV are interpreted as
RPOS and RNEG, with RPOS having a
positive pulse in place of every positive AMI
pulse and RNEG having a negative pulse in
place of every negative AMI pulse.
0 = NRZ format. Transmit data pins TPOS
and TNEG are interpreted as TNRZ and NC
(not connected). Receive data pins RPOS
and RNEG are interpreted as RNRZ and
RLCV. In this mode, all line code violations
are reported as active high on RLCV.
—
51
40
61
—
40
61
51
40
TAIS1
Transmit Ch1 AIS mode
enable
I
I
I
Transmission of Alarm Indication Signal
(AIS) for a given channel. Replace transmit
data with AIS signal. The AMI form of AIS
supported is alternating 1s.
(+1, -1, +1, -1, +1, ...)
Looping takes precedence over AIS.
1 = AIS mode enabled
TAIS/
TAIS2
Transmit Ch2 AIS mode
enable
TAIS2/
TAIS3
Transmit Ch3 AIS mode
enable
0 = AIS mode disabled
43
43
43
E3MODE
E3MODE
I
When the pin is set to high, it enables the
E3 mode on all channels, instead of the
DS3/STS-1 mode. This also changes the
pulse shaper to E3 mode and overrides all
LBO pins. It also changes the
encoder/decoder from B3ZS mode to HDB3
mode.
1 = E3 mode
0 = DS3/STS-1 mode
44
—
—
72
29
—
72
44
29
LBO/
LBO1
Transmit line Ch1
build-out mode
I
I
I
Line build-out mode per channel, based on
the length of cable on the transmit side of
the cross-connect block. This bit is
overridden and the pulse shaper is disabled
(no pulse shaping) if E3MODE = 1.
LBO2
Transmit line Ch2
build-out mode
LBO3
Transmit line Ch3
build-out mode
1 = Inserts line build-out into the transmit
channel. Usually used when the transmit
cable is less than 350 feet in length.
0 = Line build-out bypassed (not inserted).
Usually used when the transmit cable is
greater than 350 feet in length.
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1.0 Pin Description
CN8331/CN8332/CN8333
1.1 Pin Assignments
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions (4 of 6)
Pin #
Signal Name
Description
I/O/P
Notes
CN8331 CN8332 CN8333
56
—
—
57
—
—
45
—
—
—
46
—
74
27
—
75
26
—
71
30
—
70
—
31
74
56
27
75
57
26
71
45
30
70
46
31
LLOOP/
LLOOP1
Local loopback enable
Ch1
I
I
I
I
I
I
I
I
I
I
I
I
Local loopback enable per channel. The
transmit data is looped back immediately
from the encoder to the decoder in place of
the received data.
LLOOP2
Local loopback enable
Ch2
1 = local loopback enabled
0 = local loopback disabled
LLOOP3
Local loopback enable
Ch3
RLOOP/
RLOOP1
Remote loopback
enable Ch1
Remote loopback enable per channel. The
receive data, retimed after clock recovery, is
looped back into the AMI generator in place
of the transmit data.
RLOOP2
Remote loopback
enable Ch2
1 = remote loopback enabled
0 = remote loopback disabled
RLOOP3
Remote loopback
enable Ch3
XOE/
XOE1
Transmit output enable
Ch1
Transmit output enable per channel.
1 = transmit line output driver enabled
0 = transmit output driver set to high
impedance state
XOE2
Transmit output enable
Ch2
XOE3
Transmit output enable
Ch3
REQH1
Ch1 Receive High EQ
Gain Enable
The equalizer in the CN833x has two gain
settings. The higher gain setting is designed
to optimally equalize a nominally-shaped
(meets the pulse template), pulse-driven
DS3 or STS-1 waveform that is driven
through 0–900 feet of cable.
Square-shaped pulses such as E3 or
DS3-HIGH require less high-frequency gain
and should use the low EQ gain setting.
REQH/
REQH2
Ch2 Receive High EQ
Gain Enable
REQH3
Ch3 Receive High EQ
Gain Enable
REQH = 1 high EQ gain (DS3/STS-1 modes)
REQH = 0 low EQ gain (E3/DS3
Square Modes)
Power/Ground
12
—
—
9
4
20
—
1
4
12
20
1
TVDD/ TVDD1
TVDD2
TX power Ch1
TX power Ch2
TX power Ch3
TX ground Ch1
TX ground Ch2
TX ground Ch3
RX power Ch1
P
P
P
P
P
P
P
Power pins for transmit circuitry per
channel (3.3 V).
TVDD3
TVSS/ TVSS1
TVSS2
Ground pins for transmit circuitry per
channel.
—
—
13
17
—
5
9
17
5
TVSS3
RVDD/
RVDD1
Power pins for receive circuitry per channel
(3.3 V).
—
—
13
13
21
RVDD2
RVDD3
RX power Ch2
RX power Ch3
P
P
Connect to 3.3 V power.
—
1-8
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CN8331/CN8332/CN8333
1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.1 Pin Assignments
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions (5 of 6)
Pin #
Signal Name
Description
I/O/P
Notes
CN8331 CN8332 CN8333
16
8
8
RVSS
RVSS1
RX ground Ch1
P
Ground pins for receive circuitry per
channel.
—
—
60
41
79
24
—
60
41
79
16
24
60
41
79
RVSS2
RVSS3
DVDDC
DVSSC
VGG
RX ground Ch2
RX ground Ch3
P
P
P
P
P
Connect to ground.
Digital core power
Digital core ground
Digital core power for all channels (3.3 V).
Digital core ground for all channels.
5 V/3.3 V ESD pin (1)
5 V supply for 5 V-tolerant, digital pad ESD
diodes. No static power is drawn from pin.
73
28
73
28
73
28
—
DVDDIO
DVSSIO
VDD
Digital I/O power
Digital ground
Power
P
P
P
Connect to 3.3 V digital power.
Digital ground.
4, 5, 20,
21
12, 13
Connect to 3.3 V power.
1, 8, 17,
24
9, 16
76
—
VSS
Ground
P
Connect to ground.
Miscellaneous
58
76
PD/
PD1
Power down for Ch1
I
Power down transceiver channel
0 = Power down channel (off)
1 = Channel active (on)
—
—
25
58
25
PD2
PD3
Power down for Ch2
Power down for Ch3
I
I
Note: A special power-down mode exists
when all three PDBs are set low. This
special mode shuts off the entire chip
(including biasing). This is useful for static
Idd testing. (See PD pin).
—
47
65
65
REFCLK/
REFCLK1
Reference clock for Ch1
I
Reference clock from off-chip.
This clock should be set to one of the
following:
—
—
36
47
36
REFCLK2
REFCLK3
Reference clock for Ch2
Reference clock for Ch3
I
I
•
•
•
E3 rate (34.368 MHz)
DS3 rate (44.736 MHz)
STS-1 rate (51.84 MHz)
—
The clock rate should correspond to the
mode of operation that has been chosen for
the channel.
80
80
80
RBIAS
Bias resistor
O
A 12.1 kΩ ±1% resistor tied from this pin to
ground provides the current reference to
the entire chip.(2)
78
77
78
77
78
77
Reset
GPD
Reset
I/O Asynchronous reset (reset entire device).
Global Power Down
I/O Power Down (device enter low power state
for Static Idd testing).
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1.0 Pin Description
CN8331/CN8332/CN8333
1.1 Pin Assignments
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions (6 of 6)
Pin #
Signal Name
Description
I/O/P
Notes
CN8331 CN8332 CN8333
2, 3, 6, 7,
18, 19,
22, 23,
25, 26,
27, 29,
30, 31,
32, 33,
34, 35,
10, 11,
14, 15,
42, 44,
45, 47,
48, 49,
50, 51,
52, 53,
54, 55,
—
NC
No connect
—
Not connected.
36, 37, 56, 57, 58
38, 39,
40, 42,
61, 62,
63, 64,
65, 66,
67, 68,
69, 70,
71, 72,
74, 75, 76
NOTE(S):
(1)
This pin should be connected to 3.3 V in an all-3.3 V design.
Placing a capacitor from this pin to ground may result in instabilities.
(2)
3. All digital input pins contain a 75 KΩ pull-down resistor from input to DVSS.
1-10
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2
2.0 Functional Description
2.1 Overview
CN8333 is a triple E3/DS3/STS-1 Line Interface Unit (LIU). It is the physical
layer interface between the data framer (or other terminal-side equipment) and the
electrical cable used for data transmission.
The CN8333 LIU consists of three independent data transceivers that can
operate over type 734/728 coaxial cable at the rates of 34.368 Mbps (E3), 44.736
Mbps (DS3), and 51.84 Mbps (STS-1). The transmit side takes an NRZ or
already-encoded dual rail input and encodes it into AMI B3ZS (for DS3/STS-1)
or HDB3 (for E3) analog waveforms to be transmitted over the coaxial cable. The
receiver side takes in the attenuated and distorted analog receive signal and
equalizes, slices, and resynchronizes the signal before decoding it to the NRZ
output or sending out a non-decoded dual rail.
CN8331 and CN8332 are single- and dual-E3/DS3/STS-1 LIUs, respectively.
In all respects, their performance and features are identical to the CN8333.
The architecture of the CN833x includes the following internal functions for
each channel:
General:
•
•
•
bias generator
power-on reset
loopback MUXes
Transmitter:
•
•
•
•
B3ZS/HDB3 encoder
Alarm Indication Signal (AIS) insertion
pulse shaper
line driver
Receiver:
•
•
•
•
•
Automatic Gain Control
receive equalizer
Clock Recovery Circuit
Loss Of Signal (LOS) detector
B3ZS/HDB3 decoder with bipolar violation detector
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2.0 Functional Description
CN8331/CN8332/CN8333
2.1 Overview
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
In addition, each channel has the ability to perform remote and local
loopbacks. Figure 2-1 illustrates a typical application using the CN833x in a
channel.
External pins are provided to configure the various line rates and formats for
each channel.
The CN833x is used as a data transceiver over a coaxial cable that is up to
900 feet long (or up to 450 feet from the DSX) in an on-premise environment
within any public or private networks which use these data rates.
Figure 2-1. Typical Application Of Single CN833x Channel
0–450 ft COAX
(type 734/728)
0–450 ft COAX
(type 734/728)
TX
RX
DSX
0–450 ft COAX
(type 734/728)
0–450 ft COAX
(type 734/728)
RX
DSX
TX
100604_012
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CN8331/CN8332/CN8333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2 Transmitter
2.2 Transmitter
This section describes the detailed operation of the various blocks in the CN833x
transmitter.
2.2.1 AMI B3ZS/HDB3 Encoder
ENDECDIS and the E3MODE pins configure the encoder mode.
When ENDECDIS = 0, the encoder is receiving non-encoded Nonreturn to
Zero (NRZ) data on the TNRZ (TPOS) pin alone, and the NC (no connect)
(TNEG) pin is ignored.
Data is encoded into a representation of a three-level B3ZS (E3MODE = 0) or
HDB3 (E3MODE = 1) signal (conforming to the coding rules as specified in
Appendix A) before going on to the pulse shaper in the form of two binary signals
representing the positive and negative three-level pulses.
When ENDECDIS = 1, the encoder is disabled. The encoder passes
already-encoded data over TPOS (TNRZ) and TNEG (NC) to the pulse shaper.
The transmit digital data is clocked into the chip via a rising TCLK edge,
which must be equal to the symbol rate (line rate). A small delay added to the data
provides a certain amount of negative data hold time.
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CN8331/CN8332/CN8333
2.2 Transmitter
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2.2 Pulse Shaper
The pulse shaper converts the two digital (clocked) positive and negative pulses
into a single analog three-level Alternate Mark Inversion (AMI) pulse. The pulses
are in Return to Zero (RZ) format, meaning that all positive and negative pulses
have a duration of the first half of the symbol period.
For the E3 rate (E3MODE = 1), the AMI pulse is a full-amplitude,
square-shaped pulse with very little slope.
Figure 2-2. Pulse Shaper
E3
Mode
+ Pulse
– Pulse
LBO
LBO = 0
Pulse
Shaper
Line Driver
LBO = 1
100604_008
For DS3/STS-1 rates, a pulse-shaper block is used to shape the transmit
waveform and reduce its high-frequency energy content. This ensures that the
transmit pulse template is met at the cross-connect block, which follows 0–450
feet of transmit-side coaxial cable.
2-4
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2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2 Transmitter
2.2.3 Line Driver
The differential line driver takes the filtered transmit waveform, increases it to the
proper level, and drives it into the transmit magnetics. The two external discrete
back-matching resistors (36 Ωs) aid in line matching. The driver is presented with
an approximately 150 Ω differential load. Driver gain accounts for the 6 dB gain
loss in the back-matching resistors.
Figure 2-3 illustrates the Pulse/Power template measurement points for the
various data rates.
Figure 2-3. Pulse Measurement Points
Pulse/Power Template for DS3/STS-1
0–450 ft COAX
(type 734/728)
0–450 ft COAX
(type 734/728)
RX
DSX
TX
Pulse/Power Template for E3
0–450 ft COAX
(type 734/728)
0–450 ft COAX
(type 734/728)
DSX
TX
RX
100604_013
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CN8331/CN8332/CN8333
2.2 Transmitter
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2.4 Transmit Pulse Mask Templates and Power Measurements
Figure 2-4. Transmit Pulse Mask for E3 Rate
Transmit Pulse Mask for E3
1.2
1
0.8
0.6
0.4
0.2
0
0.2
0.5
0.33
0.167
0
0.167
0.33
0.5
Normalized Symbol Time
8333_007
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2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2 Transmitter
Figure 2-5. Transmit Pulse Mask for DS3 and STS-1 Rates
Transmit Pulse Mask for DS3 Rates
1.2
1
0.8
0.6
0.4
0.2
0
0.2
1
0.5
0
0.5
1
1.5
Normalized Symbol Time
Transmit Pulse Mask for STS-1 Rates
1.2
1
0.8
0.6
0.4
0.2
0
0.2
1
0.5
0
0.5
1
1.5
Normalized Symbol Time
8333_008
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CN8331/CN8332/CN8333
2.2 Transmitter
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2.5 Alarm Indication Signal (AIS) Generator
When selected by asserting TAIS, an AIS replaces the transmit data at TPOS and
TNEG. The E3 type of AIS signal (all 1s) is supported. In three-level signal form,
this is a continuously alternating positive and negative pulse stream, as if the
transmit data were a continuous string of logical 1s. Figure 2-6 illustrates the AIS
signal.
The TAIS pin has the same data latency as the TX data pins and can be used to
replace single symbols within a data stream. When the encoder is disabled
(ENDECDIS = 1), the TAIS mode maintains the proper phase, based upon the
polarity of the last 1 received.
The AIS signal follows the same path as the TX data during remote or local
loopback.
Figure 2-6. AIS Signal
POSITIVE
PULSE
NEGATIVE
PULSE
TLINEP
(output voltage)
TLINEM
(output voltage)
8333_009
2.2.6 Jitter Generation (Intrinsic)
The CN833x device meets the jitter generation requirements for various rates
with large margins, with the condition that the input transmit clock (TCLK) is
jitter-free. Data rates and jitter generation requirements are defined in the
following documents:
•
•
E3 rate—ETSI TBR24, ITU-T 9.823
DS3 rate—Bellcore Telecardia GR499, AT&T Accunet TR54014,
ITU-T 9.824
•
STS-1 rate—Bellcore Telecardia GR253
2-8
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CN8331/CN8332/CN8333
2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.3 Receiver
2.3 Receiver
This section describes in detail various blocks in the CN8331/CN8332/CN8333
receiver.
2.3.1 Receive Sensitivity
The receiver recovers data from the coaxial cable that is attenuated due to the
frequency-dependent characteristics of the cable. In addition, the receiver
compensates for the flat loss (across all frequencies) in the various electrical
components and the variation in transmitted signal power.
The CN833x device is able to recover data that has been attenuated by a
maximum of 900 feet of coax having characteristics and attenuation consistent
with ANSI T1.102-1993, Annex C, Figure C.2. This approximates the
characteristics of AT&T type 734/728 cable; almost the same attenuation
characteristic is achieved by one-half the length of AT&T type 735 cable.
2.3.2 AGC/VGA Block
The Variable Gain Amplifier (VGA) receives the AMI input signal from the
coaxial cable. The VGA supplies flat gain (independent of frequency) to make up
for various flat losses in the transmission channel and for loss at one-half the
symbol rate that cannot be made up by the equalizer. The VGA gain is controlled
by a feedback loop which senses the amplitude of the equalizer output, acting to
servo this amplitude for optimal slicing.
2.3.3 Receive Equalizer
The receive equalizer receives the differential signal from a VGA and acts to
boost the high frequency content of the signal to reduce inter-symbol interference
(ISI) to the point that correct decisions can be made by the slicer with a minimum
of jitter in the recovered data.
The REQH pin is provided to allow lower amounts of equalization (shorter
equivalent cable lengths) for cases where a square-shaped pulse (that does not
meet the DS3/STS-1 standards) is transmitted to the receiver. A square-shaped
input has a much larger high-frequency content and could have overshoots at the
EQ output high enough to cause bit errors. Setting REQH = 0 will lower the gain
and reduce the amount of overshoot.
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2.3 Receiver
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.3.4 The PLL Clock Recovery Circuit
The clock recovery circuit (RX PLL) extracts the embedded clock from the sliced
data and provides this clock and the retimed data to the decoder (data mode).
Upon startup (after the internal reset is deasserted), the RX PLL uses a reference
clock (REFCLK, running at the symbol rate) and a phase-frequency detector to
lock to the correct data rate (reference mode). During reference mode, the data
outputs are squelched (set to 0). The RX PLL is kept in reference mode until a
valid input is detected.
2.3.5 Loss Of Signal (LOS) Detector
The Receive Loss Of Signal (RLOS) is a digital function which monitors the
retimed data from the clock recovery block. The AMI data is checked for a
continuous run of zeroes. When a continuous run of 128 ± 1 consecutive zeroes
occurs, the RLOS signal is asserted. After the RLOS signal is asserted, a 1s count
is made on every block of 128 AMI symbols. The RLOS signal is deasserted
when the 1s count within a block of 128 symbols is at least:
B3ZS: Minimum 1s density = 39 ± 1 count out of 128 (~30.5%)
HDB3: Minimum 1s density = 29 ± 1 count out of 128 (~22.7%)
The RLOS detector will always monitor the cable-side RX inputs. The
detector is not affected by the state of remote or local looping.
2.3.6 Jitter Tolerance
The CN833x receiver is able to tolerate a specified amount of high-frequency
jitter in the received signal while providing error-free operation (generally
defined as a bit error rate of less than 10-9). The specifications (illustrated in
Figure 2-7) for jitter tolerance are discussed in the following documents:
•
E3 rate – ITU-T G.823 and ETSI TBR24 contain frequency masks for input
jitter tolerance.
NOTE: To meet jitter transfer requirements for loop-timed operation, an external
jitter attenuator is required. The jitter attenuator lessens jitter from the
receive clock.
•
DS3 rate – ITU-T G.823 and Bellcore GR499 specify jitter tolerance
frequency masks for Category I and Category II interfaces.
•
STS-1 rate – Bellcore GR253 specifies a jitter tolerance. It is noted that the
STS-1 jitter tolerance differs from DS3 requirements only for Category II
interfaces.
2-10
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2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.3 Receiver
Figure 2-7. Minimum Input Jitter Tolerance Requirement
E3 Rate
1.0 UI
0.1 UI
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
Jitter Frequency
DS3 / STS-1 Rates
STS-1
DS3 Category I
DS3 Category II
10 UI
1.0 UI
0.1 UI
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Jitter Frequency
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2.3 Receiver
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.3.7 B3ZS/HDB3 Decoder With Bipolar Violation Detector
In the CN833x device, when ENDECDIS = 0 (encoder/decoder enabled), the
decoder takes the output from the clock recovery circuit and decodes the data
(HDB3 or B3ZS) into a single retimed NRZ data signal. The data signal is then
sent out of the CN833x over the RNRZ (RPOS) pin. Any detected Line Code
Violations (LCV) are sent out over the corresponding RLCV (RNEG) pin. The
RLCV pin is asserted for one symbol period at the time the violation appears on
the RX output pin (RNRZ).
The following shows data sequence criteria for LCV; violations are indicated
in bold text. A valid bipolar pulse is indicated by a B. A bipolar violation
(non-alternating positive or negative) pulse is indicated by a V.
•
•
Excessive zeros: 0, 0, 0, 0 (HDB3) or 0, 0, 0 (B3ZS). These violations are
passed on as 0 data on the RNRZ pin.
Bipolar violation: B, 0, V (i.e., +1, 0, +1 or -1, 0, -1 for HDB3) B, V
(B3ZS and HDB3). These violations are passed on as 1 data on the RNRZ
pin.
•
Coding violation: 0, 0, V (HDB3) or 0, V (B3ZS) with an even number of
Bs since the last valid 0 substitution V (follows coding rule). These
violations are passed on as 0 data on the RNRZ pin.
The even/odd counter (used to count the number of Bs between Vs) will count
a bipolar violation as a B. A coding violation or a valid 0 substitution resets the
counter.
When ENDECDIS = 1, the decoder is disabled, and the retimed slicer outputs
are sent out over RPOS (RNRZ) and RNEG (RLCV) pins. These outputs are then
decoded by the CN8340/CN8330 or other downstream device. Line code
violations are not detected in this mode of operation. The decoder is configurable
for either:
•
•
E3 mode using HDB3 coding (E3MODE = 1)
DS3/STS-1 mode using B3ZS coding (E3MODE = 0)
The receiver digital data outputs are centered on the rising edge of RCLK
(see Section 2.8).
2.3.8 Data Squelching
A counter in the receiver keeps track of the number of consecutive symbol
periods without a valid data pulse. When 128 or more 0s in a row are counted, the
receiver assumes that it has lost the signal and resets itself to try and regain the
signal. While the receiver is reacquiring the signal, the clock recovery block locks
to the reference clock and the data squelching is achieved by forcing the data bits
to zero. The data squelching is true in both NRZ and dual rail mode. When the
input signal has been properly amplified and equalized, the clock recovery PLL
will then switch to the incoming data.
2-12
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2.0 Functional Description
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2.4 Additional CN8331/CN8332/CN8333 Functions
2.4 Additional CN8331/CN8332/CN8333
Functions
2.4.1 Bias Generator
To achieve good isolation between the channels, each channel utilizes an
independent power and ground to both transmit and receive. Additionally, each
channel has its own band gap voltage reference. Because only one external
resistor for current generation exists, only one band gap voltage can be used. The
band gap from Ch1 has been chosen for this task.
The 12.1 kΩ external resistor from pin RBIAS to ground, is specified to have
a tolerance of ±1%. This helps to keep tighter control on power dissipation and
circuit performance.
NOTE: Capacitance should be kept to a minimum on the RBIAS pin.
2.4.2 Power-On Reset (POR)
A POR function is provided in the CN833x device to ensure all of the resettable
digital logic and analog control lines are starting from a known state. This circuit
uses a fixed RC timer (~1µs); additionally, 128 clocks from REFCLK are counted
(after the RC timer has timed-out) before reset is deasserted, which begins timing
after a minimum supply voltage is reached (see Table 2-2).
2.4.3 Loopback Multiplexers (MUXes)
Two loopback MUXes per channel in the CN833x allow for local loopback
(terminal or framer side), remote loopback (cable side), or both (the AIS signal
follows the same path as the transmit data during loopback). The RLOS signal
monitors the RX cable inputs irrespective of any loopback.
In remote loopback, set by asserting pin RLOOP high, the receive data
(retimed after clock recovery but not decoded) loops back into the pulse shaper in
place of the transmit data. Additionally, this data sent out the RPOS, RNEG, and
RCLK pins.
In local loopback, set by asserting pin LLOOP, the transmit data loops back
immediately from the encoder output to the decoder input in place of the received
data. Additionally, this data is sent out the TLINEP and TLINEM pins.
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CN8331/CN8332/CN8333
2.5 Mechanical Specifications
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.5 Mechanical Specifications
Figure 2-8. Mechanical Drawing—Dimensions
D
D
1
Pin #1
Ref. Mark
D
2
D
3
D
D
1
D
D
D
3
1
2
e
b
TOP
BOTTOM
Millimeters
Inches
Dim.
Min.
1.20 MAX.
0.05
Max.
Min.
Max.
A
A
A
0.047 MAX.
0.002
0.040
See DETAIL B
0.15
1.05
0.006
0.041
0.640
0.555
1
0.95
15.75
13.90
2
16.25 0.620
14.10 0.547
D
D
D
D
L
1
2
3
12.35 REF.
6.50 REF.
0.45
0.486 REF.
0.256 REF.
0.018 0.030
A
2
A
c
A
1
0.75
L
1.00 REF.
0.32 REF.
0.039 REF.
0.026 REF.
0.013 REF.
1
b
c
e
0.09
0.65 REF.
0.10 MAX.
Ref. 80-Pin ETQFP (GP00-D537)
0.20
L
0.004
0.008
L
1
Coplanarity
0.004 MAX.
DETAIL B
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Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.6 Electrical Characteristics
2.6 Electrical Characteristics
2.6.1 Absolute Maximum Ratings
Table 2-1. Absolute Maximum Ratings
Symbol
DVDDC
Parameter
Min
Max
Unit
Power Supply Voltage
–0.3
6
V
RVDD
TVDD
VDD
V
Voltage on Any Signal
Pin
–1.0
VGG + 0.3 V
V
I
TST
Storage Temperature
–40
125
220
°C
°C
TVSOL
Vapor Phase Soldering
Temperature (1 min.)
—
Thermal Resistance (Still
air, socketed)
—
—
40
24
°
θJA
θJA
C
/
W
W
W
Thermal Resistance (Still
air, soldered)
°
°
C
/
—
—
—
7.40
313
θJc
C
/
FIT
Failures in time @
89,000 device hours,
temperature of 55 °C,
0 failures.
fits
NOTE(S):
1. Stresses above those listed as absolute maximum ratings may cause permanent damage
to the device. This is a stress rating only, and functional operation of the device at these or
any other conditions beyond those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
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2.6 Electrical Characteristics
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.6.2 Recommended Operating Conditions
Table 2-2 specifies various operating conditions, power supplies, and the bias
resistor.
Table 2-2. Recommended Operating Conditions
Parameter
Conditions
Min
Nom
Max
Unit
Power supply
voltage
DVDDC, RVDD, TVDD,
VDD
3.135
3.3
3.465
V
ESD voltage(1)
VGG
3.135
5
5.5
1.0
V
Power dissipation
(CN8333)
Total chip
—
0.83
W
Power dissipation
(CN8332)
Total chip
—
—
—
—
0.8
.450
W
W
Power dissipation
(CN8331)
Total chip
External bias
resistor
Pin RBIAS to GND; ±1%
11.98
12.1
12.22
kΩ
NOTE(S):
(1)
With 5 V logic input, VGG should be tied to 5 V. With 3.3 V logic input, VGG should be tied
to 3.3 V.
2-16
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Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.7 DC Characteristics
2.7 DC Characteristics
Table 2-3. DC Characteristics
Parameter
Conditions
Min
2.0
Nom
—
Max
VGG + 0.3
0.8
Unit
V
V high threshold
Digital inputs
Digital inputs
ih
V low threshold
–0.3
2.4
—
V
il
V
oh high threshold
Digital outputs,
—
—
V
Ioh = –4 mA
V low threshold
Digital outputs,
Iol = 4 mA
—
—
—
0.4
V
ol
ILEAK
–10
200
µA
0 V ≤ digital
Vin ≤ VGG
Input capacitance
Load capacitance
NOTE(S):
—
—
—
—
—
10
15
pF
pF
Digital outputs
1. The digital inputs of CN833x are TTL 5 V compliant. These inputs are diode protected to
DVDDIO and DVSSIO pins. Additionally, all of the CN8331/CN8332/CN8333 digital inputs
contain 75 kΩ pull-down resistors.
2. The digital outputs of CN8331/CN8332/CN8333 are also TTL 5 V compliant. However,
these outputs will not drive to 5 V, nor will they accept 5 V external pullups. The output is
DVDDC (3.3 V).
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2.8 AC Characteristics
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.8 AC Characteristics
Table 2-4. AC Characteristics (Logic Timing)
Parameter
Conditions
Min
Nom
Max
Unit
Tosym, Tisym
RCLK and TCLK
E3
DS-3
STS-1
—
29.10
22.35
19.29
—
ns
ns
ns
Clock Duty Cycle
Towidth/Tosym, RCLK
Tiwidth/Tisym, TCLK
Tiwidth/Tisym, REFCLK
45
40
40
—
55
60
60
%
%
%
Todelay
Tisetup
5
ns
ns
TPOS/TNRZ, TNEG,
TAIS
4
0
—
—
—
Tihold
TPOS/TNRZ, TNEG,
TAIS
—
ns
NOTE(S):
1. The description applies to the DS3, E3, and STS-1 clock rates and other parameters such
as pulse width, set-up time, hold time, and duty cycle.
2. The timing diagram, illustrated in Figure 2-9, describes the logical relationship between
various clock and data signals, and parameter values.
2-18
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Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.8 AC Characteristics
Figure 2-9. Timing Diagram
Tosym
DATA OUTPUTS
RCLK
Towidth
Todelay
RPOS/RNRZ,
RNEG/RLCV
Tisym
DATA INPUTS
Tiwidth
TCLK
Tisetup
Tihold
TPOS/TNRZ,
TNEG, TAIS,
Don't
Care
Don't
Care
Valid Data
100604_016
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2.8 AC Characteristics
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2-20
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3
3.0 Applications
The CN8331/CN8332/CN8333 can be used in a variety of applications.
Figure 3-1 illustrates an example of three DS3 lines being terminated by the
CN8333. The data and clock are extracted and passed on to the framer chip for
further data manipulation and user interface.
It is important to employ high-frequency design techniques for the printed
board layout.
3.1 PCB Design Considerations for
CN8331/CN8332/CN8333
The CN8333 device is a triple LIU operating at frequencies up to 52 MHz. The
high-speed nature of the device calls for a careful design of the PCB using this
part. Some design considerations are outlined below.
3.1.1 Power Supply and Ground Plane
A unified power plane with properly placed capacitors of the correct size will
mitigate most power rail-related voltage transients. A properly placed bulk
capacitor, where the power enters the board, with noise-bypassing capacitors at
the power pins on the integrated circuits should be adequate. The noise-bypassing
capacitors must be able to supply all the switching current.
Ferrite beads are used with power rails to filter the high-frequency noise. For
every design, noise frequencies and levels are different. Therefore, whether beads
are necessary, and the effective frequency where they should operate, is difficult
to determine. It is a good idea to provision for ferrite beads on the boards.
The board trace from the CN8333 power supply pin to the noise-bypassing
capacitor should be minimized. Additionally, ground connections from the
ground plane to the CN8333 ground pins and the noise-bypassing capacitor
ground pins should be minimized.
A unified ground plane is the best way to minimize ground impedance. Most
of the ground noise is produced by the return currents and power supply transients
during switching. This effect is minimized by reducing the ground plane
impedance.
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3.1 PCB Design Considerations for CN8331/CN8332/CN8333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
3.1.2 Impedance Matching
It is critical that traces around the transformers and matching resistors be kept to a
minimum length and, in the following cases, the trace impedance be matched to
75 Ω:
•
•
The impedance from the BNC connector to the transformer
The impedance from the transformer to the matching resistors
3.1.3 Other Passive Parts
The reference design uses the Pulse T3001 extended temperature range 1:1
transformer for the coupling of the BNC connector to the device.
The ferrite beads used to decouple the receive- and transmit-VDD pins and the
ferrite beads on all analog input VDD pins are type 2508056017Y0 from
Fair-Rite. The bulk capacitor used for where the power enters the board can be a
electrolytic or tantulum type capacitor, the recommended value and type is a
220µf tantulum capacitor.
3.1.4 IBIS Models
IBIS (Input/Output Buffer Interface Specification) models for the
CN8331/CN8332/CN8333 are available from Conexant.
3.1.5 Recommended Vendors
Part #
T3001, Data Sheet - T619
America
Address:
Pulse
Fair-Rite Products Corp.
P.O. Box J
One Commercial Row
Wallkill, NY 12589
914-895-2055
Corporate Office
12220 World Trade Drive
San Diego, CA 92128
858-674-8100
Telo:
Fax:
Telo:
858-674-8262
Northern Asia
Pulse
3F-4, No. 81, Sec. 1
Hsin Tai Wu Road
Hsi-Chih
Tapei Hsien, Taiwan
R.O.C.
Telo:
886-2-26980228
886-2-26980948
Northern Europe
Pulse
1S2 Huxley Road
The Surrey Research Park
Guildford, Surrey GU2 5RE
United Kingdom
Telo:
Fax:
44-1483-401700
44-1483-401701
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3.1 PCB Design Considerations for CN8331/CN8332/CN8333
Figure 3-1. Typical Connection of CN8333
CN8333
Type 728, 734, 735
75
31.6
1:1
TPOS
TNEG
TCLK
TLINEP
TLINEM
TX
31.6
37.4
Type 728, 734, 735
75
Framer
Framer
Framer
Channel 1
1:1
1:1
1:1
RLINEP
RLINEM
RPOS
0.01µF
RNEG
RCLK
RX
37.4
MODE
BIAS RESET
Type 728, 734, 735
75
31.6
1:1
TLINEP
TPOS
TNEG
TCLK
TX
TLINEM
31.6
37.4
Type 728, 734, 735
75
Channel 2
RLINEP
RLINEM
RPOS
RNEG
RCLK
0.01µF
RX
37.4
MODE
BIAS RESET
Type 728, 734, 735
75
31.6
1:1
TLINEP
TPOS
TNEG
TCLK
TX
TLINEM
31.6
37.4
Type 728, 734, 735
75
Channel 2
RLINEP
RLINEM
RPOS
RNEG
RCLK
0.01µF
RX
37.4
MODE
BIAS RESET
MODE
BIAS
RESET
RBIAS
12.1K
Mode/Status Pins
NOTE(S): All transformers are part number T3001 from Pulse Technology. (See Recommended Vendors, page 3.2.)
100604_004
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3.1 PCB Design Considerations for CN8331/CN8332/CN8333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
3-4
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A
Appendix A
A.1 Applicable Standards
The applicable standards documents are as follows:
•
•
•
•
•
ANSI T1.102-1993 (DS3 and STS-1 standard)
ANSI T1.404a-1996 (DS3 metallic interface)
ITU Recommendation G.703 (DS3 and E3 standard)
ITU Recommendation G.823 and G.824 (jitter and wander)
Bellcore GR499, Issue 1, 12/89 (formerly TR-TSY-000499)
(DS3 and STS-1 requirements)
•
Bellcore GR253, Issue 2, 12/91 (formerly TA-NWT-000253)
(STS-1 requirements and jitter)
•
•
•
•
Bellcore TR-TSY-000191, Issue 1, 5/86 (AIS and LOS)
ETSI TBR24 and TBR25 (E3 terminal equipment interface)
ETSI ETS 300 686 and ETS 300 687 (E3 standard)
AT&T Technical Reference TR54014, May 1992 (Accunet Interface
Specification for DS-3 jitter only)
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Appendix A
CN8331/CN8332/CN8333
A.1 Applicable Standards
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
A-2
Conexant
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B
Appendix B
B.1 Evaluation Module Schematic
100604B
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B-1
Preliminary Information/Conexant Proprietary and Confidential
Appendix B
CN8331/CN8332/CN8333
B.1 Evaluation Module Schematic
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure B-1. Recommended Schematic for the CN833x Device
21
80
RVDD3
RBIAS
22
79
RLINE3P
VGG
23
78
RLINE3M
TMUXIO1
24
77
RVSS3
TMUXIO2
25
76
PDB3
PDB1
26
75
RLOOP3
RLOOP1
27
74
LLOOP3
LLOOP1
28
73
DVSS2
DVDD2
LBO1
29
72
LBO3
30
71
XOE3
XOE1
31
70
REQH3/TMUXA1
REQH1/TMUXDAT
32
69
RNEG3/RLCV3
RNEG1/RLCV1
33
68
RPOS3/RNRZ3
RPOS1/RNRZ1
34
67
RCLK3
RCLK1
35
66
RLOS3
RLOS1
36
65
REFCLK3
REFCLK1
37
64
TNEG3/NC3
TNEG1/NC1
38
63
TPOS3/TNRZ3
TPOS1/TNRZ1
39
62
TCLK3
TCLK1
40
61
TAIS3/TMUXA4
TAIS1/TMUXA2
SW5
12
11
10
9
1
2
3
4
5
6
SW1
8
7
14
13
12
11
10
1
2
3
4
5
6
7
9
8
SW3
14
13
12
11
10
9
1
2
3
4
5
6
7
SW2
8
14
13
12
11
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8333_027
B-2
Conexant
100604B
Preliminary Information/Conexant Proprietary and Confidential
0.0 Sales Offices
Further Information:
Hong Kong
literature@conexant.com
Phone: (852) 2 827 0181
1-800-854-8099 (North America)
33-14-906-3980 (International)
Fax: (852) 2 827 6488
India
Web Site
Phone: (91 11) 692 4780
www.conexant.com
Fax: (91 11) 692 4712
World Headquarters
Conexant Systems, Inc.
4311 Jamboree Road,
P.O. Box C
Korea
Phone: (82 2) 565 2880
Fax: (82 2) 565 1440
Newport Beach, CA 92658-8902
Phone: (949) 483-4600
Fax: (949) 483-6375
Europe Headquarters
Conexant Systems France
Les Taissounieres B1
1681 Route des Dolines
BP 283
U.S. Florida/South America
Phone: (727) 799-8406
Fax: (727) 799-8306
06905 Sophia Antipolis Cedex
France
Phone: (33 4) 93 00 33 35
Fax: (33 4) 93 00 33 03
U.S. Los Angeles
Phone: (805) 376-0559
Fax: (805) 376-8180
Europe Central
Phone: (49 89) 829 1320
U.S. Mid-Atlantic
Fax: (49 89) 834 2734
Phone: (215) 244-6784
Fax: (215) 244-9292
Europe Mediterranean
Phone: (39 02) 9317 9911
Fax: (39 02) 9317 9913
U.S. North Central
Phone: (630) 773-3454
Fax: (630) 773-3907
Europe North
Phone: (44 1344) 486 444
U.S. Northeast
Fax: (44 1344) 486 555
Phone: (978) 692-7660
Fax: (978) 692-8185
Europe South
Phone: (33 1) 41 44 36 50
U.S. Northwest/Pacific West
Phone: (408) 249-9696
Fax: (408) 249-7113
Fax: (33 1) 41 44 36 90
Middle East Headquarters
Conexant Systems
U.S. South Central
Phone: (972) 733-0723
Fax: (972) 407-0639
Commercial (Israel) Ltd.
P.O. Box 12660
Herzlia 46733, Israel
Phone: (972 9) 952 4064
Fax: (972 9) 951 3924
U.S. Southeast
Phone: (919) 858-9110
Fax: (919) 858-8669
Japan Headquarters
Conexant Systems Japan Co., Ltd.
Shimomoto Building
1-46-3 Hatsudai,
U.S. Southwest
Phone: (949) 483-9119
Fax: (949) 483-9090
Shibuya-ku, Tokyo
151-0061 Japan
APAC Headquarters
Conexant Systems Singapore,
Pte. Ltd.
Phone: (81 3) 5371 1567
Fax: (81 3) 5371 1501
1 Kim Seng Promenade
Great World City
#09-01 East Tower
Singapore 237994
Phone: (65) 737 7355
Fax: (65) 737 9077
Taiwan Headquarters
Conexant Systems, Taiwan Co., Ltd.
Room 2808
International Trade Building
333 Keelung Road, Section 1
Taipei 110, Taiwan, ROC
Phone: (886 2) 2720 0282
Fax: (886 2) 2757 6760
Australia
Phone: (61 2) 9869 4088
Fax: (61 2) 9869 4077
China
Phone: (86 2) 6361 2515
Fax: (86 2) 6361 2516
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